stm32l4xx_hal_pwr.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   PWR HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Power Controller (PWR) peripheral:
00010   *           + Initialization/de-initialization functions
00011   *           + Peripheral Control functions
00012   *
00013   ******************************************************************************
00014   * @attention
00015   *
00016   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00017   *
00018   * Redistribution and use in source and binary forms, with or without modification,
00019   * are permitted provided that the following conditions are met:
00020   *   1. Redistributions of source code must retain the above copyright notice,
00021   *      this list of conditions and the following disclaimer.
00022   *   2. Redistributions in binary form must reproduce the above copyright notice,
00023   *      this list of conditions and the following disclaimer in the documentation
00024   *      and/or other materials provided with the distribution.
00025   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00026   *      may be used to endorse or promote products derived from this software
00027   *      without specific prior written permission.
00028   *
00029   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00030   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00031   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00032   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00033   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00034   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00035   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00036   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00037   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00038   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00039   *
00040   ******************************************************************************
00041   */
00042 
00043 /* Includes ------------------------------------------------------------------*/
00044 #include "stm32l4xx_hal.h"
00045 
00046 /** @addtogroup STM32L4xx_HAL_Driver
00047   * @{
00048   */
00049 
00050 /** @defgroup PWR PWR
00051   * @brief PWR HAL module driver
00052   * @{
00053   */
00054 
00055 #ifdef HAL_PWR_MODULE_ENABLED
00056 
00057 /* Private typedef -----------------------------------------------------------*/
00058 /* Private define ------------------------------------------------------------*/ 
00059 
00060 /** @defgroup PWR_Private_Defines PWR Private Defines
00061   * @{
00062   */
00063   
00064 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
00065   * @{
00066   */ 
00067 #define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */ 
00068 #define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */ 
00069 #define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */ 
00070 #define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */ 
00071 /**
00072   * @}
00073   */
00074 
00075 /**
00076   * @}
00077   */
00078   
00079 /* Private macro -------------------------------------------------------------*/
00080 /* Private variables ---------------------------------------------------------*/
00081 /* Private function prototypes -----------------------------------------------*/
00082 /* Exported functions --------------------------------------------------------*/
00083 
00084 /** @defgroup PWR_Exported_Functions PWR Exported Functions
00085   * @{
00086   */
00087 
00088 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
00089   *  @brief    Initialization and de-initialization functions
00090   *
00091 @verbatim
00092  ===============================================================================
00093               ##### Initialization and de-initialization functions #####
00094  ===============================================================================
00095     [..]
00096 
00097 @endverbatim
00098   * @{
00099   */
00100 
00101 /**
00102   * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
00103   * @retval None
00104   */
00105 void HAL_PWR_DeInit(void)
00106 {
00107   __HAL_RCC_PWR_FORCE_RESET();
00108   __HAL_RCC_PWR_RELEASE_RESET();
00109 }
00110 
00111 /**
00112   * @brief Enable access to the backup domain 
00113   *        (RTC registers, RTC backup data registers).
00114   * @note  After reset, the backup domain is protected against 
00115   *        possible unwanted write accesses.
00116   * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
00117   *        In order to set or modify the RTC clock, the backup domain access must be
00118   *        disabled. 
00119   * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
00120   *        back-up domain.                
00121   * @retval None
00122   */
00123 void HAL_PWR_EnableBkUpAccess(void)
00124 {
00125   SET_BIT(PWR->CR1, PWR_CR1_DBP);    
00126 }
00127 
00128 /**
00129   * @brief Disable access to the backup domain
00130   *        (RTC registers, RTC backup data registers).    
00131   * @retval None
00132   */
00133 void HAL_PWR_DisableBkUpAccess(void)
00134 {
00135   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);   
00136 }
00137 
00138 
00139 
00140 
00141 /**
00142   * @}
00143   */
00144 
00145 
00146 
00147 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
00148   *  @brief Low Power modes configuration functions
00149   *
00150 @verbatim
00151 
00152  ===============================================================================
00153                  ##### Peripheral Control functions #####
00154  ===============================================================================
00155  
00156      [..]
00157      *** PVD configuration ***
00158     =========================
00159     [..]
00160       (+) The PVD is used to monitor the VDD power supply by comparing it to a
00161           threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
00162 
00163       (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
00164           than the PVD threshold. This event is internally connected to the EXTI
00165           line16 and can generate an interrupt if enabled. This is done through
00166           __HAL_PVD_EXTI_ENABLE_IT() macro.
00167       (+) The PVD is stopped in Standby mode.
00168  
00169     
00170     *** WakeUp pin configuration ***
00171     ================================
00172     [..]
00173       (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. 
00174           The polarity of these pins can be set to configure event detection on high 
00175           level (rising edge) or low level (falling edge).
00176 
00177 
00178    
00179     *** Low Power modes configuration ***
00180     =====================================
00181     [..]
00182       The devices feature 8 low-power modes:
00183       (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
00184       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
00185       (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
00186       (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
00187       (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
00188       (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.      
00189       (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. 
00190       (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
00191       (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
00192 
00193 
00194    *** Low-power run mode ***
00195    ==========================
00196     [..]
00197       (+) Entry: (from main run mode)
00198         (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. 
00199      
00200       (+) Exit:
00201         (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
00202              then can the system clock frequency be increased above 2 MHz.
00203 
00204 
00205    *** Sleep mode / Low-power sleep mode ***
00206    =========================================
00207     [..]
00208       (+) Entry:                                                         
00209           The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
00210           in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. 
00211           (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).              
00212           (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
00213           In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.           
00214           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
00215           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
00216      
00217       (+) WFI Exit:
00218         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
00219              controller (NVIC) or any wake-up event.
00220              
00221       (+) WFE Exit:
00222         (++) Any wake-up event such as an EXTI line configured in event mode.             
00223              
00224          [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, 
00225              the MCU is in Low-power Run mode. 
00226 
00227    *** Stop 0, Stop 1 and Stop 2 modes ***
00228    ===============================
00229     [..]
00230       (+) Entry:                                                 
00231           The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
00232           (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
00233           (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.  
00234       (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
00235           (++) PWR_MAINREGULATOR_ON
00236           (++) PWR_LOWPOWERREGULATOR_ON
00237       (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
00238           (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
00239           (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
00240           
00241       (+) WFI Exit:
00242           (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
00243           (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts 
00244                when programmed in wakeup mode. 
00245       (+) WFE Exit:  
00246           (++) Any EXTI Line (Internal or External) configured in Event mode.
00247        
00248        [..]                      
00249           When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
00250           depending on the LPR bit setting. 
00251           When exiting Stop 2 mode, the MCU is in Run mode. 
00252 
00253    *** Standby mode ***
00254    ====================
00255      [..]
00256       The Standby mode offers two options: 
00257       (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
00258         SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers 
00259         and Standby circuitry.      
00260       (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
00261         SRAM and register contents are lost except for the RTC registers, RTC backup registers 
00262         and Standby circuitry.
00263 
00264       (++) Entry:                                    
00265           (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. 
00266                 SRAM1 and register contents are lost except for registers in the Backup domain and 
00267                 Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
00268                 To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
00269                 to set RRS bit.   
00270           
00271       (++) Exit:
00272           (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
00273                 external reset in NRST pin, IWDG reset.
00274                 
00275       [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
00276           
00277 
00278     *** Shutdown mode ***
00279    ======================
00280      [..]
00281       In Shutdown mode, 
00282         voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
00283         SRAM and registers contents are lost except for backup domain registers.
00284 
00285       (+) Entry:                                    
00286           The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
00287           
00288       (+) Exit:
00289           (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
00290                external reset in NRST pin.
00291                
00292          [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
00293 
00294 
00295    *** Auto-wakeup (AWU) from low-power mode ***
00296    =============================================
00297     [..]
00298       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
00299       Wakeup event, a tamper event or a time-stamp event, without depending on
00300       an external interrupt (Auto-wakeup mode).
00301 
00302       (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
00303   
00304 
00305         (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
00306              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
00307 
00308         (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
00309              is necessary to configure the RTC to detect the tamper or time stamp event using the
00310              HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
00311 
00312         (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
00313               configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
00314 
00315 @endverbatim
00316   * @{
00317   */
00318 
00319 
00320 
00321 /**
00322   * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
00323   * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD 
00324   *        configuration information.
00325   * @note Refer to the electrical characteristics of your device datasheet for
00326   *         more details about the voltage thresholds corresponding to each
00327   *         detection level.
00328   * @retval None
00329   */
00330 HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
00331 {
00332   /* Check the parameters */
00333   assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
00334   assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
00335 
00336   /* Set PLS bits according to PVDLevel value */
00337   MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
00338   
00339   /* Clear any previous config. Keep it clear if no event or IT mode is selected */
00340   __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
00341   __HAL_PWR_PVD_EXTI_DISABLE_IT();
00342   __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
00343   __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
00344 
00345   /* Configure interrupt mode */
00346   if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
00347   {
00348     __HAL_PWR_PVD_EXTI_ENABLE_IT();
00349   }
00350   
00351   /* Configure event mode */
00352   if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
00353   {
00354     __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
00355   }
00356   
00357   /* Configure the edge */
00358   if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
00359   {
00360     __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
00361   }
00362   
00363   if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
00364   {
00365     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
00366   }
00367   
00368   return HAL_OK;
00369 }
00370 
00371 
00372 /**
00373   * @brief Enable the Power Voltage Detector (PVD).
00374   * @retval None
00375   */
00376 void HAL_PWR_EnablePVD(void)
00377 {
00378   SET_BIT(PWR->CR2, PWR_CR2_PVDE);  
00379 }
00380 
00381 /**
00382   * @brief Disable the Power Voltage Detector (PVD).
00383   * @retval None
00384   */
00385 void HAL_PWR_DisablePVD(void)
00386 {
00387   CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);   
00388 }
00389 
00390 
00391 
00392 
00393 /**
00394   * @brief Enable the WakeUp PINx functionality.
00395   * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
00396   *         This parameter can be one of the following legacy values which set the default polarity 
00397   *         i.e. detection on high level (rising edge):
00398   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
00399   *             
00400   *         or one of the following value where the user can explicitly specify the enabled pin and
00401   *         the chosen polarity:  
00402   *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 
00403   *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 
00404   *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 
00405   *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
00406   *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 
00407   * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               
00408   * @retval None
00409   */
00410 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
00411 {
00412   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); 
00413   
00414   /* Specifies the Wake-Up pin polarity for the event detection 
00415     (rising or falling edge) */
00416   MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); 
00417     
00418   /* Enable wake-up pin */
00419   SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
00420 
00421     
00422 }
00423 
00424 /**
00425   * @brief Disable the WakeUp PINx functionality.
00426   * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
00427   *         This parameter can be one of the following values:
00428   *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 
00429   * @retval None
00430   */
00431 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
00432 {
00433   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
00434 
00435   CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); 
00436 }
00437 
00438 
00439 /**
00440   * @brief Enter Sleep or Low-power Sleep mode.
00441   * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
00442   * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
00443   *          This parameter can be one of the following values:
00444   *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
00445   *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) 
00446   * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet 
00447   *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set 
00448   *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the    
00449   *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
00450   *        Additionally, the clock frequency must be reduced below 2 MHz.
00451   *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must 
00452   *        be done before calling HAL_PWR_EnterSLEEPMode() API. 
00453   * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in 
00454   *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.       
00455   * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
00456   *           This parameter can be one of the following values:
00457   *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
00458   *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
00459   * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as 
00460   *        the interrupt wake up source.   
00461   * @retval None
00462   */
00463 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
00464 {
00465   /* Check the parameters */
00466   assert_param(IS_PWR_REGULATOR(Regulator));
00467   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
00468 
00469   /* Set Regulator parameter */
00470   if (Regulator == PWR_MAINREGULATOR_ON)
00471   {
00472     /* If in low-power run mode at this point, exit it */
00473     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
00474     {
00475       HAL_PWREx_DisableLowPowerRunMode();  
00476     } 
00477     /* Regulator now in main mode. */
00478   }
00479   else
00480   {
00481     /* If in run mode, first move to low-power run mode.
00482        The system clock frequency must be below 2 MHz at this point. */
00483     if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
00484     {
00485       HAL_PWREx_EnableLowPowerRunMode();  
00486     } 
00487   } 
00488     
00489   /* Clear SLEEPDEEP bit of Cortex System Control Register */
00490   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00491   
00492   /* Select SLEEP mode entry -------------------------------------------------*/
00493   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
00494   {
00495     /* Request Wait For Interrupt */
00496     __WFI();
00497   }
00498   else
00499   {
00500     /* Request Wait For Event */
00501     __SEV();
00502     __WFE();
00503     __WFE();
00504   }
00505 
00506 }
00507 
00508 
00509 /**
00510   * @brief Enter Stop mode
00511   * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
00512   *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
00513   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.          
00514   * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
00515   *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
00516   *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
00517   *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
00518   *        only to the peripheral requesting it.
00519   *        SRAM1, SRAM2 and register contents are preserved.
00520   *        The BOR is available.
00521   *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).  
00522   * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
00523   *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
00524   *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
00525   * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
00526   *         startup delay is incurred when waking up.
00527   *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
00528   *         is higher although the startup time is reduced.
00529   * @param Regulator: Specifies the regulator state in Stop mode.
00530   *          This parameter can be one of the following values:
00531   *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
00532   *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON) 
00533   * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
00534   *          This parameter can be one of the following values:
00535   *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
00536   *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
00537   * @retval None
00538   */
00539 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
00540 {
00541   /* Check the parameters */
00542   assert_param(IS_PWR_REGULATOR(Regulator));
00543   
00544   if(Regulator == PWR_LOWPOWERREGULATOR_ON)
00545   {
00546     HAL_PWREx_EnterSTOP1Mode(STOPEntry);
00547   }
00548   else
00549   {
00550     HAL_PWREx_EnterSTOP0Mode(STOPEntry);
00551   }
00552 }
00553 
00554 /**
00555   * @brief Enter Standby mode.
00556   * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched 
00557   *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
00558   *        in which case the regulator is in low-power mode. 
00559   *        SRAM1 and register contents are lost except for registers in the Backup domain and 
00560   *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
00561   *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
00562   *        to set RRS bit.   
00563   *        The BOR is available.  
00564   * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
00565   *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
00566   *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
00567   *        same.
00568   *        These states are effective in Standby mode only if APC bit is set through
00569   *        HAL_PWREx_EnablePullUpPullDownConfig() API.        
00570   * @retval None
00571   */
00572 void HAL_PWR_EnterSTANDBYMode(void)
00573 {
00574   /* Set Stand-by mode */
00575   MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
00576 
00577   /* Set SLEEPDEEP bit of Cortex System Control Register */
00578   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
00579 
00580 /* This option is used to ensure that store operations are completed */
00581 #if defined ( __CC_ARM)
00582   __force_stores();
00583 #endif
00584   /* Request Wait For Interrupt */
00585   __WFI();
00586 }
00587 
00588 
00589 
00590 /**
00591   * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. 
00592   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
00593   *       re-enters SLEEP mode when an interruption handling is over.
00594   *       Setting this bit is useful when the processor is expected to run only on
00595   *       interruptions handling.         
00596   * @retval None
00597   */
00598 void HAL_PWR_EnableSleepOnExit(void)
00599 {
00600   /* Set SLEEPONEXIT bit of Cortex System Control Register */
00601   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00602 }
00603 
00604 
00605 /**
00606   * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
00607   * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
00608   *       re-enters SLEEP mode when an interruption handling is over.          
00609   * @retval None
00610   */
00611 void HAL_PWR_DisableSleepOnExit(void)
00612 {
00613   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
00614   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
00615 }
00616 
00617 
00618 
00619 /**
00620   * @brief Enable CORTEX M4 SEVONPEND bit. 
00621   * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes 
00622   *       WFE to wake up when an interrupt moves from inactive to pended.
00623   * @retval None
00624   */
00625 void HAL_PWR_EnableSEVOnPend(void)
00626 {
00627   /* Set SEVONPEND bit of Cortex System Control Register */
00628   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00629 }
00630 
00631 
00632 /**
00633   * @brief Disable CORTEX M4 SEVONPEND bit. 
00634   * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes 
00635   *       WFE to wake up when an interrupt moves from inactive to pended.         
00636   * @retval None
00637   */
00638 void HAL_PWR_DisableSEVOnPend(void)
00639 {
00640   /* Clear SEVONPEND bit of Cortex System Control Register */
00641   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
00642 }
00643 
00644 
00645 
00646 
00647 
00648 /**
00649   * @brief PWR PVD interrupt callback
00650   * @retval None
00651   */
00652 __weak void HAL_PWR_PVDCallback(void)
00653 {
00654   /* NOTE : This function should not be modified; when the callback is needed,
00655             the HAL_PWR_PVDCallback can be implemented in the user file
00656    */
00657 }
00658 
00659 /**
00660   * @}
00661   */
00662 
00663 /**
00664   * @}
00665   */
00666 
00667 #endif /* HAL_PWR_MODULE_ENABLED */
00668 /**
00669   * @}
00670   */
00671 
00672 /**
00673   * @}
00674   */
00675 
00676 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/