stm32l4xx_hal_nor.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_nor.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of NOR HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */ 
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_NOR_H
00040 #define __STM32L4xx_HAL_NOR_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00047 
00048 /* Includes ------------------------------------------------------------------*/
00049 #include "stm32l4xx_ll_fmc.h"
00050 
00051 
00052 /** @addtogroup STM32L4xx_HAL_Driver
00053   * @{
00054   */
00055 
00056 /** @addtogroup NOR
00057   * @{
00058   */ 
00059 
00060 /** @addtogroup NOR_Private_Constants
00061   * @{
00062   */
00063 
00064 /* NOR device IDs addresses */
00065 #define MC_ADDRESS               ((uint16_t)0x0000)
00066 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
00067 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
00068 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
00069 
00070 /* NOR CFI IDs addresses */
00071 #define CFI1_ADDRESS             ((uint16_t)0x10)
00072 #define CFI2_ADDRESS             ((uint16_t)0x11)
00073 #define CFI3_ADDRESS             ((uint16_t)0x12)
00074 #define CFI4_ADDRESS             ((uint16_t)0x13)
00075 
00076 /* NOR memory data width */
00077 #define NOR_MEMORY_8B            ((uint8_t)0x0)
00078 #define NOR_MEMORY_16B           ((uint8_t)0x1)
00079 
00080 /* NOR memory device read/write start address */
00081 #define NOR_MEMORY_ADRESS1       FMC_BANK1_1
00082 #define NOR_MEMORY_ADRESS2       FMC_BANK1_2
00083 #define NOR_MEMORY_ADRESS3       FMC_BANK1_3
00084 #define NOR_MEMORY_ADRESS4       FMC_BANK1_4
00085 
00086 /**
00087   * @}
00088   */
00089 
00090 /** @addtogroup NOR_Private_Macros
00091   * @{
00092   */
00093 
00094 /**
00095   * @brief  NOR memory address shifting.
00096   * @param  __NOR_ADDRESS: NOR base address 
00097   * @param  __NOR_MEMORY_WIDTH_: NOR memory width
00098   * @param  __ADDRESS__: NOR memory address 
00099   * @retval NOR shifted address value
00100   */
00101 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
00102             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
00103               ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
00104               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
00105 
00106 /**
00107   * @brief  NOR memory write data to specified address.
00108   * @param  __ADDRESS__: NOR memory address 
00109   * @param  __DATA__: Data to write
00110   * @retval None
00111   */
00112 #define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
00113 
00114 /**
00115   * @}
00116   */
00117 
00118 /* Exported typedef ----------------------------------------------------------*/
00119 /** @defgroup NOR_Exported_Types NOR Exported Types
00120   * @{
00121   */
00122 
00123 /** 
00124   * @brief  HAL SRAM State structures definition  
00125   */ 
00126 typedef enum
00127 {  
00128   HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
00129   HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
00130   HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
00131   HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */
00132   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected   */
00133 }HAL_NOR_StateTypeDef;
00134 
00135 /**
00136   * @brief  FMC NOR Status typedef
00137   */
00138 typedef enum
00139 {
00140   HAL_NOR_STATUS_SUCCESS = 0,
00141   HAL_NOR_STATUS_ONGOING,
00142   HAL_NOR_STATUS_ERROR,
00143   HAL_NOR_STATUS_TIMEOUT
00144 }HAL_NOR_StatusTypeDef; 
00145 
00146 /**
00147   * @brief  FMC NOR ID typedef
00148   */
00149 typedef struct
00150 {
00151   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
00152 
00153   uint16_t Device_Code1;
00154 
00155   uint16_t Device_Code2;
00156 
00157   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory. 
00158                                     These codes can be accessed by performing read operations with specific 
00159                                     control signals and addresses set.They can also be accessed by issuing 
00160                                     an Auto Select command.                                                   */    
00161 }NOR_IDTypeDef;
00162 
00163 /**
00164   * @brief  FMC NOR CFI typedef
00165   */
00166 typedef struct
00167 {
00168   uint16_t CFI_1;
00169 
00170   uint16_t CFI_2;
00171 
00172   uint16_t CFI_3;
00173 
00174   uint16_t CFI_4;  /*!< Defines the information stored in the memory's Common flash interface
00175                         which contains a description of various electrical and timing parameters, 
00176                         density information and functions supported by the memory.                   */
00177 }NOR_CFITypeDef;
00178 
00179 /** 
00180   * @brief  NOR handle Structure definition
00181   */ 
00182 typedef struct
00183 {
00184   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
00185 
00186   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
00187 
00188   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
00189 
00190   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
00191 
00192   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
00193 
00194 }NOR_HandleTypeDef; 
00195 
00196 /**
00197   * @}
00198   */
00199 
00200 /* Exported constants --------------------------------------------------------*/
00201 /* Exported macro ------------------------------------------------------------*/
00202 /** @defgroup NOR_Exported_Macros NOR Exported Macros
00203   * @{
00204   */
00205 
00206 /** @brief Reset NOR handle state.
00207   * @param  __HANDLE__: NOR handle
00208   * @retval None
00209   */
00210 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
00211 
00212 /**
00213   * @}
00214   */
00215 
00216 /* Exported functions --------------------------------------------------------*/
00217 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
00218   * @{
00219   */
00220 
00221 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions 
00222   * @{
00223   */
00224 
00225 /* Initialization/de-initialization functions  ********************************/
00226 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
00227 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
00228 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
00229 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
00230 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
00231 
00232 /**
00233   * @}
00234   */
00235 
00236 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions 
00237   * @{
00238   */
00239 
00240 /* I/O operation functions  ***************************************************/
00241 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
00242 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
00243 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00244 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
00245 
00246 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00247 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
00248 
00249 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
00250 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
00251 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
00252 
00253 /**
00254   * @}
00255   */
00256   
00257 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions 
00258   * @{
00259   */
00260 
00261 /* NOR Control functions  *****************************************************/
00262 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
00263 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
00264 
00265 /**
00266   * @}
00267   */  
00268   
00269 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions 
00270   * @{
00271   */
00272 
00273 /* NOR State functions ********************************************************/
00274 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
00275 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
00276 
00277 /**
00278   * @}
00279   */ 
00280 
00281 /**
00282   * @}
00283   */
00284 
00285 /**
00286   * @}
00287   */ 
00288 
00289 /**
00290   * @}
00291   */
00292 
00293 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00294 
00295 #ifdef __cplusplus
00296 }
00297 #endif
00298 
00299 #endif /* __STM32L4xx_HAL_NOR_H */
00300 
00301 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/