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stm32l4xx_hal_adc_ex.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc_ex.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of ADC HAL extended module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_ADC_EX_H 00040 #define __STM32L4xx_ADC_EX_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup ADCEx ADCEx 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief Structure definition of ADC initialization and regular group 00064 * @note Parameters of this structure are shared within 2 scopes: 00065 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler and ClockDivider, Resolution, DataAlign, 00066 * ScanConvMode, EOCSelection, LowPowerAutoWait. 00067 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, 00068 * ExternalTrigConv, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 00069 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned by ADC state. 00070 * ADC state can be either: 00071 * - For all parameters: ADC disabled 00072 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on regular group. 00073 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups. 00074 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00075 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter 00076 * (which fulfills the ADC state condition) on the fly). 00077 */ 00078 typedef struct 00079 { 00080 uint32_t ClockPrescaler; /*!< Selects ADC clock source (asynchronous System/PLLSAI1/PLLSAI2 clocks or synchronous AHB clock) as well as 00081 the division factor applied to the clock. 00082 This parameter can be a value of @ref ADC_ClockPrescaler. 00083 Note: The clock is common for all the ADCs. 00084 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 00085 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 00086 Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level. 00087 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the AHB clock prescaler is set to 1 00088 and if the system clock has a 50% duty cycle. 00089 Note: This parameter can be modified only if all ADCs are disabled. */ 00090 00091 uint32_t Resolution; /*!< Configures the ADC resolution. 00092 This parameter can be a value of @ref ADC_Resolution */ 00093 00094 uint32_t DataAlign; /*!< Specifies ADC data alignment (right or left). 00095 See reference manual for alignments formats versus resolutions. 00096 This parameter can be a value of @ref ADC_Data_align */ 00097 00098 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. 00099 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 00100 If disabled: Conversion is performed in single mode (one channel converted, that defined in rank 1). 00101 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 00102 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or'InjectedNbrOfConversion'). 00103 Scan direction is upward: from rank 1 to rank 'n'. 00104 This parameter can be a value of @ref ADC_Scan_mode */ 00105 00106 uint32_t EOCSelection; /*!< Specifies which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. 00107 This parameter can be a value of @ref ADC_EOCSelection. */ 00108 00109 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous 00110 conversion (for regular group) or previous sequence (for injected group) has been processed by user software 00111 (EOC bit cleared or DR read for regular conversions, JEOS cleared for injected conversions). 00112 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun 00113 for low frequency applications. 00114 This parameter can be set to ENABLE or DISABLE. 00115 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(), HAL_ADCEx_InjectedStart_IT()) when it is necessary 00116 to clear immediately the EOC flag to free the IRQ vector sequencer. 00117 Do use with polling: 1. Start conversion with HAL_ADC_Start() or HAL_ADCEx_InjectedStart(), 2. When conversion data is available: use 00118 HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another 00119 conversion. For injected conversion, resort to HAL_ADCEx_InjectedPollForConversion() then HAL_ADCEx_InjectedGetValue() */ 00120 00121 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, 00122 after software start or external trigger occurred. 00123 This parameter can be set to ENABLE or DISABLE. */ 00124 00125 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. 00126 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00127 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00128 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 00129 continuous mode or external trigger that could launch a conversion). */ 00130 00131 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence 00132 subdivided in successive parts). 00133 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00134 Discontinuous mode can be enabled only if continuous mode is disabled. 00135 This parameter can be set to ENABLE or DISABLE. */ 00136 00137 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. 00138 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 00139 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 00140 00141 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. 00142 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00143 This parameter can be a value of @ref ADC_Regular_External_Trigger_Source. 00144 Caution: external trigger source is common to ADCs. */ 00145 00146 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. 00147 If set to ADC_EXTERNALTRIGCONVEDGE_NONE, external triggers are disabled and software trigger is used instead. 00148 This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge */ 00149 00150 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 00151 or in Continuous mode (DMA transfer unlimited, whatever number of conversions). 00152 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. 00153 This parameter can be set to ENABLE or DISABLE. 00154 Note: This parameter must be modified when no conversion is on going on both regular and injected groups 00155 (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */ 00156 00157 uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten or preserved (default). 00158 This parameter applies to regular group only. 00159 This parameter can be a value of @ref ADC_Overrun. 00160 Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear 00161 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved by user-developped function 00162 HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear). 00163 Note: Error reporting with respect to the conversion mode: 00164 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 00165 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 00166 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 00167 00168 uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 00169 This parameter can be set to ENABLE or DISABLE. 00170 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00171 00172 ADC_OversamplingTypeDef Oversampling; /*!< Specifies the Oversampling parameters. 00173 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 00174 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00175 }ADC_InitTypeDef; 00176 00177 00178 /** 00179 * @brief ADC handle Structure definition 00180 */ 00181 typedef struct 00182 { 00183 ADC_TypeDef *Instance; /*!< Register base address */ 00184 00185 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 00186 00187 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 00188 00189 HAL_LockTypeDef Lock; /*!< ADC locking object */ 00190 00191 __IO uint32_t State; /*!< ADC communication state (bit-map of ADC states) */ 00192 00193 __IO uint32_t ErrorCode; /*!< ADC Error code */ 00194 00195 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 00196 }ADC_HandleTypeDef; 00197 00198 00199 /** 00200 * @brief ADC Injected Conversion Oversampling structure definition 00201 */ 00202 typedef struct 00203 { 00204 uint32_t Ratio; /*!< Configures the oversampling ratio. 00205 This parameter can be a value of @ref ADCEx_Oversampling_Ratio */ 00206 00207 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00208 This parameter can be a value of @ref ADCEx_Right_Bit_Shift */ 00209 }ADC_InjOversamplingTypeDef; 00210 00211 00212 00213 /** 00214 * @brief Structure definition of ADC injected group and ADC channel for injected group 00215 * @note Parameters of this structure are shared within 2 scopes: 00216 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 00217 * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 00218 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv, InjecOversamplingMode, InjecOversampling. 00219 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned by ADC state. 00220 * ADC state can be either: 00221 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 00222 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 00223 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 00224 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 00225 * on regular and injected groups. 00226 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00227 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 00228 */ 00229 typedef struct 00230 { 00231 uint32_t InjectedChannel; /*!< Configure the ADC injected channel. 00232 This parameter can be a value of @ref ADC_channels 00233 Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */ 00234 uint32_t InjectedRank; /*!< The rank in the injected group sequencer. 00235 This parameter must be a value of @ref ADCEx_injected_rank. 00236 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00237 the new channel setting (or parameter number of conversions adjusted). */ 00238 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 00239 Unit: ADC clock cycles. 00240 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 00241 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00242 This parameter can be a value of @ref ADC_sampling_times. 00243 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00244 It overwrites the last setting. 00245 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00246 sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time 00247 setting). Refer to device DataSheet for timings values. */ 00248 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 00249 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00250 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00251 This parameter must be a value of @ref ADCEx_SingleDifferential. 00252 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00253 It overwrites the last setting. 00254 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00255 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00256 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00257 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case 00258 of another parameter update on the fly) */ 00259 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 00260 This parameter can be a value of @ref ADCEx_OffsetNumber. 00261 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00262 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 00263 Offset value must be a positive number. 00264 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 00265 0x3FF, 0xFF or 0x3F respectively. 00266 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00267 without continuous mode or external trigger that could launch a conversion). */ 00268 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. 00269 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00270 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 00271 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00272 configure a channel on injected group can impact the configuration of other channels previously set. */ 00273 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence 00274 subdivided in successive parts). 00275 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00276 Discontinuous mode can be enabled only if continuous mode is disabled. 00277 This parameter can be set to ENABLE or DISABLE. 00278 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00279 Note: For injected group, discontinuous mode converts the sequence channel by channel (only one channel at a time). 00280 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00281 configure a channel on injected group can impact the configuration of other channels previously set. */ 00282 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one 00283 This parameter can be set to ENABLE or DISABLE. 00284 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 00285 Note: To use Automatic injected conversion, injected group external triggers must be disabled. 00286 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 00287 To maintain JAUTO always enabled, DMA must be configured in circular mode. 00288 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00289 configure a channel on injected group can impact the configuration of other channels previously set. */ 00290 uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 00291 This parameter can be set to ENABLE or DISABLE. 00292 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 00293 new injected context is set when queue is full, error is triggered by interruption and through function 00294 'HAL_ADCEx_InjectedQueueOverflowCallback'. 00295 Caution: This feature request that the sequence is fully configured before injected conversion start. 00296 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 00297 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00298 configure a channel on injected group can impact the configuration of other channels previously set. 00299 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 00300 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 00301 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00302 This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source. 00303 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00304 configure a channel on injected group can impact the configuration of other channels previously set. */ 00305 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 00306 This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source_Edge. 00307 If trigger edge is set to ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, external triggers are disabled and software trigger is used instead. 00308 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00309 configure a channel on injected group can impact the configuration of other channels previously set. */ 00310 00311 uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 00312 This parameter can be set to ENABLE or DISABLE. 00313 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00314 00315 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 00316 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 00317 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00318 }ADC_InjectionConfTypeDef; 00319 00320 00321 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00322 /** 00323 * @brief Structure definition of ADC multimode 00324 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 00325 * Both Master and Slave ADCs must be disabled. 00326 */ 00327 typedef struct 00328 { 00329 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 00330 This parameter can be a value of @ref ADCEx_Common_mode. */ 00331 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 00332 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 00333 This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */ 00334 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 00335 This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases. 00336 Delay range depends on selected resolution: 00337 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 00338 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 00339 }ADC_MultiModeTypeDef; 00340 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00341 00342 /** 00343 * @} 00344 */ 00345 00346 /* Exported constants --------------------------------------------------------*/ 00347 00348 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 00349 * @{ 00350 */ 00351 00352 /** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode 00353 * @{ 00354 */ 00355 #define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel set in single-ended input mode */ 00356 #define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /*!< ADC channel set in differential mode */ 00357 /** 00358 * @} 00359 */ 00360 00361 /** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number 00362 * @{ 00363 */ 00364 #define ADC_OFFSET_NONE ((uint32_t)0x00) /*!< No offset correction */ 00365 #define ADC_OFFSET_1 ((uint32_t)0x01) /*!< Offset correction to apply to a first channel */ 00366 #define ADC_OFFSET_2 ((uint32_t)0x02) /*!< Offset correction to apply to a second channel */ 00367 #define ADC_OFFSET_3 ((uint32_t)0x03) /*!< Offset correction to apply to a third channel */ 00368 #define ADC_OFFSET_4 ((uint32_t)0x04) /*!< Offset correction to apply to a fourth channel */ 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank 00374 * @{ 00375 */ 00376 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ 00377 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ 00378 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ 00379 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ 00380 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ 00381 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ 00382 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ 00383 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ 00384 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ 00385 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ 00386 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ 00387 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ 00388 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ 00389 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ 00390 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ 00391 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ 00392 /** 00393 * @} 00394 */ 00395 00396 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank 00397 * @{ 00398 */ 00399 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */ 00400 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */ 00401 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */ 00402 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */ 00403 /**injected 00404 * @} 00405 */ 00406 00407 /** @defgroup ADCEx_Injected_External_Trigger_Source_Edge ADC External Trigger Source Edge for Injected Group 00408 * @{ 00409 */ 00410 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /*!< Injected conversions hardware trigger detection disabled */ 00411 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 00412 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 00413 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group 00419 * @{ 00420 */ 00421 #define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /*!< Event 0 triggers injected group conversion start */ 00422 #define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /*!< Event 1 triggers injected group conversion start */ 00423 #define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /*!< Event 2 triggers injected group conversion start */ 00424 #define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 3 triggers injected group conversion start */ 00425 #define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /*!< Event 4 triggers injected group conversion start */ 00426 #define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 5 triggers injected group conversion start */ 00427 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 6 triggers injected group conversion start */ 00428 #define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 7 triggers injected group conversion start */ 00429 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /*!< Event 8 triggers injected group conversion start */ 00430 #define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0)) /*!< Event 9 triggers injected group conversion start */ 00431 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1)) /*!< Event 10 triggers injected group conversion start */ 00432 #define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0)) /*!< Event 11 triggers injected group conversion start */ 00433 #define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2)) /*!< Event 12 triggers injected group conversion start */ 00434 #define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0)) /*!< Event 13 triggers injected group conversion start */ 00435 #define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1)) /*!< Event 14 triggers injected group conversion start */ 00436 #define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /*!< Event 15 triggers injected group conversion start */ 00437 00438 #define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers injected group conversion start */ 00439 /** 00440 * @} 00441 */ 00442 00443 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00444 /** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode 00445 * @{ 00446 */ 00447 #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */ 00448 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /*!< Combined regular simultaneous + injected simultaneous mode */ 00449 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /*!< Combined regular simultaneous + alternate trigger mode */ 00450 #define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Combined Interleaved mode + injected simultaneous mode */ 00451 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0)) /*!< Injected simultaneous mode only */ 00452 #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1)) /*!< Regular simultaneous mode only */ 00453 #define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0)) /*!< Interleaved mode only */ 00454 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0)) /*!< Alternate trigger mode only */ 00455 /** 00456 * @} 00457 */ 00458 00459 /** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode 00460 * @{ 00461 */ 00462 #define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 00463 #define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 00464 #define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 00465 /** 00466 * @} 00467 */ 00468 00469 /** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases 00470 * @{ 00471 */ 00472 #define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /*!< 1 ADC clock cycle delay */ 00473 #define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /*!< 2 ADC clock cycles delay */ 00474 #define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /*!< 3 ADC clock cycles delay */ 00475 #define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 4 ADC clock cycles delay */ 00476 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /*!< 5 ADC clock cycles delay */ 00477 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) /*!< 6 ADC clock cycles delay */ 00478 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) /*!< 7 ADC clock cycles delay (lower for non 12-bit resolution) */ 00479 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 8 ADC clock cycles delay (lower for non 12-bit resolution) */ 00480 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /*!< 9 ADC clock cycles delay (lower for non 12-bit resolution) */ 00481 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) /*!< 10 ADC clock cycles delay (lower for non 12-bit resolution) */ 00482 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) /*!< 11 ADC clock cycles delay (lower for non 12-bit resolution) */ 00483 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) /*!< 12 ADC clock cycles delay (lower for non 12-bit resolution) */ 00484 /** 00485 * @} 00486 */ 00487 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 00488 /** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode 00489 * @{ 00490 */ 00491 #define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /*!< Independent ADC conversions mode */ 00492 /** 00493 * @} 00494 */ 00495 00496 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00497 00498 /** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection 00499 * @{ 00500 */ 00501 #define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /*!< Analog watchdog 1 selection */ 00502 #define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /*!< Analog watchdog 2 selection */ 00503 #define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /*!< Analog watchdog 3 selection */ 00504 /** 00505 * @} 00506 */ 00507 00508 /** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode 00509 * @{ 00510 */ 00511 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /*!< No analog watchdog selected */ 00512 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)) /*!< Analog watchdog applied to a regular group single channel */ 00513 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to an injected group single channel */ 00514 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to a regular and injected groups single channel */ 00515 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 00516 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 00517 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)) /*!< Analog watchdog applied to regular and injected groups all channels */ 00518 /** 00519 * @} 00520 */ 00521 00522 /** @defgroup ADCEx_conversion_group ADC Extended Conversion Group 00523 * @{ 00524 */ 00525 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) /*!< ADC regular group selection */ 00526 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC injected group selection */ 00527 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS)) /*!< ADC regular and injected groups selection */ 00528 /** 00529 * @} 00530 */ 00531 00532 /** @defgroup ADCEx_Event_type ADC Extended Event Type 00533 * @{ 00534 */ 00535 #define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 00536 #define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ 00537 #define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ 00538 #define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ 00539 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ 00540 #define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 00541 00542 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00543 /** 00544 * @} 00545 */ 00546 00547 /** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition 00548 * @{ 00549 */ 00550 #define ADC_IT_RDY ADC_IER_ADRDY /*!< ADC Ready (ADRDY) interrupt source */ 00551 #define ADC_IT_EOSMP ADC_IER_EOSMP /*!< ADC End of sampling interrupt source */ 00552 #define ADC_IT_EOC ADC_IER_EOC /*!< ADC End of regular conversion interrupt source */ 00553 #define ADC_IT_EOS ADC_IER_EOS /*!< ADC End of regular sequence of conversions interrupt source */ 00554 #define ADC_IT_OVR ADC_IER_OVR /*!< ADC overrun interrupt source */ 00555 #define ADC_IT_JEOC ADC_IER_JEOC /*!< ADC End of injected conversion interrupt source */ 00556 #define ADC_IT_JEOS ADC_IER_JEOS /*!< ADC End of injected sequence of conversions interrupt source */ 00557 #define ADC_IT_AWD1 ADC_IER_AWD1 /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 00558 #define ADC_IT_AWD2 ADC_IER_AWD2 /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 00559 #define ADC_IT_AWD3 ADC_IER_AWD3 /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 00560 #define ADC_IT_JQOVF ADC_IER_JQOVF /*!< ADC Injected Context Queue Overflow interrupt source */ 00561 00562 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 00563 00564 /** 00565 * @} 00566 */ 00567 00568 /** @defgroup ADCEx_flags_definition ADC Extended Flags Definition 00569 * @{ 00570 */ 00571 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready (ADRDY) flag */ 00572 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 00573 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 00574 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 00575 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 00576 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 00577 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 00578 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 00579 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 00580 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 00581 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 00582 00583 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00584 00585 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 00586 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ 00587 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ 00588 00589 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ 00590 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ 00591 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ 00592 ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ 00593 00594 /** 00595 * @} 00596 */ 00597 00598 00599 /** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank 00600 * @{ 00601 */ 00602 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /*!< ADC injected conversion rank 1 */ 00603 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /*!< ADC injected conversion rank 2 */ 00604 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /*!< ADC injected conversion rank 3 */ 00605 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /*!< ADC injected conversion rank 4 */ 00606 /** 00607 * @} 00608 */ 00609 00610 00611 00612 /** @defgroup ADCEx_Oversampling_Ratio ADC Extended Oversampling Ratio 00613 * @{ 00614 */ 00615 00616 #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC Oversampling ratio 2x */ 00617 #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /*!< ADC Oversampling ratio 4x */ 00618 #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /*!< ADC Oversampling ratio 8x */ 00619 #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 16x */ 00620 #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /*!< ADC Oversampling ratio 32x */ 00621 #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0)) /*!< ADC Oversampling ratio 64x */ 00622 #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1)) /*!< ADC Oversampling ratio 128x */ 00623 #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /*!< ADC Oversampling ratio 256x */ 00624 /** 00625 * @} 00626 */ 00627 00628 /** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift 00629 * @{ 00630 */ 00631 #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC No bit shift for oversampling */ 00632 #define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC 1 bit shift for oversampling */ 00633 #define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC 2 bits shift for oversampling */ 00634 #define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 3 bits shift for oversampling */ 00635 #define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC 4 bits shift for oversampling */ 00636 #define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0)) /*!< ADC 5 bits shift for oversampling */ 00637 #define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1)) /*!< ADC 6 bits shift for oversampling */ 00638 #define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0)) /*!< ADC 7 bits shift for oversampling */ 00639 #define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC 8 bits shift for oversampling */ 00640 /** 00641 * @} 00642 */ 00643 00644 /** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling 00645 * @{ 00646 */ 00647 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /*!< A single trigger for all channel oversampled conversions */ 00648 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /*!< A trigger for each oversampled conversion */ 00649 /** 00650 * @} 00651 */ 00652 00653 /** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode 00654 * @{ 00655 */ 00656 #define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /*!< Oversampling buffer maintained during injection sequence */ 00657 #define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during injection sequence */ 00658 /** 00659 * @} 00660 */ 00661 00662 /** @defgroup ADC_sampling_times ADC Sampling Times 00663 * @{ 00664 */ 00665 #define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000) /*!< Sampling time 2.5 ADC clock cycle */ 00666 #define ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */ 00667 #define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /*!< Sampling time 12.5 ADC clock cycles */ 00668 #define ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 24.5 ADC clock cycles */ 00669 #define ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /*!< Sampling time 47.5 ADC clock cycles */ 00670 #define ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0)) /*!< Sampling time 92.5 ADC clock cycles */ 00671 #define ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1)) /*!< Sampling time 247.5 ADC clock cycles */ 00672 #define ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /*!< Sampling time 640.5 ADC clock cycles */ 00673 /** 00674 * @} 00675 */ 00676 00677 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 00678 * @{ 00679 */ 00680 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 00681 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 00682 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 00683 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00684 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 00685 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 00686 /** 00687 * @} 00688 */ 00689 00690 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 00691 * @{ 00692 */ 00693 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 00694 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 00695 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 00696 ADC_SMPR1_SMP0) 00697 /** 00698 * @} 00699 */ 00700 00701 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 00702 * @{ 00703 */ 00704 /* ADC_CFGR fields of parameters that can be updated when no conversion 00705 (neither regular nor injected) is on-going */ 00706 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 00707 /** 00708 * @} 00709 */ 00710 00711 /** 00712 * @} 00713 */ 00714 00715 00716 00717 /* Private macros -----------------------------------------------------------*/ 00718 00719 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 00720 * @{ 00721 */ 00722 00723 /** 00724 * @brief Test if conversion trigger of injected group is software start 00725 * or external trigger. 00726 * @param __HANDLE__: ADC handle. 00727 * @retval SET (software start) or RESET (external trigger). 00728 */ 00729 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 00730 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET) 00731 00732 /** 00733 * @brief Check if conversion is on going on regular or injected groups. 00734 * @param __HANDLE__: ADC handle. 00735 * @retval SET (conversion is on going) or RESET (no conversion is on going). 00736 */ 00737 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 00738 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == RESET \ 00739 ) ? RESET : SET) 00740 00741 00742 /** 00743 * @brief Check if conversion is on going on injected group. 00744 * @param __HANDLE__: ADC handle. 00745 * @retval SET (conversion is on going) or RESET (no conversion is on going). 00746 */ 00747 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 00748 (( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \ 00749 ) ? RESET : SET) 00750 00751 00752 00753 /** 00754 * @brief Check whether or not ADC is independent. 00755 * @param __HANDLE__: ADC handle. 00756 * @note When multimode feature is not available, the macro always returns SET. 00757 * @retval SET (ADC is independent) or RESET (ADC is not). 00758 */ 00759 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00760 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 00761 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 00762 )? \ 00763 SET \ 00764 : \ 00765 RESET \ 00766 ) 00767 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 00768 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 00769 #endif 00770 00771 00772 /** 00773 * @brief Set the sample time for Channels numbers between 0 and 9. 00774 * @param __SAMPLETIME__: Sample time parameter. 00775 * @param __CHANNELNB__: Channel number. 00776 * @retval None 00777 */ 00778 #define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__))) 00779 00780 /** 00781 * @brief Set the sample time for Channels numbers between 10 and 18. 00782 * @param __SAMPLETIME__: Sample time parameter. 00783 * @param __CHANNELNB__: Channel number. 00784 * @retval None 00785 */ 00786 #define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10)))) 00787 00788 /** 00789 * @brief Write SMPR1 register. 00790 * @param __HANDLE__ : ADC handle. 00791 * @param __SAMPLETIME__: Sample time parameter. 00792 * @param __CHANNELNB__ : Channel number. 00793 * @retval None 00794 */ 00795 #define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ 00796 MODIFY_REG((__HANDLE__)->Instance->SMPR1, \ 00797 ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \ 00798 ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__))) 00799 00800 /** 00801 * @brief Write SMPR2 register. 00802 * @param __HANDLE__ : ADC handle. 00803 * @param __SAMPLETIME__: Sample time parameter. 00804 * @param __CHANNELNB__ : Channel number. 00805 * @retval None 00806 */ 00807 #define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \ 00808 MODIFY_REG((__HANDLE__)->Instance->SMPR2, \ 00809 ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \ 00810 ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__))) 00811 00812 00813 /** 00814 * @brief Set the selected regular Channel rank for rank between 1 and 4. 00815 * @param __CHANNELNB__: Channel number. 00816 * @param __RANKNB__: Rank number. 00817 * @retval None 00818 */ 00819 #define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__))) 00820 00821 /** 00822 * @brief Set the selected regular Channel rank for rank between 5 and 9. 00823 * @param __CHANNELNB__: Channel number. 00824 * @param __RANKNB__: Rank number. 00825 * @retval None 00826 */ 00827 #define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5))) 00828 00829 /** 00830 * @brief Set the selected regular Channel rank for rank between 10 and 14. 00831 * @param __CHANNELNB__: Channel number. 00832 * @param __RANKNB__: Rank number. 00833 * @retval None 00834 */ 00835 #define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10))) 00836 00837 /** 00838 * @brief Set the selected regular Channel rank for rank between 15 and 16. 00839 * @param __CHANNELNB__: Channel number. 00840 * @param __RANKNB__: Rank number. 00841 * @retval None 00842 */ 00843 #define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15))) 00844 00845 /** 00846 * @brief Set the selected injected Channel rank. 00847 * @param __CHANNELNB__: Channel number. 00848 * @param __RANKNB__: Rank number. 00849 * @retval None 00850 */ 00851 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2)) 00852 00853 00854 /** 00855 * @brief Set the Analog Watchdog 1 channel. 00856 * @param __CHANNEL__: channel to be monitored by Analog Watchdog 1. 00857 * @retval None 00858 */ 00859 #define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH)) 00860 00861 /** 00862 * @brief Configure the channel number in Analog Watchdog 2 or 3. 00863 * @param __CHANNEL__: ADC Channel 00864 * @retval None 00865 */ 00866 #define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__)) 00867 00868 /** 00869 * @brief Configure ADC injected context queue 00870 * @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode. 00871 * @retval None 00872 */ 00873 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM)) 00874 00875 /** 00876 * @brief Configure ADC discontinuous conversion mode for injected group 00877 * @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode. 00878 * @retval None 00879 */ 00880 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN)) 00881 00882 /** 00883 * @brief Configure ADC discontinuous conversion mode for regular group 00884 * @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode. 00885 * @retval None 00886 */ 00887 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN)) 00888 /** 00889 * @brief Configure the number of discontinuous conversions for regular group. 00890 * @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions. 00891 * @retval None 00892 */ 00893 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM)) 00894 00895 /** 00896 * @brief Configure the ADC auto delay mode. 00897 * @param __AUTOWAIT__: Auto delay bit enable or disable. 00898 * @retval None 00899 */ 00900 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY)) 00901 00902 /** 00903 * @brief Configure ADC continuous conversion mode. 00904 * @param __CONTINUOUS_MODE__: Continuous mode. 00905 * @retval None 00906 */ 00907 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT)) 00908 00909 /** 00910 * @brief Configure the ADC DMA continuous request. 00911 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 00912 * @retval None 00913 */ 00914 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG)) 00915 00916 00917 /** 00918 * @brief Configure the channel number into offset OFRx register. 00919 * @param __CHANNEL__: ADC Channel. 00920 * @retval None 00921 */ 00922 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH)) 00923 00924 /** 00925 * @brief Configure the channel number into differential mode selection register. 00926 * @param __CHANNEL__: ADC Channel. 00927 * @retval None 00928 */ 00929 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__)) 00930 00931 /** 00932 * @brief Configure calibration factor in differential mode to be set into calibration register. 00933 * @param __CALIBRATION_FACTOR__: Calibration factor value. 00934 * @retval None 00935 */ 00936 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D)) 00937 /** 00938 * @brief Calibration factor in differential mode to be retrieved from calibration register. 00939 * @param __CALIBRATION_FACTOR__: Calibration factor value. 00940 * @retval None 00941 */ 00942 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) 00943 00944 /** 00945 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 00946 * @param __THRESHOLD__: Threshold value. 00947 * @retval None 00948 */ 00949 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16) 00950 00951 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00952 /** 00953 * @brief Configure the ADC DMA continuous request for ADC multimode. 00954 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 00955 * @retval None 00956 */ 00957 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG)) 00958 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00959 00960 /** 00961 * @brief Enable the ADC peripheral. 00962 * @param __HANDLE__: ADC handle. 00963 * @retval None 00964 */ 00965 #define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) 00966 00967 /** 00968 * @brief Verification of hardware constraints before ADC can be enabled. 00969 * @param __HANDLE__: ADC handle. 00970 * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) 00971 */ 00972 #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ 00973 (( ( ((__HANDLE__)->Instance->CR) & \ 00974 (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | \ 00975 ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN ) \ 00976 ) == RESET \ 00977 ) ? SET : RESET) 00978 00979 /** 00980 * @brief Disable the ADC peripheral. 00981 * @param __HANDLE__: ADC handle. 00982 * @retval None 00983 */ 00984 #define ADC_DISABLE(__HANDLE__) \ 00985 do{ \ 00986 (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ 00987 __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ 00988 } while(0) 00989 00990 /** 00991 * @brief Verification of hardware constraints before ADC can be disabled. 00992 * @param __HANDLE__: ADC handle. 00993 * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) 00994 */ 00995 #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ 00996 (( ( ((__HANDLE__)->Instance->CR) & \ 00997 (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ 00998 ) ? SET : RESET) 00999 01000 01001 /** 01002 * @brief Shift the offset with respect to the selected ADC resolution. 01003 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 01004 * If resolution 12 bits, no shift. 01005 * If resolution 10 bits, shift of 2 ranks on the left. 01006 * If resolution 8 bits, shift of 4 ranks on the left. 01007 * If resolution 6 bits, shift of 6 ranks on the left. 01008 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 01009 * @param __HANDLE__: ADC handle 01010 * @param __OFFSET__: Value to be shifted 01011 * @retval None 01012 */ 01013 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 01014 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) 01015 01016 01017 /** 01018 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 01019 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 01020 * If resolution 12 bits, no shift. 01021 * If resolution 10 bits, shift of 2 ranks on the left. 01022 * If resolution 8 bits, shift of 4 ranks on the left. 01023 * If resolution 6 bits, shift of 6 ranks on the left. 01024 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 01025 * @param __HANDLE__: ADC handle 01026 * @param __THRESHOLD__: Value to be shifted 01027 * @retval None 01028 */ 01029 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 01030 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2)) 01031 01032 /** 01033 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 01034 * @note Thresholds have to be left-aligned on bit 7. 01035 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 01036 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 01037 * If resolution 8 bits, no shift. 01038 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 01039 * @param __HANDLE__: ADC handle 01040 * @param __THRESHOLD__: Value to be shifted 01041 * @retval None 01042 */ 01043 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 01044 ( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) ? \ 01045 ((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \ 01046 (__THRESHOLD__) << 2 ) 01047 01048 01049 /** 01050 * @brief Report ADC common register. 01051 * @param __HANDLE__: ADC handle. 01052 * @retval Common control register 01053 */ 01054 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01055 #define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON) 01056 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01057 #define ADC_COMMON_REGISTER(__HANDLE__) (ADC1_COMMON) 01058 #endif 01059 01060 /** 01061 * @brief Report Master Instance. 01062 * @param __HANDLE__: ADC handle. 01063 * @note Return same instance if ADC of input handle is independent ADC or if 01064 * multimode feature is not available. 01065 * @retval Master Instance 01066 */ 01067 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01068 #define ADC_MASTER_REGISTER(__HANDLE__) \ 01069 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ 01070 )? \ 01071 ((__HANDLE__)->Instance) \ 01072 : \ 01073 (ADC1) \ 01074 ) 01075 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01076 #define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance) 01077 #endif 01078 01079 01080 /** 01081 * @brief Clear Common Control Register. 01082 * @param __HANDLE__: ADC handle. 01083 * @retval None 01084 */ 01085 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01086 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \ 01087 ADC_CCR_PRESC | \ 01088 ADC_CCR_VBATEN | \ 01089 ADC_CCR_TSEN | \ 01090 ADC_CCR_VREFEN | \ 01091 ADC_CCR_MDMA | \ 01092 ADC_CCR_DMACFG | \ 01093 ADC_CCR_DELAY | \ 01094 ADC_CCR_DUAL ) 01095 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01096 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE | \ 01097 ADC_CCR_PRESC | \ 01098 ADC_CCR_VBATEN | \ 01099 ADC_CCR_TSEN | \ 01100 ADC_CCR_VREFEN ) 01101 #endif 01102 01103 01104 /** 01105 * @brief Check whether or not dual conversions are enabled. 01106 * @param __HANDLE__: ADC handle. 01107 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. 01108 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 01109 */ 01110 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01111 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \ 01112 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 01113 )? \ 01114 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \ 01115 : \ 01116 RESET \ 01117 ) 01118 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01119 #define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET) 01120 #endif 01121 01122 /** 01123 * @brief Check whether or not dual regular conversions are enabled. 01124 * @param __HANDLE__: ADC handle. 01125 * @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available. 01126 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 01127 */ 01128 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01129 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 01130 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 01131 )? \ 01132 ( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 01133 (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 01134 (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 01135 : \ 01136 RESET \ 01137 ) 01138 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01139 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET) 01140 #endif 01141 01142 01143 /** 01144 * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master. 01145 * @param __HANDLE__: ADC handle. 01146 * @note Return SET if multimode feature is not available. 01147 * @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode) 01148 */ 01149 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01150 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 01151 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 01152 )? \ 01153 SET \ 01154 : \ 01155 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 01156 ) 01157 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01158 #define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET) 01159 #endif 01160 01161 /** 01162 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled. 01163 * @param __HANDLE__: ADC handle. 01164 * @note Return SET if multimode feature is not available. 01165 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 01166 */ 01167 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01168 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 01169 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 01170 )? \ 01171 SET \ 01172 : \ 01173 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 01174 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 01175 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 01176 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01177 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET) 01178 #endif 01179 01180 /** 01181 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled. 01182 * @param __HANDLE__: ADC handle. 01183 * @note Return SET if multimode feature is not available. 01184 * @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 01185 */ 01186 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01187 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 01188 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 01189 )? \ 01190 SET \ 01191 : \ 01192 ( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 01193 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 01194 ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 01195 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01196 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET) 01197 #endif 01198 01199 /** 01200 * @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter. 01201 * @param __INSTANCE__: ADC instance. 01202 * @retval SET (ADC enabled) or RESET (ADC disabled) 01203 */ 01204 #define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \ 01205 (( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 01206 ((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 01207 ) ? SET : RESET) 01208 01209 /** 01210 * @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle. 01211 * @param __HANDLE__: ADC handle. 01212 * @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled) 01213 */ 01214 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01215 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) \ 01216 ( ( ((__HANDLE__)->Instance == ADC1) \ 01217 )? \ 01218 (ADC_INSTANCE_IS_ENABLED(ADC2)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ 01219 : \ 01220 ( ( ((__HANDLE__)->Instance == ADC2) \ 01221 )? \ 01222 (ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC3)) \ 01223 : \ 01224 ADC_INSTANCE_IS_ENABLED(ADC1)) || (ADC_INSTANCE_IS_ENABLED(ADC2)) \ 01225 ) 01226 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01227 #define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET) 01228 #endif 01229 01230 01231 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01232 /** 01233 * @brief Set handle instance of the ADC slave associated to the ADC master. 01234 * @param __HANDLE_MASTER__: ADC master handle. 01235 * @param __HANDLE_SLAVE__: ADC slave handle. 01236 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL. 01237 * @retval None 01238 */ 01239 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 01240 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 01241 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01242 01243 01244 /** 01245 * @brief Check whether or not multimode is configured in DMA mode. 01246 * @note Return RESET if multimode feature is not available. 01247 * @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled) 01248 */ 01249 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01250 #define ADC_MULTIMODE_DMA_ENABLED() \ 01251 ((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \ 01252 || (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS)) 01253 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01254 #define ADC_MULTIMODE_DMA_ENABLED() (RESET) 01255 #endif 01256 01257 01258 /** 01259 * @brief Verify the ADC instance connected to the temperature sensor. 01260 * @param __HANDLE__: ADC handle. 01261 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 01262 */ 01263 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01264 /* The temperature sensor measurement path (channel 17) is available on ADC1 */ 01265 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 01266 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01267 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ 01268 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 01269 #endif 01270 01271 /** 01272 * @brief Verify the ADC instance connected to the battery voltage VBAT. 01273 * @param __HANDLE__: ADC handle. 01274 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 01275 */ 01276 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01277 /* The battery voltage measurement path (channel 18) is available on ADC1 */ 01278 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 01279 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01280 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ 01281 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) 01282 #endif 01283 01284 /** 01285 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 01286 * @param __HANDLE__: ADC handle. 01287 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 01288 */ 01289 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ 01290 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 01291 01292 01293 /** 01294 * @brief Verify the length of scheduled injected conversions group. 01295 * @param __LENGTH__: number of programmed conversions. 01296 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 01297 */ 01298 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) 01299 01300 01301 /** 01302 * @brief Calibration factor size verification (7 bits maximum). 01303 * @param __CALIBRATION_FACTOR__: Calibration factor value. 01304 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 01305 */ 01306 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F)) 01307 01308 01309 /** 01310 * @brief Verify the ADC channel setting. 01311 * @param __HANDLE__: ADC handle. 01312 * @param __CHANNEL__: programmed ADC channel. 01313 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01314 */ 01315 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01316 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 01317 (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 01318 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 01319 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01320 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01321 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01322 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01323 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01324 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01325 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01326 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01327 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01328 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01329 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01330 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01331 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01332 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 01333 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 01334 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 01335 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 01336 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 01337 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) 01338 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01339 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 01340 (((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 01341 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 01342 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01343 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01344 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01345 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01346 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01347 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01348 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01349 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01350 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01351 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01352 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01353 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01354 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01355 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 01356 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 01357 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 01358 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 01359 ((((__HANDLE__)->Instance) == ADC2) && \ 01360 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01361 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01362 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01363 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01364 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01365 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01366 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01367 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01368 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01369 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01370 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01371 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01372 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01373 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01374 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 01375 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 01376 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 01377 ((__CHANNEL__) == ADC_CHANNEL_18))) || \ 01378 ((((__HANDLE__)->Instance) == ADC3) && \ 01379 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01380 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01381 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01382 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01383 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01384 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01385 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01386 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01387 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01388 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01389 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01390 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01391 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01392 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 01393 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 01394 ((__CHANNEL__) == ADC_CHANNEL_VBAT) ))) 01395 #endif 01396 01397 /** 01398 * @brief Verify the ADC channel setting in differential mode. 01399 * @param __HANDLE__: ADC handle. 01400 * @param __CHANNEL__: programmed ADC channel. 01401 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01402 */ 01403 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 01404 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01405 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01406 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01407 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01408 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01409 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01410 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01411 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01412 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01413 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01414 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01415 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01416 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01417 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01418 ((__CHANNEL__) == ADC_CHANNEL_15) ) 01419 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01420 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 01421 channels 0, 16 to 18 can be only used in single-ended mode. 01422 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, 01423 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ 01424 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ 01425 (((__HANDLE__)->Instance) == ADC2)) && \ 01426 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01427 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01428 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01429 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 01430 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01431 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01432 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01433 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01434 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01435 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01436 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01437 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 01438 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01439 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01440 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 01441 ((((__HANDLE__)->Instance) == ADC3) && \ 01442 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 01443 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 01444 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 01445 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 01446 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 01447 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 01448 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 01449 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01450 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01451 ((__CHANNEL__) == ADC_CHANNEL_12) ))) 01452 #endif 01453 01454 /** 01455 * @brief Verify the ADC single-ended input or differential mode setting. 01456 * @param __SING_DIFF__: programmed channel setting. 01457 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 01458 */ 01459 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 01460 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 01461 01462 /** 01463 * @brief Verify the ADC offset management setting. 01464 * @param __OFFSET_NUMBER__: ADC offset management. 01465 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 01466 */ 01467 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 01468 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 01469 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 01470 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 01471 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 01472 01473 /** 01474 * @brief Verify the ADC regular channel setting. 01475 * @param __CHANNEL__: programmed ADC regular channel. 01476 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01477 */ 01478 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 01479 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 01480 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 01481 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 01482 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 01483 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 01484 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 01485 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 01486 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 01487 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 01488 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 01489 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 01490 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 01491 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 01492 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 01493 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 01494 01495 01496 /** 01497 * @brief Verify the ADC injected channel setting. 01498 * @param __CHANNEL__: programmed ADC injected channel. 01499 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01500 */ 01501 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 01502 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 01503 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 01504 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 01505 01506 /** 01507 * @brief Verify the ADC edge trigger setting for injected group. 01508 * @param __EDGE__: programmed ADC edge trigger setting. 01509 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 01510 */ 01511 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 01512 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 01513 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 01514 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 01515 01516 01517 /** 01518 * @brief Verify the ADC injected conversions external trigger. 01519 * @param __INJTRIG__: programmed ADC injected conversions external trigger. 01520 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 01521 */ 01522 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 01523 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 01524 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 01525 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 01526 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 01527 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 01528 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 01529 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 01530 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 01531 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 01532 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 01533 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 01534 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 01535 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 01536 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 01537 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 01538 \ 01539 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 01540 01541 01542 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01543 /** 01544 * @brief Verify the ADC multimode setting. 01545 * @param __MODE__: programmed ADC multimode setting. 01546 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01547 */ 01548 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 01549 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 01550 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 01551 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 01552 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 01553 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 01554 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 01555 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 01556 01557 /** 01558 * @brief Verify the ADC multimode DMA access setting. 01559 * @param __MODE__: programmed ADC multimode DMA access setting. 01560 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01561 */ 01562 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 01563 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 01564 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 01565 01566 /** 01567 * @brief Verify the ADC multimode delay setting. 01568 * @param __DELAY__: programmed ADC multimode delay setting. 01569 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 01570 */ 01571 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 01572 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 01573 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 01574 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 01575 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 01576 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 01577 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 01578 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 01579 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 01580 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 01581 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 01582 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 01583 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01584 01585 /** 01586 * @brief Verify the ADC analog watchdog setting. 01587 * @param __WATCHDOG__: programmed ADC analog watchdog setting. 01588 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 01589 */ 01590 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 01591 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 01592 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 01593 01594 /** 01595 * @brief Verify the ADC analog watchdog mode setting. 01596 * @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting. 01597 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 01598 */ 01599 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 01600 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 01601 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 01602 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 01603 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 01604 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 01605 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 01606 01607 /** 01608 * @brief Verify the ADC conversion (regular or injected or both). 01609 * @param __CONVERSION__: ADC conversion group. 01610 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 01611 */ 01612 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 01613 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 01614 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 01615 01616 /** 01617 * @brief Verify the ADC event type. 01618 * @param __EVENT__: ADC event. 01619 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 01620 */ 01621 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 01622 ((__EVENT__) == ADC_AWD_EVENT) || \ 01623 ((__EVENT__) == ADC_AWD2_EVENT) || \ 01624 ((__EVENT__) == ADC_AWD3_EVENT) || \ 01625 ((__EVENT__) == ADC_OVR_EVENT) || \ 01626 ((__EVENT__) == ADC_JQOVF_EVENT) ) 01627 01628 /** 01629 * @brief Verify the ADC oversampling ratio. 01630 * @param __RATIO__: programmed ADC oversampling ratio. 01631 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 01632 */ 01633 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 01634 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 01635 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 01636 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 01637 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 01638 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 01639 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 01640 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 01641 01642 /** 01643 * @brief Verify the ADC oversampling shift. 01644 * @param __SHIFT__: programmed ADC oversampling shift. 01645 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 01646 */ 01647 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 01648 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 01649 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 01650 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 01651 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 01652 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 01653 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 01654 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 01655 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 01656 01657 /** 01658 * @brief Verify the ADC oversampling triggered mode. 01659 * @param __MODE__: programmed ADC oversampling triggered mode. 01660 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01661 */ 01662 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 01663 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 01664 01665 /** 01666 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 01667 * @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode. 01668 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01669 */ 01670 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 01671 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 01672 01673 01674 /** 01675 * @brief Verify the DFSDM mode configuration. 01676 * @param __HANDLE__: ADC handle. 01677 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 01678 * this reason, the input parameter is the ADC handle and not the configuration parameter 01679 * directly. 01680 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 01681 */ 01682 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 01683 01684 /** 01685 * @brief Return the DFSDM configuration mode. 01686 * @param __HANDLE__: ADC handle. 01687 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 01688 * For this reason, the input parameter is the ADC handle and not the configuration parameter 01689 * directly. 01690 * @retval DFSDM configuration mode 01691 */ 01692 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0) 01693 01694 01695 /** 01696 * @} 01697 */ 01698 01699 01700 /* Exported functions --------------------------------------------------------*/ 01701 /** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions 01702 * @{ 01703 */ 01704 01705 /* Initialization/de-initialization functions *********************************/ 01706 01707 /** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions 01708 * @brief Extended IO operation functions 01709 * @{ 01710 */ 01711 /* I/O operation functions ****************************************************/ 01712 01713 /* ADC calibration */ 01714 01715 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); 01716 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 01717 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 01718 01719 01720 01721 /* Blocking mode: Polling */ 01722 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); 01723 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); 01724 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 01725 01726 /* Non-blocking mode: Interruption */ 01727 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); 01728 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); 01729 01730 01731 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01732 /* ADC multimode */ 01733 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 01734 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 01735 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 01736 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01737 01738 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01739 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); 01740 01741 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 01742 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); 01743 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); 01744 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); 01745 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); 01746 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); 01747 01748 01749 /* ADC Regular conversions stop */ 01750 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); 01751 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); 01752 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); 01753 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01754 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc); 01755 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01756 01757 /** 01758 * @} 01759 */ 01760 01761 /** @addtogroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions 01762 * @brief Extended Peripheral Control functions 01763 * @{ 01764 */ 01765 /* Peripheral Control functions ***********************************************/ 01766 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); 01767 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 01768 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 01769 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 01770 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); 01771 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); 01772 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); 01773 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); 01774 01775 /** 01776 * @} 01777 */ 01778 01779 /** 01780 * @} 01781 */ 01782 01783 /** 01784 * @} 01785 */ 01786 01787 /** 01788 * @} 01789 */ 01790 01791 #ifdef __cplusplus 01792 } 01793 #endif 01794 01795 #endif /*__STM32L4xx_ADC_EX_H */ 01796 01797 01798 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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