stm32l4xx_hal_adc_ex.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_adc_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Calibration functions
00011   *             ++ Calibration start-up
00012   *             ++ Calibration value reading or setting 
00013   *           + Operation functions
00014   *             ++ Start, stop, get result of conversions of injected
00015   *             groups, using 3 possible modes: polling or interruption.
00016   *             ++ Multimode feature when available
00017   *           + Control functions
00018   *             ++ Configure channels on injected group
00019   *           + State functions
00020   *             ++ Injected group queues management
00021   *  
00022    @verbatim           
00023   ==============================================================================
00024                     ##### ADC specific features #####
00025   ==============================================================================
00026   [..] 
00027   (#) Interrupt generation at the end of injected conversion and in case of 
00028       injected queues overflow.
00029   
00030   (#) External trigger (timer or EXTI) with configurable polarity for  
00031       injected groups.
00032 
00033   (#) Multimode Dual mode when multimode feature is available.
00034   
00035   (#) Configurable DMA data storage in Multimode Dual mode.
00036   
00037   (#) Configurable delay between conversions in Dual interleaved mode.
00038   
00039   (#) ADC calibration.
00040 
00041   (#) ADC channels selectable single/differential input.
00042 
00043   (#) ADC Injected sequencer&channels configuration context queue.
00044 
00045   (#) ADC offset on injected groups.
00046   
00047   (#) ADC oversampling.
00048 
00049 
00050                      ##### How to use this driver #####
00051   ==============================================================================
00052     [..]
00053   
00054      (#) Configure the ADC parameters (conversion resolution, data alignment,  
00055          continuous mode, ...) using the HAL_ADC_Init() function.
00056 
00057      (#) Activate the ADC peripheral using one of the start functions: 
00058          HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() for injected conversions
00059          or 
00060          HAL_ADC_MultiModeStart_DMA() for multimode conversions when multimode
00061          feature is available.
00062   
00063   
00064      *** Channels to injected group configuration ***
00065      =============================================    
00066      [..]
00067        (+) To configure the ADC Injected channels group features, use 
00068            HAL_ADCEx_InjectedConfigChannel() functions.
00069        (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() 
00070            function.  
00071             
00072             
00073      *** Multimode ADCs configuration (when  multimode feature is available) ***
00074      ========================================================================
00075      [..]
00076        (+) Multimode feature is available and applicable to Master and
00077            Slave ADCs.
00078        (+) Refer to "Channels to regular group configuration" description to  
00079            configure the Master and Slave regular groups.        
00080        (+) Select the Multi mode ADC  features (dual mode
00081            simultaneous, interleaved, ...) and configure the DMA mode using 
00082            HAL_ADCEx_MultiModeConfigChannel() functions. 
00083        (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue()
00084            function.
00085 
00086   
00087     @endverbatim
00088   ******************************************************************************
00089   * @attention
00090   *
00091   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00092   *
00093   * Redistribution and use in source and binary forms, with or without modification,
00094   * are permitted provided that the following conditions are met:
00095   *   1. Redistributions of source code must retain the above copyright notice,
00096   *      this list of conditions and the following disclaimer.
00097   *   2. Redistributions in binary form must reproduce the above copyright notice,
00098   *      this list of conditions and the following disclaimer in the documentation
00099   *      and/or other materials provided with the distribution.
00100   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00101   *      may be used to endorse or promote products derived from this software
00102   *      without specific prior written permission.
00103   *
00104   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00105   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00106   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00107   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00108   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00109   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00110   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00111   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00112   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00113   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00114   *
00115   ******************************************************************************  
00116   */
00117 
00118 /* Includes ------------------------------------------------------------------*/
00119 #include "stm32l4xx_hal.h"
00120 
00121 /** @addtogroup STM32L4xx_HAL_Driver
00122   * @{
00123   */
00124 
00125 /** @defgroup ADCEx ADCEx
00126   * @brief ADC Extended HAL module driver
00127   * @{
00128   */
00129 
00130 #ifdef HAL_ADC_MODULE_ENABLED
00131     
00132 /* Private typedef -----------------------------------------------------------*/
00133 /* Private define ------------------------------------------------------------*/
00134 
00135 /** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
00136   * @{
00137   */
00138 
00139 #define ADC_JSQR_FIELDS  ((uint32_t)(ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
00140                                      ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
00141                                       ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
00142                                                                              once the ADC is enabled */
00143                                       
00144 #define ADC_CFGR2_INJ_FIELDS  ((uint32_t)(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR  |\
00145                                        ADC_CFGR2_OVSS ))     /*!< ADC_CFGR2 injected oversampling parameters that can be updated
00146                                                                   when no conversion is on-going (neither regular nor injected) */
00147                                        
00148 /* Fixed timeout value for ADC calibration.                                   */
00149 /* Values defined to be higher than worst cases: low clock frequency,         */
00150 /* maximum prescalers.                                                        */
00151 /* Ex of profile low frequency : f_ADC at 0.14 MHz (minimum value             */
00152 /* according to Data sheet), calibration_time MAX = 112 / f_ADC               */
00153 /*           112 / 140,000 = 0.8 ms                                           */
00154 /* At maximum CPU speed (80 MHz), this means                                  */
00155 /*    0.8 ms * 80 MHz = 64000 CPU cycles                                      */  
00156 #define ADC_CALIBRATION_TIMEOUT         ((uint32_t) 64000)    /*!< ADC calibration time-out value */ 
00157                                     
00158 /**
00159   * @}
00160   */
00161 
00162 /* Private macro -------------------------------------------------------------*/
00163 /* Private variables ---------------------------------------------------------*/
00164 /* Private function prototypes -----------------------------------------------*/
00165 /* Exported functions --------------------------------------------------------*/
00166 
00167 /** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
00168   * @{
00169   */ 
00170 
00171 
00172 
00173 /** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
00174   * @brief    Extended IO operation functions
00175   *
00176 @verbatim   
00177  ===============================================================================
00178              ##### IO operation functions #####
00179  ===============================================================================  
00180     [..]  This section provides functions allowing to:
00181     
00182       (+) Perform the ADC self-calibration for single or differential ending.
00183       (+) Get calibration factors for single or differential ending.
00184       (+) Set calibration factors for single or differential ending.
00185           
00186       (+) Start conversion of injected group.
00187       (+) Stop conversion of injected group.
00188       (+) Poll for conversion complete on injected group.
00189       (+) Get result of injected channel conversion.
00190       (+) Start conversion of injected group and enable interruptions.
00191       (+) Stop conversion of injected group and disable interruptions.
00192 
00193       (+) When multimode feature is available, start multimode and enable DMA transfer.
00194       (+) Stop multimode and disable ADC DMA transfer.
00195       (+) Get result of multimode conversion.
00196 
00197 
00198 
00199 @endverbatim
00200   * @{
00201   */
00202   
00203 
00204 
00205 /**
00206   * @brief  Perform an ADC automatic self-calibration
00207   *         Calibration prerequisite: ADC must be disabled (execute this
00208   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
00209   * @param  hadc: ADC handle.
00210   * @param  SingleDiff: Selection of single-ended or differential input
00211   *          This parameter can be one of the following values:
00212   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00213   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00214   * @retval HAL status
00215   */
00216 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
00217 {
00218   HAL_StatusTypeDef tmp_status = HAL_OK;
00219   uint32_t WaitLoopIndex = 0;
00220   
00221   /* Check the parameters */
00222   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00223   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
00224 
00225   /* Process locked */
00226   __HAL_LOCK(hadc);
00227    
00228   /* Calibration prerequisite: ADC must be disabled. */
00229    
00230   /* Disable the ADC (if not already disabled) */
00231   tmp_status = ADC_Disable(hadc);
00232   
00233   /* Check if ADC is effectively disabled */
00234   if (tmp_status == HAL_OK)
00235   {
00236     /* Change ADC state */
00237     /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_BUSY_INTERNAL bit */
00238     ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_BUSY_INTERNAL);
00239     
00240     /* Select calibration mode single ended or differential ended */
00241     MODIFY_REG(hadc->Instance->CR, ADC_CR_ADCALDIF, SingleDiff);
00242 
00243     /* Start ADC calibration */
00244     SET_BIT(hadc->Instance->CR, ADC_CR_ADCAL);
00245 
00246 
00247     /* Wait for calibration completion */
00248     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADCAL))
00249     {
00250       WaitLoopIndex++;
00251       if (WaitLoopIndex >= ADC_CALIBRATION_TIMEOUT)
00252       {
00253         /* Update ADC state machine to error */
00254         /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_ERROR_INTERNAL bit */
00255         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_ERROR_INTERNAL);
00256         
00257         /* Process unlocked */
00258         __HAL_UNLOCK(hadc);
00259         
00260         return HAL_ERROR;
00261       }
00262     }
00263     
00264     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00265     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00266   }
00267   else
00268   {
00269     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00270     
00271     /* Update ADC state machine to error */
00272     tmp_status = HAL_ERROR; 
00273   }
00274   
00275   
00276   /* Process unlocked */
00277   __HAL_UNLOCK(hadc);
00278   
00279   /* Return function status */
00280   return tmp_status;
00281 }
00282 
00283 
00284 
00285 
00286 /**
00287   * @brief  Get the calibration factor from automatic conversion result.
00288   * @param  hadc: ADC handle.
00289   * @param  SingleDiff: Selection of single-ended or differential input
00290   *          This parameter can be one of the following values:
00291   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00292   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00293   * @retval Converted value
00294   */
00295 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
00296 {
00297   /* Check the parameters */
00298   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00299   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
00300   
00301   /* Return the selected ADC calibration value */ 
00302   if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
00303   {
00304     return ADC_CALFACT_DIFF_GET(hadc->Instance->CALFACT);
00305   }
00306   else
00307   {
00308     return ((hadc->Instance->CALFACT) & ADC_CALFACT_CALFACT_S);
00309   }
00310 }
00311 
00312 
00313 
00314 /**
00315   * @brief  Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
00316   * @param  hadc: ADC handle.
00317   * @param  SingleDiff: Selection of single-ended or differential input.
00318   *          This parameter can be one of the following values:
00319   *            @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
00320   *            @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
00321   * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
00322   * @retval HAL state
00323   */
00324 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
00325 {
00326   HAL_StatusTypeDef tmp_status = HAL_OK;
00327   
00328   /* Check the parameters */
00329   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00330   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff)); 
00331   assert_param(IS_ADC_CALFACT(CalibrationFactor)); 
00332   
00333   /* Process locked */
00334   __HAL_LOCK(hadc);
00335   
00336   /* Verification of hardware constraints before modifying the calibration    */
00337   /* factors register: ADC must be enabled, no conversion on going.           */
00338   if ( (ADC_IS_ENABLE(hadc) != RESET)                            &&
00339        (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)  )
00340   {
00341     /* Set the selected ADC calibration value */ 
00342     if (SingleDiff == ADC_DIFFERENTIAL_ENDED)
00343     {
00344       MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D, ADC_CALFACT_DIFF_SET(CalibrationFactor));
00345     }
00346     else
00347     {
00348       MODIFY_REG(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_S, CalibrationFactor);
00349     }
00350   }
00351   else
00352   {
00353     /* Update ADC state machine */
00354     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00355     
00356     /* Update ADC state machine to error */
00357     tmp_status = HAL_ERROR;
00358   }
00359   
00360   /* Process unlocked */
00361   __HAL_UNLOCK(hadc);
00362   
00363   /* Return function status */
00364   return tmp_status;
00365 }
00366 
00367 
00368 
00369 /**
00370   * @brief  Enable ADC, start conversion of injected group.
00371   * @note   Interruptions enabled in this function: None.
00372   * @note   Case of multimode enabled when multimode feature is available: 
00373   *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first, 
00374   *         then for ADC master. 
00375   *         For ADC slave, ADC is enabled only (conversion is not started).  
00376   *         For ADC master, ADC is enabled and multimode conversion is started.
00377   * @param  hadc: ADC handle.
00378   * @retval HAL status
00379   */
00380 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
00381 {
00382   HAL_StatusTypeDef tmp_status = HAL_OK;  
00383   
00384   /* Check the parameters */
00385   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00386   
00387   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
00388   {
00389     return HAL_BUSY;
00390   }
00391   else
00392   {
00393   
00394     /* In case of software trigger detection enabled, JQDIS must be set 
00395       (which can be done only if ADSTART and JADSTART are both cleared).
00396        If JQDIS is not set at that point, returns an error
00397        - since software trigger detection is disabled. User needs to
00398        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.  
00399        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 
00400          the queue is empty */
00401     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)   
00402     && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))  
00403     {
00404       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
00405       return HAL_ERROR;
00406     }
00407 
00408       
00409     /* Process locked */
00410     __HAL_LOCK(hadc);
00411       
00412     /* Enable the ADC peripheral */
00413     tmp_status = ADC_Enable(hadc);
00414     
00415     /* Start conversion if ADC is effectively enabled */
00416     if (tmp_status == HAL_OK)
00417     {
00418       /* Check if a regular conversion is ongoing */
00419       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY)) 
00420       {
00421         /* Reset ADC error code field related to injected conversions only */
00422         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);             
00423       }
00424       else
00425       {
00426         /* Set ADC error code to none */
00427         ADC_CLEAR_ERRORCODE(hadc);        
00428       }
00429       /* Update ADC state */
00430       /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
00431       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
00432       
00433       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00434         - by default if ADC is Master or Independent or if multimode feature is not available
00435         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
00436       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00437       {
00438         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00439       }      
00440 
00441       
00442       /* Clear injected group conversion flag */
00443       /* (To ensure of no unknown state from potential previous ADC operations) */
00444       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00445       
00446       /* Enable conversion of injected group, if automatic injected conversion  */
00447       /* is disabled.                                                           */
00448       /* If software start has been selected, conversion starts immediately.    */
00449       /* If external trigger has been selected, conversion will start at next   */
00450       /* trigger event.                                                         */
00451       /* Case of multimode enabled (when multimode feature is available):       */
00452       /* if ADC is slave,                                                       */
00453       /*    - ADC is enabled only (conversion is not started).                  */
00454       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00455       /*     and conversion is started.                                         */
00456       /* If ADC is master or independent,                                       */
00457       /*    - ADC is enabled and conversion is started.                         */
00458 
00459       /* Are injected conversions that of a dual Slave ? */      
00460       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
00461       {
00462         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00463            set ADSTART only if JAUTO is cleared */
00464         /* Process unlocked */
00465         __HAL_UNLOCK(hadc);            
00466         if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
00467         {
00468           SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
00469         }
00470       }
00471       else
00472       {
00473         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00474            ADSTART is not set */
00475           SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00476         /* Process unlocked */
00477         __HAL_UNLOCK(hadc);            
00478       }
00479     } 
00480     else
00481     {
00482       /* Process unlocked */
00483       __HAL_UNLOCK(hadc);    
00484     } /* if (tmp_status == HAL_OK) */
00485   
00486   
00487     /* Return function status */
00488     return tmp_status;
00489   } /*  if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc)) */
00490 }
00491 
00492 
00493 
00494 /**
00495   * @brief  Stop conversion of injected channels, disable ADC peripheral if no regular conversion is on going.
00496   * @note   If ADC must be disabled and if regular conversion
00497   *         is on going, function HAL_ADC_Stop() must be used.
00498   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00499   * @note   In case of multimode enabled (when multimode feature is available), 
00500   *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
00501   *         For ADC master, conversion is stopped and ADC is disabled. 
00502   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00503   *         has already stopped conversion of ADC slave).
00504   * @param  hadc: ADC handle.
00505   * @retval None
00506   */
00507 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
00508 {  
00509   HAL_StatusTypeDef tmp_status = HAL_OK;
00510   
00511   /* Check the parameters */
00512   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00513   
00514   /* Process locked */
00515   __HAL_LOCK(hadc);
00516   
00517   /* 1. Stop potential conversion on going on injected group only. */
00518   tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00519   
00520   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00521   /* and if no conversion on regular group is on-going                       */
00522   if (tmp_status == HAL_OK)
00523   {
00524     if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
00525     {
00526       /* 2. Disable the ADC peripheral */
00527       tmp_status = ADC_Disable(hadc);
00528       
00529       /* Check if ADC is effectively disabled */
00530       if (tmp_status == HAL_OK)
00531       {
00532         /* Change ADC state */
00533       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00534       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00535       }
00536     }
00537     /* Conversion on injected group is stopped, but ADC not disabled since    */
00538     /* conversion on regular group is still running.                          */
00539     else
00540     {
00541       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00542       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
00543     }
00544   }
00545   
00546   /* Process unlocked */
00547   __HAL_UNLOCK(hadc);
00548   
00549   /* Return function status */
00550   return tmp_status;
00551 }
00552 
00553 
00554 
00555 /**
00556   * @brief  Wait for injected group conversion to be completed.
00557   * @param  hadc: ADC handle
00558   * @param  Timeout: Timeout value in millisecond.
00559   * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is 
00560   *         checked and cleared depending on AUTDLY bit status.    
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00564 {
00565   uint32_t           tickstart;
00566   uint32_t           tmp_Flag_End        = 0x00;
00567   ADC_TypeDef        *tmpADC_Master;
00568   uint32_t           tmp_cfgr            = 0x00;
00569   uint32_t           tmp_cfgr_jqm_autdly = 0x00;   
00570   uint32_t           tmp_jeos_raised     = 0x01; /* by default, assume that JEOS is set, 
00571                                                     tmp_jeos_raised will be corrected
00572                                                     accordingly during API execution */       
00573  
00574   /* Check the parameters */
00575   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00576 
00577   /* If end of sequence selected */
00578   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00579   {
00580     tmp_Flag_End = ADC_FLAG_JEOS;
00581   }
00582   else /* end of conversion selected */
00583   {
00584     tmp_Flag_End = ADC_FLAG_JEOC;
00585   }
00586   
00587   /* Get timeout */
00588   tickstart = HAL_GetTick();  
00589      
00590    /* Wait until End of Conversion or Sequence flag is raised */
00591   while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
00592   {
00593     /* Check if timeout is disabled (set to infinite wait) */
00594     if(Timeout != HAL_MAX_DELAY)
00595     {
00596       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
00597       {
00598         /* Update ADC state machine to timeout */
00599         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
00600         
00601         /* Process unlocked */
00602         __HAL_UNLOCK(hadc);
00603         
00604         return HAL_TIMEOUT;
00605       }
00606     }
00607   }
00608   
00609   /* Next, to clear the polled flag as well as to update the handle State,
00610      JEOS is checked and the relevant configuration registers are retrieved. 
00611      JQM, JAUTO and CONT bits will have to be read for the State update,
00612      AUTDLY for JEOS clearing. */
00613   /*   1. Check whether or not JEOS is set */
00614   if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_JEOS))
00615   {
00616     tmp_jeos_raised = 0;   
00617   }
00618   /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
00619         injected conversions enabled. */
00620   if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc) == RESET)  
00621   {
00622     /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00623         check JQM and AUTDLY bits directly in ADC CFGR register */     
00624     tmp_cfgr_jqm_autdly = READ_REG(hadc->Instance->CFGR);  
00625   }
00626   else
00627   {
00628     /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00629         need to check JQM and AUTDLY bits of Master ADC CFGR register */    
00630     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00631     tmp_cfgr_jqm_autdly = READ_REG(tmpADC_Master->CFGR);
00632   }  
00633   /* 3. Check whether or not hadc is the handle of a Slave ADC with dual
00634         regular conversions enabled. */ 
00635   if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
00636   {
00637     /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
00638        check JAUTO and CONT bits directly in ADC CFGR register */        
00639     tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
00640   }
00641   else
00642   {
00643     /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
00644       check JAUTO and CONT bits of Master ADC CFGR register */  
00645     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
00646     tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
00647   }        
00648   
00649   
00650   
00651   /* Clear polled flag */                         
00652   if (tmp_Flag_End == ADC_FLAG_JEOS)
00653   {
00654     /* Clear end of sequence JEOS flag of injected group if low power feature */
00655     /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
00656     /* For injected groups, no new conversion will start before JEOS is       */
00657     /* cleared.                                                               */
00658     /* Note that 1. reading ADCx_JDRy clears JEOC.                            */ 
00659     /*           2. in multimode with dual injected conversions enabled (when */
00660     /*              multimode feature is available), Master AUTDLY bit is     */
00661     /*              checked.                                                  */        
00662     if (READ_BIT (tmp_cfgr_jqm_autdly, ADC_CFGR_AUTDLY) == RESET)
00663     {
00664       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
00665     }
00666   }
00667   else
00668   {
00669     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);    
00670   }  
00671   
00672   
00673   /* Update ADC state machine */
00674   SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 
00675   /* Are injected conversions over ? This is the case if JEOS is set AND
00676         - injected conversions are software-triggered when injected queue management is disabled
00677         OR
00678         - auto-injection is enabled, continuous mode is disabled,
00679           and regular conversions are software-triggered */
00680           
00681   if (tmp_jeos_raised)
00682   {  
00683     if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm_autdly, ADC_CFGR_JQM) != ADC_CFGR_JQM))  
00684        && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&    
00685            (ADC_IS_SOFTWARE_START_REGULAR(hadc)))    ))           
00686     {
00687       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00688       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
00689       /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */                   
00690       if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
00691       { 
00692         SET_BIT(hadc->State, HAL_ADC_STATE_READY); 
00693       }           
00694     }      
00695   }
00696 
00697 
00698     
00699   /* Return API HAL status */
00700   return HAL_OK;
00701 }
00702 
00703 
00704 
00705 /**
00706   * @brief  Enable ADC, start conversion of injected group with interruption.
00707   * @note   Interruptions enabled in this function according to initialization
00708   *         setting : JEOC (end of conversion) or JEOS (end of sequence) 
00709   * @note   Case of multimode enabled (when multimode feature is enabled): 
00710   *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first, 
00711   *         then for ADC master. 
00712   *         For ADC slave, ADC is enabled only (conversion is not started).  
00713   *         For ADC master, ADC is enabled and multimode conversion is started.
00714   * @param  hadc: ADC handle.
00715   * @retval HAL status.
00716   */
00717 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
00718 {
00719   HAL_StatusTypeDef tmp_status = HAL_OK;  
00720   
00721   /* Check the parameters */
00722   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00723   
00724   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc))
00725   {
00726     return HAL_BUSY;
00727   }
00728   else
00729   {
00730 
00731     /* In case of software trigger detection enabled, JQDIS must be set 
00732       (which can be done only if ADSTART and JADSTART are both cleared).
00733        If JQDIS is not set at that point, returns an error
00734        - since software trigger detection is disabled. User needs to
00735        resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.  
00736        - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means 
00737          the queue is empty */
00738     if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == RESET)   
00739     && (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS) == RESET))  
00740     {
00741       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
00742       return HAL_ERROR;
00743     }
00744 
00745     /* Process locked */
00746     __HAL_LOCK(hadc);
00747       
00748     /* Enable the ADC peripheral */
00749     tmp_status = ADC_Enable(hadc);
00750     
00751     /* Start conversion if ADC is effectively enabled */
00752     if (tmp_status == HAL_OK)
00753     {
00754       /* Check if a regular conversion is ongoing */
00755       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_REG_BUSY))
00756       {
00757         /* Reset ADC error code field related to injected conversions only */
00758         CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);            
00759       }
00760       else
00761       {
00762         /* Set ADC error code to none */
00763         ADC_CLEAR_ERRORCODE(hadc);
00764       }
00765       /* Clear HAL_ADC_STATE_READY and HAL_ADC_STATE_INJ_EOC bits, set HAL_ADC_STATE_INJ_BUSY bit */
00766       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_INJ_EOC), HAL_ADC_STATE_INJ_BUSY);
00767       
00768       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00769         - by default if ADC is Master or Independent or if multimode feature is not available
00770         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
00771       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00772       {
00773         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00774       }      
00775     
00776       /* Clear injected group conversion flag */
00777       /* (To ensure of no unknown state from potential previous ADC operations) */
00778       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
00779       
00780       /* Enable ADC Injected context queue overflow interrupt if this feature   */
00781       /* is enabled.                                                            */
00782       if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != RESET)
00783       {
00784         __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
00785       }
00786       
00787       /* Enable ADC end of conversion interrupt */
00788       switch(hadc->Init.EOCSelection)
00789       {
00790         case ADC_EOC_SEQ_CONV: 
00791           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
00792           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
00793           break;
00794         /* case ADC_EOC_SINGLE_CONV */
00795         default:
00796           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
00797           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
00798           break;
00799       }
00800       
00801       /* Enable conversion of injected group, if automatic injected conversion  */
00802       /* is disabled.                                                           */
00803       /* If software start has been selected, conversion starts immediately.    */
00804       /* If external trigger has been selected, conversion will start at next   */
00805       /* trigger event.                                                         */
00806       /* Case of multimode enabled (when multimode feature is available):       */
00807       /* if ADC is slave,                                                       */
00808       /*    - ADC is enabled only (conversion is not started),                  */
00809       /*    - if multimode only concerns regular conversion, ADC is enabled     */
00810       /*     and conversion is started.                                         */
00811       /* If ADC is master or independent,                                       */
00812       /*    - ADC is enabled and conversion is started.                         */
00813 
00814       /* Are injected conversions that of a dual Slave ? */      
00815       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
00816       {
00817         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
00818            set ADSTART only if JAUTO is cleared */
00819         /* Process unlocked */
00820         __HAL_UNLOCK(hadc);            
00821         if (HAL_IS_BIT_CLR(hadc->Instance->CFGR, ADC_CFGR_JAUTO))
00822         {
00823           SET_BIT(hadc->Instance->CR, ADC_CR_JADSTART) ;
00824         }
00825       }
00826       else
00827       {
00828         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
00829            ADSTART is not set */
00830           SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00831         /* Process unlocked */
00832         __HAL_UNLOCK(hadc);          
00833       }
00834     }
00835     else
00836     {
00837       /* Process unlocked */
00838       __HAL_UNLOCK(hadc);
00839     }
00840     
00841     /* Return function status */
00842     return tmp_status;
00843 }
00844 }
00845 
00846 
00847 
00848 /**
00849   * @brief  Stop conversion of injected channels, disable interruption of end-of-conversion. 
00850   * @note   Disable ADC peripheral if no regular conversion
00851   *         is on going.
00852   * @note   If ADC must be disabled and if regular conversion
00853   *         is on going, function HAL_ADC_Stop must be used first.
00854   * @note   Case of multimode enabled (when multimode feature is available): 
00855   *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first, 
00856   *         then for ADC slave.
00857   *         For ADC master, conversion is stopped and ADC is disabled. 
00858   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
00859   *         has already stopped conversion of ADC slave).
00860   * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
00861   * @param  hadc: ADC handle
00862   * @retval None
00863   */
00864 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
00865 { 
00866   HAL_StatusTypeDef tmp_status = HAL_OK;
00867   
00868   /* Check the parameters */
00869   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00870   
00871   /* Process locked */
00872   __HAL_LOCK(hadc);
00873   
00874   /* 1. Stop potential conversion on going on injected group only. */
00875   tmp_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
00876   
00877   /* Disable ADC peripheral if injected conversions are effectively stopped   */
00878   /* and if no conversion on the other group (regular group) is intended to   */
00879   /* continue.                                                                */
00880   if (tmp_status == HAL_OK)
00881   {
00882     /* Disable ADC end of conversion interrupt for injected channels */
00883     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
00884     
00885     if ((ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET))
00886     {
00887       /* 2. Disable the ADC peripheral */
00888       tmp_status = ADC_Disable(hadc);
00889       
00890       /* Check if ADC is effectively disabled */
00891       if (tmp_status == HAL_OK)
00892       {
00893         /* Change ADC state */
00894         /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00895         ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00896       }
00897     }
00898     /* Conversion on injected group is stopped, but ADC not disabled since    */
00899     /* conversion on regular group is still running.                          */
00900     else
00901     {
00902       /* Clear HAL_ADC_STATE_INJ_BUSY bit */
00903       CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 
00904     }
00905   }
00906 
00907   /* Process unlocked */
00908   __HAL_UNLOCK(hadc);
00909   
00910   /* Return function status */
00911   return tmp_status;
00912 }
00913 
00914 
00915 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00916 /**
00917   * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
00918   * @note   Multimode must have been previously configured using 
00919   *         HAL_ADCEx_MultiModeConfigChannel() function.
00920   *         Interruptions enabled in this function:
00921   *          overrun, DMA half transfer, DMA transfer complete. 
00922   *         Each of these interruptions has its dedicated callback function.
00923   * @note   State field of Slave ADC handle is not updated in this configuration: 
00924   *          user should not rely on it for information related to Slave regular 
00925   *         conversions.                                                                          
00926   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
00927   * @param  pData: Destination Buffer address.
00928   * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes).
00929   * @retval None
00930   */
00931 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
00932 {
00933   HAL_StatusTypeDef tmp_status = HAL_OK;
00934   ADC_HandleTypeDef tmphadcSlave;
00935   ADC_Common_TypeDef *tmpADC_Common;
00936 
00937   /* Check the parameters */
00938   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
00939   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00940   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00941   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00942   
00943   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
00944   {
00945     return HAL_BUSY;
00946   }
00947   else
00948   {
00949     /* Process locked */
00950     __HAL_LOCK(hadc);
00951 
00952     /* Set a temporary handle of the ADC slave associated to the ADC master   */
00953     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
00954   
00955     if (tmphadcSlave.Instance == NULL)
00956     {
00957       /* Update ADC state machine to error */
00958       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00959     
00960       /* Process unlocked */
00961       __HAL_UNLOCK(hadc);
00962     
00963       return HAL_ERROR;
00964     }
00965     
00966   
00967     /* Enable the ADC peripherals: master and slave (in case if not already   */
00968     /* enabled previously)                                                    */
00969     tmp_status = ADC_Enable(hadc);
00970     if (tmp_status == HAL_OK)
00971     {
00972       tmp_status = ADC_Enable(&tmphadcSlave);
00973     }
00974   
00975     /* Start multimode conversion of ADCs pair */
00976     if (tmp_status == HAL_OK)
00977     {
00978       /* Update Master State */
00979       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
00980       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
00981 
00982        
00983       /* Set ADC error code to none */
00984       ADC_CLEAR_ERRORCODE(hadc);
00985       
00986       
00987       /* Set the DMA transfer complete callback */
00988       hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
00989          
00990       /* Set the DMA half transfer complete callback */
00991       hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
00992       
00993       /* Set the DMA error callback */
00994       hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
00995       
00996       /* Pointer to the common control register  */
00997       tmpADC_Common = ADC_COMMON_REGISTER(hadc);
00998       
00999       
01000       /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
01001       /* start (in case of SW start):                                           */
01002   
01003       /* Clear regular group conversion flag and overrun flag */
01004       /* (To ensure of no unknown state from potential previous ADC operations) */
01005       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01006       
01007       /* Enable ADC overrun interrupt */
01008       __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
01009   
01010       /* Start the DMA channel */
01011       HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
01012           
01013       /* Enable conversion of regular group.                                    */
01014       /* Process unlocked */
01015       __HAL_UNLOCK(hadc);      
01016       /* If software start has been selected, conversion starts immediately.    */
01017       /* If external trigger has been selected, conversion will start at next   */
01018       /* trigger event.                                                         */
01019       SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01020 
01021     }
01022     else
01023     {
01024       /* Process unlocked */
01025       __HAL_UNLOCK(hadc);
01026     }
01027   
01028     /* Return function status */
01029     return tmp_status;
01030   }
01031 }
01032 
01033 /**
01034   * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
01035   * @note   Multimode is kept enabled after this function. MultiMode DMA bits
01036   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable 
01037   *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 
01038   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01039   *         resort to HAL_ADCEx_DisableMultiMode() API.
01040   * @note   In case of DMA configured in circular mode, function 
01041   *         HAL_ADC_Stop_DMA() must be called after this function with handle of
01042   *         ADC slave, to properly disable the DMA channel.
01043   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
01044   * @retval None
01045   */
01046 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
01047 {
01048   HAL_StatusTypeDef tmp_status = HAL_OK;
01049   uint32_t tickstart;
01050   ADC_HandleTypeDef tmphadcSlave;
01051   
01052   /* Check the parameters */
01053   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01054   
01055   /* Process locked */
01056   __HAL_LOCK(hadc);
01057   
01058  
01059   /* 1. Stop potential multimode conversion on going, on regular and injected groups */
01060   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01061 
01062   /* Disable ADC peripheral if conversions are effectively stopped */
01063   if (tmp_status == HAL_OK)
01064   {                                      
01065     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01066     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01067     
01068     if (tmphadcSlave.Instance == NULL)
01069     {
01070       /* Update ADC state machine to error */
01071       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01072       
01073       /* Process unlocked */
01074       __HAL_UNLOCK(hadc);
01075       
01076       return HAL_ERROR;
01077     }
01078     
01079     /* Procedure to disable the ADC peripheral: wait for conversions          */
01080     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01081     
01082     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
01083     tickstart = HAL_GetTick();  
01084 
01085     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          || 
01086           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
01087     {
01088       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01089       {
01090         /* Update ADC state machine to error */
01091         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01092         
01093         /* Process unlocked */
01094         __HAL_UNLOCK(hadc);
01095         
01096         return HAL_ERROR;
01097       }
01098     }
01099     
01100     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01101     /* while DMA transfer is on going)                                        */
01102     /* Note: DMA channel of ADC slave should be stopped after this function   */
01103     /*       with HAL_ADC_Stop_DMA() API.                                     */
01104     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
01105     
01106     /* Check if DMA channel effectively disabled */
01107     if (tmp_status == HAL_ERROR)
01108     {
01109       /* Update ADC state machine to error */
01110       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 
01111     }
01112     
01113     /* Disable ADC overrun interrupt */
01114     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01115     
01116     
01117     
01118     /* 2. Disable the ADC peripherals: master and slave */
01119     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01120     /* memory a potential failing status.                                     */
01121     if (tmp_status == HAL_OK)
01122     {
01123       /* Check if ADC are effectively disabled */
01124       if ((ADC_Disable(hadc) == HAL_OK)         &&
01125           (ADC_Disable(&tmphadcSlave) == HAL_OK)   )
01126       {
01127         tmp_status = HAL_OK;
01128       }
01129     }
01130     else
01131     {
01132       ADC_Disable(hadc);
01133       ADC_Disable(&tmphadcSlave);
01134     }
01135     /* Change ADC state (ADC master) */
01136     /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01137     ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
01138     
01139   }
01140   
01141   /* Process unlocked */
01142   __HAL_UNLOCK(hadc);
01143   
01144   /* Return function status */
01145   return tmp_status;
01146 }
01147 
01148 
01149 /**
01150   * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
01151   * @param  hadc: ADC handle of ADC Master (handle of ADC Slave must not be used)
01152   * @retval The converted data values.
01153   */
01154 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
01155 {
01156   ADC_Common_TypeDef *tmpADC_Common;
01157   
01158   /* Check the parameters */
01159   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01160   
01161   /* Pointer to the common control register  */
01162   tmpADC_Common = ADC_COMMON_REGISTER(hadc);
01163   
01164   /* Return the multi mode conversion value */
01165   return tmpADC_Common->CDR;
01166 }
01167 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01168 
01169 
01170 /**
01171   * @brief  Get ADC injected group conversion result.
01172   * @param  hadc: ADC handle
01173   * @param  InjectedRank: the converted ADC injected rank.
01174   *          This parameter can be one of the following values:
01175   *            @arg @ref ADC_INJECTED_RANK_1 Injected Channel1 selected
01176   *            @arg @ref ADC_INJECTED_RANK_2 Injected Channel2 selected
01177   *            @arg @ref ADC_INJECTED_RANK_3 Injected Channel3 selected
01178   *            @arg @ref ADC_INJECTED_RANK_4 Injected Channel4 selected
01179   * @note   Reading JDRy register automatically clears JEOC flag. To reset JEOS 
01180   *         flag the user must resort to the macro 
01181   *         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS).    
01182   * @retval None
01183   */
01184 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
01185 {
01186   uint32_t tmp_jdr = 0;
01187 
01188   /* Check the parameters */
01189   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01190   assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
01191   
01192   
01193   /* Get ADC converted value */ 
01194   switch(InjectedRank)
01195   {  
01196     case ADC_INJECTED_RANK_4: 
01197       tmp_jdr = hadc->Instance->JDR4;
01198       break;
01199     case ADC_INJECTED_RANK_3: 
01200       tmp_jdr = hadc->Instance->JDR3;
01201       break;
01202     case ADC_INJECTED_RANK_2: 
01203       tmp_jdr = hadc->Instance->JDR2;
01204       break;
01205     case ADC_INJECTED_RANK_1:
01206     default:
01207       tmp_jdr = hadc->Instance->JDR1;
01208       break;
01209   }
01210   
01211   /* Return ADC converted value */ 
01212   return tmp_jdr;
01213 }
01214 
01215 /**
01216   * @brief  Injected conversion complete callback in non-blocking mode. 
01217   * @param  hadc: ADC handle
01218   * @retval None
01219   */
01220 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
01221 {
01222   /* Prevent unused argument(s) compilation warning */
01223   UNUSED(hadc);
01224 
01225   /* NOTE : This function should not be modified. When the callback is needed,
01226             function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
01227   */
01228 }
01229 
01230 
01231 /**
01232   * @brief  Injected context queue overflow callback. 
01233   * @note   This callback is called if injected context queue is enabled
01234             (parameter "QueueInjectedContext" in injected channel configuration)
01235             and if a new injected context is set when queue is full (maximum 2
01236             contexts).
01237   * @param  hadc: ADC handle
01238   * @retval None
01239   */
01240 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
01241 {
01242   /* Prevent unused argument(s) compilation warning */
01243   UNUSED(hadc);
01244 
01245   /* NOTE : This function should not be modified. When the callback is needed,
01246             function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
01247   */
01248 }
01249 
01250 /**
01251   * @brief  Analog watchdog 2 callback in non-blocking mode.        
01252   * @param  hadc: ADC handle
01253   * @retval None
01254   */
01255 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
01256 {
01257   /* Prevent unused argument(s) compilation warning */
01258   UNUSED(hadc);
01259 
01260   /* NOTE : This function should not be modified. When the callback is needed,
01261             function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
01262   */
01263 }
01264 
01265 /**
01266   * @brief  Analog watchdog 3 callback in non-blocking mode.        
01267   * @param  hadc: ADC handle
01268   * @retval None
01269   */
01270 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
01271 {
01272   /* Prevent unused argument(s) compilation warning */
01273   UNUSED(hadc);
01274 
01275   /* NOTE : This function should not be modified. When the callback is needed,
01276             function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
01277   */
01278 }
01279 
01280 
01281 /**
01282   * @brief  End Of Sampling callback in non-blocking mode.        
01283   * @param  hadc: ADC handle
01284   * @retval None
01285   */
01286 __weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc)
01287 {
01288   /* Prevent unused argument(s) compilation warning */
01289   UNUSED(hadc);
01290 
01291   /* NOTE : This function should not be modified. When the callback is needed,
01292             function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
01293   */
01294 }
01295 
01296 
01297 
01298 /**  
01299   * @brief  Stop ADC conversion of regular groups, disable ADC peripheral if no injected conversion is on-going.
01300   * @param  hadc: ADC handle
01301   * @retval HAL status.
01302   */
01303 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
01304 { 
01305   HAL_StatusTypeDef tmp_status = HAL_OK;
01306   
01307   /* Check the parameters */
01308   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01309   
01310   /* Process locked */
01311   __HAL_LOCK(hadc);
01312   
01313   /* 1. Stop potential regular conversion on going */
01314   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01315   
01316   /* Disable ADC peripheral if regular conversions are effectively stopped 
01317      and if no injected conversions are on-going */
01318   if (tmp_status == HAL_OK)
01319   {
01320     /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
01321     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 
01322      
01323     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01324     {
01325       /* 2. Disable the ADC peripheral */
01326       tmp_status = ADC_Disable(hadc);
01327       
01328       /* Check if ADC is effectively disabled */
01329       if (tmp_status == HAL_OK)
01330       {
01331         /* Change ADC state */
01332         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01333         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01334       }
01335     }
01336     /* Conversion on injected group is stopped, but ADC not disabled since    */
01337     /* conversion on regular group is still running.                          */
01338     else
01339     {
01340       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01341     }
01342   }
01343 
01344   /* Process unlocked */
01345   __HAL_UNLOCK(hadc);
01346   
01347   /* Return function status */
01348   return tmp_status;
01349 }
01350 
01351 
01352 /**  
01353   * @brief  Stop ADC conversion of regular groups when interruptions are enabled, disable ADC peripheral if no injected conversion is on-going.
01354   * @param  hadc: ADC handle
01355   * @retval HAL status.
01356   */  
01357 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
01358 {
01359   HAL_StatusTypeDef tmp_status = HAL_OK;
01360   
01361   /* Check the parameters */
01362   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01363   
01364   /* Process locked */
01365   __HAL_LOCK(hadc);
01366   
01367   /* 1. Stop potential regular conversion on going */
01368   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01369   
01370   /* Disable ADC peripheral if conversions are effectively stopped
01371     and if no injected conversion is on-going */
01372   if (tmp_status == HAL_OK)
01373   {
01374     /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
01375     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);  
01376      
01377     /* Disable all regular-related interrupts */
01378     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01379     
01380     /* 2. Disable ADC peripheral if no injected conversions are on-going */
01381     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01382     {     
01383       tmp_status = ADC_Disable(hadc);
01384       /* if no issue reported */
01385       if (tmp_status == HAL_OK)
01386       {
01387         /* Change ADC state */
01388         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01389         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01390       }
01391     }
01392     else
01393     {
01394       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
01395     }
01396   }
01397 
01398   /* Process unlocked */
01399   __HAL_UNLOCK(hadc);
01400   
01401   /* Return function status */
01402   return tmp_status;
01403 }
01404 
01405 
01406 /**
01407   * @brief  Stop ADC conversion of regular groups and disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
01408   * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only. 
01409   *         For multimode (when multimode feature is available), 
01410   *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
01411   * @param  hadc: ADC handle
01412   * @retval HAL status.
01413   */
01414 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
01415 {  
01416   HAL_StatusTypeDef tmp_status = HAL_OK;
01417   
01418   /* Check the parameters */
01419   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01420 
01421   /* Process locked */
01422   __HAL_LOCK(hadc);
01423   
01424   /* 1. Stop potential regular conversion on going */
01425   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01426   
01427   /* Disable ADC peripheral if conversions are effectively stopped 
01428      and if no injected conversion is on-going */
01429   if (tmp_status == HAL_OK)
01430   {
01431     /* Clear HAL_ADC_STATE_REG_BUSY bit */ 
01432     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01433     
01434     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
01435     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 
01436     
01437     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01438     /* while DMA transfer is on going)                                        */
01439     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);   
01440     
01441     /* Check if DMA channel effectively disabled */
01442     if (tmp_status != HAL_OK)
01443     {
01444       /* Update ADC state machine to error */
01445       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);   
01446     }
01447     
01448     /* Disable ADC overrun interrupt */
01449     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01450     
01451     /* 2. Disable the ADC peripheral */
01452     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01453     /* memory a potential failing status.                                     */
01454     if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01455     {    
01456       if (tmp_status == HAL_OK)
01457       {
01458         tmp_status = ADC_Disable(hadc);
01459       }
01460       else
01461       {
01462         ADC_Disable(hadc);
01463       }
01464 
01465       /* Check if ADC is effectively disabled */
01466       if (tmp_status == HAL_OK)
01467       {
01468         /* Change ADC state */
01469         /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01470         ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);      
01471       }
01472     }
01473     else
01474     {
01475       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);  
01476     }
01477   }
01478 
01479   /* Process unlocked */
01480   __HAL_UNLOCK(hadc);
01481   
01482   /* Return function status */
01483   return tmp_status;
01484 }
01485 
01486 
01487 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)  
01488 /**
01489   * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected conversion is on-going.
01490   * @note   Multimode is kept enabled after this function. Multimode DMA bits
01491   *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable 
01492   *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be 
01493   *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
01494   *         resort to HAL_ADCEx_DisableMultiMode() API.  
01495   * @note   In case of DMA configured in circular mode, function 
01496   *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
01497   *         ADC slave, to properly disable the DMA channel.
01498   * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
01499   * @retval None
01500   */
01501 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
01502 {
01503   HAL_StatusTypeDef tmp_status = HAL_OK;
01504   uint32_t tickstart;
01505   ADC_HandleTypeDef tmphadcSlave;
01506   
01507   /* Check the parameters */
01508   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
01509   
01510   /* Process locked */
01511   __HAL_LOCK(hadc);
01512   
01513  
01514   /* 1. Stop potential multimode conversion on going, on regular groups */
01515   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
01516 
01517   /* Disable ADC peripheral if conversions are effectively stopped */
01518   if (tmp_status == HAL_OK)
01519   { 
01520     /* Clear HAL_ADC_STATE_REG_BUSY bit */                                     
01521     CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
01522     
01523     /* Set a temporary handle of the ADC slave associated to the ADC master   */
01524     ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
01525     
01526     if (tmphadcSlave.Instance == NULL)
01527     {
01528       /* Update ADC state machine to error */
01529       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01530       
01531       /* Process unlocked */
01532       __HAL_UNLOCK(hadc);
01533       
01534       return HAL_ERROR;
01535     }
01536     
01537     /* Procedure to disable the ADC peripheral: wait for conversions          */
01538     /* effectively stopped (ADC master and ADC slave), then disable ADC       */
01539     
01540     /* 1. Wait until ADSTP=0 for ADC master and ADC slave*/
01541     tickstart = HAL_GetTick();  
01542 
01543     while(ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)          || 
01544           ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave)   )
01545     {
01546       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
01547       {
01548         /* Update ADC state machine to error */
01549         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01550         
01551         /* Process unlocked */
01552         __HAL_UNLOCK(hadc);
01553         
01554         return HAL_ERROR;
01555       }
01556     }
01557     
01558     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
01559     /* while DMA transfer is on going)                                        */
01560     /* Note: DMA channel of ADC slave should be stopped after this function   */
01561     /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
01562     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);
01563     
01564     /* Check if DMA channel effectively disabled */
01565     if (tmp_status != HAL_OK)
01566     {
01567       /* Update ADC state machine to error */
01568       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);  
01569     }
01570     
01571     /* Disable ADC overrun interrupt */
01572     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01573     
01574     
01575     
01576     /* 2. Disable the ADC peripherals: master and slave if no injected        */
01577     /*   conversion is on-going.                                              */
01578     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01579     /* memory a potential failing status.                                     */
01580     if (tmp_status == HAL_OK)
01581     {
01582        if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01583        {  
01584          tmp_status =  ADC_Disable(hadc);
01585          if (tmp_status == HAL_OK)
01586          {
01587            if (ADC_IS_CONVERSION_ONGOING_INJECTED(&tmphadcSlave) == RESET)
01588            {
01589              tmp_status =  ADC_Disable(&tmphadcSlave);
01590            }
01591          }
01592        }
01593        
01594        if (tmp_status == HAL_OK)
01595        {
01596          /* Both Master and Slave ADC's could be disabled. Update Master State */
01597          /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
01598          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
01599        }
01600        else
01601        {
01602          /* injected (Master or Slave) conversions are still on-going,
01603             no Master State change */
01604        }
01605           
01606 
01607     }
01608 
01609     
01610   }
01611   
01612   /* Process unlocked */
01613   __HAL_UNLOCK(hadc);
01614   
01615   /* Return function status */
01616   return tmp_status;
01617 }
01618 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
01619 
01620 /**
01621   * @}
01622   */
01623 
01624 /** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
01625   * @brief    Extended Peripheral Control functions
01626   *
01627 @verbatim   
01628  ===============================================================================
01629              ##### Peripheral Control functions #####
01630  ===============================================================================  
01631     [..]  This section provides functions allowing to:
01632       (+) Configure channels on injected group
01633       (+) Configure multimode when multimode feature is available
01634       (+) Enable or Disable Injected Queue
01635       (+) Disable ADC voltage regulator
01636       (+) Enter ADC deep-power-down mode      
01637       
01638       
01639 @endverbatim
01640   * @{
01641   */
01642 
01643 /**  
01644   * @brief  Configure the ADC injected group and the selected channel to be linked to the injected group.
01645   * @note   Possibility to update parameters on the fly:
01646   *         This function initializes injected group, consecutive calls to this 
01647   *         function can be used to reconfigure some parameters of structure
01648   *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
01649   *         The setting of these parameters is conditioned to ADC state.
01650   *         For parameters constraints, see comments of structure 
01651   *         "ADC_InjectionConfTypeDef".
01652   * @note   In case of usage of internal measurement channels (Vbat/VrefInt/TempSensor),
01653   *         The internal paths can be disabled using function HAL_ADC_DeInit().
01654   * @note   To reset injected sequencer, function HAL_ADCEx_InjectedStop() can
01655   *         be used.
01656   * @note   Caution: For Injected Context Queue use, a context must be fully 
01657   *         defined before start of injected conversion. All channels are configured 
01658   *         consecutively for the same ADC instance. Therefore, the number of calls to 
01659   *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter 
01660   *         InjectedNbrOfConversion for each context.
01661   *  - Example 1: If 1 context is intended to be used (or if there is no use of the 
01662   *    Injected Queue Context feature) and if the context contains 3 injected ranks 
01663   *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be  
01664   *    called once for each channel (i.e. 3 times) before starting a conversion.   
01665   *    This function must not be called to configure a 4th injected channel:   
01666   *    it would start a new context into context queue.
01667   *  - Example 2: If 2 contexts are intended to be used and each of them contains 
01668   *    3 injected ranks (InjectedNbrOfConversion = 3),  
01669   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and  
01670   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can  
01671   *    start once the 1st context is set, that is after the first three 
01672   *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
01673   * @param  hadc: ADC handle
01674   * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
01675   *         injected group.
01676   * @retval None
01677   */
01678 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
01679 {
01680   HAL_StatusTypeDef tmp_status = HAL_OK;
01681   ADC_Common_TypeDef *tmpADC_Common;
01682   uint32_t tmpOffsetShifted;
01683   uint32_t wait_loop_index = 0;
01684   
01685 
01686   uint32_t tmp_JSQR_ContextQueueBeingBuilt = 0;
01687   
01688   /* Check the parameters */
01689   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01690   assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
01691   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfigInjected->InjectedSingleDiff));
01692   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
01693   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->QueueInjectedContext));
01694   assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
01695   assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
01696   assert_param(IS_ADC_OFFSET_NUMBER(sConfigInjected->InjectedOffsetNumber));
01697   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfigInjected->InjectedOffset));
01698   assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjecOversamplingMode));
01699   
01700   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
01701   {
01702     assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
01703     assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
01704     assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
01705   }
01706   
01707   
01708   /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is  
01709      ignored (considered as reset) */
01710   assert_param(!((sConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE) && (sConfigInjected->InjecOversamplingMode == ENABLE))); 
01711     
01712   /* JDISCEN and JAUTO bits can't be set at the same time  */
01713   assert_param(!((sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE))); 
01714 
01715   /*  DISCEN and JAUTO bits can't be set at the same time */
01716   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (sConfigInjected->AutoInjectedConv == ENABLE)));  
01717 
01718   /* Verification of channel number */
01719   if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
01720   {
01721      assert_param(IS_ADC_CHANNEL(hadc, sConfigInjected->InjectedChannel));
01722   }
01723   else
01724   {
01725     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfigInjected->InjectedChannel));
01726   }                
01727  
01728     
01729   /* Process locked */
01730   __HAL_LOCK(hadc);
01731 
01732 
01733 
01734   /* Configuration of Injected group sequencer.                               */
01735   /* Hardware constraint: Must fully define injected context register JSQR    */
01736   /* before make it entering into injected sequencer queue.                   */
01737   /*                                                                          */
01738   /* - if scan mode is disabled:                                              */
01739   /*    * Injected channels sequence length is set to 0x00: 1 channel         */
01740   /*      converted (channel on injected rank 1)                              */
01741   /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
01742   /*    * Injected context register JSQR setting is simple: register is fully */
01743   /*      defined on one call of this function (for injected rank 1) and can  */
01744   /*      be entered into queue directly.                                     */
01745   /* - if scan mode is enabled:                                               */
01746   /*    * Injected channels sequence length is set to parameter               */
01747   /*      "InjectedNbrOfConversion".                                          */
01748   /*    * Injected context register JSQR setting more complex: register is    */
01749   /*      fully defined over successive calls of this function, for each      */
01750   /*      injected channel rank. It is entered into queue only when all       */
01751   /*      injected ranks have been set.                                       */
01752   /*   Note: Scan mode is not present by hardware on this device, but used    */
01753   /*   by software for alignment over all STM32 devices.                      */
01754 
01755   if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
01756       (sConfigInjected->InjectedNbrOfConversion == 1)  )
01757   {
01758     /* Configuration of context register JSQR:                                */
01759     /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
01760     /*    (scan mode disabled, only rank 1 used)                              */
01761     /*  - external trigger to start conversion                                */
01762     /*  - external trigger polarity                                           */
01763     /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
01764     
01765     if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
01766     {
01767       /* Enable external trigger if trigger selection is different of         */
01768       /* software start.                                                      */
01769       /* Note: This configuration keeps the hardware feature of parameter     */
01770       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01771       /*       software start.                                                */
01772       if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01773          && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01774       {
01775         tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) |
01776                                              sConfigInjected->ExternalTrigInjecConv     |
01777                                              sConfigInjected->ExternalTrigInjecConvEdge                                );                                              
01778       }
01779       else
01780       {
01781         tmp_JSQR_ContextQueueBeingBuilt = ( ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1) );
01782       }
01783       
01784 
01785       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_JSQR_ContextQueueBeingBuilt); 
01786       /* For debug and informative reasons, hadc handle saves JSQR setting */
01787       hadc->InjectionConfig.ContextQueue = tmp_JSQR_ContextQueueBeingBuilt;
01788     
01789     }
01790   }
01791   else
01792   {
01793     /* Case of scan mode enabled, several channels to set into injected group */
01794     /* sequencer.                                                             */
01795     /*                                                                        */
01796     /* Procedure to define injected context register JSQR over successive     */
01797     /* calls of this function, for each injected channel rank:                */
01798     /* 1. Start new context and set parameters related to all injected        */
01799     /*    channels: injected sequence length and trigger.                     */
01800     
01801     /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
01802     /*   call of the context under setting                                    */
01803     if (hadc->InjectionConfig.ChannelCount == 0) 
01804     {
01805       /* Initialize number of channels that will be configured on the context */
01806       /*  being built                                                         */
01807       hadc->InjectionConfig.ChannelCount = sConfigInjected->InjectedNbrOfConversion;
01808       /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
01809          call, this context will be written in JSQR register at the last call.
01810          At this point, the context is merely reset  */
01811        hadc->InjectionConfig.ContextQueue = (uint32_t)0x00000000;
01812 
01813       /* Configuration of context register JSQR:                              */
01814       /*  - number of ranks in injected group sequencer                       */
01815       /*  - external trigger to start conversion                              */
01816       /*  - external trigger polarity                                         */
01817         
01818       /* Enable external trigger if trigger selection is different of         */
01819       /* software start.                                                      */
01820       /* Note: This configuration keeps the hardware feature of parameter     */
01821       /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
01822       /*       software start.                                                */
01823       if ((sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
01824          && (sConfigInjected->ExternalTrigInjecConvEdge != ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01825       {      
01826         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1)              |
01827                                              sConfigInjected->ExternalTrigInjecConv |
01828                                              sConfigInjected->ExternalTrigInjecConvEdge                            );        
01829       }
01830       else
01831       {
01832         tmp_JSQR_ContextQueueBeingBuilt = ((sConfigInjected->InjectedNbrOfConversion - (uint32_t)1) );
01833       }
01834      
01835       
01836     } /* if (hadc->InjectionConfig.ChannelCount == 0) */  
01837     
01838 
01839     /* 2. Continue setting of context under definition with parameter       */
01840     /*    related to each channel: channel rank sequence                    */ 
01841     /* Clear the old JSQx bits for the selected rank */
01842     tmp_JSQR_ContextQueueBeingBuilt &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, sConfigInjected->InjectedRank);
01843     
01844     /* Set the JSQx bits for the selected rank */
01845     tmp_JSQR_ContextQueueBeingBuilt |= ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank);
01846 
01847     /* Decrease channel count  */
01848     hadc->InjectionConfig.ChannelCount--;
01849     
01850     
01851     /* 3. tmp_JSQR_ContextQueueBeingBuilt is fully built for this HAL_ADCEx_InjectedConfigChannel()
01852           call, aggregate the setting to those already built during the previous  
01853           HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
01854     hadc->InjectionConfig.ContextQueue |= tmp_JSQR_ContextQueueBeingBuilt;
01855           
01856     /* 4. End of context setting: if this is the last channel set, then write context
01857         into register JSQR and make it enter into queue                   */
01858     if (hadc->InjectionConfig.ChannelCount == 0)
01859     {
01860       MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue); 
01861     }
01862 
01863     
01864   } 
01865 
01866   /* Parameters update conditioned to ADC state:                              */
01867   /* Parameters that can be updated when ADC is disabled or enabled without   */
01868   /* conversion on going on injected group:                                   */
01869   /*  - Injected context queue: Queue disable (active context is kept) or     */
01870   /*    enable (context decremented, up to 2 contexts queued)                 */
01871   /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
01872   /*    mode is disabled.                                                     */
01873   if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01874   {
01875      
01876     /* If auto-injected mode is disabled: no constraint                       */
01877     if (sConfigInjected->AutoInjectedConv == DISABLE)
01878     {                               
01879       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 
01880                                ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext)          | 
01881                                ADC_CFGR_INJECT_DISCCONTINUOUS(sConfigInjected->InjectedDiscontinuousConvMode) );                          
01882     }
01883     /* If auto-injected mode is enabled: Injected discontinuous setting is   */
01884     /* discarded.                                                             */
01885     else
01886     {
01887             MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_JQM | ADC_CFGR_JDISCEN, 
01888                                ADC_CFGR_INJECT_CONTEXT_QUEUE(sConfigInjected->QueueInjectedContext) );  
01889     }
01890 
01891   }
01892   
01893   
01894   /* Parameters update conditioned to ADC state:                              */
01895   /* Parameters that can be updated when ADC is disabled or enabled without   */
01896   /* conversion on going on regular and injected groups:                      */
01897   /*  - Automatic injected conversion: can be enabled if injected group       */
01898   /*    external triggers are disabled.                                       */
01899   /*  - Channel sampling time                                                 */
01900   /*  - Channel offset                                                        */
01901   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
01902   {    
01903     /* If injected group external triggers are disabled (set to injected      */
01904     /* software start): no constraint                                         */
01905     if ((sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
01906        || (sConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
01907     {
01908          if (sConfigInjected->AutoInjectedConv == ENABLE)
01909          {
01910            SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);    
01911          }
01912          else
01913          {
01914            CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);    
01915          }                                                                                  
01916     }
01917     /* If Automatic injected conversion was intended to be set and could not  */
01918     /* due to injected group external triggers enabled, error is reported.    */
01919     else
01920     {
01921       if (sConfigInjected->AutoInjectedConv == ENABLE)
01922       {
01923         /* Update ADC state machine to error */
01924         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
01925         
01926         tmp_status = HAL_ERROR;
01927       }
01928       else
01929       {
01930         CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO); 
01931       }
01932     }
01933     
01934     
01935     
01936     if (sConfigInjected->InjecOversamplingMode == ENABLE)
01937     {
01938       assert_param(IS_ADC_OVERSAMPLING_RATIO(sConfigInjected->InjecOversampling.Ratio));
01939       assert_param(IS_ADC_RIGHT_BIT_SHIFT(sConfigInjected->InjecOversampling.RightBitShift));
01940       
01941       /*  JOVSE must be reset in case of triggered regular mode  */
01942       assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS) == (ADC_CFGR2_ROVSE|ADC_CFGR2_TROVS)));
01943 
01944       /* Configuration of Injected Oversampler:                                 */
01945       /*  - Oversampling Ratio                                                  */
01946       /*  - Right bit shift                                                     */
01947       
01948       /* Enable OverSampling mode */
01949   
01950        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_INJ_FIELDS, 
01951                                  ADC_CFGR2_JOVSE                     | 
01952                                  sConfigInjected->InjecOversampling.Ratio         |
01953                                  sConfigInjected->InjecOversampling.RightBitShift );
01954     }  
01955     else
01956     {
01957       /* Disable Regular OverSampling */
01958        CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
01959     }    
01960         
01961   
01962     /* Sampling time configuration of the selected channel */
01963     /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
01964     if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
01965     {
01966       /* Clear the old sample time and set the new one */
01967       ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);                
01968     }
01969     else /* if ADC_Channel_0 ... ADC_Channel_9 is selected */
01970     {
01971      /* Clear the old sample time and set the new one */
01972       ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);             
01973     }
01974     
01975         
01976     /* Configure the offset: offset enable/disable, channel, offset value */
01977   
01978     /* Shift the offset with respect to the selected ADC resolution. */
01979     /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
01980     tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfigInjected->InjectedOffset);
01981     
01982     switch (sConfigInjected->InjectedOffsetNumber)
01983     {
01984     case ADC_OFFSET_1:
01985       /* Configure offset register 1:                                         */
01986       /* - Enable offset                                                      */
01987       /* - Set channel number                                                 */
01988       /* - Set offset value                                                   */
01989       MODIFY_REG(hadc->Instance->OFR1, 
01990                 ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN, 
01991                 ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                    
01992       break;
01993     
01994     case ADC_OFFSET_2:
01995       /* Configure offset register 2:                                         */
01996       /* - Enable offset                                                      */
01997       /* - Set channel number                                                 */
01998       /* - Set offset value                                                   */
01999       MODIFY_REG(hadc->Instance->OFR2, 
02000                 ADC_OFR2_OFFSET2 | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2_EN, 
02001                 ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                     
02002       break;
02003         
02004     case ADC_OFFSET_3:
02005       /* Configure offset register 3:                                         */
02006       /* - Enable offset                                                      */
02007       /* - Set channel number                                                 */
02008       /* - Set offset value                                                   */
02009       MODIFY_REG(hadc->Instance->OFR3, 
02010                 ADC_OFR3_OFFSET3 | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3_EN, 
02011                 ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                   
02012       break;
02013     
02014     case ADC_OFFSET_4:
02015       /* Configure offset register 1:                                         */
02016       /* - Enable offset                                                      */
02017       /* - Set channel number                                                 */
02018       /* - Set offset value                                                   */
02019       MODIFY_REG(hadc->Instance->OFR4, 
02020                 ADC_OFR4_OFFSET4 | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4_EN, 
02021                 ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel) | tmpOffsetShifted);                                  
02022       break;
02023     
02024     /* Case ADC_OFFSET_NONE */
02025     default :
02026     /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. If this is the case, offset OFRx is disabled. */
02027       if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02028       {
02029         /* Disable offset OFR1*/
02030         CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
02031       }
02032       if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02033       {
02034         /* Disable offset OFR2*/
02035         CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 
02036       }
02037       if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02038       {
02039         /* Disable offset OFR3*/
02040         CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 
02041       }
02042       if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfigInjected->InjectedChannel))
02043       {
02044         /* Disable offset OFR4*/
02045         CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN); 
02046       }
02047       break;
02048     }
02049 
02050   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
02051   
02052   
02053   /* Parameters update conditioned to ADC state:                              */
02054   /* Parameters that can be updated only when ADC is disabled:                */
02055   /*  - Single or differential mode                                           */
02056   /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02057   if (ADC_IS_ENABLE(hadc) == RESET)
02058   {
02059     /* Configuration of differential mode */
02060     if (sConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
02061     {
02062       /* Disable differential mode (default mode: single-ended) */
02063       CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
02064     }
02065     else
02066     {
02067       /* Enable differential mode */
02068       SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfigInjected->InjectedChannel));
02069       
02070       /* Sampling time configuration of channel ADC_IN+1 (negative input).
02071          Starting from channel 9, SMPR2 register must be configured.      */
02072       if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_9)
02073       {
02074         /* Clear the old sample time and set the new one */
02075         ADC_SMPR2_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);                     
02076       }
02077       else /* For channels 0 to 8 */
02078       {
02079          /* Clear the old sample time and set the new one */
02080         ADC_SMPR1_SETTING(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel+1);                 
02081       }
02082     }
02083     
02084 
02085     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
02086     /* internal measurement paths enable: If internal channel selected,       */
02087     /* enable dedicated internal buffers and path.                            */
02088     /* Note: these internal measurement paths can be disabled using           */
02089     /* HAL_ADC_DeInit().                                                      */
02090 
02091     /* Configuration of common ADC parameters                                 */
02092 
02093     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
02094   
02095     /* If the requested internal measurement path has already been enabled,   */
02096     /* bypass the configuration processing.                                   */
02097     if (( (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) &&
02098           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
02099         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)       &&
02100           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
02101         ( (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)    &&
02102           (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
02103        )
02104     {
02105       /* Configuration of common ADC parameters (continuation)                */
02106       /* Software is allowed to change common parameters only when all ADCs   */
02107       /* of the common group are disabled.                                    */
02108       if ((ADC_IS_ENABLE(hadc) == RESET)   &&
02109          (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )              
02110       {
02111         if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
02112         {
02113           if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
02114           {
02115             SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
02116           
02117             /* Delay for temperature sensor stabilization time */
02118             /* Compute number of CPU cycles to wait for */
02119             wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
02120             while(wait_loop_index != 0)
02121             {
02122               wait_loop_index--;
02123             }
02124           }
02125         }
02126         else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
02127         { 
02128           if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02129           {
02130             SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
02131           }
02132         }
02133         else if (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
02134         { 
02135           if (ADC_VREFINT_INSTANCE(hadc))
02136           {
02137             SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
02138           }                       
02139         }       
02140       }
02141       /* If the requested internal measurement path has already been enabled  */
02142       /* and other ADC of the common group are enabled, internal              */
02143       /* measurement paths cannot be enabled.                                 */
02144       else  
02145       {
02146         /* Update ADC state machine to error */
02147         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02148         
02149         tmp_status = HAL_ERROR;
02150       }
02151     }
02152     
02153   } /* if (ADC_IS_ENABLE(hadc) == RESET) */
02154   
02155   /* Process unlocked */
02156   __HAL_UNLOCK(hadc);
02157 
02158   /* Return function status */
02159   return tmp_status;
02160 }
02161 
02162 
02163 
02164 
02165 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
02166 /**
02167   * @brief  Enable ADC multimode and configure multimode parameters
02168   * @note   Possibility to update parameters on the fly:
02169   *         This function initializes multimode parameters, following  
02170   *         calls to this function can be used to reconfigure some parameters 
02171   *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting 
02172   *         the ADCs.
02173   *         The setting of these parameters is conditioned to ADC state.
02174   *         For parameters constraints, see comments of structure 
02175   *         "ADC_MultiModeTypeDef".
02176   * @note   To move back configuration from multimode to single mode, ADC must
02177   *         be reset (using function HAL_ADC_Init() ).
02178   * @param  hadc: Master ADC handle
02179   * @param  multimode : Structure of ADC multimode configuration
02180   * @retval HAL status
02181   */
02182 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
02183 {
02184   HAL_StatusTypeDef  tmp_status = HAL_OK;
02185   ADC_Common_TypeDef *tmpADC_Common;
02186   ADC_HandleTypeDef  tmphadcSlave;
02187   
02188   /* Check the parameters */
02189   assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
02190   assert_param(IS_ADC_MULTIMODE(multimode->Mode));
02191   if(multimode->Mode != ADC_MODE_INDEPENDENT)
02192   {
02193     assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(multimode->DMAAccessMode));
02194     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
02195   }
02196   
02197   /* Process locked */
02198   __HAL_LOCK(hadc);
02199 
02200   ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
02201   
02202   /* Parameters update conditioned to ADC state:                              */
02203   /* Parameters that can be updated when ADC is disabled or enabled without   */
02204   /* conversion on going on regular group:                                    */
02205   /*  - Multimode DMA configuration                                           */
02206   /*  - Multimode DMA mode                                                    */
02207   if ( (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 
02208     && (ADC_IS_CONVERSION_ONGOING_REGULAR(&tmphadcSlave) == RESET) )
02209   {
02210     /* Pointer to the common control register */
02211     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
02212     
02213     /* If multimode is selected, configure all multimode paramaters.          */
02214     /* Otherwise, reset multimode parameters (can be used in case of          */
02215     /* transition from multimode to independent mode).                        */
02216     if(multimode->Mode != ADC_MODE_INDEPENDENT)
02217     {
02218       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, 
02219                  multimode->DMAAccessMode |
02220                  ADC_CCR_MULTI_DMACONTREQ(hadc->Init.DMAContinuousRequests));
02221       
02222       /* Parameters that can be updated only when ADC is disabled:                */
02223       /*  - Multimode mode selection                                              */
02224       /*  - Multimode delay                                                       */
02225       /*    Note: Delay range depends on selected resolution:                     */
02226       /*      from 1 to 12 clock cycles for 12 bits                               */
02227       /*      from 1 to 10 clock cycles for 10 bits,                              */
02228       /*      from 1 to 8 clock cycles for 8 bits                                 */
02229       /*      from 1 to 6 clock cycles for 6 bits                                 */
02230       /*    If a higher delay is selected, it will be clipped to maximum delay    */
02231       /*    range                                                                 */
02232       if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
02233           (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
02234       {
02235           MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY, 
02236                      multimode->Mode | multimode->TwoSamplingDelay );
02237       }
02238     }
02239     else /* ADC_MODE_INDEPENDENT */
02240     {
02241       CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
02242       
02243       /* Parameters that can be updated only when ADC is disabled:                */
02244       /*  - Multimode mode selection                                              */
02245       /*  - Multimode delay                                                       */
02246       if ((ADC_IS_ENABLE(hadc) == RESET)                             &&
02247           (ADC_IS_ENABLE(&tmphadcSlave) == RESET)  )
02248       {
02249         CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
02250       }
02251     }
02252   }
02253   /* If one of the ADC sharing the same common group is enabled, no update    */
02254   /* could be done on neither of the multimode structure parameters.          */
02255   else
02256   {
02257     /* Update ADC state machine to error */
02258     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02259     
02260     tmp_status = HAL_ERROR;
02261   }
02262     
02263     
02264   /* Process unlocked */
02265   __HAL_UNLOCK(hadc);
02266   
02267   /* Return function status */
02268   return tmp_status;
02269 } 
02270 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
02271 
02272 
02273 /**
02274   * @brief  Enable Injected Queue
02275   * @note   This function resets CFGR register JQDIS bit in order to enable the
02276   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02277   *         are both equal to 0 to ensure that no regular nor injected 
02278   *         conversion is ongoing. 
02279   * @param  hadc: ADC handle
02280   * @retval HAL status
02281   */
02282 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc)
02283 {
02284 
02285   /* Parameter can be set only if no conversion is on-going                   */
02286   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02287   {
02288     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02289     
02290     /* Update state, clear previous result related to injected queue overflow */
02291     CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
02292     
02293     return HAL_OK;
02294   }
02295   else
02296   {
02297     return HAL_ERROR;
02298   }
02299 
02300 }
02301 
02302 /**
02303   * @brief  Disable Injected Queue
02304   * @note   This function sets CFGR register JQDIS bit in order to disable the
02305   *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
02306   *         are both equal to 0 to ensure that no regular nor injected 
02307   *         conversion is ongoing. 
02308   * @param  hadc: ADC handle
02309   * @retval HAL status
02310   */
02311 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc)
02312 {
02313 
02314   /* Parameter can be set only if no conversion is on-going                   */
02315   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02316   {
02317     SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
02318     return HAL_OK;    
02319   }
02320   else
02321   {
02322     return HAL_ERROR;
02323   }
02324 
02325 }
02326 
02327 
02328 /**
02329   * @brief  Disable ADC voltage regulator.
02330   * @note   Disabling voltage regulator allows to save power. This operation can
02331   *         be carried out only when ADC is disabled.
02332   * @note   To enable again the voltage regulator, the user is expected to 
02333   *         resort to HAL_ADC_Init() API.           
02334   * @param  hadc: ADC handle
02335   * @retval HAL status
02336   */
02337 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc)
02338 {
02339 
02340   /* ADVREGEN can be written only when the ADC is disabled  */
02341   if (ADC_IS_ENABLE(hadc) == RESET)
02342   {
02343     CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
02344     return HAL_OK;    
02345   }
02346   else
02347   {
02348     return HAL_ERROR;
02349   }
02350 }
02351 
02352 /**
02353   * @brief  Enter ADC deep-power-down mode
02354   * @note   This mode is achieved in setting DEEPPWD bit and allows to save power 
02355   *         in reducing leakage currents. It is particularly interesting before 
02356   *         entering stop modes.
02357   * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
02358   *         ADC voltage regulator. This means that this API encompasses
02359   *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
02360   *         calibration is lost.    
02361   * @note   To exit the ADC deep-power-down mode, the user is expected to 
02362   *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
02363   *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
02364   *         saved calibration factor.
02365   * @param  hadc: ADC handle
02366   * @retval HAL status
02367   */
02368 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc)
02369 {
02370 
02371   /* DEEPPWD can be written only when the ADC is disabled  */
02372   if (ADC_IS_ENABLE(hadc) == RESET)
02373   {
02374     SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
02375     return HAL_OK;    
02376   }
02377   else
02378   {
02379     return HAL_ERROR;
02380   }
02381 }
02382 
02383 /**
02384   * @}
02385   */
02386 
02387 /**
02388   * @}
02389   */
02390   
02391 
02392   
02393 #endif /* HAL_ADC_MODULE_ENABLED */
02394 /**
02395   * @}
02396   */
02397 
02398 /**
02399   * @}
02400   */ 
02401 
02402 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/