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stm32l4xx_hal_adc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of ADC HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_ADC_H 00040 #define __STM32L4xx_ADC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup ADC 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup ADC_Exported_Types ADC Exported Types 00059 * @{ 00060 */ 00061 00062 00063 /** 00064 * @brief ADC Regular Conversion Oversampling structure definition 00065 */ 00066 typedef struct 00067 { 00068 uint32_t Ratio; /*!< Configures the oversampling ratio. 00069 This parameter can be a value of @ref ADCEx_Oversampling_Ratio */ 00070 00071 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00072 This parameter can be a value of @ref ADCEx_Right_Bit_Shift */ 00073 00074 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 00075 This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */ 00076 00077 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 00078 The oversampling is either temporary stopped or reset upon an injected 00079 sequence interruption. 00080 If oversampling is enabled on both regular and injected groups, this parameter 00081 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 00082 (the oversampling buffer is zeroed during injection sequence). 00083 This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */ 00084 00085 }ADC_OversamplingTypeDef; 00086 00087 00088 00089 00090 /** @defgroup ADC_States ADC States 00091 * @{ 00092 */ 00093 00094 /** 00095 * @brief HAL ADC state machine: ADC State bitfield definition 00096 */ 00097 /* States of ADC global scope */ 00098 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ 00099 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ 00100 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy because of an internal process (initialization, calibration) */ 00101 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ 00102 00103 /* States of ADC errors */ 00104 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ 00105 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ 00106 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ 00107 00108 /* States of ADC regular group */ 00109 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A regular conversion is ongoing or can occur (either by continuous mode, 00110 external trigger, low power auto power-on, multimode ADC master control 00111 when multimode feature available) */ 00112 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Regular conversion data available */ 00113 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ 00114 #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< End Of Sampling flag raised */ 00115 00116 /* States of ADC injected group */ 00117 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< An injected conversion is ongoing or can occur (either by auto-injection mode, 00118 external trigger, low power auto power-on, multimode ADC master control 00119 when multimode feature available) */ 00120 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Injected conversion data available */ 00121 #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */ 00122 00123 /* States of ADC analog watchdogs */ 00124 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of Analog Watchdog 1 */ 00125 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of Analog Watchdog 2 */ 00126 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of Analog Watchdog 3 */ 00127 00128 /* States of ADC multi-mode when feature available */ 00129 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 00130 00131 /** 00132 * @} 00133 */ 00134 00135 /** 00136 * @brief ADC Injection Configuration 00137 */ 00138 typedef struct 00139 { 00140 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 00141 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 00142 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 00143 00144 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 00145 }ADC_InjectionConfigTypeDef; 00146 00147 00148 00149 00150 /** 00151 * @brief Structure definition of ADC channel for regular group 00152 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned by ADC state. 00153 * ADC state can be either: 00154 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 00155 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 00156 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 00157 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00158 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter 00159 * (which fulfills the ADC state condition) on the fly). 00160 */ 00161 typedef struct 00162 { 00163 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. 00164 This parameter can be a value of @ref ADC_channels 00165 Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */ 00166 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. 00167 This parameter can be a value of @ref ADCEx_regular_rank 00168 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00169 the new channel setting (or parameter number of conversions adjusted) */ 00170 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 00171 Unit: ADC clock cycles 00172 Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 00173 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00174 This parameter can be a value of @ref ADC_sampling_times 00175 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00176 It overwrites the last setting. 00177 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00178 sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time setting) 00179 Refer to device DataSheet for timings values. */ 00180 uint32_t SingleDiff; /*!< Selection of single-ended or differential input. 00181 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00182 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00183 This parameter must be a value of @ref ADCEx_SingleDifferential 00184 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00185 It overwrites the last setting. 00186 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00187 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00188 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00189 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case 00190 of another parameter update on the fly) */ 00191 uint32_t OffsetNumber; /*!< Selects the offset number 00192 This parameter can be a value of @ref ADCEx_OffsetNumber 00193 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00194 uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data. 00195 Offset value must be a positive number. 00196 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 00197 0x3FF, 0xFF or 0x3F respectively. 00198 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00199 without continuous mode or external trigger that could launch a conversion). */ 00200 }ADC_ChannelConfTypeDef; 00201 00202 00203 /** 00204 * @brief Structure definition of ADC analog watchdog 00205 * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned by ADC state. 00206 * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups. 00207 */ 00208 typedef struct 00209 { 00210 uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog is applied to the selected channel. 00211 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 00212 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 00213 This parameter can be a value of @ref ADCEx_analog_watchdog_number. */ 00214 uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group. 00215 For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset 00216 channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored. 00217 This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */ 00218 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. 00219 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 00220 For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel. 00221 Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE'). 00222 This parameter can be a value of @ref ADC_channels. */ 00223 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. 00224 This parameter can be set to ENABLE or DISABLE */ 00225 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. 00226 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 00227 0x3FF, 0xFF or 0x3F respectively. 00228 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00229 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ 00230 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 00231 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00232 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00233 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ 00234 }ADC_AnalogWDGConfTypeDef; 00235 00236 00237 /** 00238 * @} 00239 */ 00240 00241 /* Exported constants --------------------------------------------------------*/ 00242 00243 /** @defgroup ADC_Exported_Constants ADC Exported Constants 00244 * @{ 00245 */ 00246 00247 /** @defgroup ADC_Error_Code ADC Error Code 00248 * @{ 00249 */ 00250 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ 00251 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: problem of 00252 clocking, enable/disable, erroneous state */ 00253 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */ 00254 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */ 00255 #define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */ 00256 /** 00257 * @} 00258 */ 00259 00260 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler 00261 * @{ 00262 */ 00263 #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */ 00264 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ 00265 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ 00266 00267 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ 00268 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ 00269 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ 00270 00271 #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock not divided */ 00272 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 2 */ 00273 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock divided by 4 */ 00274 #define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 6 */ 00275 #define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock divided by 8 */ 00276 #define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 10 */ 00277 #define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 12 */ 00278 #define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16 */ 00279 #define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock divided by 32 */ 00280 #define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 64 */ 00281 #define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 128 */ 00282 #define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */ 00283 /** 00284 * @} 00285 */ 00286 00287 00288 /** @defgroup ADC_Resolution ADC Resolution 00289 * @{ 00290 */ 00291 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ 00292 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 10-bit resolution */ 00293 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 8-bit resolution */ 00294 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /*!< ADC 6-bit resolution */ 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup ADC_Data_align ADC Data Alignment 00300 * @{ 00301 */ 00302 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000) /*!< Data right alignment */ 00303 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN) /*!< Data left alignment */ 00304 /** 00305 * @} 00306 */ 00307 00308 /** @defgroup ADC_Scan_mode ADC Scan Mode 00309 * @{ 00310 */ 00311 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ 00312 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ 00313 /** 00314 * @} 00315 */ 00316 00317 /** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group 00318 * @{ 00319 */ 00320 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */ 00321 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ 00322 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ 00323 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ 00324 /** 00325 * @} 00326 */ 00327 00328 /** @defgroup ADC_Regular_External_Trigger_Source ADC External Trigger Source for Regular Group 00329 * @{ 00330 */ 00331 00332 /* External triggers of ADC regular group */ 00333 #define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000) /*!< Event 0 triggers regular group conversion start */ 00334 #define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0) /*!< Event 1 triggers regular group conversion start */ 00335 #define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1) /*!< Event 2 triggers regular group conversion start */ 00336 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 3 triggers regular group conversion start */ 00337 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2) /*!< Event 4 triggers regular group conversion start */ 00338 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 5 triggers regular group conversion start */ 00339 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 6 triggers regular group conversion start */ 00340 #define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 7 triggers regular group conversion start */ 00341 #define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3) /*!< Event 8 triggers regular group conversion start */ 00342 #define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0)) /*!< Event 9 triggers regular group conversion start */ 00343 #define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1)) /*!< Event 10 triggers regular group conversion start */ 00344 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0)) /*!< Event 11 triggers regular group conversion start */ 00345 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2)) /*!< Event 12 triggers regular group conversion start */ 00346 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0)) /*!< Event 13 triggers regular group conversion start */ 00347 #define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1)) /*!< Event 14 triggers regular group conversion start */ 00348 #define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL) /*!< Event 15 triggers regular group conversion start */ 00349 00350 #define ADC_SOFTWARE_START ((uint32_t)0x00000001) /*!< Software triggers regular group conversion start */ 00351 /** 00352 * @} 00353 */ 00354 00355 00356 /** @defgroup ADC_EOCSelection ADC End of Regular Sequence/Conversion 00357 * @{ 00358 */ 00359 #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of conversion flag */ 00360 #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence flag */ 00361 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< Reserved for future use */ 00362 /** 00363 * @} 00364 */ 00365 00366 /** @defgroup ADC_Overrun ADC overrun 00367 * @{ 00368 */ 00369 #define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /*!< Data preserved in case of overrun */ 00370 #define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD) /*!< Data overwritten in case of overrun */ 00371 /** 00372 * @} 00373 */ 00374 00375 /** @defgroup ADC_channels ADC Channels 00376 * @{ 00377 */ 00378 #define ADC_CHANNEL_0 ((uint32_t)(0x00000000)) /*!< ADC channel 0 */ 00379 #define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0)) /*!< ADC channel 1 */ 00380 #define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1)) /*!< ADC channel 2 */ 00381 #define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 3 */ 00382 #define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2)) /*!< ADC channel 4 */ 00383 #define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 5 */ 00384 #define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 6 */ 00385 #define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 7 */ 00386 #define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3)) /*!< ADC channel 8 */ 00387 #define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0)) /*!< ADC channel 9 */ 00388 #define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1)) /*!< ADC channel 10 */ 00389 #define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 11 */ 00390 #define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2)) /*!< ADC channel 12 */ 00391 #define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0)) /*!< ADC channel 13 */ 00392 #define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1)) /*!< ADC channel 14 */ 00393 #define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0)) /*!< ADC channel 15 */ 00394 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4)) /*!< ADC channel 16 */ 00395 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0)) /*!< ADC channel 17 */ 00396 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1)) /*!< ADC channel 18 */ 00397 00398 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on all ADC's 00399 (information present in Reference Manual) */ 00400 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_17 /*!< ADC temperature sensor channel */ 00401 #define ADC_CHANNEL_VBAT ADC_CHANNEL_18 /*!< ADC Vbat channel */ 00402 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_0 /*!< ADC Vrefint channel */ 00403 /** 00404 * @} 00405 */ 00406 00407 00408 00409 /** 00410 * @} 00411 */ 00412 00413 /* Private macros ------------------------------------------------------------*/ 00414 00415 /** @defgroup ADC_Private_Macro ADC Private Macros 00416 * @{ 00417 */ 00418 00419 /** 00420 * @brief Test if conversion trigger of regular group is software start 00421 * or external trigger. 00422 * @param __HANDLE__: ADC handle. 00423 * @retval SET (software start) or RESET (external trigger) 00424 */ 00425 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 00426 (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) 00427 00428 /** 00429 * @brief Return resolution bits in CFGR register RES[1:0] field. 00430 * @param __HANDLE__: ADC handle. 00431 * @retval 2-bit field RES of CFGR register. 00432 */ 00433 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES) 00434 00435 /** 00436 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 00437 * @param __HANDLE__: ADC handle. 00438 * @retval None 00439 */ 00440 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 00441 00442 /** 00443 * @brief Verification of ADC state: enabled or disabled. 00444 * @param __HANDLE__: ADC handle. 00445 * @retval SET (ADC enabled) or RESET (ADC disabled) 00446 */ 00447 #define ADC_IS_ENABLE(__HANDLE__) \ 00448 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 00449 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 00450 ) ? SET : RESET) 00451 00452 00453 /** 00454 * @brief Check if conversion is on going on regular group. 00455 * @param __HANDLE__: ADC handle. 00456 * @retval SET (conversion is on going) or RESET (no conversion is on going) 00457 */ 00458 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 00459 (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ 00460 ) ? RESET : SET) 00461 00462 00463 /** 00464 * @brief Simultaneously clear and set specific bits of the handle State. 00465 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 00466 * the first parameter is the ADC handle State, the second parameter is the 00467 * bit field to clear, the third and last parameter is the bit field to set. 00468 * @retval None 00469 */ 00470 #define ADC_STATE_CLR_SET MODIFY_REG 00471 00472 /** 00473 * @brief Verify that a given value is aligned with the ADC resolution range. 00474 * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits). 00475 * @param __ADC_VALUE__: value checked against the resolution. 00476 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 00477 */ 00478 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 00479 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ 00480 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ 00481 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ 00482 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))) ) 00483 00484 00485 /** 00486 * @brief Verify the length of the scheduled regular conversions group. 00487 * @param __LENGTH__: number of programmed conversions. 00488 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 00489 */ 00490 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) 00491 00492 00493 /** 00494 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 00495 * @param NUMBER: number of scheduled regular conversions in discontinuous mode. 00496 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large) 00497 */ 00498 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8))) 00499 00500 00501 /** 00502 * @brief Verify the ADC clock setting. 00503 * @param __ADC_CLOCK__: programmed ADC clock. 00504 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 00505 */ 00506 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 00507 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 00508 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 00509 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 00510 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 00511 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 00512 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 00513 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 00514 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 00515 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 00516 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 00517 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 00518 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 00519 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 00520 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 00521 00522 00523 /** 00524 * @brief Verify the ADC resolution setting. 00525 * @param __RESOLUTION__: programmed ADC resolution. 00526 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 00527 */ 00528 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 00529 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 00530 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 00531 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 00532 00533 /** 00534 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 00535 * @param __RESOLUTION__: programmed ADC resolution when limited to 6 or 8 bits. 00536 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 00537 */ 00538 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 00539 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 00540 00541 /** 00542 * @brief Verify the ADC converted data alignment. 00543 * @param __ALIGN__: programmed ADC converted data alignment. 00544 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 00545 */ 00546 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 00547 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 00548 00549 00550 /** 00551 * @brief Verify the ADC scan mode. 00552 * @param __SCAN_MODE__: programmed ADC scan mode. 00553 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 00554 */ 00555 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 00556 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 00557 00558 /** 00559 * @brief Verify the ADC edge trigger setting for regular group. 00560 * @param __EDGE__: programmed ADC edge trigger setting. 00561 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 00562 */ 00563 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 00564 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 00565 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 00566 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 00567 00568 00569 00570 /** 00571 * @brief Verify the ADC regular conversions external trigger. 00572 * @param __REGTRIG__: programmed ADC regular conversions external trigger. 00573 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 00574 */ 00575 #define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 00576 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 00577 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 00578 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 00579 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 00580 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 00581 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 00582 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 00583 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 00584 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 00585 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 00586 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 00587 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 00588 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 00589 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 00590 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 00591 \ 00592 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 00593 00594 00595 00596 /** 00597 * @brief Verify the ADC regular conversions check for converted data availability. 00598 * @param __EOC_SELECTION__: converted data availability check. 00599 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 00600 */ 00601 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 00602 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) || \ 00603 ((__EOC_SELECTION__) == ADC_EOC_SINGLE_SEQ_CONV) ) 00604 00605 /** 00606 * @brief Verify the ADC regular conversions overrun handling. 00607 * @param __OVR__: ADC regular conversions overrun handling. 00608 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 00609 */ 00610 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 00611 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 00612 00613 /** 00614 * @brief Verify the ADC conversions sampling time. 00615 * @param __TIME__: ADC conversions sampling time. 00616 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 00617 */ 00618 #if defined (ADC_SMPR1_SMPPLUS) 00619 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 00620 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 00621 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 00622 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 00623 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 00624 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 00625 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 00626 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 00627 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 00628 #else 00629 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 00630 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 00631 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 00632 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 00633 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 00634 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 00635 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 00636 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 00637 #endif 00638 /** 00639 * @} 00640 */ 00641 00642 00643 /* Private constants ---------------------------------------------------------*/ 00644 00645 /** @defgroup ADC_Private_Constants ADC Private Constants 00646 * @{ 00647 */ 00648 00649 /* Fixed timeout values for ADC conversion (including sampling time) */ 00650 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 00651 /* Maximum conversion time is 12.5 + Maximum sampling time */ 00652 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 00653 /* Minimum ADC Clock frequency is 0.14 MHz */ 00654 /* Maximum conversion time is */ 00655 /* 653 / 0.14 MHz = 4.66 ms */ 00656 #define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5) /*!< ADC stop time-out value */ 00657 00658 /* Delay for temperature sensor stabilization time. */ 00659 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 00660 /* Unit: us */ 00661 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120) 00662 00663 /** 00664 * @} 00665 */ 00666 00667 /* Exported macros -----------------------------------------------------------*/ 00668 00669 /** @defgroup ADC_Exported_Macro ADC Exported Macros 00670 * @{ 00671 */ 00672 00673 /** @brief Reset ADC handle state. 00674 * @param __HANDLE__: ADC handle. 00675 * @retval None 00676 */ 00677 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 00678 00679 00680 /** @brief Check whether the specified ADC interrupt source is enabled or not. 00681 * @param __HANDLE__: ADC handle. 00682 * @param __INTERRUPT__: ADC interrupt source to check 00683 * This parameter can be one of the following values: 00684 * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source 00685 * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source 00686 * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source 00687 * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source 00688 * @arg @ref ADC_IT_OVR, ADC overrun interrupt source 00689 * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source 00690 * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source 00691 * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) 00692 * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) 00693 * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) 00694 * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. 00695 * @retval State of interruption (SET or RESET) 00696 */ 00697 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 00698 (( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \ 00699 )? SET : RESET \ 00700 ) 00701 00702 /** 00703 * @brief Enable an ADC interrupt. 00704 * @param __HANDLE__: ADC handle. 00705 * @param __INTERRUPT__: ADC Interrupt to enable 00706 * This parameter can be one of the following values: 00707 * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source 00708 * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source 00709 * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source 00710 * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source 00711 * @arg @ref ADC_IT_OVR, ADC overrun interrupt source 00712 * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source 00713 * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source 00714 * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) 00715 * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) 00716 * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) 00717 * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. 00718 * @retval None 00719 */ 00720 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 00721 00722 /** 00723 * @brief Disable an ADC interrupt. 00724 * @param __HANDLE__: ADC handle. 00725 * @param __INTERRUPT__: ADC Interrupt to disable 00726 * @arg @ref ADC_IT_RDY, ADC Ready (ADRDY) interrupt source 00727 * @arg @ref ADC_IT_EOSMP, ADC End of Sampling interrupt source 00728 * @arg @ref ADC_IT_EOC, ADC End of Regular Conversion interrupt source 00729 * @arg @ref ADC_IT_EOS, ADC End of Regular sequence of Conversions interrupt source 00730 * @arg @ref ADC_IT_OVR, ADC overrun interrupt source 00731 * @arg @ref ADC_IT_JEOC, ADC End of Injected Conversion interrupt source 00732 * @arg @ref ADC_IT_JEOS, ADC End of Injected sequence of Conversions interrupt source 00733 * @arg @ref ADC_IT_AWD1, ADC Analog watchdog 1 interrupt source (main analog watchdog) 00734 * @arg @ref ADC_IT_AWD2, ADC Analog watchdog 2 interrupt source (additional analog watchdog) 00735 * @arg @ref ADC_IT_AWD3, ADC Analog watchdog 3 interrupt source (additional analog watchdog) 00736 * @arg @ref ADC_IT_JQOVF, ADC Injected Context Queue Overflow interrupt source. 00737 * @retval None 00738 */ 00739 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 00740 00741 /** 00742 * @brief Check whether the specified ADC flag is set or not. 00743 * @param __HANDLE__: ADC handle. 00744 * @param __FLAG__: ADC flag to check 00745 * This parameter can be one of the following values: 00746 * @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag 00747 * @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag 00748 * @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag 00749 * @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag 00750 * @arg @ref ADC_FLAG_OVR, ADC overrun flag 00751 * @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag 00752 * @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag 00753 * @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog) 00754 * @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog) 00755 * @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog) 00756 * @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag. 00757 * @retval The new state of __FLAG__ (TRUE or FALSE). 00758 */ 00759 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 00760 00761 /** 00762 * @brief Clear a specified ADC flag. 00763 * @param __HANDLE__: ADC handle. 00764 * @param __FLAG__: ADC flag to clear 00765 * This parameter can be one of the following values: 00766 * @arg @ref ADC_FLAG_RDY, ADC Ready (ADRDY) flag 00767 * @arg @ref ADC_FLAG_EOSMP, ADC End of Sampling flag 00768 * @arg @ref ADC_FLAG_EOC, ADC End of Regular Conversion flag 00769 * @arg @ref ADC_FLAG_EOS, ADC End of Regular sequence of Conversions flag 00770 * @arg @ref ADC_FLAG_OVR, ADC overrun flag 00771 * @arg @ref ADC_FLAG_JEOC, ADC End of Injected Conversion flag 00772 * @arg @ref ADC_FLAG_JEOS, ADC End of Injected sequence of Conversions flag 00773 * @arg @ref ADC_FLAG_AWD1, ADC Analog watchdog 1 flag (main analog watchdog) 00774 * @arg @ref ADC_FLAG_AWD2, ADC Analog watchdog 2 flag (additional analog watchdog) 00775 * @arg @ref ADC_FLAG_AWD3, ADC Analog watchdog 3 flag (additional analog watchdog) 00776 * @arg @ref ADC_FLAG_JQOVF, ADC Injected Context Queue Overflow flag. 00777 * @note Bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR). 00778 * @retval None 00779 */ 00780 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 00781 00782 00783 /** 00784 * @} 00785 */ 00786 00787 /* Include ADC HAL Extended module */ 00788 #include "stm32l4xx_hal_adc_ex.h" 00789 00790 /* Exported functions --------------------------------------------------------*/ 00791 /** @addtogroup ADC_Exported_Functions ADC Exported Functions 00792 * @{ 00793 */ 00794 00795 /** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 00796 * @brief Initialization and Configuration functions 00797 * @{ 00798 */ 00799 /* Initialization and de-initialization functions **********************************/ 00800 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 00801 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 00802 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 00803 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 00804 /** 00805 * @} 00806 */ 00807 00808 /** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions 00809 * @brief IO operation functions 00810 * @{ 00811 */ 00812 /* Blocking mode: Polling */ 00813 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 00814 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 00815 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 00816 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 00817 00818 /* Non-blocking mode: Interruption */ 00819 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 00820 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 00821 00822 /* Non-blocking mode: DMA */ 00823 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 00824 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 00825 00826 /* ADC retrieve conversion value intended to be used with polling or interruption */ 00827 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 00828 00829 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 00830 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 00831 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 00832 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 00833 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 00834 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 00835 /** 00836 * @} 00837 */ 00838 00839 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 00840 * @brief Peripheral Control functions 00841 * @{ 00842 */ 00843 /* Peripheral Control functions ***********************************************/ 00844 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 00845 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 00846 /** 00847 * @} 00848 */ 00849 00850 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions 00851 * @brief ADC Peripheral State functions 00852 * @{ 00853 */ 00854 /* Peripheral State functions *************************************************/ 00855 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 00856 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 00857 /** 00858 * @} 00859 */ 00860 00861 /** 00862 * @} 00863 */ 00864 00865 /* Private functions -----------------------------------------------------------*/ 00866 /** @addtogroup ADC_Private_Functions ADC Private Functions 00867 * @{ 00868 */ 00869 00870 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); 00871 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 00872 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); 00873 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 00874 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 00875 void ADC_DMAError(DMA_HandleTypeDef *hdma); 00876 00877 /** 00878 * @} 00879 */ 00880 00881 /** 00882 * @} 00883 */ 00884 00885 /** 00886 * @} 00887 */ 00888 00889 #ifdef __cplusplus 00890 } 00891 #endif 00892 00893 #endif /*__STM32L4xx_ADC_H */ 00894 00895 00896 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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