stm32l4xx_hal.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file contains all the functions prototypes for the HAL
00008   *          module driver.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038 
00039 /* Define to prevent recursive inclusion -------------------------------------*/
00040 #ifndef __STM32L4xx_HAL_H
00041 #define __STM32L4xx_HAL_H
00042 
00043 #ifdef __cplusplus
00044  extern "C" {
00045 #endif
00046 
00047 /* Includes ------------------------------------------------------------------*/
00048 #include "stm32l4xx_hal_conf.h"
00049 
00050 /** @addtogroup STM32L4xx_HAL_Driver
00051   * @{
00052   */
00053 
00054 /** @addtogroup HAL
00055   * @{
00056   */
00057 
00058 /* Exported types ------------------------------------------------------------*/
00059 /* Exported constants --------------------------------------------------------*/
00060 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
00061   * @{
00062   */
00063 
00064 /** @defgroup SYSCFG_BootMode Boot Mode
00065   * @{
00066   */
00067 #define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
00068 #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0
00069 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00070 #define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1
00071 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00072 #define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
00073 #define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
00074 
00075 /**
00076   * @}
00077   */
00078 
00079 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
00080   * @{
00081   */
00082 #define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
00083 #define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
00084 #define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
00085 #define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
00086 #define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
00087 #define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
00088 
00089 /**
00090   * @}
00091   */
00092 
00093 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
00094   * @{
00095   */
00096 #define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
00097 #define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
00098 #define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
00099 #define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
00100 #define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
00101 #define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
00102 #define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
00103 #define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
00104 #define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
00105 #define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
00106 #define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
00107 #define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
00108 #define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
00109 #define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
00110 #define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
00111 #define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
00112 #define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
00113 #define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
00114 #define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
00115 #define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
00116 #define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
00117 #define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
00118 #define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
00119 #define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
00120 #define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
00121 #define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
00122 #define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
00123 #define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
00124 #define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
00125 #define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
00126 #define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
00127 #define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
00128 
00129 /**
00130   * @}
00131   */
00132 
00133 #if defined(VREFBUF)
00134 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
00135   * @{
00136   */
00137 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0  ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
00138 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
00139 
00140 /**
00141   * @}
00142   */
00143 
00144 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
00145   * @{
00146   */
00147 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
00148 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
00149 
00150 /**
00151   * @}
00152   */
00153 #endif /* VREFBUF */
00154 
00155 /** @defgroup SYSCFG_flags_definition Flags
00156   * @{
00157   */
00158 
00159 #define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */
00160 #define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */
00161 
00162 /**
00163   * @}
00164   */
00165 
00166 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
00167   * @{
00168   */
00169 
00170 /** @brief  Fast-mode Plus driving capability on a specific GPIO
00171   */  
00172 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
00173 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
00174 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00175 #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
00176 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00177 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00178 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
00179 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00180 
00181 /**
00182  * @}
00183  */
00184 
00185 /**
00186   * @}
00187   */
00188 
00189 /* Exported macros -----------------------------------------------------------*/
00190 
00191 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
00192   * @{
00193   */
00194 
00195 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
00196   */
00197 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00198 #define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00199 #define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
00200 #endif
00201 
00202 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00203 #define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00204 #define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
00205 #endif
00206 
00207 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00208 #define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00209 #define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
00210 #endif
00211 
00212 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00213 #define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00214 #define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
00215 #endif
00216 
00217 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00218 #define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00219 #define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
00220 #endif
00221 
00222 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00223 #define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00224 #define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
00225 #endif
00226 
00227 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
00228 #define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
00229 #define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
00230 #endif
00231 
00232 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00233 #define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00234 #define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
00235 #endif
00236 
00237 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00238 #define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00239 #define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
00240 #endif
00241 
00242 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00243 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00244 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
00245 #endif
00246 
00247 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00248 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00249 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
00250 #endif
00251 
00252 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00253 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00254 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
00255 #endif
00256 
00257 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
00258 #define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
00259 #define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
00260 #endif
00261 
00262 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00263 #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00264 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
00265 #endif
00266 
00267 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
00268 #define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
00269 #define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
00270 #endif
00271 
00272 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
00273 #define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
00274 #define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
00275 #endif
00276 
00277 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
00278 #define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
00279 #define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
00280 #endif
00281 
00282 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
00283 #define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
00284 #define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
00285 #endif
00286 
00287 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
00288 #define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
00289 #define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
00290 #endif
00291 
00292 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
00293 #define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
00294 #define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
00295 #endif
00296 
00297 /**
00298   * @}
00299   */
00300 
00301 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
00302   * @{
00303   */
00304 
00305 /** @brief  Main Flash memory mapped at 0x00000000.
00306   */
00307 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
00308 
00309 /** @brief  System Flash memory mapped at 0x00000000.
00310   */
00311 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
00312 
00313 /** @brief  Embedded SRAM mapped at 0x00000000.
00314   */
00315 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
00316 
00317 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00318 /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
00319   */
00320 #define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
00321 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00322 
00323 /** @brief  QUADSPI mapped at 0x00000000.
00324   */
00325 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
00326 
00327 /**
00328   * @brief  Return the boot mode as configured by user.
00329   * @retval The boot mode as configured by user. The returned value can be one
00330   *         of the following values:
00331   *           @arg @ref SYSCFG_BOOT_MAINFLASH
00332   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
00333   @if STM32L486xx
00334   *           @arg @ref SYSCFG_BOOT_FMC
00335   @endif
00336   *           @arg @ref SYSCFG_BOOT_SRAM
00337   *           @arg @ref SYSCFG_BOOT_QUADSPI
00338   */
00339 #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
00340 
00341 /** @brief  SRAM2 page write protection enable macro
00342   * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
00343   * @note   write protection can only be disabled by a system reset
00344   */
00345 #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
00346                                                          SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
00347                                                         }while(0)
00348 
00349 /** @brief  SRAM2 page write protection unlock prior to erase
00350   * @note   Writing a wrong key reactivates the write protection
00351   */
00352 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\
00353                                                  SYSCFG->SKR = 0x53;\
00354                                                 }while(0)
00355 
00356 /** @brief  SRAM2 erase
00357   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
00358   */
00359 #define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
00360 
00361 /** @brief  Floating Point Unit interrupt enable/disable macros
00362   * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
00363   */
00364 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00365                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00366                                                             }while(0)
00367 
00368 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
00369                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
00370                                                             }while(0)
00371 
00372 /** @brief  SYSCFG Break ECC lock.
00373   *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
00374   * @note   The selected configuration is locked and can be unlocked only by system reset.
00375   */
00376 #define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
00377 
00378 /** @brief  SYSCFG Break Cortex-M4 Lockup lock.
00379   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
00380   * @note   The selected configuration is locked and can be unlocked only by system reset.
00381   */
00382 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
00383 
00384 /** @brief  SYSCFG Break PVD lock.
00385   *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
00386   * @note   The selected configuration is locked and can be unlocked only by system reset.
00387   */
00388 #define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
00389 
00390 /** @brief  SYSCFG Break SRAM2 parity lock.
00391   *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
00392   * @note   The selected configuration is locked and can be unlocked by system reset.
00393   */
00394 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
00395 
00396 /** @brief  Check SYSCFG flag is set or not.
00397   * @param  __FLAG__: specifies the flag to check.
00398   *         This parameter can be one of the following values:
00399   *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
00400   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
00401   * @retval The new state of __FLAG__ (TRUE or FALSE).
00402   */
00403 #define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
00404 
00405 /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
00406   */
00407 #define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
00408 
00409 /** @brief  Fast-mode Plus driving capability enable/disable macros
00410   * @param __FASTMODEPLUS__: This parameter can be a value of : 
00411   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
00412   *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 
00413   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
00414   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
00415   */
00416 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00417                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00418                                                                }while(0)
00419 
00420 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
00421                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
00422                                                                }while(0)
00423 
00424 /**
00425   * @}
00426   */
00427 
00428 /* Private macros ------------------------------------------------------------*/
00429 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
00430   * @{
00431   */
00432 
00433 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
00434                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
00435                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
00436                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
00437                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
00438                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
00439 
00440 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
00441                                             ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
00442                                             ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
00443                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
00444 
00445 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
00446 
00447 #if defined(VREFBUF)
00448 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
00449                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
00450 
00451 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
00452                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
00453 
00454 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
00455 #endif /* VREFBUF */
00456 
00457 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
00458 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00459                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00460                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
00461                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00462 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
00463 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00464                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00465                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
00466 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
00467 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00468                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
00469                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
00470 #else
00471 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
00472                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
00473 #endif
00474 /**
00475   * @}
00476   */
00477 
00478 /* Exported functions --------------------------------------------------------*/
00479 
00480 /** @addtogroup HAL_Exported_Functions
00481   * @{
00482   */
00483 
00484 /** @addtogroup HAL_Exported_Functions_Group1
00485   * @{
00486   */
00487 
00488 /* Initialization and de-initialization functions  ******************************/
00489 HAL_StatusTypeDef HAL_Init(void);
00490 HAL_StatusTypeDef HAL_DeInit(void);
00491 void HAL_MspInit(void);
00492 void HAL_MspDeInit(void);
00493 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
00494 
00495 /**
00496   * @}
00497   */
00498 
00499 /** @addtogroup HAL_Exported_Functions_Group2
00500   * @{
00501   */
00502 
00503 /* Peripheral Control functions  ************************************************/
00504 void HAL_IncTick(void);
00505 void HAL_Delay(uint32_t Delay);
00506 uint32_t HAL_GetTick(void);
00507 void HAL_SuspendTick(void);
00508 void HAL_ResumeTick(void);
00509 uint32_t HAL_GetHalVersion(void);
00510 uint32_t HAL_GetREVID(void);
00511 uint32_t HAL_GetDEVID(void);
00512 
00513 /**
00514   * @}
00515   */
00516 
00517 /** @addtogroup HAL_Exported_Functions_Group3
00518   * @{
00519   */
00520 
00521 /* DBGMCU Peripheral Control functions  *****************************************/
00522 void HAL_DBGMCU_EnableDBGSleepMode(void);
00523 void HAL_DBGMCU_DisableDBGSleepMode(void);
00524 void HAL_DBGMCU_EnableDBGStopMode(void);
00525 void HAL_DBGMCU_DisableDBGStopMode(void);
00526 void HAL_DBGMCU_EnableDBGStandbyMode(void);
00527 void HAL_DBGMCU_DisableDBGStandbyMode(void);
00528 
00529 /**
00530   * @}
00531   */
00532 
00533 /** @addtogroup HAL_Exported_Functions_Group4
00534   * @{
00535   */
00536 
00537 /* SYSCFG Control functions  ****************************************************/
00538 void HAL_SYSCFG_SRAM2Erase(void);
00539 void HAL_SYSCFG_EnableMemorySwappingBank(void);
00540 void HAL_SYSCFG_DisableMemorySwappingBank(void);
00541 
00542 #if defined(VREFBUF)
00543 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
00544 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
00545 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
00546 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
00547 void HAL_SYSCFG_DisableVREFBUF(void);
00548 #endif /* VREFBUF */
00549 
00550 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
00551 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
00552 
00553 /**
00554   * @}
00555   */
00556 
00557 /**
00558   * @}
00559   */
00560 
00561 /**
00562   * @}
00563   */
00564 
00565 /**
00566   * @}
00567   */
00568 
00569 #ifdef __cplusplus
00570 }
00571 #endif
00572 
00573 #endif /* __STM32L4xx_HAL_H */
00574 
00575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/