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n25q128a.h
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00001 /** 00002 ****************************************************************************** 00003 * @file n25q128a.h 00004 * @author MCD Application Team 00005 * @version V1.0.0 00006 * @date 29-May-2015 00007 * @brief This file contains all the description of the N25Q128A QSPI memory. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __N25Q128A_H 00040 #define __N25Q128A_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 00048 /** @addtogroup BSP 00049 * @{ 00050 */ 00051 00052 /** @addtogroup Components 00053 * @{ 00054 */ 00055 00056 /** @addtogroup n25q128a 00057 * @{ 00058 */ 00059 00060 /** @defgroup N25Q128A_Exported_Types 00061 * @{ 00062 */ 00063 00064 /** 00065 * @} 00066 */ 00067 00068 /** @defgroup N25Q128A_Exported_Constants 00069 * @{ 00070 */ 00071 00072 /** 00073 * @brief N25Q128A Configuration 00074 */ 00075 #define N25Q128A_FLASH_SIZE 0x1000000 /* 128 MBits => 16MBytes */ 00076 #define N25Q128A_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */ 00077 #define N25Q128A_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */ 00078 #define N25Q128A_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */ 00079 00080 #define N25Q128A_DUMMY_CYCLES_READ 8 00081 #define N25Q128A_DUMMY_CYCLES_READ_QUAD 10 00082 00083 #define N25Q128A_BULK_ERASE_MAX_TIME 250000 00084 #define N25Q128A_SECTOR_ERASE_MAX_TIME 3000 00085 #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME 800 00086 00087 /** 00088 * @brief N25Q128A Commands 00089 */ 00090 /* Reset Operations */ 00091 #define RESET_ENABLE_CMD 0x66 00092 #define RESET_MEMORY_CMD 0x99 00093 00094 /* Identification Operations */ 00095 #define READ_ID_CMD 0x9E 00096 #define READ_ID_CMD2 0x9F 00097 #define MULTIPLE_IO_READ_ID_CMD 0xAF 00098 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A 00099 00100 /* Read Operations */ 00101 #define READ_CMD 0x03 00102 #define FAST_READ_CMD 0x0B 00103 #define DUAL_OUT_FAST_READ_CMD 0x3B 00104 #define DUAL_INOUT_FAST_READ_CMD 0xBB 00105 #define QUAD_OUT_FAST_READ_CMD 0x6B 00106 #define QUAD_INOUT_FAST_READ_CMD 0xEB 00107 00108 /* Write Operations */ 00109 #define WRITE_ENABLE_CMD 0x06 00110 #define WRITE_DISABLE_CMD 0x04 00111 00112 /* Register Operations */ 00113 #define READ_STATUS_REG_CMD 0x05 00114 #define WRITE_STATUS_REG_CMD 0x01 00115 00116 #define READ_LOCK_REG_CMD 0xE8 00117 #define WRITE_LOCK_REG_CMD 0xE5 00118 00119 #define READ_FLAG_STATUS_REG_CMD 0x70 00120 #define CLEAR_FLAG_STATUS_REG_CMD 0x50 00121 00122 #define READ_NONVOL_CFG_REG_CMD 0xB5 00123 #define WRITE_NONVOL_CFG_REG_CMD 0xB1 00124 00125 #define READ_VOL_CFG_REG_CMD 0x85 00126 #define WRITE_VOL_CFG_REG_CMD 0x81 00127 00128 #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 00129 #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 00130 00131 /* Program Operations */ 00132 #define PAGE_PROG_CMD 0x02 00133 #define DUAL_IN_FAST_PROG_CMD 0xA2 00134 #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 00135 #define QUAD_IN_FAST_PROG_CMD 0x32 00136 #define EXT_QUAD_IN_FAST_PROG_CMD 0x12 00137 00138 /* Erase Operations */ 00139 #define SUBSECTOR_ERASE_CMD 0x20 00140 #define SECTOR_ERASE_CMD 0xD8 00141 #define BULK_ERASE_CMD 0xC7 00142 00143 #define PROG_ERASE_RESUME_CMD 0x7A 00144 #define PROG_ERASE_SUSPEND_CMD 0x75 00145 00146 /* One-Time Programmable Operations */ 00147 #define READ_OTP_ARRAY_CMD 0x4B 00148 #define PROG_OTP_ARRAY_CMD 0x42 00149 00150 /** 00151 * @brief N25Q128A Registers 00152 */ 00153 /* Status Register */ 00154 #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ 00155 #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ 00156 #define N25Q128A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ 00157 #define N25Q128A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */ 00158 #define N25Q128A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ 00159 00160 /* Nonvolatile Configuration Register */ 00161 #define N25Q128A_NVCR_LOCK ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */ 00162 #define N25Q128A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */ 00163 #define N25Q128A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */ 00164 #define N25Q128A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */ 00165 #define N25Q128A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */ 00166 #define N25Q128A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */ 00167 #define N25Q128A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */ 00168 00169 /* Volatile Configuration Register */ 00170 #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */ 00171 #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */ 00172 #define N25Q128A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */ 00173 00174 /* Enhanced Volatile Configuration Register */ 00175 #define N25Q128A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */ 00176 #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */ 00177 #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */ 00178 #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */ 00179 #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */ 00180 00181 /* Flag Status Register */ 00182 #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */ 00183 #define N25Q128A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */ 00184 #define N25Q128A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */ 00185 #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */ 00186 #define N25Q128A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */ 00187 #define N25Q128A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */ 00188 #define N25Q128A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */ 00189 00190 /** 00191 * @} 00192 */ 00193 00194 /** @defgroup N25Q128A_Exported_Functions 00195 * @{ 00196 */ 00197 /** 00198 * @} 00199 */ 00200 00201 /** 00202 * @} 00203 */ 00204 00205 /** 00206 * @} 00207 */ 00208 00209 /** 00210 * @} 00211 */ 00212 00213 #ifdef __cplusplus 00214 } 00215 #endif 00216 00217 #endif /* __N25Q128A_H */ 00218 00219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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