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HAL_L476/stm32l4xx_ll_i2c.h@3:b69e098b4613, 2017-02-25 (annotated)

Committer:: elmot
Date:: Sat Feb 25 09:03:15 2017 +0000
Revision:: 3:b69e098b4613
Parent:: 1:d0dfbce63a89

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elmot	1:d0dfbce63a89	1	/**
elmot	1:d0dfbce63a89	2	******************************************************************************
elmot	1:d0dfbce63a89	3	* @file stm32l4xx_ll_i2c.h
elmot	1:d0dfbce63a89	4	* @author MCD Application Team
elmot	1:d0dfbce63a89	5	* @version V1.5.1
elmot	1:d0dfbce63a89	6	* @date 31-May-2016
elmot	1:d0dfbce63a89	7	* @brief Header file of I2C LL module.
elmot	1:d0dfbce63a89	8	******************************************************************************
elmot	1:d0dfbce63a89	9	* @attention
elmot	1:d0dfbce63a89	10	*
elmot	1:d0dfbce63a89	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
elmot	1:d0dfbce63a89	12	*
elmot	1:d0dfbce63a89	13	* Redistribution and use in source and binary forms, with or without modification,
elmot	1:d0dfbce63a89	14	* are permitted provided that the following conditions are met:
elmot	1:d0dfbce63a89	15	* 1. Redistributions of source code must retain the above copyright notice,
elmot	1:d0dfbce63a89	16	* this list of conditions and the following disclaimer.
elmot	1:d0dfbce63a89	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
elmot	1:d0dfbce63a89	18	* this list of conditions and the following disclaimer in the documentation
elmot	1:d0dfbce63a89	19	* and/or other materials provided with the distribution.
elmot	1:d0dfbce63a89	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
elmot	1:d0dfbce63a89	21	* may be used to endorse or promote products derived from this software
elmot	1:d0dfbce63a89	22	* without specific prior written permission.
elmot	1:d0dfbce63a89	23	*
elmot	1:d0dfbce63a89	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
elmot	1:d0dfbce63a89	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
elmot	1:d0dfbce63a89	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
elmot	1:d0dfbce63a89	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
elmot	1:d0dfbce63a89	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
elmot	1:d0dfbce63a89	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
elmot	1:d0dfbce63a89	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
elmot	1:d0dfbce63a89	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
elmot	1:d0dfbce63a89	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
elmot	1:d0dfbce63a89	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
elmot	1:d0dfbce63a89	34	*
elmot	1:d0dfbce63a89	35	******************************************************************************
elmot	1:d0dfbce63a89	36	*/
elmot	1:d0dfbce63a89	37
elmot	1:d0dfbce63a89	38	/* Define to prevent recursive inclusion -------------------------------------*/
elmot	1:d0dfbce63a89	39	#ifndef __STM32L4xx_LL_I2C_H
elmot	1:d0dfbce63a89	40	#define __STM32L4xx_LL_I2C_H
elmot	1:d0dfbce63a89	41
elmot	1:d0dfbce63a89	42	#ifdef __cplusplus
elmot	1:d0dfbce63a89	43	extern "C" {
elmot	1:d0dfbce63a89	44	#endif
elmot	1:d0dfbce63a89	45
elmot	1:d0dfbce63a89	46	/* Includes ------------------------------------------------------------------*/
elmot	1:d0dfbce63a89	47	#include "stm32l4xx.h"
elmot	1:d0dfbce63a89	48
elmot	1:d0dfbce63a89	49	/** @addtogroup STM32L4xx_LL_Driver
elmot	1:d0dfbce63a89	50	* @{
elmot	1:d0dfbce63a89	51	*/
elmot	1:d0dfbce63a89	52
elmot	1:d0dfbce63a89	53	#if defined (I2C1) \|\| defined (I2C2) \|\| defined (I2C3)
elmot	1:d0dfbce63a89	54
elmot	1:d0dfbce63a89	55	/** @defgroup I2C_LL I2C
elmot	1:d0dfbce63a89	56	* @{
elmot	1:d0dfbce63a89	57	*/
elmot	1:d0dfbce63a89	58
elmot	1:d0dfbce63a89	59	/* Private types -------------------------------------------------------------*/
elmot	1:d0dfbce63a89	60	/* Private variables ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	61
elmot	1:d0dfbce63a89	62	/* Private constants ---------------------------------------------------------*/
elmot	1:d0dfbce63a89	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
elmot	1:d0dfbce63a89	64	* @{
elmot	1:d0dfbce63a89	65	*/
elmot	1:d0dfbce63a89	66	/* Defines used for the bit position in the register and perform offsets */
elmot	1:d0dfbce63a89	67	#define I2C_POSITION_CR1_DNF (uint32_t)POSITION_VAL(I2C_CR1_DNF)
elmot	1:d0dfbce63a89	68	#define I2C_POSITION_CR2_NBYTES (uint32_t)POSITION_VAL(I2C_CR2_NBYTES)
elmot	1:d0dfbce63a89	69	#define I2C_POSITION_TIMINGR_PRESC (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)
elmot	1:d0dfbce63a89	70	#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)
elmot	1:d0dfbce63a89	71	#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)
elmot	1:d0dfbce63a89	72	#define I2C_POSITION_TIMINGR_SCLH (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)
elmot	1:d0dfbce63a89	73	#define I2C_POSITION_TIMINGR_SCLL (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)
elmot	1:d0dfbce63a89	74	#define I2C_POSITION_ISR_ADDCODE (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE)
elmot	1:d0dfbce63a89	75	#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB)
elmot	1:d0dfbce63a89	76	/**
elmot	1:d0dfbce63a89	77	* @}
elmot	1:d0dfbce63a89	78	*/
elmot	1:d0dfbce63a89	79
elmot	1:d0dfbce63a89	80	/* Private macros ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	81	#if defined(USE_FULL_LL_DRIVER)
elmot	1:d0dfbce63a89	82	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
elmot	1:d0dfbce63a89	83	* @{
elmot	1:d0dfbce63a89	84	*/
elmot	1:d0dfbce63a89	85	/**
elmot	1:d0dfbce63a89	86	* @}
elmot	1:d0dfbce63a89	87	*/
elmot	1:d0dfbce63a89	88	#endif /USE_FULL_LL_DRIVER/
elmot	1:d0dfbce63a89	89
elmot	1:d0dfbce63a89	90	/* Exported types ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	91	#if defined(USE_FULL_LL_DRIVER)
elmot	1:d0dfbce63a89	92	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
elmot	1:d0dfbce63a89	93	* @{
elmot	1:d0dfbce63a89	94	*/
elmot	1:d0dfbce63a89	95	typedef struct
elmot	1:d0dfbce63a89	96	{
elmot	1:d0dfbce63a89	97	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
elmot	1:d0dfbce63a89	98	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
elmot	1:d0dfbce63a89	99
elmot	1:d0dfbce63a89	100	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
elmot	1:d0dfbce63a89	101
elmot	1:d0dfbce63a89	102	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
elmot	1:d0dfbce63a89	103	This parameter must be set by referring to the STM32CubeMX Tool and
elmot	1:d0dfbce63a89	104	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
elmot	1:d0dfbce63a89	105
elmot	1:d0dfbce63a89	106	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
elmot	1:d0dfbce63a89	107
elmot	1:d0dfbce63a89	108	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
elmot	1:d0dfbce63a89	109	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
elmot	1:d0dfbce63a89	110
elmot	1:d0dfbce63a89	111	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
elmot	1:d0dfbce63a89	112
elmot	1:d0dfbce63a89	113	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
elmot	1:d0dfbce63a89	114	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
elmot	1:d0dfbce63a89	115
elmot	1:d0dfbce63a89	116	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
elmot	1:d0dfbce63a89	117
elmot	1:d0dfbce63a89	118	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
elmot	1:d0dfbce63a89	119	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
elmot	1:d0dfbce63a89	120
elmot	1:d0dfbce63a89	121	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
elmot	1:d0dfbce63a89	122
elmot	1:d0dfbce63a89	123	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
elmot	1:d0dfbce63a89	124	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
elmot	1:d0dfbce63a89	125
elmot	1:d0dfbce63a89	126	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
elmot	1:d0dfbce63a89	127
elmot	1:d0dfbce63a89	128	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
elmot	1:d0dfbce63a89	129	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
elmot	1:d0dfbce63a89	130
elmot	1:d0dfbce63a89	131	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
elmot	1:d0dfbce63a89	132	} LL_I2C_InitTypeDef;
elmot	1:d0dfbce63a89	133	/**
elmot	1:d0dfbce63a89	134	* @}
elmot	1:d0dfbce63a89	135	*/
elmot	1:d0dfbce63a89	136	#endif /USE_FULL_LL_DRIVER/
elmot	1:d0dfbce63a89	137
elmot	1:d0dfbce63a89	138	/* Exported constants --------------------------------------------------------*/
elmot	1:d0dfbce63a89	139	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
elmot	1:d0dfbce63a89	140	* @{
elmot	1:d0dfbce63a89	141	*/
elmot	1:d0dfbce63a89	142
elmot	1:d0dfbce63a89	143	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
elmot	1:d0dfbce63a89	144	* @brief Flags defines which can be used with LL_I2C_WriteReg function
elmot	1:d0dfbce63a89	145	* @{
elmot	1:d0dfbce63a89	146	*/
elmot	1:d0dfbce63a89	147	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
elmot	1:d0dfbce63a89	148	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
elmot	1:d0dfbce63a89	149	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
elmot	1:d0dfbce63a89	150	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
elmot	1:d0dfbce63a89	151	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
elmot	1:d0dfbce63a89	152	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
elmot	1:d0dfbce63a89	153	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
elmot	1:d0dfbce63a89	154	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
elmot	1:d0dfbce63a89	155	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
elmot	1:d0dfbce63a89	156	/**
elmot	1:d0dfbce63a89	157	* @}
elmot	1:d0dfbce63a89	158	*/
elmot	1:d0dfbce63a89	159
elmot	1:d0dfbce63a89	160	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
elmot	1:d0dfbce63a89	161	* @brief Flags defines which can be used with LL_I2C_ReadReg function
elmot	1:d0dfbce63a89	162	* @{
elmot	1:d0dfbce63a89	163	*/
elmot	1:d0dfbce63a89	164	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
elmot	1:d0dfbce63a89	165	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
elmot	1:d0dfbce63a89	166	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
elmot	1:d0dfbce63a89	167	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
elmot	1:d0dfbce63a89	168	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
elmot	1:d0dfbce63a89	169	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
elmot	1:d0dfbce63a89	170	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
elmot	1:d0dfbce63a89	171	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
elmot	1:d0dfbce63a89	172	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
elmot	1:d0dfbce63a89	173	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
elmot	1:d0dfbce63a89	174	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
elmot	1:d0dfbce63a89	175	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
elmot	1:d0dfbce63a89	176	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
elmot	1:d0dfbce63a89	177	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
elmot	1:d0dfbce63a89	178	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
elmot	1:d0dfbce63a89	179	/**
elmot	1:d0dfbce63a89	180	* @}
elmot	1:d0dfbce63a89	181	*/
elmot	1:d0dfbce63a89	182
elmot	1:d0dfbce63a89	183	/** @defgroup I2C_LL_EC_IT IT Defines
elmot	1:d0dfbce63a89	184	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
elmot	1:d0dfbce63a89	185	* @{
elmot	1:d0dfbce63a89	186	*/
elmot	1:d0dfbce63a89	187	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
elmot	1:d0dfbce63a89	188	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
elmot	1:d0dfbce63a89	189	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
elmot	1:d0dfbce63a89	190	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
elmot	1:d0dfbce63a89	191	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
elmot	1:d0dfbce63a89	192	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
elmot	1:d0dfbce63a89	193	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
elmot	1:d0dfbce63a89	194	/**
elmot	1:d0dfbce63a89	195	* @}
elmot	1:d0dfbce63a89	196	*/
elmot	1:d0dfbce63a89	197
elmot	1:d0dfbce63a89	198	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
elmot	1:d0dfbce63a89	199	* @{
elmot	1:d0dfbce63a89	200	*/
elmot	1:d0dfbce63a89	201	#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /!< I2C Master or Slave mode /
elmot	1:d0dfbce63a89	202	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
elmot	1:d0dfbce63a89	203	#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /!< SMBus Device default mode (Default address not acknowledge) /
elmot	1:d0dfbce63a89	204	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
elmot	1:d0dfbce63a89	205	/**
elmot	1:d0dfbce63a89	206	* @}
elmot	1:d0dfbce63a89	207	*/
elmot	1:d0dfbce63a89	208
elmot	1:d0dfbce63a89	209	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
elmot	1:d0dfbce63a89	210	* @{
elmot	1:d0dfbce63a89	211	*/
elmot	1:d0dfbce63a89	212	#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /!< Analog filter is enabled. /
elmot	1:d0dfbce63a89	213	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
elmot	1:d0dfbce63a89	214	/**
elmot	1:d0dfbce63a89	215	* @}
elmot	1:d0dfbce63a89	216	*/
elmot	1:d0dfbce63a89	217
elmot	1:d0dfbce63a89	218	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
elmot	1:d0dfbce63a89	219	* @{
elmot	1:d0dfbce63a89	220	*/
elmot	1:d0dfbce63a89	221	#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /!< Master operates in 7-bit addressing mode. /
elmot	1:d0dfbce63a89	222	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
elmot	1:d0dfbce63a89	223	/**
elmot	1:d0dfbce63a89	224	* @}
elmot	1:d0dfbce63a89	225	*/
elmot	1:d0dfbce63a89	226
elmot	1:d0dfbce63a89	227	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
elmot	1:d0dfbce63a89	228	* @{
elmot	1:d0dfbce63a89	229	*/
elmot	1:d0dfbce63a89	230	#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /!< Own address 1 is a 7-bit address. /
elmot	1:d0dfbce63a89	231	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
elmot	1:d0dfbce63a89	232	/**
elmot	1:d0dfbce63a89	233	* @}
elmot	1:d0dfbce63a89	234	*/
elmot	1:d0dfbce63a89	235
elmot	1:d0dfbce63a89	236	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
elmot	1:d0dfbce63a89	237	* @{
elmot	1:d0dfbce63a89	238	*/
elmot	1:d0dfbce63a89	239	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
elmot	1:d0dfbce63a89	240	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
elmot	1:d0dfbce63a89	241	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
elmot	1:d0dfbce63a89	242	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
elmot	1:d0dfbce63a89	243	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
elmot	1:d0dfbce63a89	244	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
elmot	1:d0dfbce63a89	245	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
elmot	1:d0dfbce63a89	246	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
elmot	1:d0dfbce63a89	247	/**
elmot	1:d0dfbce63a89	248	* @}
elmot	1:d0dfbce63a89	249	*/
elmot	1:d0dfbce63a89	250
elmot	1:d0dfbce63a89	251	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
elmot	1:d0dfbce63a89	252	* @{
elmot	1:d0dfbce63a89	253	*/
elmot	1:d0dfbce63a89	254	#define LL_I2C_ACK ((uint32_t) 0x00000000U) /!< ACK is sent after current received byte. /
elmot	1:d0dfbce63a89	255	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
elmot	1:d0dfbce63a89	256	/**
elmot	1:d0dfbce63a89	257	* @}
elmot	1:d0dfbce63a89	258	*/
elmot	1:d0dfbce63a89	259
elmot	1:d0dfbce63a89	260	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
elmot	1:d0dfbce63a89	261	* @{
elmot	1:d0dfbce63a89	262	*/
elmot	1:d0dfbce63a89	263	#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /!< Slave Address in 7-bit. /
elmot	1:d0dfbce63a89	264	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
elmot	1:d0dfbce63a89	265	/**
elmot	1:d0dfbce63a89	266	* @}
elmot	1:d0dfbce63a89	267	*/
elmot	1:d0dfbce63a89	268
elmot	1:d0dfbce63a89	269	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
elmot	1:d0dfbce63a89	270	* @{
elmot	1:d0dfbce63a89	271	*/
elmot	1:d0dfbce63a89	272	#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /!< Master request a write transfer. /
elmot	1:d0dfbce63a89	273	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
elmot	1:d0dfbce63a89	274	/**
elmot	1:d0dfbce63a89	275	* @}
elmot	1:d0dfbce63a89	276	*/
elmot	1:d0dfbce63a89	277
elmot	1:d0dfbce63a89	278	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
elmot	1:d0dfbce63a89	279	* @{
elmot	1:d0dfbce63a89	280	*/
elmot	1:d0dfbce63a89	281	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
elmot	1:d0dfbce63a89	282	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
elmot	1:d0dfbce63a89	283	#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /!< Enable I2C Software end mode with no HW PEC comparison. /
elmot	1:d0dfbce63a89	284	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
elmot	1:d0dfbce63a89	285	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
elmot	1:d0dfbce63a89	286	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
elmot	1:d0dfbce63a89	287	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
elmot	1:d0dfbce63a89	288	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
elmot	1:d0dfbce63a89	289	/**
elmot	1:d0dfbce63a89	290	* @}
elmot	1:d0dfbce63a89	291	*/
elmot	1:d0dfbce63a89	292
elmot	1:d0dfbce63a89	293	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
elmot	1:d0dfbce63a89	294	* @{
elmot	1:d0dfbce63a89	295	*/
elmot	1:d0dfbce63a89	296	#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /!< Don't Generate Stop and Start condition. /
elmot	1:d0dfbce63a89	297	#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /!< Generate Stop condition (Size should be set to 0). /
elmot	1:d0dfbce63a89	298	#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
elmot	1:d0dfbce63a89	299	#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /!< Generate Start for write request. /
elmot	1:d0dfbce63a89	300	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
elmot	1:d0dfbce63a89	301	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 7Bit address. /
elmot	1:d0dfbce63a89	302	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
elmot	1:d0dfbce63a89	303	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 10Bit address./
elmot	1:d0dfbce63a89	304	/**
elmot	1:d0dfbce63a89	305	* @}
elmot	1:d0dfbce63a89	306	*/
elmot	1:d0dfbce63a89	307
elmot	1:d0dfbce63a89	308	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
elmot	1:d0dfbce63a89	309	* @{
elmot	1:d0dfbce63a89	310	*/
elmot	1:d0dfbce63a89	311	#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /!< Write transfer request by master, slave enters receiver mode. /
elmot	1:d0dfbce63a89	312	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
elmot	1:d0dfbce63a89	313	/**
elmot	1:d0dfbce63a89	314	* @}
elmot	1:d0dfbce63a89	315	*/
elmot	1:d0dfbce63a89	316
elmot	1:d0dfbce63a89	317	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
elmot	1:d0dfbce63a89	318	* @{
elmot	1:d0dfbce63a89	319	*/
elmot	1:d0dfbce63a89	320	#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /!< Get address of data register used for transmission /
elmot	1:d0dfbce63a89	321	#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /!< Get address of data register used for reception /
elmot	1:d0dfbce63a89	322	/**
elmot	1:d0dfbce63a89	323	* @}
elmot	1:d0dfbce63a89	324	*/
elmot	1:d0dfbce63a89	325
elmot	1:d0dfbce63a89	326	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
elmot	1:d0dfbce63a89	327	* @{
elmot	1:d0dfbce63a89	328	*/
elmot	1:d0dfbce63a89	329	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /!< TimeoutA is used to detect SCL low level timeout. /
elmot	1:d0dfbce63a89	330	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
elmot	1:d0dfbce63a89	331	/**
elmot	1:d0dfbce63a89	332	* @}
elmot	1:d0dfbce63a89	333	*/
elmot	1:d0dfbce63a89	334
elmot	1:d0dfbce63a89	335	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
elmot	1:d0dfbce63a89	336	* @{
elmot	1:d0dfbce63a89	337	*/
elmot	1:d0dfbce63a89	338	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
elmot	1:d0dfbce63a89	339	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
elmot	1:d0dfbce63a89	340	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
elmot	1:d0dfbce63a89	341	/**
elmot	1:d0dfbce63a89	342	* @}
elmot	1:d0dfbce63a89	343	*/
elmot	1:d0dfbce63a89	344
elmot	1:d0dfbce63a89	345	/**
elmot	1:d0dfbce63a89	346	* @}
elmot	1:d0dfbce63a89	347	*/
elmot	1:d0dfbce63a89	348
elmot	1:d0dfbce63a89	349	/* Exported macro ------------------------------------------------------------*/
elmot	1:d0dfbce63a89	350	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
elmot	1:d0dfbce63a89	351	* @{
elmot	1:d0dfbce63a89	352	*/
elmot	1:d0dfbce63a89	353
elmot	1:d0dfbce63a89	354	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
elmot	1:d0dfbce63a89	355	* @{
elmot	1:d0dfbce63a89	356	*/
elmot	1:d0dfbce63a89	357
elmot	1:d0dfbce63a89	358	/**
elmot	1:d0dfbce63a89	359	* @brief Write a value in I2C register
elmot	1:d0dfbce63a89	360	* @param __INSTANCE__ I2C Instance
elmot	1:d0dfbce63a89	361	* @param __REG__ Register to be written
elmot	1:d0dfbce63a89	362	* @param __VALUE__ Value to be written in the register
elmot	1:d0dfbce63a89	363	* @retval None
elmot	1:d0dfbce63a89	364	*/
elmot	1:d0dfbce63a89	365	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
elmot	1:d0dfbce63a89	366
elmot	1:d0dfbce63a89	367	/**
elmot	1:d0dfbce63a89	368	* @brief Read a value in I2C register
elmot	1:d0dfbce63a89	369	* @param __INSTANCE__ I2C Instance
elmot	1:d0dfbce63a89	370	* @param __REG__ Register to be read
elmot	1:d0dfbce63a89	371	* @retval Register value
elmot	1:d0dfbce63a89	372	*/
elmot	1:d0dfbce63a89	373	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
elmot	1:d0dfbce63a89	374	/**
elmot	1:d0dfbce63a89	375	* @}
elmot	1:d0dfbce63a89	376	*/
elmot	1:d0dfbce63a89	377
elmot	1:d0dfbce63a89	378	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
elmot	1:d0dfbce63a89	379	* @{
elmot	1:d0dfbce63a89	380	*/
elmot	1:d0dfbce63a89	381	/**
elmot	1:d0dfbce63a89	382	* @brief Configure the SDA setup, hold time and the SCL high, low period.
elmot	1:d0dfbce63a89	383	* @param __PRESCALER__ This parameter must be a value between 0 and 0xF.
elmot	1:d0dfbce63a89	384	* @param __DATA_SETUP_TIME__ This parameter must be a value between 0 and 0xF. (tscldel = (SCLDEL+1)xtpresc)
elmot	1:d0dfbce63a89	385	* @param __DATA_HOLD_TIME__ This parameter must be a value between 0 and 0xF. (tsdadel = SDADELxtpresc)
elmot	1:d0dfbce63a89	386	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between 0 and 0xFF. (tsclh = (SCLH+1)xtpresc)
elmot	1:d0dfbce63a89	387	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between 0 and 0xFF. (tscll = (SCLL+1)xtpresc)
elmot	1:d0dfbce63a89	388	* @retval Value between 0 and 0xFFFFFFFF
elmot	1:d0dfbce63a89	389	*/
elmot	1:d0dfbce63a89	390	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
elmot	1:d0dfbce63a89	391	((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) \| \
elmot	1:d0dfbce63a89	392	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) \| \
elmot	1:d0dfbce63a89	393	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) \| \
elmot	1:d0dfbce63a89	394	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) \| \
elmot	1:d0dfbce63a89	395	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL))
elmot	1:d0dfbce63a89	396	/**
elmot	1:d0dfbce63a89	397	* @}
elmot	1:d0dfbce63a89	398	*/
elmot	1:d0dfbce63a89	399
elmot	1:d0dfbce63a89	400	/**
elmot	1:d0dfbce63a89	401	* @}
elmot	1:d0dfbce63a89	402	*/
elmot	1:d0dfbce63a89	403
elmot	1:d0dfbce63a89	404	/* Exported functions --------------------------------------------------------*/
elmot	1:d0dfbce63a89	405	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
elmot	1:d0dfbce63a89	406	* @{
elmot	1:d0dfbce63a89	407	*/
elmot	1:d0dfbce63a89	408
elmot	1:d0dfbce63a89	409	/** @defgroup I2C_LL_EF_Configuration Configuration
elmot	1:d0dfbce63a89	410	* @{
elmot	1:d0dfbce63a89	411	*/
elmot	1:d0dfbce63a89	412
elmot	1:d0dfbce63a89	413	/**
elmot	1:d0dfbce63a89	414	* @brief Enable I2C peripheral (PE = 1).
elmot	1:d0dfbce63a89	415	* @rmtoll CR1 PE LL_I2C_Enable
elmot	1:d0dfbce63a89	416	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	417	* @retval None
elmot	1:d0dfbce63a89	418	*/
elmot	1:d0dfbce63a89	419	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	420	{
elmot	1:d0dfbce63a89	421	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
elmot	1:d0dfbce63a89	422	}
elmot	1:d0dfbce63a89	423
elmot	1:d0dfbce63a89	424	/**
elmot	1:d0dfbce63a89	425	* @brief Disable I2C peripheral (PE = 0).
elmot	1:d0dfbce63a89	426	* @note When PE = 0, the I2C SCL and SDA lines are released.
elmot	1:d0dfbce63a89	427	* Internal state machines and status bits are put back to their reset value.
elmot	1:d0dfbce63a89	428	* When cleared, PE must be kept low for at least 3 APB clock cycles.
elmot	1:d0dfbce63a89	429	* @rmtoll CR1 PE LL_I2C_Disable
elmot	1:d0dfbce63a89	430	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	431	* @retval None
elmot	1:d0dfbce63a89	432	*/
elmot	1:d0dfbce63a89	433	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	434	{
elmot	1:d0dfbce63a89	435	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
elmot	1:d0dfbce63a89	436	}
elmot	1:d0dfbce63a89	437
elmot	1:d0dfbce63a89	438	/**
elmot	1:d0dfbce63a89	439	* @brief Check if the I2C peripheral is enabled or disabled.
elmot	1:d0dfbce63a89	440	* @rmtoll CR1 PE LL_I2C_IsEnabled
elmot	1:d0dfbce63a89	441	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	442	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	443	*/
elmot	1:d0dfbce63a89	444	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	445	{
elmot	1:d0dfbce63a89	446	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
elmot	1:d0dfbce63a89	447	}
elmot	1:d0dfbce63a89	448
elmot	1:d0dfbce63a89	449	/**
elmot	1:d0dfbce63a89	450	* @brief Configure Noise Filters (Analog and Digital).
elmot	1:d0dfbce63a89	451	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
elmot	1:d0dfbce63a89	452	* The filters can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	453	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
elmot	1:d0dfbce63a89	454	* CR1 DNF LL_I2C_ConfigFilters
elmot	1:d0dfbce63a89	455	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	456	* @param AnalogFilter This parameter can be one of the following values:
elmot	1:d0dfbce63a89	457	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
elmot	1:d0dfbce63a89	458	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
elmot	1:d0dfbce63a89	459	* @param DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
elmot	1:d0dfbce63a89	460	* This parameter is used to configure the digital noise filter on SDA and SCL input.
elmot	1:d0dfbce63a89	461	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
elmot	1:d0dfbce63a89	462	* @retval None
elmot	1:d0dfbce63a89	463	*/
elmot	1:d0dfbce63a89	464	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
elmot	1:d0dfbce63a89	465	{
elmot	1:d0dfbce63a89	466	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_POSITION_CR1_DNF));
elmot	1:d0dfbce63a89	467	}
elmot	1:d0dfbce63a89	468
elmot	1:d0dfbce63a89	469	/**
elmot	1:d0dfbce63a89	470	* @brief Configure Digital Noise Filter.
elmot	1:d0dfbce63a89	471	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
elmot	1:d0dfbce63a89	472	* This filter can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	473	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
elmot	1:d0dfbce63a89	474	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	475	* @param DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
elmot	1:d0dfbce63a89	476	* This parameter is used to configure the digital noise filter on SDA and SCL input.
elmot	1:d0dfbce63a89	477	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
elmot	1:d0dfbce63a89	478	* @retval None
elmot	1:d0dfbce63a89	479	*/
elmot	1:d0dfbce63a89	480	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
elmot	1:d0dfbce63a89	481	{
elmot	1:d0dfbce63a89	482	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
elmot	1:d0dfbce63a89	483	}
elmot	1:d0dfbce63a89	484
elmot	1:d0dfbce63a89	485	/**
elmot	1:d0dfbce63a89	486	* @brief Get the current Digital Noise Filter configuration.
elmot	1:d0dfbce63a89	487	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
elmot	1:d0dfbce63a89	488	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	489	* @retval Value between Min_Data=0x0 and Max_Data=0xF
elmot	1:d0dfbce63a89	490	*/
elmot	1:d0dfbce63a89	491	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	492	{
elmot	1:d0dfbce63a89	493	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
elmot	1:d0dfbce63a89	494	}
elmot	1:d0dfbce63a89	495
elmot	1:d0dfbce63a89	496	/**
elmot	1:d0dfbce63a89	497	* @brief Enable Analog Noise Filter.
elmot	1:d0dfbce63a89	498	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	499	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
elmot	1:d0dfbce63a89	500	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	501	* @retval None
elmot	1:d0dfbce63a89	502	*/
elmot	1:d0dfbce63a89	503	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	504	{
elmot	1:d0dfbce63a89	505	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
elmot	1:d0dfbce63a89	506	}
elmot	1:d0dfbce63a89	507
elmot	1:d0dfbce63a89	508	/**
elmot	1:d0dfbce63a89	509	* @brief Disable Analog Noise Filter.
elmot	1:d0dfbce63a89	510	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	511	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
elmot	1:d0dfbce63a89	512	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	513	* @retval None
elmot	1:d0dfbce63a89	514	*/
elmot	1:d0dfbce63a89	515	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	516	{
elmot	1:d0dfbce63a89	517	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
elmot	1:d0dfbce63a89	518	}
elmot	1:d0dfbce63a89	519
elmot	1:d0dfbce63a89	520	/**
elmot	1:d0dfbce63a89	521	* @brief Check if Analog Noise Filter is enabled or disabled.
elmot	1:d0dfbce63a89	522	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
elmot	1:d0dfbce63a89	523	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	524	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	525	*/
elmot	1:d0dfbce63a89	526	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	527	{
elmot	1:d0dfbce63a89	528	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
elmot	1:d0dfbce63a89	529	}
elmot	1:d0dfbce63a89	530
elmot	1:d0dfbce63a89	531	/**
elmot	1:d0dfbce63a89	532	* @brief Enable DMA transmission requests.
elmot	1:d0dfbce63a89	533	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
elmot	1:d0dfbce63a89	534	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	535	* @retval None
elmot	1:d0dfbce63a89	536	*/
elmot	1:d0dfbce63a89	537	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	538	{
elmot	1:d0dfbce63a89	539	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
elmot	1:d0dfbce63a89	540	}
elmot	1:d0dfbce63a89	541
elmot	1:d0dfbce63a89	542	/**
elmot	1:d0dfbce63a89	543	* @brief Disable DMA transmission requests.
elmot	1:d0dfbce63a89	544	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
elmot	1:d0dfbce63a89	545	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	546	* @retval None
elmot	1:d0dfbce63a89	547	*/
elmot	1:d0dfbce63a89	548	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	549	{
elmot	1:d0dfbce63a89	550	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
elmot	1:d0dfbce63a89	551	}
elmot	1:d0dfbce63a89	552
elmot	1:d0dfbce63a89	553	/**
elmot	1:d0dfbce63a89	554	* @brief Check if DMA transmission requests are enabled or disabled.
elmot	1:d0dfbce63a89	555	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
elmot	1:d0dfbce63a89	556	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	557	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	558	*/
elmot	1:d0dfbce63a89	559	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	560	{
elmot	1:d0dfbce63a89	561	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
elmot	1:d0dfbce63a89	562	}
elmot	1:d0dfbce63a89	563
elmot	1:d0dfbce63a89	564	/**
elmot	1:d0dfbce63a89	565	* @brief Enable DMA reception requests.
elmot	1:d0dfbce63a89	566	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
elmot	1:d0dfbce63a89	567	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	568	* @retval None
elmot	1:d0dfbce63a89	569	*/
elmot	1:d0dfbce63a89	570	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	571	{
elmot	1:d0dfbce63a89	572	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
elmot	1:d0dfbce63a89	573	}
elmot	1:d0dfbce63a89	574
elmot	1:d0dfbce63a89	575	/**
elmot	1:d0dfbce63a89	576	* @brief Disable DMA reception requests.
elmot	1:d0dfbce63a89	577	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
elmot	1:d0dfbce63a89	578	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	579	* @retval None
elmot	1:d0dfbce63a89	580	*/
elmot	1:d0dfbce63a89	581	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	582	{
elmot	1:d0dfbce63a89	583	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
elmot	1:d0dfbce63a89	584	}
elmot	1:d0dfbce63a89	585
elmot	1:d0dfbce63a89	586	/**
elmot	1:d0dfbce63a89	587	* @brief Check if DMA reception requests are enabled or disabled.
elmot	1:d0dfbce63a89	588	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
elmot	1:d0dfbce63a89	589	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	590	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	591	*/
elmot	1:d0dfbce63a89	592	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	593	{
elmot	1:d0dfbce63a89	594	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
elmot	1:d0dfbce63a89	595	}
elmot	1:d0dfbce63a89	596
elmot	1:d0dfbce63a89	597	/**
elmot	1:d0dfbce63a89	598	* @brief Get the data register address used for DMA transfer
elmot	1:d0dfbce63a89	599	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
elmot	1:d0dfbce63a89	600	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
elmot	1:d0dfbce63a89	601	* @param I2Cx I2C Instance
elmot	1:d0dfbce63a89	602	* @param Direction This parameter can be one of the following values:
elmot	1:d0dfbce63a89	603	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
elmot	1:d0dfbce63a89	604	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
elmot	1:d0dfbce63a89	605	* @retval Address of data register
elmot	1:d0dfbce63a89	606	*/
elmot	1:d0dfbce63a89	607	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
elmot	1:d0dfbce63a89	608	{
elmot	1:d0dfbce63a89	609	register uint32_t data_reg_addr = 0U;
elmot	1:d0dfbce63a89	610
elmot	1:d0dfbce63a89	611	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
elmot	1:d0dfbce63a89	612	{
elmot	1:d0dfbce63a89	613	/* return address of TXDR register */
elmot	1:d0dfbce63a89	614	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
elmot	1:d0dfbce63a89	615	}
elmot	1:d0dfbce63a89	616	else
elmot	1:d0dfbce63a89	617	{
elmot	1:d0dfbce63a89	618	/* return address of RXDR register */
elmot	1:d0dfbce63a89	619	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
elmot	1:d0dfbce63a89	620	}
elmot	1:d0dfbce63a89	621
elmot	1:d0dfbce63a89	622	return data_reg_addr;
elmot	1:d0dfbce63a89	623	}
elmot	1:d0dfbce63a89	624
elmot	1:d0dfbce63a89	625	/**
elmot	1:d0dfbce63a89	626	* @brief Enable Clock stretching.
elmot	1:d0dfbce63a89	627	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	628	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
elmot	1:d0dfbce63a89	629	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	630	* @retval None
elmot	1:d0dfbce63a89	631	*/
elmot	1:d0dfbce63a89	632	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	633	{
elmot	1:d0dfbce63a89	634	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
elmot	1:d0dfbce63a89	635	}
elmot	1:d0dfbce63a89	636
elmot	1:d0dfbce63a89	637	/**
elmot	1:d0dfbce63a89	638	* @brief Disable Clock stretching.
elmot	1:d0dfbce63a89	639	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	640	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
elmot	1:d0dfbce63a89	641	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	642	* @retval None
elmot	1:d0dfbce63a89	643	*/
elmot	1:d0dfbce63a89	644	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	645	{
elmot	1:d0dfbce63a89	646	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
elmot	1:d0dfbce63a89	647	}
elmot	1:d0dfbce63a89	648
elmot	1:d0dfbce63a89	649	/**
elmot	1:d0dfbce63a89	650	* @brief Check if Clock stretching is enabled or disabled.
elmot	1:d0dfbce63a89	651	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
elmot	1:d0dfbce63a89	652	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	653	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	654	*/
elmot	1:d0dfbce63a89	655	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	656	{
elmot	1:d0dfbce63a89	657	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
elmot	1:d0dfbce63a89	658	}
elmot	1:d0dfbce63a89	659
elmot	1:d0dfbce63a89	660	/**
elmot	1:d0dfbce63a89	661	* @brief Enable hardware byte control in slave mode.
elmot	1:d0dfbce63a89	662	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
elmot	1:d0dfbce63a89	663	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	664	* @retval None
elmot	1:d0dfbce63a89	665	*/
elmot	1:d0dfbce63a89	666	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	667	{
elmot	1:d0dfbce63a89	668	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
elmot	1:d0dfbce63a89	669	}
elmot	1:d0dfbce63a89	670
elmot	1:d0dfbce63a89	671	/**
elmot	1:d0dfbce63a89	672	* @brief Disable hardware byte control in slave mode.
elmot	1:d0dfbce63a89	673	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
elmot	1:d0dfbce63a89	674	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	675	* @retval None
elmot	1:d0dfbce63a89	676	*/
elmot	1:d0dfbce63a89	677	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	678	{
elmot	1:d0dfbce63a89	679	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
elmot	1:d0dfbce63a89	680	}
elmot	1:d0dfbce63a89	681
elmot	1:d0dfbce63a89	682	/**
elmot	1:d0dfbce63a89	683	* @brief Check if hardware byte control in slave mode is enabled or disabled.
elmot	1:d0dfbce63a89	684	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
elmot	1:d0dfbce63a89	685	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	686	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	687	*/
elmot	1:d0dfbce63a89	688	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	689	{
elmot	1:d0dfbce63a89	690	return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
elmot	1:d0dfbce63a89	691	}
elmot	1:d0dfbce63a89	692
elmot	1:d0dfbce63a89	693	/**
elmot	1:d0dfbce63a89	694	* @brief Enable Wakeup from STOP.
elmot	1:d0dfbce63a89	695	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	696	* WakeUpFromStop feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	697	* @note This bit can only be programmed when Digital Filter is disabled.
elmot	1:d0dfbce63a89	698	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
elmot	1:d0dfbce63a89	699	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	700	* @retval None
elmot	1:d0dfbce63a89	701	*/
elmot	1:d0dfbce63a89	702	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	703	{
elmot	1:d0dfbce63a89	704	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
elmot	1:d0dfbce63a89	705	}
elmot	1:d0dfbce63a89	706
elmot	1:d0dfbce63a89	707	/**
elmot	1:d0dfbce63a89	708	* @brief Disable Wakeup from STOP.
elmot	1:d0dfbce63a89	709	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	710	* WakeUpFromStop feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	711	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
elmot	1:d0dfbce63a89	712	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	713	* @retval None
elmot	1:d0dfbce63a89	714	*/
elmot	1:d0dfbce63a89	715	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	716	{
elmot	1:d0dfbce63a89	717	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
elmot	1:d0dfbce63a89	718	}
elmot	1:d0dfbce63a89	719
elmot	1:d0dfbce63a89	720	/**
elmot	1:d0dfbce63a89	721	* @brief Check if Wakeup from STOP is enabled or disabled.
elmot	1:d0dfbce63a89	722	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	723	* WakeUpFromStop feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	724	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
elmot	1:d0dfbce63a89	725	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	726	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	727	*/
elmot	1:d0dfbce63a89	728	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	729	{
elmot	1:d0dfbce63a89	730	return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
elmot	1:d0dfbce63a89	731	}
elmot	1:d0dfbce63a89	732
elmot	1:d0dfbce63a89	733	/**
elmot	1:d0dfbce63a89	734	* @brief Enable General Call.
elmot	1:d0dfbce63a89	735	* @note When enabled the Address 0x00 is ACKed.
elmot	1:d0dfbce63a89	736	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
elmot	1:d0dfbce63a89	737	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	738	* @retval None
elmot	1:d0dfbce63a89	739	*/
elmot	1:d0dfbce63a89	740	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	741	{
elmot	1:d0dfbce63a89	742	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
elmot	1:d0dfbce63a89	743	}
elmot	1:d0dfbce63a89	744
elmot	1:d0dfbce63a89	745	/**
elmot	1:d0dfbce63a89	746	* @brief Disable General Call.
elmot	1:d0dfbce63a89	747	* @note When disabled the Address 0x00 is NACKed.
elmot	1:d0dfbce63a89	748	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
elmot	1:d0dfbce63a89	749	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	750	* @retval None
elmot	1:d0dfbce63a89	751	*/
elmot	1:d0dfbce63a89	752	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	753	{
elmot	1:d0dfbce63a89	754	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
elmot	1:d0dfbce63a89	755	}
elmot	1:d0dfbce63a89	756
elmot	1:d0dfbce63a89	757	/**
elmot	1:d0dfbce63a89	758	* @brief Check if General Call is enabled or disabled.
elmot	1:d0dfbce63a89	759	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
elmot	1:d0dfbce63a89	760	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	761	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	762	*/
elmot	1:d0dfbce63a89	763	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	764	{
elmot	1:d0dfbce63a89	765	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
elmot	1:d0dfbce63a89	766	}
elmot	1:d0dfbce63a89	767
elmot	1:d0dfbce63a89	768	/**
elmot	1:d0dfbce63a89	769	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
elmot	1:d0dfbce63a89	770	* @note Changing this bit is not allowed, when the START bit is set.
elmot	1:d0dfbce63a89	771	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
elmot	1:d0dfbce63a89	772	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	773	* @param AddressingMode This parameter can be one of the following values:
elmot	1:d0dfbce63a89	774	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
elmot	1:d0dfbce63a89	775	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
elmot	1:d0dfbce63a89	776	* @retval None
elmot	1:d0dfbce63a89	777	*/
elmot	1:d0dfbce63a89	778	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
elmot	1:d0dfbce63a89	779	{
elmot	1:d0dfbce63a89	780	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
elmot	1:d0dfbce63a89	781	}
elmot	1:d0dfbce63a89	782
elmot	1:d0dfbce63a89	783	/**
elmot	1:d0dfbce63a89	784	* @brief Get the Master addressing mode.
elmot	1:d0dfbce63a89	785	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
elmot	1:d0dfbce63a89	786	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	787	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	788	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
elmot	1:d0dfbce63a89	789	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
elmot	1:d0dfbce63a89	790	*/
elmot	1:d0dfbce63a89	791	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	792	{
elmot	1:d0dfbce63a89	793	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
elmot	1:d0dfbce63a89	794	}
elmot	1:d0dfbce63a89	795
elmot	1:d0dfbce63a89	796	/**
elmot	1:d0dfbce63a89	797	* @brief Set the Own Address1.
elmot	1:d0dfbce63a89	798	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
elmot	1:d0dfbce63a89	799	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
elmot	1:d0dfbce63a89	800	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	801	* @param OwnAddress1 This parameter must be a value between 0 and 0x3FF.
elmot	1:d0dfbce63a89	802	* @param OwnAddrSize This parameter can be one of the following values:
elmot	1:d0dfbce63a89	803	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
elmot	1:d0dfbce63a89	804	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
elmot	1:d0dfbce63a89	805	* @retval None
elmot	1:d0dfbce63a89	806	*/
elmot	1:d0dfbce63a89	807	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
elmot	1:d0dfbce63a89	808	{
elmot	1:d0dfbce63a89	809	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
elmot	1:d0dfbce63a89	810	}
elmot	1:d0dfbce63a89	811
elmot	1:d0dfbce63a89	812	/**
elmot	1:d0dfbce63a89	813	* @brief Enable acknowledge on Own Address1 match address.
elmot	1:d0dfbce63a89	814	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
elmot	1:d0dfbce63a89	815	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	816	* @retval None
elmot	1:d0dfbce63a89	817	*/
elmot	1:d0dfbce63a89	818	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	819	{
elmot	1:d0dfbce63a89	820	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
elmot	1:d0dfbce63a89	821	}
elmot	1:d0dfbce63a89	822
elmot	1:d0dfbce63a89	823	/**
elmot	1:d0dfbce63a89	824	* @brief Disable acknowledge on Own Address1 match address.
elmot	1:d0dfbce63a89	825	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
elmot	1:d0dfbce63a89	826	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	827	* @retval None
elmot	1:d0dfbce63a89	828	*/
elmot	1:d0dfbce63a89	829	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	830	{
elmot	1:d0dfbce63a89	831	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
elmot	1:d0dfbce63a89	832	}
elmot	1:d0dfbce63a89	833
elmot	1:d0dfbce63a89	834	/**
elmot	1:d0dfbce63a89	835	* @brief Check if Own Address1 acknowledge is enabled or disabled.
elmot	1:d0dfbce63a89	836	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
elmot	1:d0dfbce63a89	837	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	838	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	839	*/
elmot	1:d0dfbce63a89	840	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	841	{
elmot	1:d0dfbce63a89	842	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
elmot	1:d0dfbce63a89	843	}
elmot	1:d0dfbce63a89	844
elmot	1:d0dfbce63a89	845	/**
elmot	1:d0dfbce63a89	846	* @brief Set the 7bits Own Address2.
elmot	1:d0dfbce63a89	847	* @note This action has no effect if own address2 is enabled.
elmot	1:d0dfbce63a89	848	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
elmot	1:d0dfbce63a89	849	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
elmot	1:d0dfbce63a89	850	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	851	* @param OwnAddress2 Value between 0 and 0x7F.
elmot	1:d0dfbce63a89	852	* @param OwnAddrMask This parameter can be one of the following values:
elmot	1:d0dfbce63a89	853	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
elmot	1:d0dfbce63a89	854	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
elmot	1:d0dfbce63a89	855	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
elmot	1:d0dfbce63a89	856	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
elmot	1:d0dfbce63a89	857	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
elmot	1:d0dfbce63a89	858	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
elmot	1:d0dfbce63a89	859	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
elmot	1:d0dfbce63a89	860	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
elmot	1:d0dfbce63a89	861	* @retval None
elmot	1:d0dfbce63a89	862	*/
elmot	1:d0dfbce63a89	863	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
elmot	1:d0dfbce63a89	864	{
elmot	1:d0dfbce63a89	865	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
elmot	1:d0dfbce63a89	866	}
elmot	1:d0dfbce63a89	867
elmot	1:d0dfbce63a89	868	/**
elmot	1:d0dfbce63a89	869	* @brief Enable acknowledge on Own Address2 match address.
elmot	1:d0dfbce63a89	870	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
elmot	1:d0dfbce63a89	871	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	872	* @retval None
elmot	1:d0dfbce63a89	873	*/
elmot	1:d0dfbce63a89	874	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	875	{
elmot	1:d0dfbce63a89	876	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
elmot	1:d0dfbce63a89	877	}
elmot	1:d0dfbce63a89	878
elmot	1:d0dfbce63a89	879	/**
elmot	1:d0dfbce63a89	880	* @brief Disable acknowledge on Own Address2 match address.
elmot	1:d0dfbce63a89	881	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
elmot	1:d0dfbce63a89	882	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	883	* @retval None
elmot	1:d0dfbce63a89	884	*/
elmot	1:d0dfbce63a89	885	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	886	{
elmot	1:d0dfbce63a89	887	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
elmot	1:d0dfbce63a89	888	}
elmot	1:d0dfbce63a89	889
elmot	1:d0dfbce63a89	890	/**
elmot	1:d0dfbce63a89	891	* @brief Check if Own Address1 acknowledge is enabled or disabled.
elmot	1:d0dfbce63a89	892	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
elmot	1:d0dfbce63a89	893	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	894	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	895	*/
elmot	1:d0dfbce63a89	896	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	897	{
elmot	1:d0dfbce63a89	898	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
elmot	1:d0dfbce63a89	899	}
elmot	1:d0dfbce63a89	900
elmot	1:d0dfbce63a89	901	/**
elmot	1:d0dfbce63a89	902	* @brief Configure the SDA setup, hold time and the SCL high, low period.
elmot	1:d0dfbce63a89	903	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
elmot	1:d0dfbce63a89	904	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
elmot	1:d0dfbce63a89	905	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	906	* @param Timing This parameter must be a value between 0 and 0xFFFFFFFF.
elmot	1:d0dfbce63a89	907	* @note This parameter is computed with the STM32CubeMX Tool.
elmot	1:d0dfbce63a89	908	* @retval None
elmot	1:d0dfbce63a89	909	*/
elmot	1:d0dfbce63a89	910	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
elmot	1:d0dfbce63a89	911	{
elmot	1:d0dfbce63a89	912	WRITE_REG(I2Cx->TIMINGR, Timing);
elmot	1:d0dfbce63a89	913	}
elmot	1:d0dfbce63a89	914
elmot	1:d0dfbce63a89	915	/**
elmot	1:d0dfbce63a89	916	* @brief Get the Timing Prescaler setting.
elmot	1:d0dfbce63a89	917	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
elmot	1:d0dfbce63a89	918	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	919	* @retval Value between Min_Data=0x0 and Max_Data=0xF
elmot	1:d0dfbce63a89	920	*/
elmot	1:d0dfbce63a89	921	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	922	{
elmot	1:d0dfbce63a89	923	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
elmot	1:d0dfbce63a89	924	}
elmot	1:d0dfbce63a89	925
elmot	1:d0dfbce63a89	926	/**
elmot	1:d0dfbce63a89	927	* @brief Get the SCL low period setting.
elmot	1:d0dfbce63a89	928	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
elmot	1:d0dfbce63a89	929	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	930	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
elmot	1:d0dfbce63a89	931	*/
elmot	1:d0dfbce63a89	932	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	933	{
elmot	1:d0dfbce63a89	934	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
elmot	1:d0dfbce63a89	935	}
elmot	1:d0dfbce63a89	936
elmot	1:d0dfbce63a89	937	/**
elmot	1:d0dfbce63a89	938	* @brief Get the SCL high period setting.
elmot	1:d0dfbce63a89	939	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
elmot	1:d0dfbce63a89	940	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	941	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
elmot	1:d0dfbce63a89	942	*/
elmot	1:d0dfbce63a89	943	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	944	{
elmot	1:d0dfbce63a89	945	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
elmot	1:d0dfbce63a89	946	}
elmot	1:d0dfbce63a89	947
elmot	1:d0dfbce63a89	948	/**
elmot	1:d0dfbce63a89	949	* @brief Get the SDA hold time.
elmot	1:d0dfbce63a89	950	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
elmot	1:d0dfbce63a89	951	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	952	* @retval Value between Min_Data=0x0 and Max_Data=0xF
elmot	1:d0dfbce63a89	953	*/
elmot	1:d0dfbce63a89	954	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	955	{
elmot	1:d0dfbce63a89	956	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
elmot	1:d0dfbce63a89	957	}
elmot	1:d0dfbce63a89	958
elmot	1:d0dfbce63a89	959	/**
elmot	1:d0dfbce63a89	960	* @brief Get the SDA setup time.
elmot	1:d0dfbce63a89	961	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
elmot	1:d0dfbce63a89	962	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	963	* @retval Value between Min_Data=0x0 and Max_Data=0xF
elmot	1:d0dfbce63a89	964	*/
elmot	1:d0dfbce63a89	965	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	966	{
elmot	1:d0dfbce63a89	967	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
elmot	1:d0dfbce63a89	968	}
elmot	1:d0dfbce63a89	969
elmot	1:d0dfbce63a89	970	/**
elmot	1:d0dfbce63a89	971	* @brief Configure peripheral mode.
elmot	1:d0dfbce63a89	972	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	973	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	974	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
elmot	1:d0dfbce63a89	975	* CR1 SMBDEN LL_I2C_SetMode
elmot	1:d0dfbce63a89	976	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	977	* @param PeripheralMode This parameter can be one of the following values:
elmot	1:d0dfbce63a89	978	* @arg @ref LL_I2C_MODE_I2C
elmot	1:d0dfbce63a89	979	* @arg @ref LL_I2C_MODE_SMBUS_HOST
elmot	1:d0dfbce63a89	980	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
elmot	1:d0dfbce63a89	981	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
elmot	1:d0dfbce63a89	982	* @retval None
elmot	1:d0dfbce63a89	983	*/
elmot	1:d0dfbce63a89	984	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
elmot	1:d0dfbce63a89	985	{
elmot	1:d0dfbce63a89	986	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
elmot	1:d0dfbce63a89	987	}
elmot	1:d0dfbce63a89	988
elmot	1:d0dfbce63a89	989	/**
elmot	1:d0dfbce63a89	990	* @brief Get peripheral mode.
elmot	1:d0dfbce63a89	991	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	992	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	993	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
elmot	1:d0dfbce63a89	994	* CR1 SMBDEN LL_I2C_GetMode
elmot	1:d0dfbce63a89	995	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	996	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	997	* @arg @ref LL_I2C_MODE_I2C
elmot	1:d0dfbce63a89	998	* @arg @ref LL_I2C_MODE_SMBUS_HOST
elmot	1:d0dfbce63a89	999	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
elmot	1:d0dfbce63a89	1000	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
elmot	1:d0dfbce63a89	1001	*/
elmot	1:d0dfbce63a89	1002	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1003	{
elmot	1:d0dfbce63a89	1004	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
elmot	1:d0dfbce63a89	1005	}
elmot	1:d0dfbce63a89	1006
elmot	1:d0dfbce63a89	1007	/**
elmot	1:d0dfbce63a89	1008	* @brief Enable SMBus alert (Host or Device mode)
elmot	1:d0dfbce63a89	1009	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1010	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1011	* @note SMBus Device mode:
elmot	1:d0dfbce63a89	1012	* - SMBus Alert pin is drived low and
elmot	1:d0dfbce63a89	1013	* Alert Response Address Header acknowledge is enabled.
elmot	1:d0dfbce63a89	1014	* SMBus Host mode:
elmot	1:d0dfbce63a89	1015	* - SMBus Alert pin management is supported.
elmot	1:d0dfbce63a89	1016	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
elmot	1:d0dfbce63a89	1017	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1018	* @retval None
elmot	1:d0dfbce63a89	1019	*/
elmot	1:d0dfbce63a89	1020	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1021	{
elmot	1:d0dfbce63a89	1022	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
elmot	1:d0dfbce63a89	1023	}
elmot	1:d0dfbce63a89	1024
elmot	1:d0dfbce63a89	1025	/**
elmot	1:d0dfbce63a89	1026	* @brief Disable SMBus alert (Host or Device mode)
elmot	1:d0dfbce63a89	1027	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1028	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1029	* @note SMBus Device mode:
elmot	1:d0dfbce63a89	1030	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
elmot	1:d0dfbce63a89	1031	* Alert Response Address Header acknowledge is disabled.
elmot	1:d0dfbce63a89	1032	* SMBus Host mode:
elmot	1:d0dfbce63a89	1033	* - SMBus Alert pin management is not supported.
elmot	1:d0dfbce63a89	1034	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
elmot	1:d0dfbce63a89	1035	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1036	* @retval None
elmot	1:d0dfbce63a89	1037	*/
elmot	1:d0dfbce63a89	1038	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1039	{
elmot	1:d0dfbce63a89	1040	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
elmot	1:d0dfbce63a89	1041	}
elmot	1:d0dfbce63a89	1042
elmot	1:d0dfbce63a89	1043	/**
elmot	1:d0dfbce63a89	1044	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
elmot	1:d0dfbce63a89	1045	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1046	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1047	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
elmot	1:d0dfbce63a89	1048	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1049	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1050	*/
elmot	1:d0dfbce63a89	1051	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1052	{
elmot	1:d0dfbce63a89	1053	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
elmot	1:d0dfbce63a89	1054	}
elmot	1:d0dfbce63a89	1055
elmot	1:d0dfbce63a89	1056	/**
elmot	1:d0dfbce63a89	1057	* @brief Enable SMBus Packet Error Calculation (PEC).
elmot	1:d0dfbce63a89	1058	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1059	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1060	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
elmot	1:d0dfbce63a89	1061	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1062	* @retval None
elmot	1:d0dfbce63a89	1063	*/
elmot	1:d0dfbce63a89	1064	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1065	{
elmot	1:d0dfbce63a89	1066	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
elmot	1:d0dfbce63a89	1067	}
elmot	1:d0dfbce63a89	1068
elmot	1:d0dfbce63a89	1069	/**
elmot	1:d0dfbce63a89	1070	* @brief Disable SMBus Packet Error Calculation (PEC).
elmot	1:d0dfbce63a89	1071	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1072	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1073	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
elmot	1:d0dfbce63a89	1074	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1075	* @retval None
elmot	1:d0dfbce63a89	1076	*/
elmot	1:d0dfbce63a89	1077	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1078	{
elmot	1:d0dfbce63a89	1079	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
elmot	1:d0dfbce63a89	1080	}
elmot	1:d0dfbce63a89	1081
elmot	1:d0dfbce63a89	1082	/**
elmot	1:d0dfbce63a89	1083	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
elmot	1:d0dfbce63a89	1084	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1085	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1086	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
elmot	1:d0dfbce63a89	1087	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1088	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1089	*/
elmot	1:d0dfbce63a89	1090	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1091	{
elmot	1:d0dfbce63a89	1092	return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
elmot	1:d0dfbce63a89	1093	}
elmot	1:d0dfbce63a89	1094
elmot	1:d0dfbce63a89	1095	/**
elmot	1:d0dfbce63a89	1096	* @brief Configure the SMBus Clock Timeout.
elmot	1:d0dfbce63a89	1097	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1098	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1099	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
elmot	1:d0dfbce63a89	1100	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
elmot	1:d0dfbce63a89	1101	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
elmot	1:d0dfbce63a89	1102	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
elmot	1:d0dfbce63a89	1103	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1104	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
elmot	1:d0dfbce63a89	1105	* @param TimeoutAMode This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1106	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
elmot	1:d0dfbce63a89	1107	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
elmot	1:d0dfbce63a89	1108	* @param TimeoutB
elmot	1:d0dfbce63a89	1109	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
elmot	1:d0dfbce63a89	1110	* @retval None
elmot	1:d0dfbce63a89	1111	*/
elmot	1:d0dfbce63a89	1112	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
elmot	1:d0dfbce63a89	1113	uint32_t TimeoutB)
elmot	1:d0dfbce63a89	1114	{
elmot	1:d0dfbce63a89	1115	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
elmot	1:d0dfbce63a89	1116	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
elmot	1:d0dfbce63a89	1117	}
elmot	1:d0dfbce63a89	1118
elmot	1:d0dfbce63a89	1119	/**
elmot	1:d0dfbce63a89	1120	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
elmot	1:d0dfbce63a89	1121	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1122	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1123	* @note These bits can only be programmed when TimeoutA is disabled.
elmot	1:d0dfbce63a89	1124	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
elmot	1:d0dfbce63a89	1125	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1126	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
elmot	1:d0dfbce63a89	1127	* @retval None
elmot	1:d0dfbce63a89	1128	*/
elmot	1:d0dfbce63a89	1129	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
elmot	1:d0dfbce63a89	1130	{
elmot	1:d0dfbce63a89	1131	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
elmot	1:d0dfbce63a89	1132	}
elmot	1:d0dfbce63a89	1133
elmot	1:d0dfbce63a89	1134	/**
elmot	1:d0dfbce63a89	1135	* @brief Get the SMBus Clock TimeoutA setting.
elmot	1:d0dfbce63a89	1136	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1137	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1138	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
elmot	1:d0dfbce63a89	1139	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1140	* @retval Value between Min_Data=0 and Max_Data=0xFFF
elmot	1:d0dfbce63a89	1141	*/
elmot	1:d0dfbce63a89	1142	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1143	{
elmot	1:d0dfbce63a89	1144	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
elmot	1:d0dfbce63a89	1145	}
elmot	1:d0dfbce63a89	1146
elmot	1:d0dfbce63a89	1147	/**
elmot	1:d0dfbce63a89	1148	* @brief Set the SMBus Clock TimeoutA mode.
elmot	1:d0dfbce63a89	1149	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1150	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1151	* @note This bit can only be programmed when TimeoutA is disabled.
elmot	1:d0dfbce63a89	1152	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
elmot	1:d0dfbce63a89	1153	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1154	* @param TimeoutAMode This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1155	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
elmot	1:d0dfbce63a89	1156	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
elmot	1:d0dfbce63a89	1157	* @retval None
elmot	1:d0dfbce63a89	1158	*/
elmot	1:d0dfbce63a89	1159	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
elmot	1:d0dfbce63a89	1160	{
elmot	1:d0dfbce63a89	1161	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
elmot	1:d0dfbce63a89	1162	}
elmot	1:d0dfbce63a89	1163
elmot	1:d0dfbce63a89	1164	/**
elmot	1:d0dfbce63a89	1165	* @brief Get the SMBus Clock TimeoutA mode.
elmot	1:d0dfbce63a89	1166	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1167	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1168	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
elmot	1:d0dfbce63a89	1169	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1170	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	1171	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
elmot	1:d0dfbce63a89	1172	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
elmot	1:d0dfbce63a89	1173	*/
elmot	1:d0dfbce63a89	1174	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1175	{
elmot	1:d0dfbce63a89	1176	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
elmot	1:d0dfbce63a89	1177	}
elmot	1:d0dfbce63a89	1178
elmot	1:d0dfbce63a89	1179	/**
elmot	1:d0dfbce63a89	1180	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
elmot	1:d0dfbce63a89	1181	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1182	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1183	* @note These bits can only be programmed when TimeoutB is disabled.
elmot	1:d0dfbce63a89	1184	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
elmot	1:d0dfbce63a89	1185	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1186	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
elmot	1:d0dfbce63a89	1187	* @retval None
elmot	1:d0dfbce63a89	1188	*/
elmot	1:d0dfbce63a89	1189	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
elmot	1:d0dfbce63a89	1190	{
elmot	1:d0dfbce63a89	1191	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
elmot	1:d0dfbce63a89	1192	}
elmot	1:d0dfbce63a89	1193
elmot	1:d0dfbce63a89	1194	/**
elmot	1:d0dfbce63a89	1195	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
elmot	1:d0dfbce63a89	1196	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1197	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1198	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
elmot	1:d0dfbce63a89	1199	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1200	* @retval Value between Min_Data=0 and Max_Data=0xFFF
elmot	1:d0dfbce63a89	1201	*/
elmot	1:d0dfbce63a89	1202	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1203	{
elmot	1:d0dfbce63a89	1204	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
elmot	1:d0dfbce63a89	1205	}
elmot	1:d0dfbce63a89	1206
elmot	1:d0dfbce63a89	1207	/**
elmot	1:d0dfbce63a89	1208	* @brief Enable the SMBus Clock Timeout.
elmot	1:d0dfbce63a89	1209	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1210	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1211	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
elmot	1:d0dfbce63a89	1212	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
elmot	1:d0dfbce63a89	1213	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1214	* @param ClockTimeout This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1215	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
elmot	1:d0dfbce63a89	1216	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
elmot	1:d0dfbce63a89	1217	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
elmot	1:d0dfbce63a89	1218	* @retval None
elmot	1:d0dfbce63a89	1219	*/
elmot	1:d0dfbce63a89	1220	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
elmot	1:d0dfbce63a89	1221	{
elmot	1:d0dfbce63a89	1222	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
elmot	1:d0dfbce63a89	1223	}
elmot	1:d0dfbce63a89	1224
elmot	1:d0dfbce63a89	1225	/**
elmot	1:d0dfbce63a89	1226	* @brief Disable the SMBus Clock Timeout.
elmot	1:d0dfbce63a89	1227	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1228	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1229	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
elmot	1:d0dfbce63a89	1230	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
elmot	1:d0dfbce63a89	1231	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1232	* @param ClockTimeout This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1233	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
elmot	1:d0dfbce63a89	1234	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
elmot	1:d0dfbce63a89	1235	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
elmot	1:d0dfbce63a89	1236	* @retval None
elmot	1:d0dfbce63a89	1237	*/
elmot	1:d0dfbce63a89	1238	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
elmot	1:d0dfbce63a89	1239	{
elmot	1:d0dfbce63a89	1240	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
elmot	1:d0dfbce63a89	1241	}
elmot	1:d0dfbce63a89	1242
elmot	1:d0dfbce63a89	1243	/**
elmot	1:d0dfbce63a89	1244	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
elmot	1:d0dfbce63a89	1245	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1246	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1247	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
elmot	1:d0dfbce63a89	1248	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
elmot	1:d0dfbce63a89	1249	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1250	* @param ClockTimeout This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1251	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
elmot	1:d0dfbce63a89	1252	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
elmot	1:d0dfbce63a89	1253	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
elmot	1:d0dfbce63a89	1254	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1255	*/
elmot	1:d0dfbce63a89	1256	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
elmot	1:d0dfbce63a89	1257	{
elmot	1:d0dfbce63a89	1258	return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
elmot	1:d0dfbce63a89	1259	}
elmot	1:d0dfbce63a89	1260
elmot	1:d0dfbce63a89	1261	/**
elmot	1:d0dfbce63a89	1262	* @}
elmot	1:d0dfbce63a89	1263	*/
elmot	1:d0dfbce63a89	1264
elmot	1:d0dfbce63a89	1265	/** @defgroup I2C_LL_EF_IT_Management IT_Management
elmot	1:d0dfbce63a89	1266	* @{
elmot	1:d0dfbce63a89	1267	*/
elmot	1:d0dfbce63a89	1268
elmot	1:d0dfbce63a89	1269	/**
elmot	1:d0dfbce63a89	1270	* @brief Enable TXIS interrupt.
elmot	1:d0dfbce63a89	1271	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
elmot	1:d0dfbce63a89	1272	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1273	* @retval None
elmot	1:d0dfbce63a89	1274	*/
elmot	1:d0dfbce63a89	1275	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1276	{
elmot	1:d0dfbce63a89	1277	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
elmot	1:d0dfbce63a89	1278	}
elmot	1:d0dfbce63a89	1279
elmot	1:d0dfbce63a89	1280	/**
elmot	1:d0dfbce63a89	1281	* @brief Disable TXIS interrupt.
elmot	1:d0dfbce63a89	1282	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
elmot	1:d0dfbce63a89	1283	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1284	* @retval None
elmot	1:d0dfbce63a89	1285	*/
elmot	1:d0dfbce63a89	1286	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1287	{
elmot	1:d0dfbce63a89	1288	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
elmot	1:d0dfbce63a89	1289	}
elmot	1:d0dfbce63a89	1290
elmot	1:d0dfbce63a89	1291	/**
elmot	1:d0dfbce63a89	1292	* @brief Check if the TXIS Interrupt is enabled or disabled.
elmot	1:d0dfbce63a89	1293	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
elmot	1:d0dfbce63a89	1294	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1295	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1296	*/
elmot	1:d0dfbce63a89	1297	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1298	{
elmot	1:d0dfbce63a89	1299	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
elmot	1:d0dfbce63a89	1300	}
elmot	1:d0dfbce63a89	1301
elmot	1:d0dfbce63a89	1302	/**
elmot	1:d0dfbce63a89	1303	* @brief Enable RXNE interrupt.
elmot	1:d0dfbce63a89	1304	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
elmot	1:d0dfbce63a89	1305	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1306	* @retval None
elmot	1:d0dfbce63a89	1307	*/
elmot	1:d0dfbce63a89	1308	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1309	{
elmot	1:d0dfbce63a89	1310	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
elmot	1:d0dfbce63a89	1311	}
elmot	1:d0dfbce63a89	1312
elmot	1:d0dfbce63a89	1313	/**
elmot	1:d0dfbce63a89	1314	* @brief Disable RXNE interrupt.
elmot	1:d0dfbce63a89	1315	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
elmot	1:d0dfbce63a89	1316	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1317	* @retval None
elmot	1:d0dfbce63a89	1318	*/
elmot	1:d0dfbce63a89	1319	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1320	{
elmot	1:d0dfbce63a89	1321	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
elmot	1:d0dfbce63a89	1322	}
elmot	1:d0dfbce63a89	1323
elmot	1:d0dfbce63a89	1324	/**
elmot	1:d0dfbce63a89	1325	* @brief Check if the RXNE Interrupt is enabled or disabled.
elmot	1:d0dfbce63a89	1326	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
elmot	1:d0dfbce63a89	1327	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1328	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1329	*/
elmot	1:d0dfbce63a89	1330	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1331	{
elmot	1:d0dfbce63a89	1332	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
elmot	1:d0dfbce63a89	1333	}
elmot	1:d0dfbce63a89	1334
elmot	1:d0dfbce63a89	1335	/**
elmot	1:d0dfbce63a89	1336	* @brief Enable Address match interrupt (slave mode only).
elmot	1:d0dfbce63a89	1337	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
elmot	1:d0dfbce63a89	1338	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1339	* @retval None
elmot	1:d0dfbce63a89	1340	*/
elmot	1:d0dfbce63a89	1341	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1342	{
elmot	1:d0dfbce63a89	1343	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
elmot	1:d0dfbce63a89	1344	}
elmot	1:d0dfbce63a89	1345
elmot	1:d0dfbce63a89	1346	/**
elmot	1:d0dfbce63a89	1347	* @brief Disable Address match interrupt (slave mode only).
elmot	1:d0dfbce63a89	1348	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
elmot	1:d0dfbce63a89	1349	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1350	* @retval None
elmot	1:d0dfbce63a89	1351	*/
elmot	1:d0dfbce63a89	1352	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1353	{
elmot	1:d0dfbce63a89	1354	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
elmot	1:d0dfbce63a89	1355	}
elmot	1:d0dfbce63a89	1356
elmot	1:d0dfbce63a89	1357	/**
elmot	1:d0dfbce63a89	1358	* @brief Check if Address match interrupt is enabled or disabled.
elmot	1:d0dfbce63a89	1359	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
elmot	1:d0dfbce63a89	1360	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1361	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1362	*/
elmot	1:d0dfbce63a89	1363	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1364	{
elmot	1:d0dfbce63a89	1365	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
elmot	1:d0dfbce63a89	1366	}
elmot	1:d0dfbce63a89	1367
elmot	1:d0dfbce63a89	1368	/**
elmot	1:d0dfbce63a89	1369	* @brief Enable Not acknowledge received interrupt.
elmot	1:d0dfbce63a89	1370	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
elmot	1:d0dfbce63a89	1371	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1372	* @retval None
elmot	1:d0dfbce63a89	1373	*/
elmot	1:d0dfbce63a89	1374	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1375	{
elmot	1:d0dfbce63a89	1376	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
elmot	1:d0dfbce63a89	1377	}
elmot	1:d0dfbce63a89	1378
elmot	1:d0dfbce63a89	1379	/**
elmot	1:d0dfbce63a89	1380	* @brief Disable Not acknowledge received interrupt.
elmot	1:d0dfbce63a89	1381	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
elmot	1:d0dfbce63a89	1382	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1383	* @retval None
elmot	1:d0dfbce63a89	1384	*/
elmot	1:d0dfbce63a89	1385	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1386	{
elmot	1:d0dfbce63a89	1387	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
elmot	1:d0dfbce63a89	1388	}
elmot	1:d0dfbce63a89	1389
elmot	1:d0dfbce63a89	1390	/**
elmot	1:d0dfbce63a89	1391	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
elmot	1:d0dfbce63a89	1392	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
elmot	1:d0dfbce63a89	1393	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1394	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1395	*/
elmot	1:d0dfbce63a89	1396	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1397	{
elmot	1:d0dfbce63a89	1398	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
elmot	1:d0dfbce63a89	1399	}
elmot	1:d0dfbce63a89	1400
elmot	1:d0dfbce63a89	1401	/**
elmot	1:d0dfbce63a89	1402	* @brief Enable STOP detection interrupt.
elmot	1:d0dfbce63a89	1403	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
elmot	1:d0dfbce63a89	1404	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1405	* @retval None
elmot	1:d0dfbce63a89	1406	*/
elmot	1:d0dfbce63a89	1407	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1408	{
elmot	1:d0dfbce63a89	1409	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
elmot	1:d0dfbce63a89	1410	}
elmot	1:d0dfbce63a89	1411
elmot	1:d0dfbce63a89	1412	/**
elmot	1:d0dfbce63a89	1413	* @brief Disable STOP detection interrupt.
elmot	1:d0dfbce63a89	1414	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
elmot	1:d0dfbce63a89	1415	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1416	* @retval None
elmot	1:d0dfbce63a89	1417	*/
elmot	1:d0dfbce63a89	1418	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1419	{
elmot	1:d0dfbce63a89	1420	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
elmot	1:d0dfbce63a89	1421	}
elmot	1:d0dfbce63a89	1422
elmot	1:d0dfbce63a89	1423	/**
elmot	1:d0dfbce63a89	1424	* @brief Check if STOP detection interrupt is enabled or disabled.
elmot	1:d0dfbce63a89	1425	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
elmot	1:d0dfbce63a89	1426	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1427	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1428	*/
elmot	1:d0dfbce63a89	1429	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1430	{
elmot	1:d0dfbce63a89	1431	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
elmot	1:d0dfbce63a89	1432	}
elmot	1:d0dfbce63a89	1433
elmot	1:d0dfbce63a89	1434	/**
elmot	1:d0dfbce63a89	1435	* @brief Enable Transfer Complete interrupt.
elmot	1:d0dfbce63a89	1436	* @note Any of these events will generate interrupt :
elmot	1:d0dfbce63a89	1437	* Transfer Complete (TC)
elmot	1:d0dfbce63a89	1438	* Transfer Complete Reload (TCR)
elmot	1:d0dfbce63a89	1439	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
elmot	1:d0dfbce63a89	1440	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1441	* @retval None
elmot	1:d0dfbce63a89	1442	*/
elmot	1:d0dfbce63a89	1443	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1444	{
elmot	1:d0dfbce63a89	1445	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
elmot	1:d0dfbce63a89	1446	}
elmot	1:d0dfbce63a89	1447
elmot	1:d0dfbce63a89	1448	/**
elmot	1:d0dfbce63a89	1449	* @brief Disable Transfer Complete interrupt.
elmot	1:d0dfbce63a89	1450	* @note Any of these events will generate interrupt :
elmot	1:d0dfbce63a89	1451	* Transfer Complete (TC)
elmot	1:d0dfbce63a89	1452	* Transfer Complete Reload (TCR)
elmot	1:d0dfbce63a89	1453	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
elmot	1:d0dfbce63a89	1454	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1455	* @retval None
elmot	1:d0dfbce63a89	1456	*/
elmot	1:d0dfbce63a89	1457	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1458	{
elmot	1:d0dfbce63a89	1459	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
elmot	1:d0dfbce63a89	1460	}
elmot	1:d0dfbce63a89	1461
elmot	1:d0dfbce63a89	1462	/**
elmot	1:d0dfbce63a89	1463	* @brief Check if Transfer Complete interrupt is enabled or disabled.
elmot	1:d0dfbce63a89	1464	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
elmot	1:d0dfbce63a89	1465	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1466	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1467	*/
elmot	1:d0dfbce63a89	1468	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1469	{
elmot	1:d0dfbce63a89	1470	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
elmot	1:d0dfbce63a89	1471	}
elmot	1:d0dfbce63a89	1472
elmot	1:d0dfbce63a89	1473	/**
elmot	1:d0dfbce63a89	1474	* @brief Enable Error interrupts.
elmot	1:d0dfbce63a89	1475	* @note Any of these errors will generate interrupt :
elmot	1:d0dfbce63a89	1476	* Arbitration Loss (ARLO)
elmot	1:d0dfbce63a89	1477	* Bus Error detection (BERR)
elmot	1:d0dfbce63a89	1478	* Overrun/Underrun (OVR)
elmot	1:d0dfbce63a89	1479	* SMBus Timeout detection (TIMEOUT)
elmot	1:d0dfbce63a89	1480	* SMBus PEC error detection (PECERR)
elmot	1:d0dfbce63a89	1481	* SMBus Alert pin event detection (ALERT)
elmot	1:d0dfbce63a89	1482	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1483	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1484	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
elmot	1:d0dfbce63a89	1485	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1486	* @retval None
elmot	1:d0dfbce63a89	1487	*/
elmot	1:d0dfbce63a89	1488	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1489	{
elmot	1:d0dfbce63a89	1490	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
elmot	1:d0dfbce63a89	1491	}
elmot	1:d0dfbce63a89	1492
elmot	1:d0dfbce63a89	1493	/**
elmot	1:d0dfbce63a89	1494	* @brief Disable Error interrupts.
elmot	1:d0dfbce63a89	1495	* @note Any of these errors will generate interrupt :
elmot	1:d0dfbce63a89	1496	* Arbitration Loss (ARLO)
elmot	1:d0dfbce63a89	1497	* Bus Error detection (BERR)
elmot	1:d0dfbce63a89	1498	* Overrun/Underrun (OVR)
elmot	1:d0dfbce63a89	1499	* SMBus Timeout detection (TIMEOUT)
elmot	1:d0dfbce63a89	1500	* SMBus PEC error detection (PECERR)
elmot	1:d0dfbce63a89	1501	* SMBus Alert pin event detection (ALERT)
elmot	1:d0dfbce63a89	1502	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1503	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1504	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
elmot	1:d0dfbce63a89	1505	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1506	* @retval None
elmot	1:d0dfbce63a89	1507	*/
elmot	1:d0dfbce63a89	1508	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1509	{
elmot	1:d0dfbce63a89	1510	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
elmot	1:d0dfbce63a89	1511	}
elmot	1:d0dfbce63a89	1512
elmot	1:d0dfbce63a89	1513	/**
elmot	1:d0dfbce63a89	1514	* @brief Check if Error interrupts is enabled of disabled.
elmot	1:d0dfbce63a89	1515	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
elmot	1:d0dfbce63a89	1516	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1517	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1518	*/
elmot	1:d0dfbce63a89	1519	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1520	{
elmot	1:d0dfbce63a89	1521	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
elmot	1:d0dfbce63a89	1522	}
elmot	1:d0dfbce63a89	1523
elmot	1:d0dfbce63a89	1524	/**
elmot	1:d0dfbce63a89	1525	* @}
elmot	1:d0dfbce63a89	1526	*/
elmot	1:d0dfbce63a89	1527
elmot	1:d0dfbce63a89	1528	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
elmot	1:d0dfbce63a89	1529	* @{
elmot	1:d0dfbce63a89	1530	*/
elmot	1:d0dfbce63a89	1531
elmot	1:d0dfbce63a89	1532	/**
elmot	1:d0dfbce63a89	1533	* @brief Indicate the status of Transmit data register empty flag.
elmot	1:d0dfbce63a89	1534	* @note RESET: When next data is written in Transmit data register.
elmot	1:d0dfbce63a89	1535	* SET: When Transmit data register is empty.
elmot	1:d0dfbce63a89	1536	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
elmot	1:d0dfbce63a89	1537	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1538	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1539	*/
elmot	1:d0dfbce63a89	1540	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1541	{
elmot	1:d0dfbce63a89	1542	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
elmot	1:d0dfbce63a89	1543	}
elmot	1:d0dfbce63a89	1544
elmot	1:d0dfbce63a89	1545	/**
elmot	1:d0dfbce63a89	1546	* @brief Indicate the status of Transmit interrupt flag.
elmot	1:d0dfbce63a89	1547	* @note RESET: When next data is written in Transmit data register.
elmot	1:d0dfbce63a89	1548	* SET: When Transmit data register is empty.
elmot	1:d0dfbce63a89	1549	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
elmot	1:d0dfbce63a89	1550	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1551	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1552	*/
elmot	1:d0dfbce63a89	1553	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1554	{
elmot	1:d0dfbce63a89	1555	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
elmot	1:d0dfbce63a89	1556	}
elmot	1:d0dfbce63a89	1557
elmot	1:d0dfbce63a89	1558	/**
elmot	1:d0dfbce63a89	1559	* @brief Indicate the status of Receive data register not empty flag.
elmot	1:d0dfbce63a89	1560	* @note RESET: When Receive data register is read.
elmot	1:d0dfbce63a89	1561	* SET: When the received data is copied in Receive data register.
elmot	1:d0dfbce63a89	1562	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
elmot	1:d0dfbce63a89	1563	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1564	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1565	*/
elmot	1:d0dfbce63a89	1566	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1567	{
elmot	1:d0dfbce63a89	1568	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
elmot	1:d0dfbce63a89	1569	}
elmot	1:d0dfbce63a89	1570
elmot	1:d0dfbce63a89	1571	/**
elmot	1:d0dfbce63a89	1572	* @brief Indicate the status of Address matched flag (slave mode).
elmot	1:d0dfbce63a89	1573	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1574	* SET: When the received slave address matched with one of the enabled slave address.
elmot	1:d0dfbce63a89	1575	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
elmot	1:d0dfbce63a89	1576	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1577	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1578	*/
elmot	1:d0dfbce63a89	1579	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1580	{
elmot	1:d0dfbce63a89	1581	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
elmot	1:d0dfbce63a89	1582	}
elmot	1:d0dfbce63a89	1583
elmot	1:d0dfbce63a89	1584	/**
elmot	1:d0dfbce63a89	1585	* @brief Indicate the status of Not Acknowledge received flag.
elmot	1:d0dfbce63a89	1586	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1587	* SET: When a NACK is received after a byte transmission.
elmot	1:d0dfbce63a89	1588	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
elmot	1:d0dfbce63a89	1589	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1590	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1591	*/
elmot	1:d0dfbce63a89	1592	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1593	{
elmot	1:d0dfbce63a89	1594	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
elmot	1:d0dfbce63a89	1595	}
elmot	1:d0dfbce63a89	1596
elmot	1:d0dfbce63a89	1597	/**
elmot	1:d0dfbce63a89	1598	* @brief Indicate the status of Stop detection flag.
elmot	1:d0dfbce63a89	1599	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1600	* SET: When a Stop condition is detected.
elmot	1:d0dfbce63a89	1601	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
elmot	1:d0dfbce63a89	1602	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1603	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1604	*/
elmot	1:d0dfbce63a89	1605	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1606	{
elmot	1:d0dfbce63a89	1607	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
elmot	1:d0dfbce63a89	1608	}
elmot	1:d0dfbce63a89	1609
elmot	1:d0dfbce63a89	1610	/**
elmot	1:d0dfbce63a89	1611	* @brief Indicate the status of Transfer complete flag (master mode).
elmot	1:d0dfbce63a89	1612	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1613	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
elmot	1:d0dfbce63a89	1614	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
elmot	1:d0dfbce63a89	1615	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1616	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1617	*/
elmot	1:d0dfbce63a89	1618	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1619	{
elmot	1:d0dfbce63a89	1620	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
elmot	1:d0dfbce63a89	1621	}
elmot	1:d0dfbce63a89	1622
elmot	1:d0dfbce63a89	1623	/**
elmot	1:d0dfbce63a89	1624	* @brief Indicate the status of Transfer complete flag (master mode).
elmot	1:d0dfbce63a89	1625	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1626	* SET: When RELOAD=1 and NBYTES date have been transferred.
elmot	1:d0dfbce63a89	1627	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
elmot	1:d0dfbce63a89	1628	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1629	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1630	*/
elmot	1:d0dfbce63a89	1631	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1632	{
elmot	1:d0dfbce63a89	1633	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
elmot	1:d0dfbce63a89	1634	}
elmot	1:d0dfbce63a89	1635
elmot	1:d0dfbce63a89	1636	/**
elmot	1:d0dfbce63a89	1637	* @brief Indicate the status of Bus error flag.
elmot	1:d0dfbce63a89	1638	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1639	* SET: When a misplaced Start or Stop condition is detected.
elmot	1:d0dfbce63a89	1640	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
elmot	1:d0dfbce63a89	1641	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1642	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1643	*/
elmot	1:d0dfbce63a89	1644	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1645	{
elmot	1:d0dfbce63a89	1646	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
elmot	1:d0dfbce63a89	1647	}
elmot	1:d0dfbce63a89	1648
elmot	1:d0dfbce63a89	1649	/**
elmot	1:d0dfbce63a89	1650	* @brief Indicate the status of Arbitration lost flag.
elmot	1:d0dfbce63a89	1651	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1652	* SET: When arbitration lost.
elmot	1:d0dfbce63a89	1653	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
elmot	1:d0dfbce63a89	1654	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1655	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1656	*/
elmot	1:d0dfbce63a89	1657	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1658	{
elmot	1:d0dfbce63a89	1659	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
elmot	1:d0dfbce63a89	1660	}
elmot	1:d0dfbce63a89	1661
elmot	1:d0dfbce63a89	1662	/**
elmot	1:d0dfbce63a89	1663	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
elmot	1:d0dfbce63a89	1664	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1665	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
elmot	1:d0dfbce63a89	1666	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
elmot	1:d0dfbce63a89	1667	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1668	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1669	*/
elmot	1:d0dfbce63a89	1670	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1671	{
elmot	1:d0dfbce63a89	1672	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
elmot	1:d0dfbce63a89	1673	}
elmot	1:d0dfbce63a89	1674
elmot	1:d0dfbce63a89	1675	/**
elmot	1:d0dfbce63a89	1676	* @brief Indicate the status of Bus Busy flag.
elmot	1:d0dfbce63a89	1677	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1678	* SET: When a Start condition is detected.
elmot	1:d0dfbce63a89	1679	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
elmot	1:d0dfbce63a89	1680	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1681	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1682	*/
elmot	1:d0dfbce63a89	1683	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1684	{
elmot	1:d0dfbce63a89	1685	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
elmot	1:d0dfbce63a89	1686	}
elmot	1:d0dfbce63a89	1687
elmot	1:d0dfbce63a89	1688	/**
elmot	1:d0dfbce63a89	1689	* @brief Clear Address Matched flag.
elmot	1:d0dfbce63a89	1690	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
elmot	1:d0dfbce63a89	1691	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1692	* @retval None
elmot	1:d0dfbce63a89	1693	*/
elmot	1:d0dfbce63a89	1694	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1695	{
elmot	1:d0dfbce63a89	1696	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
elmot	1:d0dfbce63a89	1697	}
elmot	1:d0dfbce63a89	1698
elmot	1:d0dfbce63a89	1699	/**
elmot	1:d0dfbce63a89	1700	* @brief Clear Not Acknowledge flag.
elmot	1:d0dfbce63a89	1701	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
elmot	1:d0dfbce63a89	1702	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1703	* @retval None
elmot	1:d0dfbce63a89	1704	*/
elmot	1:d0dfbce63a89	1705	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1706	{
elmot	1:d0dfbce63a89	1707	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
elmot	1:d0dfbce63a89	1708	}
elmot	1:d0dfbce63a89	1709
elmot	1:d0dfbce63a89	1710	/**
elmot	1:d0dfbce63a89	1711	* @brief Clear Stop detection flag.
elmot	1:d0dfbce63a89	1712	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
elmot	1:d0dfbce63a89	1713	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1714	* @retval None
elmot	1:d0dfbce63a89	1715	*/
elmot	1:d0dfbce63a89	1716	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1717	{
elmot	1:d0dfbce63a89	1718	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
elmot	1:d0dfbce63a89	1719	}
elmot	1:d0dfbce63a89	1720
elmot	1:d0dfbce63a89	1721	/**
elmot	1:d0dfbce63a89	1722	* @brief Clear Transmit data register empty flag (TXE).
elmot	1:d0dfbce63a89	1723	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
elmot	1:d0dfbce63a89	1724	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
elmot	1:d0dfbce63a89	1725	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1726	* @retval None
elmot	1:d0dfbce63a89	1727	*/
elmot	1:d0dfbce63a89	1728	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1729	{
elmot	1:d0dfbce63a89	1730	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
elmot	1:d0dfbce63a89	1731	}
elmot	1:d0dfbce63a89	1732
elmot	1:d0dfbce63a89	1733	/**
elmot	1:d0dfbce63a89	1734	* @brief Clear Bus error flag.
elmot	1:d0dfbce63a89	1735	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
elmot	1:d0dfbce63a89	1736	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1737	* @retval None
elmot	1:d0dfbce63a89	1738	*/
elmot	1:d0dfbce63a89	1739	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1740	{
elmot	1:d0dfbce63a89	1741	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
elmot	1:d0dfbce63a89	1742	}
elmot	1:d0dfbce63a89	1743
elmot	1:d0dfbce63a89	1744	/**
elmot	1:d0dfbce63a89	1745	* @brief Clear Arbitration lost flag.
elmot	1:d0dfbce63a89	1746	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
elmot	1:d0dfbce63a89	1747	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1748	* @retval None
elmot	1:d0dfbce63a89	1749	*/
elmot	1:d0dfbce63a89	1750	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1751	{
elmot	1:d0dfbce63a89	1752	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
elmot	1:d0dfbce63a89	1753	}
elmot	1:d0dfbce63a89	1754
elmot	1:d0dfbce63a89	1755	/**
elmot	1:d0dfbce63a89	1756	* @brief Clear Overrun/Underrun flag.
elmot	1:d0dfbce63a89	1757	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
elmot	1:d0dfbce63a89	1758	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1759	* @retval None
elmot	1:d0dfbce63a89	1760	*/
elmot	1:d0dfbce63a89	1761	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1762	{
elmot	1:d0dfbce63a89	1763	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
elmot	1:d0dfbce63a89	1764	}
elmot	1:d0dfbce63a89	1765
elmot	1:d0dfbce63a89	1766	/**
elmot	1:d0dfbce63a89	1767	* @brief Indicate the status of SMBus PEC error flag in reception.
elmot	1:d0dfbce63a89	1768	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1769	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1770	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1771	* SET: When the received PEC does not match with the PEC register content.
elmot	1:d0dfbce63a89	1772	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
elmot	1:d0dfbce63a89	1773	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1774	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1775	*/
elmot	1:d0dfbce63a89	1776	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1777	{
elmot	1:d0dfbce63a89	1778	return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
elmot	1:d0dfbce63a89	1779	}
elmot	1:d0dfbce63a89	1780
elmot	1:d0dfbce63a89	1781	/**
elmot	1:d0dfbce63a89	1782	* @brief Indicate the status of SMBus Timeout detection flag.
elmot	1:d0dfbce63a89	1783	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1784	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1785	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1786	* SET: When a timeout or extended clock timeout occurs.
elmot	1:d0dfbce63a89	1787	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
elmot	1:d0dfbce63a89	1788	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1789	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1790	*/
elmot	1:d0dfbce63a89	1791	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1792	{
elmot	1:d0dfbce63a89	1793	return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
elmot	1:d0dfbce63a89	1794	}
elmot	1:d0dfbce63a89	1795
elmot	1:d0dfbce63a89	1796	/**
elmot	1:d0dfbce63a89	1797	* @brief Indicate the status of SMBus alert flag.
elmot	1:d0dfbce63a89	1798	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1799	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1800	* @note RESET: Clear default value.
elmot	1:d0dfbce63a89	1801	* SET: When SMBus host configuration, SMBus alert enabled and
elmot	1:d0dfbce63a89	1802	* a falling edge event occurs on SMBA pin.
elmot	1:d0dfbce63a89	1803	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
elmot	1:d0dfbce63a89	1804	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1805	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1806	*/
elmot	1:d0dfbce63a89	1807	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1808	{
elmot	1:d0dfbce63a89	1809	return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
elmot	1:d0dfbce63a89	1810	}
elmot	1:d0dfbce63a89	1811
elmot	1:d0dfbce63a89	1812	/**
elmot	1:d0dfbce63a89	1813	* @brief Clear SMBus PEC error flag.
elmot	1:d0dfbce63a89	1814	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1815	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1816	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
elmot	1:d0dfbce63a89	1817	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1818	* @retval None
elmot	1:d0dfbce63a89	1819	*/
elmot	1:d0dfbce63a89	1820	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1821	{
elmot	1:d0dfbce63a89	1822	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
elmot	1:d0dfbce63a89	1823	}
elmot	1:d0dfbce63a89	1824
elmot	1:d0dfbce63a89	1825	/**
elmot	1:d0dfbce63a89	1826	* @brief Clear SMBus Timeout detection flag.
elmot	1:d0dfbce63a89	1827	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1828	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1829	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
elmot	1:d0dfbce63a89	1830	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1831	* @retval None
elmot	1:d0dfbce63a89	1832	*/
elmot	1:d0dfbce63a89	1833	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1834	{
elmot	1:d0dfbce63a89	1835	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
elmot	1:d0dfbce63a89	1836	}
elmot	1:d0dfbce63a89	1837
elmot	1:d0dfbce63a89	1838	/**
elmot	1:d0dfbce63a89	1839	* @brief Clear SMBus Alert flag.
elmot	1:d0dfbce63a89	1840	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	1841	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	1842	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
elmot	1:d0dfbce63a89	1843	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1844	* @retval None
elmot	1:d0dfbce63a89	1845	*/
elmot	1:d0dfbce63a89	1846	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1847	{
elmot	1:d0dfbce63a89	1848	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
elmot	1:d0dfbce63a89	1849	}
elmot	1:d0dfbce63a89	1850
elmot	1:d0dfbce63a89	1851	/**
elmot	1:d0dfbce63a89	1852	* @}
elmot	1:d0dfbce63a89	1853	*/
elmot	1:d0dfbce63a89	1854
elmot	1:d0dfbce63a89	1855	/** @defgroup I2C_LL_EF_Data_Management Data_Management
elmot	1:d0dfbce63a89	1856	* @{
elmot	1:d0dfbce63a89	1857	*/
elmot	1:d0dfbce63a89	1858
elmot	1:d0dfbce63a89	1859	/**
elmot	1:d0dfbce63a89	1860	* @brief Enable automatic STOP condition generation (master mode).
elmot	1:d0dfbce63a89	1861	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
elmot	1:d0dfbce63a89	1862	* This bit has no effect in slave mode or when RELOAD bit is set.
elmot	1:d0dfbce63a89	1863	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
elmot	1:d0dfbce63a89	1864	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1865	* @retval None
elmot	1:d0dfbce63a89	1866	*/
elmot	1:d0dfbce63a89	1867	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1868	{
elmot	1:d0dfbce63a89	1869	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
elmot	1:d0dfbce63a89	1870	}
elmot	1:d0dfbce63a89	1871
elmot	1:d0dfbce63a89	1872	/**
elmot	1:d0dfbce63a89	1873	* @brief Disable automatic STOP condition generation (master mode).
elmot	1:d0dfbce63a89	1874	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
elmot	1:d0dfbce63a89	1875	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
elmot	1:d0dfbce63a89	1876	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1877	* @retval None
elmot	1:d0dfbce63a89	1878	*/
elmot	1:d0dfbce63a89	1879	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1880	{
elmot	1:d0dfbce63a89	1881	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
elmot	1:d0dfbce63a89	1882	}
elmot	1:d0dfbce63a89	1883
elmot	1:d0dfbce63a89	1884	/**
elmot	1:d0dfbce63a89	1885	* @brief Check if automatic STOP condition is enabled or disabled.
elmot	1:d0dfbce63a89	1886	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
elmot	1:d0dfbce63a89	1887	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1888	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1889	*/
elmot	1:d0dfbce63a89	1890	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1891	{
elmot	1:d0dfbce63a89	1892	return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
elmot	1:d0dfbce63a89	1893	}
elmot	1:d0dfbce63a89	1894
elmot	1:d0dfbce63a89	1895	/**
elmot	1:d0dfbce63a89	1896	* @brief Enable reload mode (master mode).
elmot	1:d0dfbce63a89	1897	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
elmot	1:d0dfbce63a89	1898	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
elmot	1:d0dfbce63a89	1899	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1900	* @retval None
elmot	1:d0dfbce63a89	1901	*/
elmot	1:d0dfbce63a89	1902	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1903	{
elmot	1:d0dfbce63a89	1904	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
elmot	1:d0dfbce63a89	1905	}
elmot	1:d0dfbce63a89	1906
elmot	1:d0dfbce63a89	1907	/**
elmot	1:d0dfbce63a89	1908	* @brief Disable reload mode (master mode).
elmot	1:d0dfbce63a89	1909	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
elmot	1:d0dfbce63a89	1910	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
elmot	1:d0dfbce63a89	1911	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1912	* @retval None
elmot	1:d0dfbce63a89	1913	*/
elmot	1:d0dfbce63a89	1914	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1915	{
elmot	1:d0dfbce63a89	1916	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
elmot	1:d0dfbce63a89	1917	}
elmot	1:d0dfbce63a89	1918
elmot	1:d0dfbce63a89	1919	/**
elmot	1:d0dfbce63a89	1920	* @brief Check if reload mode is enabled or disabled.
elmot	1:d0dfbce63a89	1921	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
elmot	1:d0dfbce63a89	1922	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1923	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	1924	*/
elmot	1:d0dfbce63a89	1925	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1926	{
elmot	1:d0dfbce63a89	1927	return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
elmot	1:d0dfbce63a89	1928	}
elmot	1:d0dfbce63a89	1929
elmot	1:d0dfbce63a89	1930	/**
elmot	1:d0dfbce63a89	1931	* @brief Configure the number of bytes for transfer.
elmot	1:d0dfbce63a89	1932	* @note Changing these bits when START bit is set is not allowed.
elmot	1:d0dfbce63a89	1933	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
elmot	1:d0dfbce63a89	1934	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1935	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
elmot	1:d0dfbce63a89	1936	* @retval None
elmot	1:d0dfbce63a89	1937	*/
elmot	1:d0dfbce63a89	1938	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
elmot	1:d0dfbce63a89	1939	{
elmot	1:d0dfbce63a89	1940	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
elmot	1:d0dfbce63a89	1941	}
elmot	1:d0dfbce63a89	1942
elmot	1:d0dfbce63a89	1943	/**
elmot	1:d0dfbce63a89	1944	* @brief Get the number of bytes configured for transfer.
elmot	1:d0dfbce63a89	1945	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
elmot	1:d0dfbce63a89	1946	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1947	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
elmot	1:d0dfbce63a89	1948	*/
elmot	1:d0dfbce63a89	1949	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1950	{
elmot	1:d0dfbce63a89	1951	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
elmot	1:d0dfbce63a89	1952	}
elmot	1:d0dfbce63a89	1953
elmot	1:d0dfbce63a89	1954	/**
elmot	1:d0dfbce63a89	1955	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
elmot	1:d0dfbce63a89	1956	* @note Usage in Slave mode only.
elmot	1:d0dfbce63a89	1957	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
elmot	1:d0dfbce63a89	1958	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1959	* @param TypeAcknowledge This parameter can be one of the following values:
elmot	1:d0dfbce63a89	1960	* @arg @ref LL_I2C_ACK
elmot	1:d0dfbce63a89	1961	* @arg @ref LL_I2C_NACK
elmot	1:d0dfbce63a89	1962	* @retval None
elmot	1:d0dfbce63a89	1963	*/
elmot	1:d0dfbce63a89	1964	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
elmot	1:d0dfbce63a89	1965	{
elmot	1:d0dfbce63a89	1966	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
elmot	1:d0dfbce63a89	1967	}
elmot	1:d0dfbce63a89	1968
elmot	1:d0dfbce63a89	1969	/**
elmot	1:d0dfbce63a89	1970	* @brief Generate a STOP condition after the current byte transfer (master mode).
elmot	1:d0dfbce63a89	1971	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
elmot	1:d0dfbce63a89	1972	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1973	* @retval None
elmot	1:d0dfbce63a89	1974	*/
elmot	1:d0dfbce63a89	1975	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1976	{
elmot	1:d0dfbce63a89	1977	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
elmot	1:d0dfbce63a89	1978	}
elmot	1:d0dfbce63a89	1979
elmot	1:d0dfbce63a89	1980	/**
elmot	1:d0dfbce63a89	1981	* @brief Generate a START or RESTART condition
elmot	1:d0dfbce63a89	1982	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
elmot	1:d0dfbce63a89	1983	* This action has no effect when RELOAD is set.
elmot	1:d0dfbce63a89	1984	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
elmot	1:d0dfbce63a89	1985	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1986	* @retval None
elmot	1:d0dfbce63a89	1987	*/
elmot	1:d0dfbce63a89	1988	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	1989	{
elmot	1:d0dfbce63a89	1990	SET_BIT(I2Cx->CR2, I2C_CR2_START);
elmot	1:d0dfbce63a89	1991	}
elmot	1:d0dfbce63a89	1992
elmot	1:d0dfbce63a89	1993	/**
elmot	1:d0dfbce63a89	1994	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
elmot	1:d0dfbce63a89	1995	* @note The master sends the complete 10bit slave address read sequence :
elmot	1:d0dfbce63a89	1996	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
elmot	1:d0dfbce63a89	1997	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
elmot	1:d0dfbce63a89	1998	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	1999	* @retval None
elmot	1:d0dfbce63a89	2000	*/
elmot	1:d0dfbce63a89	2001	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2002	{
elmot	1:d0dfbce63a89	2003	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
elmot	1:d0dfbce63a89	2004	}
elmot	1:d0dfbce63a89	2005
elmot	1:d0dfbce63a89	2006	/**
elmot	1:d0dfbce63a89	2007	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
elmot	1:d0dfbce63a89	2008	* @note The master only sends the first 7 bits of 10bit address in Read direction.
elmot	1:d0dfbce63a89	2009	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
elmot	1:d0dfbce63a89	2010	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2011	* @retval None
elmot	1:d0dfbce63a89	2012	*/
elmot	1:d0dfbce63a89	2013	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2014	{
elmot	1:d0dfbce63a89	2015	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
elmot	1:d0dfbce63a89	2016	}
elmot	1:d0dfbce63a89	2017
elmot	1:d0dfbce63a89	2018	/**
elmot	1:d0dfbce63a89	2019	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
elmot	1:d0dfbce63a89	2020	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
elmot	1:d0dfbce63a89	2021	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2022	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	2023	*/
elmot	1:d0dfbce63a89	2024	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2025	{
elmot	1:d0dfbce63a89	2026	return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
elmot	1:d0dfbce63a89	2027	}
elmot	1:d0dfbce63a89	2028
elmot	1:d0dfbce63a89	2029	/**
elmot	1:d0dfbce63a89	2030	* @brief Configure the transfer direction (master mode).
elmot	1:d0dfbce63a89	2031	* @note Changing these bits when START bit is set is not allowed.
elmot	1:d0dfbce63a89	2032	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
elmot	1:d0dfbce63a89	2033	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2034	* @param TransferRequest This parameter can be one of the following values:
elmot	1:d0dfbce63a89	2035	* @arg @ref LL_I2C_REQUEST_WRITE
elmot	1:d0dfbce63a89	2036	* @arg @ref LL_I2C_REQUEST_READ
elmot	1:d0dfbce63a89	2037	* @retval None
elmot	1:d0dfbce63a89	2038	*/
elmot	1:d0dfbce63a89	2039	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
elmot	1:d0dfbce63a89	2040	{
elmot	1:d0dfbce63a89	2041	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
elmot	1:d0dfbce63a89	2042	}
elmot	1:d0dfbce63a89	2043
elmot	1:d0dfbce63a89	2044	/**
elmot	1:d0dfbce63a89	2045	* @brief Get the transfer direction requested (master mode).
elmot	1:d0dfbce63a89	2046	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
elmot	1:d0dfbce63a89	2047	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2048	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	2049	* @arg @ref LL_I2C_REQUEST_WRITE
elmot	1:d0dfbce63a89	2050	* @arg @ref LL_I2C_REQUEST_READ
elmot	1:d0dfbce63a89	2051	*/
elmot	1:d0dfbce63a89	2052	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2053	{
elmot	1:d0dfbce63a89	2054	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
elmot	1:d0dfbce63a89	2055	}
elmot	1:d0dfbce63a89	2056
elmot	1:d0dfbce63a89	2057	/**
elmot	1:d0dfbce63a89	2058	* @brief Configure the slave address for transfer (master mode).
elmot	1:d0dfbce63a89	2059	* @note Changing these bits when START bit is set is not allowed.
elmot	1:d0dfbce63a89	2060	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
elmot	1:d0dfbce63a89	2061	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2062	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
elmot	1:d0dfbce63a89	2063	* @retval None
elmot	1:d0dfbce63a89	2064	*/
elmot	1:d0dfbce63a89	2065	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
elmot	1:d0dfbce63a89	2066	{
elmot	1:d0dfbce63a89	2067	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
elmot	1:d0dfbce63a89	2068	}
elmot	1:d0dfbce63a89	2069
elmot	1:d0dfbce63a89	2070	/**
elmot	1:d0dfbce63a89	2071	* @brief Get the slave address programmed for transfer.
elmot	1:d0dfbce63a89	2072	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
elmot	1:d0dfbce63a89	2073	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2074	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
elmot	1:d0dfbce63a89	2075	*/
elmot	1:d0dfbce63a89	2076	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2077	{
elmot	1:d0dfbce63a89	2078	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
elmot	1:d0dfbce63a89	2079	}
elmot	1:d0dfbce63a89	2080
elmot	1:d0dfbce63a89	2081	/**
elmot	1:d0dfbce63a89	2082	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
elmot	1:d0dfbce63a89	2083	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2084	* CR2 ADD10 LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2085	* CR2 RD_WRN LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2086	* CR2 START LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2087	* CR2 STOP LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2088	* CR2 RELOAD LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2089	* CR2 NBYTES LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2090	* CR2 AUTOEND LL_I2C_HandleTransfer\n
elmot	1:d0dfbce63a89	2091	* CR2 HEAD10R LL_I2C_HandleTransfer
elmot	1:d0dfbce63a89	2092	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2093	* @param SlaveAddr Specifies the slave address to be programmed.
elmot	1:d0dfbce63a89	2094	* @param SlaveAddrSize This parameter can be one of the following values:
elmot	1:d0dfbce63a89	2095	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
elmot	1:d0dfbce63a89	2096	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
elmot	1:d0dfbce63a89	2097	* @param TransferSize Specifies the number of bytes to be programmed.
elmot	1:d0dfbce63a89	2098	* This parameter must be a value between 0 and 255.
elmot	1:d0dfbce63a89	2099	* @param EndMode This parameter can be one of the following values:
elmot	1:d0dfbce63a89	2100	* @arg @ref LL_I2C_MODE_RELOAD
elmot	1:d0dfbce63a89	2101	* @arg @ref LL_I2C_MODE_AUTOEND
elmot	1:d0dfbce63a89	2102	* @arg @ref LL_I2C_MODE_SOFTEND
elmot	1:d0dfbce63a89	2103	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
elmot	1:d0dfbce63a89	2104	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
elmot	1:d0dfbce63a89	2105	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
elmot	1:d0dfbce63a89	2106	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
elmot	1:d0dfbce63a89	2107	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
elmot	1:d0dfbce63a89	2108	* @param Request This parameter can be one of the following values:
elmot	1:d0dfbce63a89	2109	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
elmot	1:d0dfbce63a89	2110	* @arg @ref LL_I2C_GENERATE_STOP
elmot	1:d0dfbce63a89	2111	* @arg @ref LL_I2C_GENERATE_START_READ
elmot	1:d0dfbce63a89	2112	* @arg @ref LL_I2C_GENERATE_START_WRITE
elmot	1:d0dfbce63a89	2113	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
elmot	1:d0dfbce63a89	2114	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
elmot	1:d0dfbce63a89	2115	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
elmot	1:d0dfbce63a89	2116	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
elmot	1:d0dfbce63a89	2117	* @retval None
elmot	1:d0dfbce63a89	2118	*/
elmot	1:d0dfbce63a89	2119	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
elmot	1:d0dfbce63a89	2120	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
elmot	1:d0dfbce63a89	2121	{
elmot	1:d0dfbce63a89	2122	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
elmot	1:d0dfbce63a89	2123	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
elmot	1:d0dfbce63a89	2124	SlaveAddr \| SlaveAddrSize \| TransferSize << I2C_POSITION_CR2_NBYTES \| EndMode \| Request);
elmot	1:d0dfbce63a89	2125	}
elmot	1:d0dfbce63a89	2126
elmot	1:d0dfbce63a89	2127	/**
elmot	1:d0dfbce63a89	2128	* @brief Indicate the value of transfer direction (slave mode).
elmot	1:d0dfbce63a89	2129	* @note RESET: Write transfer, Slave enters in receiver mode.
elmot	1:d0dfbce63a89	2130	* SET: Read transfer, Slave enters in transmitter mode.
elmot	1:d0dfbce63a89	2131	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
elmot	1:d0dfbce63a89	2132	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2133	* @retval Returned value can be one of the following values:
elmot	1:d0dfbce63a89	2134	* @arg @ref LL_I2C_DIRECTION_WRITE
elmot	1:d0dfbce63a89	2135	* @arg @ref LL_I2C_DIRECTION_READ
elmot	1:d0dfbce63a89	2136	*/
elmot	1:d0dfbce63a89	2137	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2138	{
elmot	1:d0dfbce63a89	2139	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
elmot	1:d0dfbce63a89	2140	}
elmot	1:d0dfbce63a89	2141
elmot	1:d0dfbce63a89	2142	/**
elmot	1:d0dfbce63a89	2143	* @brief Return the slave matched address.
elmot	1:d0dfbce63a89	2144	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
elmot	1:d0dfbce63a89	2145	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2146	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
elmot	1:d0dfbce63a89	2147	*/
elmot	1:d0dfbce63a89	2148	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2149	{
elmot	1:d0dfbce63a89	2150	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
elmot	1:d0dfbce63a89	2151	}
elmot	1:d0dfbce63a89	2152
elmot	1:d0dfbce63a89	2153	/**
elmot	1:d0dfbce63a89	2154	* @brief Enable internal comparison of Packet Error byte (transmission or reception mode).
elmot	1:d0dfbce63a89	2155	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	2156	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	2157	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
elmot	1:d0dfbce63a89	2158	* This bit has no effect when RELOAD bit is set.
elmot	1:d0dfbce63a89	2159	* This bit has no effect in device mode when SBC bit is not set.
elmot	1:d0dfbce63a89	2160	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
elmot	1:d0dfbce63a89	2161	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2162	* @retval None
elmot	1:d0dfbce63a89	2163	*/
elmot	1:d0dfbce63a89	2164	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2165	{
elmot	1:d0dfbce63a89	2166	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
elmot	1:d0dfbce63a89	2167	}
elmot	1:d0dfbce63a89	2168
elmot	1:d0dfbce63a89	2169	/**
elmot	1:d0dfbce63a89	2170	* @brief Check if Packet Error byte internal comparison is requested or not.
elmot	1:d0dfbce63a89	2171	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	2172	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	2173	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
elmot	1:d0dfbce63a89	2174	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2175	* @retval State of bit (1 or 0).
elmot	1:d0dfbce63a89	2176	*/
elmot	1:d0dfbce63a89	2177	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2178	{
elmot	1:d0dfbce63a89	2179	return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
elmot	1:d0dfbce63a89	2180	}
elmot	1:d0dfbce63a89	2181
elmot	1:d0dfbce63a89	2182	/**
elmot	1:d0dfbce63a89	2183	* @brief Get the Packet Error byte calculated.
elmot	1:d0dfbce63a89	2184	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
elmot	1:d0dfbce63a89	2185	* SMBus feature is supported by the I2Cx Instance.
elmot	1:d0dfbce63a89	2186	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
elmot	1:d0dfbce63a89	2187	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2188	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
elmot	1:d0dfbce63a89	2189	*/
elmot	1:d0dfbce63a89	2190	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2191	{
elmot	1:d0dfbce63a89	2192	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
elmot	1:d0dfbce63a89	2193	}
elmot	1:d0dfbce63a89	2194
elmot	1:d0dfbce63a89	2195	/**
elmot	1:d0dfbce63a89	2196	* @brief Read Receive Data register.
elmot	1:d0dfbce63a89	2197	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
elmot	1:d0dfbce63a89	2198	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2199	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
elmot	1:d0dfbce63a89	2200	*/
elmot	1:d0dfbce63a89	2201	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
elmot	1:d0dfbce63a89	2202	{
elmot	1:d0dfbce63a89	2203	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
elmot	1:d0dfbce63a89	2204	}
elmot	1:d0dfbce63a89	2205
elmot	1:d0dfbce63a89	2206	/**
elmot	1:d0dfbce63a89	2207	* @brief Write in Transmit Data Register .
elmot	1:d0dfbce63a89	2208	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
elmot	1:d0dfbce63a89	2209	* @param I2Cx I2C Instance.
elmot	1:d0dfbce63a89	2210	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
elmot	1:d0dfbce63a89	2211	* @retval None
elmot	1:d0dfbce63a89	2212	*/
elmot	1:d0dfbce63a89	2213	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
elmot	1:d0dfbce63a89	2214	{
elmot	1:d0dfbce63a89	2215	WRITE_REG(I2Cx->TXDR, Data);
elmot	1:d0dfbce63a89	2216	}
elmot	1:d0dfbce63a89	2217
elmot	1:d0dfbce63a89	2218	/**
elmot	1:d0dfbce63a89	2219	* @}
elmot	1:d0dfbce63a89	2220	*/
elmot	1:d0dfbce63a89	2221
elmot	1:d0dfbce63a89	2222	#if defined(USE_FULL_LL_DRIVER)
elmot	1:d0dfbce63a89	2223	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
elmot	1:d0dfbce63a89	2224	* @{
elmot	1:d0dfbce63a89	2225	*/
elmot	1:d0dfbce63a89	2226
elmot	1:d0dfbce63a89	2227	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
elmot	1:d0dfbce63a89	2228	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
elmot	1:d0dfbce63a89	2229	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
elmot	1:d0dfbce63a89	2230
elmot	1:d0dfbce63a89	2231
elmot	1:d0dfbce63a89	2232	/**
elmot	1:d0dfbce63a89	2233	* @}
elmot	1:d0dfbce63a89	2234	*/
elmot	1:d0dfbce63a89	2235	#endif /* USE_FULL_LL_DRIVER */
elmot	1:d0dfbce63a89	2236
elmot	1:d0dfbce63a89	2237	/**
elmot	1:d0dfbce63a89	2238	* @}
elmot	1:d0dfbce63a89	2239	*/
elmot	1:d0dfbce63a89	2240
elmot	1:d0dfbce63a89	2241	/**
elmot	1:d0dfbce63a89	2242	* @}
elmot	1:d0dfbce63a89	2243	*/
elmot	1:d0dfbce63a89	2244
elmot	1:d0dfbce63a89	2245	#endif /* I2C1 \|\| I2C2 \|\| I2C3 */
elmot	1:d0dfbce63a89	2246
elmot	1:d0dfbce63a89	2247	/**
elmot	1:d0dfbce63a89	2248	* @}
elmot	1:d0dfbce63a89	2249	*/
elmot	1:d0dfbce63a89	2250
elmot	1:d0dfbce63a89	2251	#ifdef __cplusplus
elmot	1:d0dfbce63a89	2252	}
elmot	1:d0dfbce63a89	2253	#endif
elmot	1:d0dfbce63a89	2254
elmot	1:d0dfbce63a89	2255	#endif /* __STM32L4xx_LL_I2C_H */
elmot	1:d0dfbce63a89	2256
elmot	1:d0dfbce63a89	2257	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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