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stm32l4xx_ll_usb.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_usb.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief USB Low Layer HAL module driver. 00008 * 00009 * This file provides firmware functions to manage the following 00010 * functionalities of the USB Peripheral Controller: 00011 * + Initialization/de-initialization functions 00012 * + I/O operation functions 00013 * + Peripheral Control functions 00014 * + Peripheral State functions 00015 * 00016 @verbatim 00017 ============================================================================== 00018 ##### How to use this driver ##### 00019 ============================================================================== 00020 [..] 00021 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. 00022 00023 (#) Call USB_CoreInit() API to initialize the USB Core peripheral. 00024 00025 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. 00026 00027 @endverbatim 00028 ****************************************************************************** 00029 * @attention 00030 * 00031 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00032 * 00033 * Redistribution and use in source and binary forms, with or without modification, 00034 * are permitted provided that the following conditions are met: 00035 * 1. Redistributions of source code must retain the above copyright notice, 00036 * this list of conditions and the following disclaimer. 00037 * 2. Redistributions in binary form must reproduce the above copyright notice, 00038 * this list of conditions and the following disclaimer in the documentation 00039 * and/or other materials provided with the distribution. 00040 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00041 * may be used to endorse or promote products derived from this software 00042 * without specific prior written permission. 00043 * 00044 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00045 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00046 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00047 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00048 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00049 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00050 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00051 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00052 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00053 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00054 * 00055 ****************************************************************************** 00056 */ 00057 00058 /* Includes ------------------------------------------------------------------*/ 00059 #include "stm32l4xx_hal.h" 00060 00061 /** @defgroup USB_LL USB Low Layer 00062 * @brief Low layer module for USB_FS and USB_OTG_FS drivers 00063 * @{ 00064 */ 00065 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) 00066 00067 #if defined(STM32L475xx) || defined(STM32L476xx) || \ 00068 defined(STM32L485xx) || defined(STM32L486xx) || \ 00069 defined(STM32L432xx) || defined(STM32L433xx) || \ 00070 defined(STM32L442xx) || defined(STM32L443xx) 00071 00072 /** @addtogroup STM32L4xx_LL_USB_DRIVER 00073 * @{ 00074 */ 00075 00076 00077 00078 /* Private typedef -----------------------------------------------------------*/ 00079 /* Private define ------------------------------------------------------------*/ 00080 /* Private macro -------------------------------------------------------------*/ 00081 /* Private variables ---------------------------------------------------------*/ 00082 /* Private function prototypes -----------------------------------------------*/ 00083 /* Private functions ---------------------------------------------------------*/ 00084 #if defined (USB_OTG_FS) 00085 /** @defgroup USB_LL_Private_Functions USB Low Layer Private Functions 00086 * @{ 00087 */ 00088 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); 00089 /** 00090 * @} 00091 */ 00092 #endif /* USB_OTG_FS */ 00093 /* Exported functions --------------------------------------------------------*/ 00094 00095 /** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions 00096 * @{ 00097 */ 00098 00099 /** @defgroup LL_USB_Group1 Initialization/de-initialization functions 00100 * @brief Initialization and Configuration functions 00101 * 00102 @verbatim 00103 =============================================================================== 00104 ##### Initialization/de-initialization functions ##### 00105 =============================================================================== 00106 [..] This section provides functions allowing to: 00107 00108 @endverbatim 00109 * @{ 00110 */ 00111 /*============================================================================== 00112 USB OTG FS peripheral available on STM32L475xx, STM32L476xx, STM32L485xx and 00113 STM32L486xx devices 00114 ==============================================================================*/ 00115 #if defined (USB_OTG_FS) 00116 /** 00117 * @brief Initializes the USB Core 00118 * @param USBx: USB Instance 00119 * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains 00120 * the configuration information for the specified USBx peripheral. 00121 * @retval HAL status 00122 */ 00123 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) 00124 { 00125 /* Prevent unused argument(s) compilation warning */ 00126 UNUSED(cfg); 00127 00128 /* Select FS Embedded PHY */ 00129 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; 00130 00131 /* Reset after a PHY select and set Host mode */ 00132 USB_CoreReset(USBx); 00133 00134 /* Deactivate the power down*/ 00135 USBx->GCCFG = USB_OTG_GCCFG_PWRDWN; 00136 00137 return HAL_OK; 00138 } 00139 00140 /** 00141 * @brief USB_EnableGlobalInt 00142 * Enables the controller's Global Int in the AHB Config reg 00143 * @param USBx: Selected device 00144 * @retval HAL status 00145 */ 00146 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) 00147 { 00148 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; 00149 return HAL_OK; 00150 } 00151 00152 00153 /** 00154 * @brief USB_DisableGlobalInt 00155 * Disable the controller's Global Int in the AHB Config reg 00156 * @param USBx: Selected device 00157 * @retval HAL status 00158 */ 00159 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) 00160 { 00161 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; 00162 return HAL_OK; 00163 } 00164 00165 /** 00166 * @brief USB_SetCurrentMode : Set functional mode 00167 * @param USBx: Selected device 00168 * @param mode: current core mode 00169 * This parameter can be one of these values: 00170 * @arg USB_OTG_DEVICE_MODE: Peripheral mode 00171 * @arg USB_OTG_HOST_MODE: Host mode 00172 * @arg USB_OTG_DRD_MODE: Dual Role Device mode 00173 * @retval HAL status 00174 */ 00175 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_ModeTypeDef mode) 00176 { 00177 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); 00178 00179 if ( mode == USB_HOST_MODE) 00180 { 00181 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; 00182 } 00183 else if ( mode == USB_DEVICE_MODE) 00184 { 00185 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; 00186 } 00187 HAL_Delay(50); 00188 00189 return HAL_OK; 00190 } 00191 00192 /** 00193 * @brief USB_DevInit : Initializes the USB_OTG controller registers 00194 * for device mode 00195 * @param USBx: Selected device 00196 * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains 00197 * the configuration information for the specified USBx peripheral. 00198 * @retval HAL status 00199 */ 00200 HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) 00201 { 00202 uint32_t index = 0; 00203 00204 /*Activate VBUS Sensing B */ 00205 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; 00206 00207 if (cfg.vbus_sensing_enable == 0) 00208 { 00209 /* Deactivate VBUS Sensing B */ 00210 USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN; 00211 00212 /* B-peripheral session valid override enable*/ 00213 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; 00214 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; 00215 } 00216 00217 /* Restart the Phy Clock */ 00218 USBx_PCGCCTL = 0; 00219 00220 /* Device mode configuration */ 00221 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; 00222 00223 /* Set Full speed phy */ 00224 USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL); 00225 00226 /* Flush the FIFOs */ 00227 USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */ 00228 USB_FlushRxFifo(USBx); 00229 00230 /* Clear all pending Device Interrupts */ 00231 USBx_DEVICE->DIEPMSK = 0; 00232 USBx_DEVICE->DOEPMSK = 0; 00233 USBx_DEVICE->DAINT = 0xFFFFFFFF; 00234 USBx_DEVICE->DAINTMSK = 0; 00235 00236 for (index = 0; index < cfg.dev_endpoints ; index++) 00237 { 00238 if ((USBx_INEP(index)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) 00239 { 00240 USBx_INEP(index)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); 00241 } 00242 else 00243 { 00244 USBx_INEP(index)->DIEPCTL = 0; 00245 } 00246 00247 USBx_INEP(index)->DIEPTSIZ = 0; 00248 USBx_INEP(index)->DIEPINT = 0xFF; 00249 } 00250 00251 for (index = 0; index < cfg.dev_endpoints ; index++) 00252 { 00253 if ((USBx_OUTEP(index)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) 00254 { 00255 USBx_OUTEP(index)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); 00256 } 00257 else 00258 { 00259 USBx_OUTEP(index)->DOEPCTL = 0; 00260 } 00261 00262 USBx_OUTEP(index)->DOEPTSIZ = 0; 00263 USBx_OUTEP(index)->DOEPINT = 0xFF; 00264 } 00265 00266 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); 00267 00268 if (cfg.dma_enable == 1) 00269 { 00270 /*Set threshold parameters */ 00271 USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6); 00272 USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN); 00273 00274 index= USBx_DEVICE->DTHRCTL; 00275 } 00276 00277 /* Disable all interrupts. */ 00278 USBx->GINTMSK = 0; 00279 00280 /* Clear any pending interrupts */ 00281 USBx->GINTSTS = 0xBFFFFFFF; 00282 00283 /* Enable the common interrupts */ 00284 if (cfg.dma_enable == DISABLE) 00285 { 00286 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 00287 } 00288 00289 /* Enable interrupts matching to the Device mode ONLY */ 00290 USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\ 00291 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\ 00292 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\ 00293 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); 00294 00295 if(cfg.Sof_enable ) 00296 { 00297 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; 00298 } 00299 00300 if (cfg.vbus_sensing_enable == ENABLE) 00301 { 00302 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); 00303 } 00304 00305 return HAL_OK; 00306 } 00307 00308 00309 /** 00310 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO 00311 * @param USBx: Selected device 00312 * @param num: FIFO number 00313 * This parameter can be a value from 1 to 15 00314 15 means Flush all Tx FIFOs 00315 * @retval HAL status 00316 */ 00317 HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num) 00318 { 00319 uint32_t count = 0; 00320 00321 USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6)); 00322 00323 do 00324 { 00325 if (++count > 200000) 00326 { 00327 return HAL_TIMEOUT; 00328 } 00329 } 00330 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); 00331 00332 return HAL_OK; 00333 } 00334 00335 00336 /** 00337 * @brief USB_FlushRxFifo : Flush Rx FIFO 00338 * @param USBx: Selected device 00339 * @retval HAL status 00340 */ 00341 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) 00342 { 00343 uint32_t count = 0; 00344 00345 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; 00346 00347 do 00348 { 00349 if (++count > 200000) 00350 { 00351 return HAL_TIMEOUT; 00352 } 00353 } 00354 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); 00355 00356 return HAL_OK; 00357 } 00358 00359 /** 00360 * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register 00361 * depending the PHY type and the enumeration speed of the device. 00362 * @param USBx: Selected device 00363 * @param speed: device speed 00364 * This parameter can be one of these values: 00365 * @arg USB_OTG_SPEED_HIGH: High speed mode 00366 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode 00367 * @arg USB_OTG_SPEED_FULL: Full speed mode 00368 * @arg USB_OTG_SPEED_LOW: Low speed mode 00369 * @retval Hal status 00370 */ 00371 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed) 00372 { 00373 USBx_DEVICE->DCFG |= speed; 00374 return HAL_OK; 00375 } 00376 00377 /** 00378 * @brief USB_GetDevSpeed :Return the Dev Speed 00379 * @param USBx: Selected device 00380 * @retval speed : device speed 00381 * This parameter can be one of these values: 00382 * @arg USB_OTG_SPEED_HIGH: High speed mode 00383 * @arg USB_OTG_SPEED_FULL: Full speed mode 00384 * @arg USB_OTG_SPEED_LOW: Low speed mode 00385 */ 00386 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) 00387 { 00388 uint8_t speed = 0; 00389 00390 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) 00391 { 00392 speed = USB_OTG_SPEED_HIGH; 00393 } 00394 else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)|| 00395 ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ)) 00396 { 00397 speed = USB_OTG_SPEED_FULL; 00398 } 00399 else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) 00400 { 00401 speed = USB_OTG_SPEED_LOW; 00402 } 00403 00404 return speed; 00405 } 00406 00407 /** 00408 * @brief Activate and configure an endpoint 00409 * @param USBx: Selected device 00410 * @param ep: pointer to endpoint structure 00411 * @retval HAL status 00412 */ 00413 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) 00414 { 00415 if (ep->is_in == 1) 00416 { 00417 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); 00418 00419 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) 00420 { 00421 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ 00422 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 00423 } 00424 00425 } 00426 else 00427 { 00428 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); 00429 00430 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) 00431 { 00432 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ 00433 (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP)); 00434 } 00435 } 00436 return HAL_OK; 00437 } 00438 /** 00439 * @brief Activate and configure a dedicated endpoint 00440 * @param USBx: Selected device 00441 * @param ep: pointer to endpoint structure 00442 * @retval HAL status 00443 */ 00444 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) 00445 { 00446 static __IO uint32_t debug = 0; 00447 00448 /* Read DEPCTLn register */ 00449 if (ep->is_in == 1) 00450 { 00451 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0) 00452 { 00453 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ 00454 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 00455 } 00456 00457 00458 debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\ 00459 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP)); 00460 00461 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))); 00462 } 00463 else 00464 { 00465 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0) 00466 { 00467 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ 00468 ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); 00469 00470 debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE); 00471 debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL; 00472 debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\ 00473 ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP)); 00474 } 00475 00476 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16); 00477 } 00478 00479 return HAL_OK; 00480 } 00481 /** 00482 * @brief De-activate and de-initialize an endpoint 00483 * @param USBx: Selected device 00484 * @param ep: pointer to endpoint structure 00485 * @retval HAL status 00486 */ 00487 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) 00488 { 00489 /* Read DEPCTLn register */ 00490 if (ep->is_in == 1) 00491 { 00492 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); 00493 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); 00494 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; 00495 } 00496 else 00497 { 00498 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); 00499 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); 00500 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 00501 } 00502 return HAL_OK; 00503 } 00504 00505 /** 00506 * @brief De-activate and de-initialize a dedicated endpoint 00507 * @param USBx: Selected device 00508 * @param ep: pointer to endpoint structure 00509 * @retval HAL status 00510 */ 00511 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) 00512 { 00513 /* Read DEPCTLn register */ 00514 if (ep->is_in == 1) 00515 { 00516 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; 00517 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)))); 00518 } 00519 else 00520 { 00521 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; 00522 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16)); 00523 } 00524 return HAL_OK; 00525 } 00526 00527 /** 00528 * @brief USB_EPStartXfer : setup and starts a transfer over an EP 00529 * @param USBx: Selected device 00530 * @param ep: pointer to endpoint structure 00531 * @param dma: USB dma enabled or disabled 00532 * This parameter can be one of these values: 00533 * 0 : DMA feature not used 00534 * 1 : DMA feature used 00535 * @retval HAL status 00536 */ 00537 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) 00538 { 00539 uint16_t pktcnt = 0; 00540 00541 /* IN endpoint */ 00542 if (ep->is_in == 1) 00543 { 00544 /* Zero Length Packet? */ 00545 if (ep->xfer_len == 0) 00546 { 00547 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 00548 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; 00549 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 00550 } 00551 else 00552 { 00553 /* Program the transfer size and packet count 00554 * as follows: xfersize = N * maxpacket + 00555 * short_packet pktcnt = N + (short_packet 00556 * exist ? 1 : 0) 00557 */ 00558 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 00559 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 00560 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ; 00561 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 00562 00563 if (ep->type == EP_TYPE_ISOC) 00564 { 00565 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); 00566 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29)); 00567 } 00568 } 00569 if (ep->type != EP_TYPE_ISOC) 00570 { 00571 /* Enable the Tx FIFO Empty Interrupt for this EP */ 00572 if (ep->xfer_len > 0) 00573 { 00574 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num); 00575 } 00576 } 00577 00578 if (ep->type == EP_TYPE_ISOC) 00579 { 00580 if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) 00581 { 00582 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; 00583 } 00584 else 00585 { 00586 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; 00587 } 00588 } 00589 00590 /* EP enable, IN data in FIFO */ 00591 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 00592 00593 if (ep->type == EP_TYPE_ISOC) 00594 { 00595 USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma); 00596 } 00597 } 00598 else /* OUT endpoint */ 00599 { 00600 /* Program the transfer size and packet count as follows: 00601 * pktcnt = N 00602 * xfersize = N * maxpacket 00603 */ 00604 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 00605 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 00606 00607 if (ep->xfer_len == 0) 00608 { 00609 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); 00610 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; 00611 } 00612 else 00613 { 00614 pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket; 00615 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); ; 00616 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt)); 00617 } 00618 00619 if (ep->type == EP_TYPE_ISOC) 00620 { 00621 if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0) 00622 { 00623 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; 00624 } 00625 else 00626 { 00627 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; 00628 } 00629 } 00630 /* EP enable */ 00631 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 00632 } 00633 return HAL_OK; 00634 } 00635 00636 /** 00637 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0 00638 * @param USBx: Selected device 00639 * @param ep: pointer to endpoint structure 00640 * @param dma: USB dma enabled or disabled 00641 * This parameter can be one of these values: 00642 * 0 : DMA feature not used 00643 * 1 : DMA feature used 00644 * @retval HAL status 00645 */ 00646 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma) 00647 { 00648 /* IN endpoint */ 00649 if (ep->is_in == 1) 00650 { 00651 /* Zero Length Packet? */ 00652 if (ep->xfer_len == 0) 00653 { 00654 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 00655 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; 00656 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 00657 } 00658 else 00659 { 00660 /* Program the transfer size and packet count 00661 * as follows: xfersize = N * maxpacket + 00662 * short_packet pktcnt = N + (short_packet 00663 * exist ? 1 : 0) 00664 */ 00665 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); 00666 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); 00667 00668 if(ep->xfer_len > ep->maxpacket) 00669 { 00670 ep->xfer_len = ep->maxpacket; 00671 } 00672 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ; 00673 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); 00674 00675 } 00676 00677 /* Enable the Tx FIFO Empty Interrupt for this EP */ 00678 if (ep->xfer_len > 0) 00679 { 00680 atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num)); 00681 } 00682 00683 /* EP enable, IN data in FIFO */ 00684 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); 00685 } 00686 else /* OUT endpoint */ 00687 { 00688 /* Program the transfer size and packet count as follows: 00689 * pktcnt = N 00690 * xfersize = N * maxpacket 00691 */ 00692 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); 00693 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); 00694 00695 if (ep->xfer_len > 0) 00696 { 00697 ep->xfer_len = ep->maxpacket; 00698 } 00699 00700 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); 00701 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); 00702 00703 /* EP enable */ 00704 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); 00705 } 00706 return HAL_OK; 00707 } 00708 00709 /** 00710 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated 00711 * with the EP/channel 00712 * @param USBx: Selected device 00713 * @param src: pointer to source buffer 00714 * @param ch_ep_num: endpoint or host channel number 00715 * @param len: Number of bytes to write 00716 * @param dma: USB dma enabled or disabled 00717 * This parameter can be one of these values: 00718 * 0 : DMA feature not used 00719 * 1 : DMA feature used 00720 * @retval HAL status 00721 */ 00722 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) 00723 { 00724 uint32_t count32b= 0 , index= 0; 00725 count32b = (len + 3) / 4; 00726 for (index = 0; index < count32b; index++, src += 4) 00727 { 00728 USBx_DFIFO(ch_ep_num) = *((__packed uint32_t *)src); 00729 } 00730 return HAL_OK; 00731 } 00732 00733 /** 00734 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated 00735 * with the EP/channel 00736 * @param USBx: Selected device 00737 * @param src: source pointer 00738 * @param ch_ep_num: endpoint or host channel number 00739 * @param len: Number of bytes to read 00740 * @param dma: USB dma enabled or disabled 00741 * This parameter can be one of these values: 00742 * 0 : DMA feature not used 00743 * 1 : DMA feature used 00744 * @retval pointer to destination buffer 00745 */ 00746 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) 00747 { 00748 uint32_t index=0; 00749 uint32_t count32b = (len + 3) / 4; 00750 00751 for ( index = 0; index < count32b; index++, dest += 4 ) 00752 { 00753 *(__packed uint32_t *)dest = USBx_DFIFO(0); 00754 00755 } 00756 return ((void *)dest); 00757 } 00758 00759 /** 00760 * @brief USB_EPSetStall : set a stall condition over an EP 00761 * @param USBx: Selected device 00762 * @param ep: pointer to endpoint structure 00763 * @retval HAL status 00764 */ 00765 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep) 00766 { 00767 if (ep->is_in == 1) 00768 { 00769 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0) 00770 { 00771 USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); 00772 } 00773 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; 00774 } 00775 else 00776 { 00777 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0) 00778 { 00779 USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); 00780 } 00781 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; 00782 } 00783 return HAL_OK; 00784 } 00785 00786 00787 /** 00788 * @brief USB_EPClearStall : Clear a stall condition over an EP 00789 * @param USBx: Selected device 00790 * @param ep: pointer to endpoint structure 00791 * @retval HAL status 00792 */ 00793 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) 00794 { 00795 if (ep->is_in == 1) 00796 { 00797 USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; 00798 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) 00799 { 00800 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 00801 } 00802 } 00803 else 00804 { 00805 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; 00806 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) 00807 { 00808 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ 00809 } 00810 } 00811 return HAL_OK; 00812 } 00813 00814 /** 00815 * @brief USB_StopDevice : Stop the USB device mode 00816 * @param USBx: Selected device 00817 * @retval HAL status 00818 */ 00819 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) 00820 { 00821 uint32_t index; 00822 00823 /* Clear Pending interrupt */ 00824 for (index = 0; index < 15 ; index++) 00825 { 00826 USBx_INEP(index)->DIEPINT = 0xFF; 00827 USBx_OUTEP(index)->DOEPINT = 0xFF; 00828 } 00829 USBx_DEVICE->DAINT = 0xFFFFFFFF; 00830 00831 /* Clear interrupt masks */ 00832 USBx_DEVICE->DIEPMSK = 0; 00833 USBx_DEVICE->DOEPMSK = 0; 00834 USBx_DEVICE->DAINTMSK = 0; 00835 00836 /* Flush the FIFO */ 00837 USB_FlushRxFifo(USBx); 00838 USB_FlushTxFifo(USBx , 0x10 ); 00839 00840 return HAL_OK; 00841 } 00842 00843 /** 00844 * @brief USB_SetDevAddress : Stop the USB device mode 00845 * @param USBx: Selected device 00846 * @param address: new device address to be assigned 00847 * This parameter can be a value from 0 to 255 00848 * @retval HAL status 00849 */ 00850 HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address) 00851 { 00852 USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD); 00853 USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ; 00854 00855 return HAL_OK; 00856 } 00857 00858 /** 00859 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down 00860 * @param USBx: Selected device 00861 * @retval HAL status 00862 */ 00863 HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx) 00864 { 00865 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ; 00866 HAL_Delay(3); 00867 00868 return HAL_OK; 00869 } 00870 00871 /** 00872 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down 00873 * @param USBx: Selected device 00874 * @retval HAL status 00875 */ 00876 HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx) 00877 { 00878 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ; 00879 HAL_Delay(3); 00880 00881 return HAL_OK; 00882 } 00883 00884 /** 00885 * @brief USB_ReadInterrupts: return the global USB interrupt status 00886 * @param USBx: Selected device 00887 * @retval HAL status 00888 */ 00889 uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx) 00890 { 00891 uint32_t tmpreg = 0; 00892 00893 tmpreg = USBx->GINTSTS; 00894 tmpreg &= USBx->GINTMSK; 00895 return tmpreg; 00896 } 00897 00898 /** 00899 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status 00900 * @param USBx: Selected device 00901 * @retval HAL status 00902 */ 00903 uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx) 00904 { 00905 uint32_t tmpreg; 00906 tmpreg = USBx_DEVICE->DAINT; 00907 tmpreg &= USBx_DEVICE->DAINTMSK; 00908 return ((tmpreg & 0xffff0000) >> 16); 00909 } 00910 00911 /** 00912 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status 00913 * @param USBx: Selected device 00914 * @retval HAL status 00915 */ 00916 uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx) 00917 { 00918 uint32_t tmpreg; 00919 tmpreg = USBx_DEVICE->DAINT; 00920 tmpreg &= USBx_DEVICE->DAINTMSK; 00921 return ((tmpreg & 0xFFFF)); 00922 } 00923 00924 /** 00925 * @brief Returns Device OUT EP Interrupt register 00926 * @param USBx: Selected device 00927 * @param epnum: endpoint number 00928 * This parameter can be a value from 0 to 15 00929 * @retval Device OUT EP Interrupt register 00930 */ 00931 uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) 00932 { 00933 uint32_t tmpreg; 00934 tmpreg = USBx_OUTEP(epnum)->DOEPINT; 00935 tmpreg &= USBx_DEVICE->DOEPMSK; 00936 return tmpreg; 00937 } 00938 00939 /** 00940 * @brief Returns Device IN EP Interrupt register 00941 * @param USBx: Selected device 00942 * @param epnum: endpoint number 00943 * This parameter can be a value from 0 to 15 00944 * @retval Device IN EP Interrupt register 00945 */ 00946 uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum) 00947 { 00948 uint32_t tmpreg = 0, msk = 0, emp = 0; 00949 00950 msk = USBx_DEVICE->DIEPMSK; 00951 emp = USBx_DEVICE->DIEPEMPMSK; 00952 msk |= ((emp >> epnum) & 0x1) << 7; 00953 tmpreg = USBx_INEP(epnum)->DIEPINT & msk; 00954 return tmpreg; 00955 } 00956 00957 /** 00958 * @brief USB_ClearInterrupts: clear a USB interrupt 00959 * @param USBx: Selected device 00960 * @param interrupt: interrupt flag 00961 * @retval None 00962 */ 00963 void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) 00964 { 00965 USBx->GINTSTS |= interrupt; 00966 } 00967 00968 /** 00969 * @brief Returns USB core mode 00970 * @param USBx: Selected device 00971 * @retval return core mode : Host or Device 00972 * This parameter can be one of these values: 00973 * 0 : Host 00974 * 1 : Device 00975 */ 00976 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx) 00977 { 00978 return ((USBx->GINTSTS ) & 0x1); 00979 } 00980 00981 00982 /** 00983 * @brief Activate EP0 for Setup transactions 00984 * @param USBx: Selected device 00985 * @retval HAL status 00986 */ 00987 HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx) 00988 { 00989 /* Set the MPS of the IN EP based on the enumeration speed */ 00990 USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; 00991 00992 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ) 00993 { 00994 USBx_INEP(0)->DIEPCTL |= 3; 00995 } 00996 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; 00997 00998 return HAL_OK; 00999 } 01000 01001 01002 /** 01003 * @brief Prepare the EP0 to start the first control setup 01004 * @param USBx: Selected device 01005 * @param dma: USB dma enabled or disabled 01006 * This parameter can be one of these values: 01007 * 0 : DMA feature not used 01008 * 1 : DMA feature used 01009 * @param psetup: pointer to setup packet 01010 * @retval HAL status 01011 */ 01012 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup) 01013 { 01014 /* Prevent unused argument(s) compilation warning */ 01015 UNUSED(psetup); 01016 01017 USBx_OUTEP(0)->DOEPTSIZ = 0; 01018 USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ; 01019 USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8); 01020 USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; 01021 01022 return HAL_OK; 01023 } 01024 01025 /** 01026 * @brief USB_HostInit : Initializes the USB OTG controller registers 01027 * for Host mode 01028 * @param USBx: Selected device 01029 * @param cfg: pointer to a USB_OTG_CfgTypeDef structure that contains 01030 * the configuration information for the specified USBx peripheral. 01031 * @retval HAL status 01032 */ 01033 HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) 01034 { 01035 uint32_t index = 0; 01036 01037 /* Restart the Phy Clock */ 01038 USBx_PCGCCTL = 0; 01039 01040 /* Disable the FS/LS support mode only */ 01041 if((cfg.speed == USB_OTG_SPEED_FULL)&& 01042 (USBx != USB_OTG_FS)) 01043 { 01044 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; 01045 } 01046 else 01047 { 01048 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); 01049 } 01050 01051 /* Make sure the FIFOs are flushed. */ 01052 USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */ 01053 USB_FlushRxFifo(USBx); 01054 01055 /* Clear all pending HC Interrupts */ 01056 for (index = 0; index < cfg.Host_channels ; index++) 01057 { 01058 USBx_HC(index)->HCINT = 0xFFFFFFFF; 01059 USBx_HC(index)->HCINTMSK = 0; 01060 } 01061 01062 /* Enable VBUS driving */ 01063 USB_DriveVbus(USBx, 1); 01064 01065 HAL_Delay(200); 01066 01067 /* Disable all interrupts. */ 01068 USBx->GINTMSK = 0; 01069 01070 /* Clear any pending interrupts */ 01071 USBx->GINTSTS = 0xFFFFFFFF; 01072 01073 /* set Rx FIFO size */ 01074 USBx->GRXFSIZ = (uint32_t )0x80; 01075 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80); 01076 USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0); 01077 01078 /* Enable the common interrupts */ 01079 if (cfg.dma_enable == DISABLE) 01080 { 01081 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; 01082 } 01083 01084 /* Enable interrupts matching to the Host mode ONLY */ 01085 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\ 01086 USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\ 01087 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); 01088 01089 return HAL_OK; 01090 } 01091 01092 /** 01093 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the 01094 * HCFG register on the PHY type and set the right frame interval 01095 * @param USBx: Selected device 01096 * @param freq: clock frequency 01097 * This parameter can be one of these values: 01098 * HCFG_48_MHZ : Full Speed 48 MHz Clock 01099 * HCFG_6_MHZ : Low Speed 6 MHz Clock 01100 * @retval HAL status 01101 */ 01102 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq) 01103 { 01104 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); 01105 USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS); 01106 01107 if (freq == HCFG_48_MHZ) 01108 { 01109 USBx_HOST->HFIR = (uint32_t)48000; 01110 } 01111 else if (freq == HCFG_6_MHZ) 01112 { 01113 USBx_HOST->HFIR = (uint32_t)6000; 01114 } 01115 return HAL_OK; 01116 } 01117 01118 /** 01119 * @brief USB_OTG_ResetPort : Reset Host Port 01120 * @param USBx: Selected device 01121 * @retval HAL status 01122 * @note (1)The application must wait at least 10 ms 01123 * before clearing the reset bit. 01124 */ 01125 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) 01126 { 01127 __IO uint32_t hprt0 = 0; 01128 01129 hprt0 = USBx_HPRT0; 01130 01131 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ 01132 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); 01133 01134 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); 01135 HAL_Delay (10); /* See Note #1 */ 01136 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); 01137 return HAL_OK; 01138 } 01139 01140 /** 01141 * @brief USB_DriveVbus : activate or de-activate vbus 01142 * @param state: VBUS state 01143 * This parameter can be one of these values: 01144 * 0 : VBUS Active 01145 * 1 : VBUS Inactive 01146 * @retval HAL status 01147 */ 01148 HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state) 01149 { 01150 __IO uint32_t hprt0 = 0; 01151 01152 hprt0 = USBx_HPRT0; 01153 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\ 01154 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG ); 01155 01156 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 )) 01157 { 01158 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); 01159 } 01160 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 )) 01161 { 01162 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); 01163 } 01164 return HAL_OK; 01165 } 01166 01167 /** 01168 * @brief Return Host Core speed 01169 * @param USBx: Selected device 01170 * @retval speed : Host speed 01171 * This parameter can be one of these values: 01172 * @arg USB_OTG_SPEED_HIGH: High speed mode 01173 * @arg USB_OTG_SPEED_FULL: Full speed mode 01174 * @arg USB_OTG_SPEED_LOW: Low speed mode 01175 */ 01176 uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx) 01177 { 01178 __IO uint32_t hprt0 = 0; 01179 01180 hprt0 = USBx_HPRT0; 01181 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); 01182 } 01183 01184 /** 01185 * @brief Return Host Current Frame number 01186 * @param USBx: Selected device 01187 * @retval current frame number 01188 */ 01189 uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx) 01190 { 01191 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); 01192 } 01193 01194 /** 01195 * @brief Initialize a host channel 01196 * @param USBx: Selected device 01197 * @param ch_num : Channel number 01198 * This parameter can be a value from 1 to 15 01199 * @param epnum: Endpoint number 01200 * This parameter can be a value from 1 to 15 01201 * @param dev_address: Current device address 01202 * This parameter can be a value from 0 to 255 01203 * @param speed: Current device speed 01204 * This parameter can be one of these values: 01205 * @arg USB_OTG_SPEED_HIGH: High speed mode 01206 * @arg USB_OTG_SPEED_FULL: Full speed mode 01207 * @arg USB_OTG_SPEED_LOW: Low speed mode 01208 * @param ep_type: Endpoint Type 01209 * This parameter can be one of these values: 01210 * @arg EP_TYPE_CTRL: Control type 01211 * @arg EP_TYPE_ISOC: Isochronous type 01212 * @arg EP_TYPE_BULK: Bulk type 01213 * @arg EP_TYPE_INTR: Interrupt type 01214 * @param mps: Max Packet Size 01215 * This parameter can be a value from 0 to32K 01216 * @retval HAL state 01217 */ 01218 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, 01219 uint8_t ch_num, 01220 uint8_t epnum, 01221 uint8_t dev_address, 01222 uint8_t speed, 01223 uint8_t ep_type, 01224 uint16_t mps) 01225 { 01226 01227 /* Clear old interrupt conditions for this host channel. */ 01228 USBx_HC(ch_num)->HCINT = 0xFFFFFFFF; 01229 01230 /* Enable channel interrupts required for this transfer. */ 01231 switch (ep_type) 01232 { 01233 case EP_TYPE_CTRL: 01234 case EP_TYPE_BULK: 01235 01236 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ 01237 USB_OTG_HCINTMSK_STALLM |\ 01238 USB_OTG_HCINTMSK_TXERRM |\ 01239 USB_OTG_HCINTMSK_DTERRM |\ 01240 USB_OTG_HCINTMSK_AHBERR |\ 01241 USB_OTG_HCINTMSK_NAKM ; 01242 01243 if (epnum & 0x80) 01244 { 01245 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; 01246 } 01247 break; 01248 01249 case EP_TYPE_INTR: 01250 01251 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ 01252 USB_OTG_HCINTMSK_STALLM |\ 01253 USB_OTG_HCINTMSK_TXERRM |\ 01254 USB_OTG_HCINTMSK_DTERRM |\ 01255 USB_OTG_HCINTMSK_NAKM |\ 01256 USB_OTG_HCINTMSK_AHBERR |\ 01257 USB_OTG_HCINTMSK_FRMORM ; 01258 01259 if (epnum & 0x80) 01260 { 01261 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; 01262 } 01263 01264 break; 01265 case EP_TYPE_ISOC: 01266 01267 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\ 01268 USB_OTG_HCINTMSK_ACKM |\ 01269 USB_OTG_HCINTMSK_AHBERR |\ 01270 USB_OTG_HCINTMSK_FRMORM ; 01271 01272 if (epnum & 0x80) 01273 { 01274 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); 01275 } 01276 break; 01277 } 01278 01279 /* Enable the top level host channel interrupt. */ 01280 USBx_HOST->HAINTMSK |= (1 << ch_num); 01281 01282 /* Make sure host channel interrupts are enabled. */ 01283 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; 01284 01285 /* Program the HCCHAR register */ 01286 USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\ 01287 (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\ 01288 ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\ 01289 (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\ 01290 ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\ 01291 (mps & USB_OTG_HCCHAR_MPSIZ)); 01292 01293 if (ep_type == EP_TYPE_INTR) 01294 { 01295 USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; 01296 } 01297 01298 return HAL_OK; 01299 } 01300 01301 /** 01302 * @brief Start a transfer over a host channel 01303 * @param USBx: Selected device 01304 * @param hc: pointer to host channel structure 01305 * @param dma: USB dma enabled or disabled 01306 * This parameter can be one of these values: 01307 * 0 : DMA feature not used 01308 * 1 : DMA feature used 01309 * @retval HAL state 01310 */ 01311 #if defined (__CC_ARM) /*!< ARM Compiler */ 01312 #pragma O0 01313 #elif defined (__GNUC__) /*!< GNU Compiler */ 01314 #pragma GCC optimize ("O0") 01315 #endif /* __CC_ARM */ 01316 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) 01317 { 01318 uint8_t is_oddframe = 0; 01319 uint16_t len_words = 0; 01320 uint16_t num_packets = 0; 01321 uint16_t max_hc_pkt_count = 256; 01322 uint32_t tmpreg = 0; 01323 01324 /* Compute the expected number of packets associated to the transfer */ 01325 if (hc->xfer_len > 0) 01326 { 01327 num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet; 01328 01329 if (num_packets > max_hc_pkt_count) 01330 { 01331 num_packets = max_hc_pkt_count; 01332 hc->xfer_len = num_packets * hc->max_packet; 01333 } 01334 } 01335 else 01336 { 01337 num_packets = 1; 01338 } 01339 if (hc->ep_is_in) 01340 { 01341 hc->xfer_len = num_packets * hc->max_packet; 01342 } 01343 01344 /* Initialize the HCTSIZn register */ 01345 USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\ 01346 ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ 01347 (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID); 01348 01349 if (dma) 01350 { 01351 /* xfer_buff MUST be 32-bits aligned */ 01352 USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff; 01353 } 01354 01355 is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1; 01356 USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; 01357 USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29); 01358 01359 /* Set host channel enable */ 01360 tmpreg = USBx_HC(hc->ch_num)->HCCHAR; 01361 tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 01362 tmpreg |= USB_OTG_HCCHAR_CHENA; 01363 USBx_HC(hc->ch_num)->HCCHAR = tmpreg; 01364 01365 if (dma == 0) /* Slave mode */ 01366 { 01367 if((hc->ep_is_in == 0) && (hc->xfer_len > 0)) 01368 { 01369 switch(hc->ep_type) 01370 { 01371 /* Non periodic transfer */ 01372 case EP_TYPE_CTRL: 01373 case EP_TYPE_BULK: 01374 01375 len_words = (hc->xfer_len + 3) / 4; 01376 01377 /* check if there is enough space in FIFO space */ 01378 if(len_words > (USBx->HNPTXSTS & 0xFFFF)) 01379 { 01380 /* need to process data in nptxfempty interrupt */ 01381 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; 01382 } 01383 break; 01384 /* Periodic transfer */ 01385 case EP_TYPE_INTR: 01386 case EP_TYPE_ISOC: 01387 len_words = (hc->xfer_len + 3) / 4; 01388 /* check if there is enough space in FIFO space */ 01389 if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */ 01390 { 01391 /* need to process data in ptxfempty interrupt */ 01392 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; 01393 } 01394 break; 01395 01396 default: 01397 break; 01398 } 01399 01400 /* Write packet into the Tx FIFO. */ 01401 USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0); 01402 hc->xfer_count = hc->xfer_len; 01403 01404 } 01405 } 01406 01407 return HAL_OK; 01408 } 01409 01410 /** 01411 * @brief Read all host channel interrupts status 01412 * @param USBx: Selected device 01413 * @retval HAL state 01414 */ 01415 uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx) 01416 { 01417 return ((USBx_HOST->HAINT) & 0xFFFF); 01418 } 01419 01420 /** 01421 * @brief Halt a host channel 01422 * @param USBx: Selected device 01423 * @param hc_num: Host Channel number 01424 * This parameter can be a value from 1 to 15 01425 * @retval HAL state 01426 */ 01427 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num) 01428 { 01429 uint32_t count = 0; 01430 01431 /* Check for space in the request queue to issue the halt. */ 01432 if (((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_CTRL << 18)) || ((USBx_HC(hc_num)->HCCHAR) & (HCCHAR_BULK << 18))) 01433 { 01434 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; 01435 01436 if ((USBx->HNPTXSTS & 0xFFFF) == 0) 01437 { 01438 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; 01439 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 01440 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; 01441 do 01442 { 01443 if (++count > 1000) 01444 { 01445 break; 01446 } 01447 } 01448 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 01449 } 01450 else 01451 { 01452 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 01453 } 01454 } 01455 else 01456 { 01457 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; 01458 01459 if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0) 01460 { 01461 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; 01462 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 01463 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; 01464 do 01465 { 01466 if (++count > 1000) 01467 { 01468 break; 01469 } 01470 } 01471 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 01472 } 01473 else 01474 { 01475 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA; 01476 } 01477 } 01478 01479 return HAL_OK; 01480 } 01481 01482 /** 01483 * @brief Initiate Do Ping protocol 01484 * @param USBx: Selected device 01485 * @param hc_num: Host Channel number 01486 * This parameter can be a value from 1 to 15 01487 * @retval HAL state 01488 */ 01489 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num) 01490 { 01491 uint8_t num_packets = 1; 01492 uint32_t tmpreg = 0; 01493 01494 USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\ 01495 USB_OTG_HCTSIZ_DOPING; 01496 01497 /* Set host channel enable */ 01498 tmpreg = USBx_HC(ch_num)->HCCHAR; 01499 tmpreg &= ~USB_OTG_HCCHAR_CHDIS; 01500 tmpreg |= USB_OTG_HCCHAR_CHENA; 01501 USBx_HC(ch_num)->HCCHAR = tmpreg; 01502 01503 return HAL_OK; 01504 } 01505 01506 /** 01507 * @brief Stop Host Core 01508 * @param USBx: Selected device 01509 * @retval HAL state 01510 */ 01511 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) 01512 { 01513 uint8_t index; 01514 uint32_t count = 0; 01515 uint32_t value = 0; 01516 01517 USB_DisableGlobalInt(USBx); 01518 01519 /* Flush FIFO */ 01520 USB_FlushTxFifo(USBx, 0x10); 01521 USB_FlushRxFifo(USBx); 01522 01523 /* Flush out any leftover queued requests. */ 01524 for (index = 0; index <= 15; index++) 01525 { 01526 value = USBx_HC(index)->HCCHAR; 01527 value |= USB_OTG_HCCHAR_CHDIS; 01528 value &= ~USB_OTG_HCCHAR_CHENA; 01529 value &= ~USB_OTG_HCCHAR_EPDIR; 01530 USBx_HC(index)->HCCHAR = value; 01531 } 01532 01533 /* Halt all channels to put them into a known state. */ 01534 for (index = 0; index <= 15; index++) 01535 { 01536 value = USBx_HC(index)->HCCHAR ; 01537 value |= USB_OTG_HCCHAR_CHDIS; 01538 value |= USB_OTG_HCCHAR_CHENA; 01539 value &= ~USB_OTG_HCCHAR_EPDIR; 01540 USBx_HC(index)->HCCHAR = value; 01541 01542 USBx_HC(index)->HCCHAR = value; 01543 do 01544 { 01545 if (++count > 1000) 01546 { 01547 break; 01548 } 01549 } 01550 while ((USBx_HC(index)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); 01551 } 01552 01553 /* Clear any pending Host interrupts */ 01554 USBx_HOST->HAINT = 0xFFFFFFFF; 01555 USBx->GINTSTS = 0xFFFFFFFF; 01556 USB_EnableGlobalInt(USBx); 01557 return HAL_OK; 01558 } 01559 01560 /** 01561 * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling 01562 * @param USBx : Selected device 01563 * @retval HAL status 01564 */ 01565 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) 01566 { 01567 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) 01568 { 01569 /* active Remote wakeup signalling */ 01570 USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; 01571 } 01572 return HAL_OK; 01573 } 01574 01575 /** 01576 * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling 01577 * @param USBx : Selected device 01578 * @retval HAL status 01579 */ 01580 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) 01581 { 01582 /* active Remote wakeup signalling */ 01583 USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); 01584 return HAL_OK; 01585 } 01586 01587 #endif /* USB_OTG_FS */ 01588 01589 /*============================================================================== 01590 USB Device FS peripheral available on STM32L432xx, STM32L433xx, STM32L442xx) 01591 and STM32L443xx devices 01592 ==============================================================================*/ 01593 #if defined (USB) 01594 /** 01595 * @brief Initializes the USB Core 01596 * @param USBx: USB Instance 01597 * @param cfg : pointer to a USB_CfgTypeDef structure that contains 01598 * the configuration information for the specified USBx peripheral. 01599 * @retval HAL status 01600 */ 01601 HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) 01602 { 01603 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 01604 only by USB OTG FS peripheral. 01605 - This function is added to ensure compatibility across platforms. 01606 */ 01607 01608 /* Prevent unused argument(s) compilation warning */ 01609 UNUSED(USBx); 01610 UNUSED(cfg); 01611 01612 return HAL_OK; 01613 } 01614 01615 /** 01616 * @brief USB_EnableGlobalInt 01617 * Enables the controller's Global Int in the AHB Config reg 01618 * @param USBx : Selected device 01619 * @retval HAL status 01620 */ 01621 HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) 01622 { 01623 uint32_t winterruptmask = 0; 01624 01625 /* Set winterruptmask variable */ 01626 winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ 01627 | USB_CNTR_ESOFM | USB_CNTR_RESETM; 01628 01629 /* Set interrupt mask */ 01630 USBx->CNTR |= winterruptmask; 01631 01632 return HAL_OK; 01633 } 01634 01635 /** 01636 * @brief USB_DisableGlobalInt 01637 * Disable the controller's Global Int in the AHB Config reg 01638 * @param USBx : Selected device 01639 * @retval HAL status 01640 */ 01641 HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) 01642 { 01643 uint32_t winterruptmask = 0; 01644 01645 /* Set winterruptmask variable */ 01646 winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \ 01647 | USB_CNTR_ESOFM | USB_CNTR_RESETM; 01648 01649 /* Clear interrupt mask */ 01650 USBx->CNTR &= ~winterruptmask; 01651 01652 return HAL_OK; 01653 } 01654 01655 /** 01656 * @brief USB_SetCurrentMode : Set functional mode 01657 * @param USBx : Selected device 01658 * @param mode : current core mode 01659 * This parameter can be one of the these values: 01660 * @arg USB_DEVICE_MODE: Peripheral mode mode 01661 * @retval HAL status 01662 */ 01663 HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx , USB_ModeTypeDef mode) 01664 { 01665 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 01666 only by USB OTG FS peripheral. 01667 - This function is added to ensure compatibility across platforms. 01668 */ 01669 01670 /* Prevent unused argument(s) compilation warning */ 01671 UNUSED(USBx); 01672 UNUSED(mode); 01673 01674 return HAL_OK; 01675 } 01676 01677 /** 01678 * @brief USB_DevInit : Initializes the USB controller registers 01679 * for device mode 01680 * @param USBx : Selected device 01681 * @param cfg : pointer to a USB_CfgTypeDef structure that contains 01682 * the configuration information for the specified USBx peripheral. 01683 * @retval HAL status 01684 */ 01685 HAL_StatusTypeDef USB_DevInit (USB_TypeDef *USBx, USB_CfgTypeDef cfg) 01686 { 01687 /* Prevent unused argument(s) compilation warning */ 01688 UNUSED(cfg); 01689 01690 /* Init Device */ 01691 /*CNTR_FRES = 1*/ 01692 USBx->CNTR = USB_CNTR_FRES; 01693 01694 /*CNTR_FRES = 0*/ 01695 USBx->CNTR = 0; 01696 01697 /*Clear pending interrupts*/ 01698 USBx->ISTR = 0; 01699 01700 /*Set Btable Address*/ 01701 USBx->BTABLE = BTABLE_ADDRESS; 01702 01703 return HAL_OK; 01704 } 01705 01706 /** 01707 * @brief USB_FlushTxFifo : Flush a Tx FIFO 01708 * @param USBx : Selected device 01709 * @param num : FIFO number 01710 * This parameter can be a value from 1 to 15 01711 15 means Flush all Tx FIFOs 01712 * @retval HAL status 01713 */ 01714 HAL_StatusTypeDef USB_FlushTxFifo (USB_TypeDef *USBx, uint32_t num ) 01715 { 01716 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 01717 only by USB OTG FS peripheral. 01718 - This function is added to ensure compatibility across platforms. 01719 */ 01720 01721 /* Prevent unused argument(s) compilation warning */ 01722 UNUSED(USBx); 01723 UNUSED(num); 01724 01725 return HAL_OK; 01726 } 01727 01728 /** 01729 * @brief USB_FlushRxFifo : Flush Rx FIFO 01730 * @param USBx : Selected device 01731 * @retval HAL status 01732 */ 01733 HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) 01734 { 01735 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 01736 only by USB OTG FS peripheral. 01737 - This function is added to ensure compatibility across platforms. 01738 */ 01739 01740 /* Prevent unused argument(s) compilation warning */ 01741 UNUSED(USBx); 01742 01743 return HAL_OK; 01744 } 01745 01746 /** 01747 * @brief Activate and configure an endpoint 01748 * @param USBx : Selected device 01749 * @param ep: pointer to endpoint structure 01750 * @retval HAL status 01751 */ 01752 HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) 01753 { 01754 /* initialize Endpoint */ 01755 switch (ep->type) 01756 { 01757 case EP_TYPE_CTRL: 01758 PCD_SET_EPTYPE(USBx, ep->num, USB_EP_CONTROL); 01759 break; 01760 case EP_TYPE_BULK: 01761 PCD_SET_EPTYPE(USBx, ep->num, USB_EP_BULK); 01762 break; 01763 case EP_TYPE_INTR: 01764 PCD_SET_EPTYPE(USBx, ep->num, USB_EP_INTERRUPT); 01765 break; 01766 case EP_TYPE_ISOC: 01767 PCD_SET_EPTYPE(USBx, ep->num, USB_EP_ISOCHRONOUS); 01768 break; 01769 default: 01770 break; 01771 } 01772 01773 PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); 01774 01775 if (ep->doublebuffer == 0) 01776 { 01777 if (ep->is_in) 01778 { 01779 /*Set the endpoint Transmit buffer address */ 01780 PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); 01781 PCD_CLEAR_TX_DTOG(USBx, ep->num); 01782 /* Configure NAK status for the Endpoint*/ 01783 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); 01784 } 01785 else 01786 { 01787 /*Set the endpoint Receive buffer address */ 01788 PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); 01789 /*Set the endpoint Receive buffer counter*/ 01790 PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); 01791 PCD_CLEAR_RX_DTOG(USBx, ep->num); 01792 /* Configure VALID status for the Endpoint*/ 01793 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 01794 } 01795 } 01796 /*Double Buffer*/ 01797 else 01798 { 01799 /*Set the endpoint as double buffered*/ 01800 PCD_SET_EP_DBUF(USBx, ep->num); 01801 /*Set buffer address for double buffered mode*/ 01802 PCD_SET_EP_DBUF_ADDR(USBx, ep->num,ep->pmaaddr0, ep->pmaaddr1); 01803 01804 if (ep->is_in==0) 01805 { 01806 /* Clear the data toggle bits for the endpoint IN/OUT*/ 01807 PCD_CLEAR_RX_DTOG(USBx, ep->num); 01808 PCD_CLEAR_TX_DTOG(USBx, ep->num); 01809 01810 /* Reset value of the data toggle bits for the endpoint out*/ 01811 PCD_TX_DTOG(USBx, ep->num); 01812 01813 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 01814 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 01815 } 01816 else 01817 { 01818 /* Clear the data toggle bits for the endpoint IN/OUT*/ 01819 PCD_CLEAR_RX_DTOG(USBx, ep->num); 01820 PCD_CLEAR_TX_DTOG(USBx, ep->num); 01821 PCD_RX_DTOG(USBx, ep->num); 01822 /* Configure DISABLE status for the Endpoint*/ 01823 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 01824 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 01825 } 01826 } 01827 01828 return HAL_OK; 01829 } 01830 01831 /** 01832 * @brief De-activate and de-initialize an endpoint 01833 * @param USBx : Selected device 01834 * @param ep: pointer to endpoint structure 01835 * @retval HAL status 01836 */ 01837 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) 01838 { 01839 if (ep->doublebuffer == 0) 01840 { 01841 if (ep->is_in) 01842 { 01843 PCD_CLEAR_TX_DTOG(USBx, ep->num); 01844 /* Configure DISABLE status for the Endpoint*/ 01845 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 01846 } 01847 else 01848 { 01849 PCD_CLEAR_RX_DTOG(USBx, ep->num); 01850 /* Configure DISABLE status for the Endpoint*/ 01851 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 01852 } 01853 } 01854 /*Double Buffer*/ 01855 else 01856 { 01857 if (ep->is_in==0) 01858 { 01859 /* Clear the data toggle bits for the endpoint IN/OUT*/ 01860 PCD_CLEAR_RX_DTOG(USBx, ep->num); 01861 PCD_CLEAR_TX_DTOG(USBx, ep->num); 01862 01863 /* Reset value of the data toggle bits for the endpoint out*/ 01864 PCD_TX_DTOG(USBx, ep->num); 01865 01866 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 01867 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 01868 } 01869 else 01870 { 01871 /* Clear the data toggle bits for the endpoint IN/OUT*/ 01872 PCD_CLEAR_RX_DTOG(USBx, ep->num); 01873 PCD_CLEAR_TX_DTOG(USBx, ep->num); 01874 PCD_RX_DTOG(USBx, ep->num); 01875 /* Configure DISABLE status for the Endpoint*/ 01876 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); 01877 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); 01878 } 01879 } 01880 01881 return HAL_OK; 01882 } 01883 01884 /** 01885 * @brief USB_EPStartXfer : setup and starts a transfer over an EP 01886 * @param USBx : Selected device 01887 * @param ep: pointer to endpoint structure 01888 * @retval HAL status 01889 */ 01890 HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx , USB_EPTypeDef *ep, uint8_t dma) 01891 { 01892 uint16_t pmabuffer = 0; 01893 uint32_t len = ep->xfer_len; 01894 01895 /* IN endpoint */ 01896 if (ep->is_in == 1) 01897 { 01898 /*Multi packet transfer*/ 01899 if (ep->xfer_len > ep->maxpacket) 01900 { 01901 len=ep->maxpacket; 01902 ep->xfer_len-=len; 01903 } 01904 else 01905 { 01906 len=ep->xfer_len; 01907 ep->xfer_len =0; 01908 } 01909 01910 /* configure and validate Tx endpoint */ 01911 if (ep->doublebuffer == 0) 01912 { 01913 USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, len); 01914 PCD_SET_EP_TX_CNT(USBx, ep->num, len); 01915 } 01916 else 01917 { 01918 /* Write the data to the USB endpoint */ 01919 if (PCD_GET_ENDPOINT(USBx, ep->num)& USB_EP_DTOG_TX) 01920 { 01921 /* Set the Double buffer counter for pmabuffer1 */ 01922 PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 01923 pmabuffer = ep->pmaaddr1; 01924 } 01925 else 01926 { 01927 /* Set the Double buffer counter for pmabuffer0 */ 01928 PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); 01929 pmabuffer = ep->pmaaddr0; 01930 } 01931 USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, len); 01932 PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); 01933 } 01934 01935 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); 01936 } 01937 else /* OUT endpoint */ 01938 { 01939 /* Multi packet transfer*/ 01940 if (ep->xfer_len > ep->maxpacket) 01941 { 01942 len=ep->maxpacket; 01943 ep->xfer_len-=len; 01944 } 01945 else 01946 { 01947 len=ep->xfer_len; 01948 ep->xfer_len =0; 01949 } 01950 01951 /* configure and validate Rx endpoint */ 01952 if (ep->doublebuffer == 0) 01953 { 01954 /*Set RX buffer count*/ 01955 PCD_SET_EP_RX_CNT(USBx, ep->num, len); 01956 } 01957 else 01958 { 01959 /*Set the Double buffer counter*/ 01960 PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); 01961 } 01962 01963 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 01964 } 01965 01966 return HAL_OK; 01967 } 01968 01969 /** 01970 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated 01971 * with the EP/channel 01972 * @param USBx : Selected device 01973 * @param src : pointer to source buffer 01974 * @param ch_ep_num : endpoint or host channel number 01975 * @param len : Number of bytes to write 01976 * @retval HAL status 01977 */ 01978 HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) 01979 { 01980 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 01981 only by USB OTG FS peripheral. 01982 - This function is added to ensure compatibility across platforms. 01983 */ 01984 01985 /* Prevent unused argument(s) compilation warning */ 01986 UNUSED(USBx); 01987 UNUSED(src); 01988 UNUSED(ch_ep_num); 01989 UNUSED(len); 01990 01991 return HAL_OK; 01992 } 01993 01994 /** 01995 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated 01996 * with the EP/channel 01997 * @param USBx : Selected device 01998 * @param dest : destination pointer 01999 * @param len : Number of bytes to read 02000 * @retval pointer to destination buffer 02001 */ 02002 void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) 02003 { 02004 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02005 only by USB OTG FS peripheral. 02006 - This function is added to ensure compatibility across platforms. 02007 */ 02008 02009 /* Prevent unused argument(s) compilation warning */ 02010 UNUSED(USBx); 02011 UNUSED(dest); 02012 UNUSED(len); 02013 02014 return ((void *)NULL); 02015 } 02016 02017 /** 02018 * @brief USB_EPSetStall : set a stall condition over an EP 02019 * @param USBx : Selected device 02020 * @param ep: pointer to endpoint structure 02021 * @retval HAL status 02022 */ 02023 HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx , USB_EPTypeDef *ep) 02024 { 02025 if (ep->num == 0) 02026 { 02027 /* This macro sets STALL status for RX & TX*/ 02028 PCD_SET_EP_TXRX_STATUS(USBx, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); 02029 } 02030 else 02031 { 02032 if (ep->is_in) 02033 { 02034 PCD_SET_EP_TX_STATUS(USBx, ep->num , USB_EP_TX_STALL); 02035 } 02036 else 02037 { 02038 PCD_SET_EP_RX_STATUS(USBx, ep->num , USB_EP_RX_STALL); 02039 } 02040 } 02041 return HAL_OK; 02042 } 02043 02044 /** 02045 * @brief USB_EPClearStall : Clear a stall condition over an EP 02046 * @param USBx : Selected device 02047 * @param ep: pointer to endpoint structure 02048 * @retval HAL status 02049 */ 02050 HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) 02051 { 02052 if (ep->is_in) 02053 { 02054 PCD_CLEAR_TX_DTOG(USBx, ep->num); 02055 PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); 02056 } 02057 else 02058 { 02059 PCD_CLEAR_RX_DTOG(USBx, ep->num); 02060 PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); 02061 } 02062 return HAL_OK; 02063 } 02064 02065 /** 02066 * @brief USB_StopDevice : Stop the usb device mode 02067 * @param USBx : Selected device 02068 * @retval HAL status 02069 */ 02070 HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) 02071 { 02072 /* disable all interrupts and force USB reset */ 02073 USBx->CNTR = USB_CNTR_FRES; 02074 02075 /* clear interrupt status register */ 02076 USBx->ISTR = 0; 02077 02078 /* switch-off device */ 02079 USBx->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN); 02080 02081 return HAL_OK; 02082 } 02083 02084 /** 02085 * @brief USB_SetDevAddress : Stop the usb device mode 02086 * @param USBx : Selected device 02087 * @param address : new device address to be assigned 02088 * This parameter can be a value from 0 to 255 02089 * @retval HAL status 02090 */ 02091 HAL_StatusTypeDef USB_SetDevAddress (USB_TypeDef *USBx, uint8_t address) 02092 { 02093 if(address == 0) 02094 { 02095 /* set device address and enable function */ 02096 USBx->DADDR = USB_DADDR_EF; 02097 } 02098 02099 return HAL_OK; 02100 } 02101 02102 /** 02103 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down 02104 * @param USBx : Selected device 02105 * @retval HAL status 02106 */ 02107 HAL_StatusTypeDef USB_DevConnect (USB_TypeDef *USBx) 02108 { 02109 /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */ 02110 USB->BCDR |= USB_BCDR_DPPU; 02111 02112 return HAL_OK; 02113 } 02114 02115 /** 02116 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down 02117 * @param USBx : Selected device 02118 * @retval HAL status 02119 */ 02120 HAL_StatusTypeDef USB_DevDisconnect (USB_TypeDef *USBx) 02121 { 02122 /* Disable DP Pull-Down bit*/ 02123 USB->BCDR &= ~(USB_BCDR_DPPU); 02124 02125 return HAL_OK; 02126 } 02127 02128 /** 02129 * @brief USB_ReadInterrupts: return the global USB interrupt status 02130 * @param USBx : Selected device 02131 * @retval HAL status 02132 */ 02133 uint32_t USB_ReadInterrupts (USB_TypeDef *USBx) 02134 { 02135 uint32_t tmpreg = 0; 02136 02137 tmpreg = USBx->ISTR; 02138 return tmpreg; 02139 } 02140 02141 /** 02142 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status 02143 * @param USBx : Selected device 02144 * @retval HAL status 02145 */ 02146 uint32_t USB_ReadDevAllOutEpInterrupt (USB_TypeDef *USBx) 02147 { 02148 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02149 only by USB OTG FS peripheral. 02150 - This function is added to ensure compatibility across platforms. 02151 */ 02152 02153 /* Prevent unused argument(s) compilation warning */ 02154 UNUSED(USBx); 02155 02156 return (0); 02157 } 02158 02159 /** 02160 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status 02161 * @param USBx : Selected device 02162 * @retval HAL status 02163 */ 02164 uint32_t USB_ReadDevAllInEpInterrupt (USB_TypeDef *USBx) 02165 { 02166 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02167 only by USB OTG FS peripheral. 02168 - This function is added to ensure compatibility across platforms. 02169 */ 02170 02171 /* Prevent unused argument(s) compilation warning */ 02172 UNUSED(USBx); 02173 02174 return (0); 02175 } 02176 02177 /** 02178 * @brief Returns Device OUT EP Interrupt register 02179 * @param USBx : Selected device 02180 * @param epnum : endpoint number 02181 * This parameter can be a value from 0 to 15 02182 * @retval Device OUT EP Interrupt register 02183 */ 02184 uint32_t USB_ReadDevOutEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) 02185 { 02186 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02187 only by USB OTG FS peripheral. 02188 - This function is added to ensure compatibility across platforms. 02189 */ 02190 02191 /* Prevent unused argument(s) compilation warning */ 02192 UNUSED(USBx); 02193 UNUSED(epnum); 02194 02195 return (0); 02196 } 02197 02198 /** 02199 * @brief Returns Device IN EP Interrupt register 02200 * @param USBx : Selected device 02201 * @param epnum : endpoint number 02202 * This parameter can be a value from 0 to 15 02203 * @retval Device IN EP Interrupt register 02204 */ 02205 uint32_t USB_ReadDevInEPInterrupt (USB_TypeDef *USBx , uint8_t epnum) 02206 { 02207 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02208 only by USB OTG FS peripheral. 02209 - This function is added to ensure compatibility across platforms. 02210 */ 02211 02212 /* Prevent unused argument(s) compilation warning */ 02213 UNUSED(USBx); 02214 UNUSED(epnum); 02215 02216 return (0); 02217 } 02218 02219 /** 02220 * @brief USB_ClearInterrupts: clear a USB interrupt 02221 * @param USBx : Selected device 02222 * @param interrupt : interrupt flag 02223 * @retval None 02224 */ 02225 void USB_ClearInterrupts (USB_TypeDef *USBx, uint32_t interrupt) 02226 { 02227 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02228 only by USB OTG FS peripheral. 02229 - This function is added to ensure compatibility across platforms. 02230 */ 02231 02232 /* Prevent unused argument(s) compilation warning */ 02233 UNUSED(USBx); 02234 UNUSED(interrupt); 02235 } 02236 02237 /** 02238 * @brief Prepare the EP0 to start the first control setup 02239 * @param USBx : Selected device 02240 * @param psetup : pointer to setup packet 02241 * @retval HAL status 02242 */ 02243 HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t dma ,uint8_t *psetup) 02244 { 02245 /* NOTE : - This function is not required by USB Device FS peripheral, it is used 02246 only by USB OTG FS peripheral. 02247 - This function is added to ensure compatibility across platforms. 02248 */ 02249 02250 /* Prevent unused argument(s) compilation warning */ 02251 UNUSED(USBx); 02252 UNUSED(psetup); 02253 02254 return HAL_OK; 02255 } 02256 02257 /** 02258 * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling 02259 * @param USBx : Selected device 02260 * @retval HAL status 02261 */ 02262 HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) 02263 { 02264 USBx->CNTR |= USB_CNTR_RESUME; 02265 02266 return HAL_OK; 02267 } 02268 02269 /** 02270 * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling 02271 * @param USBx : Selected device 02272 * @retval HAL status 02273 */ 02274 HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) 02275 { 02276 USBx->CNTR &= ~(USB_CNTR_RESUME); 02277 return HAL_OK; 02278 } 02279 02280 /** 02281 * @brief Copy a buffer from user memory area to packet memory area (PMA) 02282 * @param USBx : pointer to USB register. 02283 * @param pbUsrBuf : pointer to user memory area. 02284 * @param wPMABufAddr : address into PMA. 02285 * @param wNBytes : number of bytes to be copied. 02286 * @retval None 02287 */ 02288 void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) 02289 { 02290 uint32_t n = (wNBytes + 1) >> 1; 02291 uint32_t i; 02292 uint16_t temp1, temp2; 02293 uint16_t *pdwVal; 02294 pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); 02295 02296 for (i = n; i != 0; i--) 02297 { 02298 temp1 = (uint16_t) * pbUsrBuf; 02299 pbUsrBuf++; 02300 temp2 = temp1 | (uint16_t) * pbUsrBuf << 8; 02301 *pdwVal++ = temp2; 02302 pbUsrBuf++; 02303 } 02304 } 02305 02306 /** 02307 * @brief Copy a buffer from user memory area to packet memory area (PMA) 02308 * @param USBx : pointer to USB register. 02309 * @param pbUsrBuf : pointer to user memory area. 02310 * @param wPMABufAddr : address into PMA. 02311 * @param wNBytes : number of bytes to be copied. 02312 * @retval None 02313 */ 02314 void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) 02315 { 02316 uint32_t n = (wNBytes + 1) >> 1; 02317 uint32_t i; 02318 uint16_t *pdwVal; 02319 pdwVal = (uint16_t *)(wPMABufAddr + (uint32_t)USBx + 0x400); 02320 for (i = n; i != 0; i--) 02321 { 02322 *(uint16_t*)pbUsrBuf++ = *pdwVal++; 02323 pbUsrBuf++; 02324 } 02325 } 02326 #endif /* USB */ 02327 /** 02328 * @} 02329 */ 02330 /** 02331 * @} 02332 */ 02333 02334 #if defined (USB_OTG_FS) 02335 /** @addtogroup USB_LL_Private_Functions 02336 * @{ 02337 */ 02338 /** 02339 * @brief Reset the USB Core (needed after USB clock settings change) 02340 * @param USBx : Selected device 02341 * @retval HAL status 02342 */ 02343 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) 02344 { 02345 uint32_t count = 0; 02346 02347 /* Wait for AHB master IDLE state. */ 02348 do 02349 { 02350 if (++count > 200000) 02351 { 02352 return HAL_TIMEOUT; 02353 } 02354 } 02355 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0); 02356 02357 /* Core Soft Reset */ 02358 count = 0; 02359 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; 02360 02361 do 02362 { 02363 if (++count > 200000) 02364 { 02365 return HAL_TIMEOUT; 02366 } 02367 } 02368 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); 02369 02370 return HAL_OK; 02371 } 02372 /** 02373 * @} 02374 */ 02375 #endif /* USB_OTG_FS */ 02376 02377 #endif /* STM32L475xx || STM32L476xx || */ 02378 /* STM32L485xx || STM32L486xx || */ 02379 /* STM32L432xx || STM32L433xx || */ 02380 /* STM32L442xx || STM32L443xx */ 02381 02382 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ 02383 /** 02384 * @} 02385 */ 02386 02387 /** 02388 * @} 02389 */ 02390 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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