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stm32l4xx_ll_tim.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_tim.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief TIM LL module driver. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 #if defined(USE_FULL_LL_DRIVER) 00038 00039 /* Includes ------------------------------------------------------------------*/ 00040 #include "stm32l4xx_ll_tim.h" 00041 #include "stm32l4xx_ll_bus.h" 00042 00043 #ifdef USE_FULL_ASSERT 00044 #include "stm32_assert.h" 00045 #else 00046 #define assert_param(expr) ((void)0U) 00047 #endif 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) 00054 00055 /** @addtogroup TIM_LL 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /* Private constants ---------------------------------------------------------*/ 00062 /* Private macros ------------------------------------------------------------*/ 00063 /** @addtogroup TIM_LL_Private_Macros 00064 * @{ 00065 */ 00066 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ 00067 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ 00068 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ 00069 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ 00070 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) 00071 00072 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ 00073 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ 00074 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) 00075 00076 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ 00077 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ 00078 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ 00079 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ 00080 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ 00081 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ 00082 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ 00083 || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ 00084 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ 00085 || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ 00086 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ 00087 || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ 00088 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \ 00089 || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2)) 00090 00091 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ 00092 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) 00093 00094 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ 00095 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) 00096 00097 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ 00098 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) 00099 00100 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ 00101 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ 00102 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) 00103 00104 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ 00105 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ 00106 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ 00107 || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) 00108 00109 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ 00110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ 00111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ 00112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ 00113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ 00114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ 00115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ 00116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ 00117 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ 00118 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ 00119 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ 00120 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ 00121 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ 00122 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ 00123 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ 00124 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) 00125 00126 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ 00127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ 00128 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) 00129 00130 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ 00131 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ 00132 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) 00133 00134 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ 00135 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) 00136 /** 00137 * @} 00138 */ 00139 00140 00141 /* Private function prototypes -----------------------------------------------*/ 00142 /** @defgroup TIM_LL_Private_Functions TIM Private Functions 00143 * @{ 00144 */ 00145 static ErrorStatus OC1Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); 00146 static ErrorStatus OC2Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); 00147 static ErrorStatus OC3Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); 00148 static ErrorStatus OC4Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); 00149 static ErrorStatus OC5Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); 00150 static ErrorStatus OC6Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct); 00151 static ErrorStatus IC1Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); 00152 static ErrorStatus IC2Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); 00153 static ErrorStatus IC3Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); 00154 static ErrorStatus IC4Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct); 00155 /** 00156 * @} 00157 */ 00158 00159 /* Exported functions --------------------------------------------------------*/ 00160 /** @addtogroup TIM_LL_Exported_Functions 00161 * @{ 00162 */ 00163 00164 /** @addtogroup TIM_LL_EF_Init 00165 * @{ 00166 */ 00167 00168 /** 00169 * @brief Set TIMx registers to their reset values. 00170 * @param TIMx Timer instance 00171 * @retval An ErrorStatus enumeration value: 00172 * - SUCCESS: TIMx registers are de-initialized 00173 * - ERROR: invalid TIMx instance 00174 */ 00175 ErrorStatus LL_TIM_DeInit(TIM_TypeDef* TIMx) 00176 { 00177 ErrorStatus result = SUCCESS; 00178 00179 /* Check the parameters */ 00180 assert_param(IS_TIM_INSTANCE(TIMx)); 00181 00182 if (TIMx == TIM1) 00183 { 00184 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); 00185 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); 00186 } 00187 else if (TIMx == TIM2) 00188 { 00189 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); 00190 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); 00191 } 00192 #if defined(TIM3) 00193 else if (TIMx == TIM3) 00194 { 00195 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); 00196 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); 00197 } 00198 #endif 00199 #if defined(TIM4) 00200 else if (TIMx == TIM4) 00201 { 00202 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); 00203 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); 00204 } 00205 #endif 00206 #if defined(TIM5) 00207 else if (TIMx == TIM5) 00208 { 00209 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); 00210 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); 00211 } 00212 #endif 00213 else if (TIMx == TIM6) 00214 { 00215 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); 00216 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); 00217 } 00218 else if (TIMx == TIM7) 00219 { 00220 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); 00221 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); 00222 } 00223 #if defined(TIM8) 00224 else if (TIMx == TIM8) 00225 { 00226 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); 00227 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); 00228 } 00229 #endif 00230 else if (TIMx == TIM15) 00231 { 00232 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15); 00233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15); 00234 } 00235 else if (TIMx == TIM16) 00236 { 00237 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16); 00238 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16); 00239 } 00240 #if defined(TIM17) 00241 else if (TIMx == TIM17) 00242 { 00243 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17); 00244 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17); 00245 } 00246 #endif 00247 else 00248 { 00249 result = ERROR; 00250 } 00251 00252 return result; 00253 } 00254 00255 /** 00256 * @brief Set the fields of the time base unit configuration data structure 00257 * to their default values. 00258 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) 00259 * @retval None 00260 */ 00261 void LL_TIM_StructInit(LL_TIM_InitTypeDef* TIM_InitStruct) 00262 { 00263 /* Set the default configuration */ 00264 TIM_InitStruct->Prescaler = (uint16_t)0x0000U; 00265 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; 00266 TIM_InitStruct->Autoreload = (uint32_t)0xFFFFFFFFU; 00267 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 00268 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; 00269 } 00270 00271 /** 00272 * @brief Configure the TIMx time base unit. 00273 * @param TIMx Timer Instance 00274 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) 00275 * @retval An ErrorStatus enumeration value: 00276 * - SUCCESS: TIMx registers are de-initialized 00277 * - ERROR: not applicable 00278 */ 00279 ErrorStatus LL_TIM_Init(TIM_TypeDef * TIMx, LL_TIM_InitTypeDef* TIM_InitStruct) 00280 { 00281 uint16_t tmpcr1 = 0U; 00282 00283 /* Check the parameters */ 00284 assert_param(IS_TIM_INSTANCE(TIMx)); 00285 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode )); 00286 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision )); 00287 00288 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); 00289 00290 if(IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 00291 { 00292 /* Select the Counter Mode */ 00293 tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); 00294 tmpcr1 |= (uint32_t)TIM_InitStruct->CounterMode ; 00295 } 00296 00297 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 00298 { 00299 /* Set the clock division */ 00300 tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); 00301 tmpcr1 |= (uint32_t)TIM_InitStruct->ClockDivision ; 00302 } 00303 00304 /* Write to TIMx CR1 */ 00305 LL_TIM_WriteReg(TIMx, CR1, tmpcr1); 00306 00307 /* Set the Autoreload value */ 00308 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload ); 00309 00310 /* Set the Prescaler value */ 00311 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler ); 00312 00313 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 00314 { 00315 /* Set the Repetition Counter value */ 00316 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter ); 00317 } 00318 00319 /* Generate an update event to reload the Prescaler 00320 and the repetition counter value (if applicable) immediately */ 00321 LL_TIM_GenerateEvent_UPDATE(TIMx); 00322 00323 return SUCCESS; 00324 } 00325 00326 /** 00327 * @brief Set the fields of the TIMx output channel configuration data 00328 * structure to their default values. 00329 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) 00330 * @retval None 00331 */ 00332 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct) 00333 { 00334 /* Set the default configuration */ 00335 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; 00336 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; 00337 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; 00338 TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U; 00339 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; 00340 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; 00341 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; 00342 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; 00343 } 00344 00345 /** 00346 * @brief Configure the TIMx output channel. 00347 * @param TIMx Timer Instance 00348 * @param Channel This parameter can be one of the following values: 00349 * @arg @ref LL_TIM_CHANNEL_CH1 00350 * @arg @ref LL_TIM_CHANNEL_CH2 00351 * @arg @ref LL_TIM_CHANNEL_CH3 00352 * @arg @ref LL_TIM_CHANNEL_CH4 00353 * @arg @ref LL_TIM_CHANNEL_CH5 00354 * @arg @ref LL_TIM_CHANNEL_CH6 00355 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) 00356 * @retval An ErrorStatus enumeration value: 00357 * - SUCCESS: TIMx output channel is initialized 00358 * - ERROR: TIMx output channel is not initialized 00359 */ 00360 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef* TIM_OC_InitStruct) 00361 { 00362 ErrorStatus result = SUCCESS; 00363 00364 switch(Channel) 00365 { 00366 case LL_TIM_CHANNEL_CH1: 00367 result = OC1Config(TIMx, TIM_OC_InitStruct); 00368 break; 00369 case LL_TIM_CHANNEL_CH2: 00370 result = OC2Config(TIMx, TIM_OC_InitStruct); 00371 break; 00372 case LL_TIM_CHANNEL_CH3: 00373 result = OC3Config(TIMx, TIM_OC_InitStruct); 00374 break; 00375 case LL_TIM_CHANNEL_CH4: 00376 result = OC4Config(TIMx, TIM_OC_InitStruct); 00377 break; 00378 case LL_TIM_CHANNEL_CH5: 00379 result = OC5Config(TIMx, TIM_OC_InitStruct); 00380 break; 00381 case LL_TIM_CHANNEL_CH6: 00382 result = OC6Config(TIMx, TIM_OC_InitStruct); 00383 break; 00384 default: 00385 result = ERROR; 00386 break; 00387 } 00388 00389 return result; 00390 } 00391 00392 /** 00393 * @brief Set the fields of the TIMx input channel configuration data 00394 * structure to their default values. 00395 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) 00396 * @retval None 00397 */ 00398 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) 00399 { 00400 /* Set the default configuration */ 00401 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; 00402 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00403 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; 00404 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; 00405 } 00406 00407 /** 00408 * @brief Configure the TIMx input channel. 00409 * @param TIMx Timer Instance 00410 * @param Channel This parameter can be one of the following values: 00411 * @arg @ref LL_TIM_CHANNEL_CH1 00412 * @arg @ref LL_TIM_CHANNEL_CH2 00413 * @arg @ref LL_TIM_CHANNEL_CH3 00414 * @arg @ref LL_TIM_CHANNEL_CH4 00415 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) 00416 * @retval An ErrorStatus enumeration value: 00417 * - SUCCESS: TIMx output channel is initialized 00418 * - ERROR: TIMx output channel is not initialized 00419 */ 00420 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef* TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef* TIM_IC_InitStruct) 00421 { 00422 ErrorStatus result = SUCCESS; 00423 00424 switch(Channel) 00425 { 00426 case LL_TIM_CHANNEL_CH1: 00427 result = IC1Config(TIMx, TIM_IC_InitStruct); 00428 break; 00429 case LL_TIM_CHANNEL_CH2: 00430 result = IC2Config(TIMx, TIM_IC_InitStruct); 00431 break; 00432 case LL_TIM_CHANNEL_CH3: 00433 result = IC3Config(TIMx, TIM_IC_InitStruct); 00434 break; 00435 case LL_TIM_CHANNEL_CH4: 00436 result = IC4Config(TIMx, TIM_IC_InitStruct); 00437 break; 00438 default: 00439 result = ERROR; 00440 break; 00441 } 00442 00443 return result; 00444 } 00445 00446 /** 00447 * @brief Fills each TIM_EncoderInitStruct field with its default value 00448 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) 00449 * @retval None 00450 */ 00451 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct) 00452 { 00453 /* Set the default configuration */ 00454 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; 00455 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; 00456 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00457 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; 00458 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; 00459 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; 00460 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00461 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; 00462 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; 00463 } 00464 00465 /** 00466 * @brief Configure the encoder interface of the timer instance. 00467 * @param TIMx Timer Instance 00468 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) 00469 * @retval An ErrorStatus enumeration value: 00470 * - SUCCESS: TIMx registers are de-initialized 00471 * - ERROR: not applicable 00472 */ 00473 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef* TIMx, LL_TIM_ENCODER_InitTypeDef* TIM_EncoderInitStruct) 00474 { 00475 uint32_t tmpccmr1 = 0U; 00476 uint32_t tmpccer = 0U; 00477 00478 /* Check the parameters */ 00479 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); 00480 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode )); 00481 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity )); 00482 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput )); 00483 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler )); 00484 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter )); 00485 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity )); 00486 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput )); 00487 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler )); 00488 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter )); 00489 00490 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ 00491 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); 00492 00493 /* Get the TIMx CCMR1 register value */ 00494 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00495 00496 /* Get the TIMx CCER register value */ 00497 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00498 00499 /* Configure TI1 */ 00500 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); 00501 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); 00502 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); 00503 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); 00504 00505 /* Configure TI2 */ 00506 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); 00507 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); 00508 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); 00509 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); 00510 00511 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ 00512 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); 00513 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity ); 00514 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); 00515 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); 00516 00517 /* Set encoder mode */ 00518 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode ); 00519 00520 /* Write to TIMx CCMR1 */ 00521 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00522 00523 /* Write to TIMx CCER */ 00524 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00525 00526 return SUCCESS; 00527 } 00528 00529 /** 00530 * @brief Set the fields of the TIMx Hall sensor interface configuration data 00531 * structure to their default values. 00532 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) 00533 * @retval None 00534 */ 00535 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct) 00536 { 00537 /* Set the default configuration */ 00538 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; 00539 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; 00540 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; 00541 TIM_HallSensorInitStruct->CommutationDelay = (uint32_t)0U; 00542 } 00543 00544 /** 00545 * @brief Configure the Hall sensor interface of the timer instance. 00546 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR 00547 * to the TI1 input channel 00548 * @note TIMx slave mode controller is configured in reset mode. 00549 Selected internal trigger is TI1F_ED. 00550 * @note Channel 1 is configured as input, IC1 is mapped on TRC. 00551 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed 00552 * between 2 changes on the inputs. It gives information about motor speed. 00553 * @note Channel 2 is configured in output PWM 2 mode. 00554 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. 00555 * @note OC2REF is selected as trigger output on TRGO. 00556 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used 00557 * when TIMx operates in Hall sensor interface mode. 00558 * @param TIMx Timer Instance 00559 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) 00560 * @retval An ErrorStatus enumeration value: 00561 * - SUCCESS: TIMx registers are de-initialized 00562 * - ERROR: not applicable 00563 */ 00564 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef* TIMx, LL_TIM_HALLSENSOR_InitTypeDef* TIM_HallSensorInitStruct) 00565 { 00566 uint32_t tmpcr2 = 0U; 00567 uint32_t tmpccmr1 = 0U; 00568 uint32_t tmpccer = 0U; 00569 uint32_t tmpsmcr = 0U; 00570 00571 /* Check the parameters */ 00572 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); 00573 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity )); 00574 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler )); 00575 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter )); 00576 00577 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ 00578 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); 00579 00580 /* Get the TIMx CR2 register value */ 00581 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00582 00583 /* Get the TIMx CCMR1 register value */ 00584 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00585 00586 /* Get the TIMx CCER register value */ 00587 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00588 00589 /* Get the TIMx SMCR register value */ 00590 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); 00591 00592 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ 00593 tmpcr2 |= TIM_CR2_TI1S; 00594 00595 /* OC2REF signal is used as trigger output (TRGO) */ 00596 tmpcr2 |= LL_TIM_TRGO_OC2REF; 00597 00598 /* Configure the slave mode controller */ 00599 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); 00600 tmpsmcr |= LL_TIM_TS_TI1F_ED; 00601 tmpsmcr |= LL_TIM_SLAVEMODE_RESET; 00602 00603 /* Configure input channel 1 */ 00604 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); 00605 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); 00606 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); 00607 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); 00608 00609 /* Configure input channel 2 */ 00610 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); 00611 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); 00612 00613 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ 00614 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); 00615 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity ); 00616 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); 00617 00618 /* Write to TIMx CR2 */ 00619 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00620 00621 /* Write to TIMx SMCR */ 00622 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); 00623 00624 /* Write to TIMx CCMR1 */ 00625 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00626 00627 /* Write to TIMx CCER */ 00628 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00629 00630 /* Write to TIMx CCR2 */ 00631 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay ); 00632 00633 return SUCCESS; 00634 } 00635 00636 /** 00637 * @} 00638 */ 00639 00640 /** 00641 * @} 00642 */ 00643 00644 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions 00645 * @brief Private functions 00646 * @{ 00647 */ 00648 /** 00649 * @brief Configure the TIMx output channel 1. 00650 * @param TIMx Timer Instance 00651 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure 00652 * @retval An ErrorStatus enumeration value: 00653 * - SUCCESS: TIMx registers are de-initialized 00654 * - ERROR: not applicable 00655 */ 00656 static ErrorStatus OC1Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) 00657 { 00658 uint32_t tmpccmr1 = 0U; 00659 uint32_t tmpccer = 0U; 00660 uint32_t tmpcr2 = 0U; 00661 00662 /* Check the parameters */ 00663 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 00664 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode )); 00665 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState )); 00666 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity )); 00667 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState )); 00668 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity )); 00669 00670 /* Disable the Channel 1: Reset the CC1E Bit */ 00671 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); 00672 00673 /* Get the TIMx CCER register value */ 00674 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00675 00676 /* Get the TIMx CR2 register value */ 00677 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00678 00679 /* Get the TIMx CCMR1 register value */ 00680 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00681 00682 /* Reset Capture/Compare selection Bits */ 00683 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); 00684 00685 /* Set the Output Compare Mode */ 00686 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode ); 00687 00688 /* Set the Output Compare Polarity */ 00689 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity ); 00690 00691 /* Set the Output State */ 00692 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState ); 00693 00694 if(IS_TIM_BREAK_INSTANCE(TIMx)) 00695 { 00696 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState )); 00697 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState )); 00698 00699 /* Set the complementary output Polarity */ 00700 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); 00701 00702 /* Set the complementary output State */ 00703 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); 00704 00705 /* Set the Output Idle state */ 00706 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState ); 00707 00708 /* Set the complementary output Idle state */ 00709 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); 00710 } 00711 00712 /* Write to TIMx CR2 */ 00713 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00714 00715 /* Write to TIMx CCMR1 */ 00716 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00717 00718 /* Set the Capture Compare Register value */ 00719 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue ); 00720 00721 /* Write to TIMx CCER */ 00722 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00723 00724 return SUCCESS; 00725 } 00726 00727 /** 00728 * @brief Configure the TIMx output channel 2. 00729 * @param TIMx Timer Instance 00730 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure 00731 * @retval An ErrorStatus enumeration value: 00732 * - SUCCESS: TIMx registers are de-initialized 00733 * - ERROR: not applicable 00734 */ 00735 static ErrorStatus OC2Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) 00736 { 00737 uint32_t tmpccmr1 = 0U; 00738 uint32_t tmpccer = 0U; 00739 uint32_t tmpcr2 = 0U; 00740 00741 /* Check the parameters */ 00742 assert_param(IS_TIM_CC2_INSTANCE(TIMx)); 00743 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode )); 00744 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState )); 00745 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity )); 00746 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState )); 00747 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity )); 00748 00749 /* Disable the Channel 2: Reset the CC2E Bit */ 00750 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); 00751 00752 /* Get the TIMx CCER register value */ 00753 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00754 00755 /* Get the TIMx CR2 register value */ 00756 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00757 00758 /* Get the TIMx CCMR1 register value */ 00759 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00760 00761 /* Reset Capture/Compare selection Bits */ 00762 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); 00763 00764 /* Select the Output Compare Mode */ 00765 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); 00766 00767 /* Set the Output Compare Polarity */ 00768 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); 00769 00770 /* Set the Output State */ 00771 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); 00772 00773 if(IS_TIM_BREAK_INSTANCE(TIMx)) 00774 { 00775 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState )); 00776 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState )); 00777 00778 /* Set the complementary output Polarity */ 00779 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); 00780 00781 /* Set the complementary output State */ 00782 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); 00783 00784 /* Set the Output Idle state */ 00785 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); 00786 00787 /* Set the complementary output Idle state */ 00788 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); 00789 } 00790 00791 /* Write to TIMx CR2 */ 00792 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00793 00794 /* Write to TIMx CCMR1 */ 00795 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00796 00797 /* Set the Capture Compare Register value */ 00798 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue ); 00799 00800 /* Write to TIMx CCER */ 00801 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00802 00803 return SUCCESS; 00804 } 00805 00806 /** 00807 * @brief Configure the TIMx output channel 3. 00808 * @param TIMx Timer Instance 00809 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure 00810 * @retval An ErrorStatus enumeration value: 00811 * - SUCCESS: TIMx registers are de-initialized 00812 * - ERROR: not applicable 00813 */ 00814 static ErrorStatus OC3Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) 00815 { 00816 uint32_t tmpccmr2 = 0U; 00817 uint32_t tmpccer = 0U; 00818 uint32_t tmpcr2 = 0U; 00819 00820 /* Check the parameters */ 00821 assert_param(IS_TIM_CC3_INSTANCE(TIMx)); 00822 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode )); 00823 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState )); 00824 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity )); 00825 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState )); 00826 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity )); 00827 00828 /* Disable the Channel 3: Reset the CC3E Bit */ 00829 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); 00830 00831 /* Get the TIMx CCER register value */ 00832 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00833 00834 /* Get the TIMx CR2 register value */ 00835 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00836 00837 /* Get the TIMx CCMR2 register value */ 00838 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); 00839 00840 /* Reset Capture/Compare selection Bits */ 00841 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); 00842 00843 /* Select the Output Compare Mode */ 00844 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode ); 00845 00846 /* Set the Output Compare Polarity */ 00847 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); 00848 00849 /* Set the Output State */ 00850 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); 00851 00852 if(IS_TIM_BREAK_INSTANCE(TIMx)) 00853 { 00854 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState )); 00855 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState )); 00856 00857 /* Set the complementary output Polarity */ 00858 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); 00859 00860 /* Set the complementary output State */ 00861 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); 00862 00863 /* Set the Output Idle state */ 00864 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); 00865 00866 /* Set the complementary output Idle state */ 00867 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); 00868 } 00869 00870 /* Write to TIMx CR2 */ 00871 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00872 00873 /* Write to TIMx CCMR2 */ 00874 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); 00875 00876 /* Set the Capture Compare Register value */ 00877 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue ); 00878 00879 /* Write to TIMx CCER */ 00880 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00881 00882 return SUCCESS; 00883 } 00884 00885 /** 00886 * @brief Configure the TIMx output channel 4. 00887 * @param TIMx Timer Instance 00888 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure 00889 * @retval An ErrorStatus enumeration value: 00890 * - SUCCESS: TIMx registers are de-initialized 00891 * - ERROR: not applicable 00892 */ 00893 static ErrorStatus OC4Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) 00894 { 00895 uint32_t tmpccmr2 = 0U; 00896 uint32_t tmpccer = 0U; 00897 uint32_t tmpcr2 = 0U; 00898 00899 /* Check the parameters */ 00900 assert_param(IS_TIM_CC4_INSTANCE(TIMx)); 00901 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode )); 00902 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState )); 00903 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity )); 00904 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity )); 00905 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState )); 00906 00907 /* Disable the Channel 4: Reset the CC4E Bit */ 00908 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); 00909 00910 /* Get the TIMx CCER register value */ 00911 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00912 00913 /* Get the TIMx CR2 register value */ 00914 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00915 00916 /* Get the TIMx CCMR2 register value */ 00917 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); 00918 00919 /* Reset Capture/Compare selection Bits */ 00920 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); 00921 00922 /* Select the Output Compare Mode */ 00923 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); 00924 00925 /* Set the Output Compare Polarity */ 00926 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); 00927 00928 /* Set the Output State */ 00929 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); 00930 00931 if(IS_TIM_BREAK_INSTANCE(TIMx)) 00932 { 00933 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState )); 00934 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState )); 00935 00936 /* Set the Output Idle state */ 00937 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); 00938 } 00939 00940 /* Write to TIMx CR2 */ 00941 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00942 00943 /* Write to TIMx CCMR2 */ 00944 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); 00945 00946 /* Set the Capture Compare Register value */ 00947 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue ); 00948 00949 /* Write to TIMx CCER */ 00950 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00951 00952 return SUCCESS; 00953 } 00954 00955 /** 00956 * @brief Configure the TIMx output channel 5. 00957 * @param TIMx Timer Instance 00958 * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure 00959 * @retval An ErrorStatus enumeration value: 00960 * - SUCCESS: TIMx registers are de-initialized 00961 * - ERROR: not applicable 00962 */ 00963 static ErrorStatus OC5Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) 00964 { 00965 uint32_t tmpccmr3 = 0U; 00966 uint32_t tmpccer = 0U; 00967 00968 /* Check the parameters */ 00969 assert_param(IS_TIM_CC5_INSTANCE(TIMx)); 00970 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode )); 00971 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState )); 00972 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity )); 00973 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity )); 00974 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState )); 00975 00976 /* Disable the Channel 5: Reset the CC5E Bit */ 00977 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); 00978 00979 /* Get the TIMx CCER register value */ 00980 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00981 00982 /* Get the TIMx CCMR3 register value */ 00983 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); 00984 00985 /* Select the Output Compare Mode */ 00986 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode ); 00987 00988 /* Set the Output Compare Polarity */ 00989 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); 00990 00991 /* Set the Output State */ 00992 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); 00993 00994 if(IS_TIM_BREAK_INSTANCE(TIMx)) 00995 { 00996 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState )); 00997 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState )); 00998 00999 /* Set the Output Idle state */ 01000 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); 01001 01002 } 01003 01004 /* Write to TIMx CCMR3 */ 01005 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); 01006 01007 /* Set the Capture Compare Register value */ 01008 LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue ); 01009 01010 /* Write to TIMx CCER */ 01011 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01012 01013 return SUCCESS; 01014 } 01015 01016 /** 01017 * @brief Configure the TIMx output channel 6. 01018 * @param TIMx Timer Instance 01019 * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure 01020 * @retval An ErrorStatus enumeration value: 01021 * - SUCCESS: TIMx registers are de-initialized 01022 * - ERROR: not applicable 01023 */ 01024 static ErrorStatus OC6Config(TIM_TypeDef* TIMx, LL_TIM_OC_InitTypeDef* TIM_OCInitStruct) 01025 { 01026 uint32_t tmpccmr3 = 0U; 01027 uint32_t tmpccer = 0U; 01028 01029 /* Check the parameters */ 01030 assert_param(IS_TIM_CC6_INSTANCE(TIMx)); 01031 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode )); 01032 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState )); 01033 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity )); 01034 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity )); 01035 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState )); 01036 01037 /* Disable the Channel 5: Reset the CC6E Bit */ 01038 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); 01039 01040 /* Get the TIMx CCER register value */ 01041 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 01042 01043 /* Get the TIMx CCMR3 register value */ 01044 tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); 01045 01046 /* Select the Output Compare Mode */ 01047 MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); 01048 01049 /* Set the Output Compare Polarity */ 01050 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); 01051 01052 /* Set the Output State */ 01053 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); 01054 01055 if(IS_TIM_BREAK_INSTANCE(TIMx)) 01056 { 01057 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState )); 01058 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState )); 01059 01060 /* Set the Output Idle state */ 01061 MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); 01062 } 01063 01064 /* Write to TIMx CCMR3 */ 01065 LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); 01066 01067 /* Set the Capture Compare Register value */ 01068 LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue ); 01069 01070 /* Write to TIMx CCER */ 01071 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01072 01073 return SUCCESS; 01074 } 01075 01076 /** 01077 * @brief Configure the TIMx input channel 1. 01078 * @param TIMx Timer Instance 01079 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure 01080 * @retval An ErrorStatus enumeration value: 01081 * - SUCCESS: TIMx registers are de-initialized 01082 * - ERROR: not applicable 01083 */ 01084 static ErrorStatus IC1Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) 01085 { 01086 /* Check the parameters */ 01087 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 01088 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity )); 01089 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput )); 01090 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler )); 01091 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter )); 01092 01093 /* Disable the Channel 1: Reset the CC1E Bit */ 01094 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; 01095 01096 /* Select the Input and set the filter and the prescaler value */ 01097 MODIFY_REG(TIMx->CCMR1, 01098 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), 01099 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler ) >> 16U); 01100 01101 /* Select the Polarity and set the CC1E Bit */ 01102 MODIFY_REG(TIMx->CCER, 01103 (TIM_CCER_CC1P | TIM_CCER_CC1NP), 01104 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); 01105 01106 return SUCCESS; 01107 } 01108 01109 /** 01110 * @brief Configure the TIMx input channel 2. 01111 * @param TIMx Timer Instance 01112 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure 01113 * @retval An ErrorStatus enumeration value: 01114 * - SUCCESS: TIMx registers are de-initialized 01115 * - ERROR: not applicable 01116 */ 01117 static ErrorStatus IC2Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) 01118 { 01119 /* Check the parameters */ 01120 assert_param(IS_TIM_CC2_INSTANCE(TIMx)); 01121 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity )); 01122 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput )); 01123 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler )); 01124 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter )); 01125 01126 /* Disable the Channel 2: Reset the CC2E Bit */ 01127 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; 01128 01129 /* Select the Input and set the filter and the prescaler value */ 01130 MODIFY_REG(TIMx->CCMR1, 01131 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), 01132 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler ) >> 8U); 01133 01134 /* Select the Polarity and set the CC2E Bit */ 01135 MODIFY_REG(TIMx->CCER, 01136 (TIM_CCER_CC2P | TIM_CCER_CC2NP), 01137 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E) ); 01138 01139 return SUCCESS; 01140 } 01141 01142 /** 01143 * @brief Configure the TIMx input channel 3. 01144 * @param TIMx Timer Instance 01145 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure 01146 * @retval An ErrorStatus enumeration value: 01147 * - SUCCESS: TIMx registers are de-initialized 01148 * - ERROR: not applicable 01149 */ 01150 static ErrorStatus IC3Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) 01151 { 01152 /* Check the parameters */ 01153 assert_param(IS_TIM_CC3_INSTANCE(TIMx)); 01154 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity )); 01155 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput )); 01156 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler )); 01157 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter )); 01158 01159 /* Disable the Channel 3: Reset the CC3E Bit */ 01160 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; 01161 01162 /* Select the Input and set the filter and the prescaler value */ 01163 MODIFY_REG(TIMx->CCMR2, 01164 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), 01165 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler ) >> 16U); 01166 01167 /* Select the Polarity and set the CC3E Bit */ 01168 MODIFY_REG(TIMx->CCER, 01169 (TIM_CCER_CC3P | TIM_CCER_CC3NP), 01170 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E) ); 01171 01172 return SUCCESS; 01173 } 01174 01175 /** 01176 * @brief Configure the TIMx input channel 4. 01177 * @param TIMx Timer Instance 01178 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure 01179 * @retval An ErrorStatus enumeration value: 01180 * - SUCCESS: TIMx registers are de-initialized 01181 * - ERROR: not applicable 01182 */ 01183 static ErrorStatus IC4Config(TIM_TypeDef* TIMx, LL_TIM_IC_InitTypeDef* TIM_ICInitStruct) 01184 { 01185 /* Check the parameters */ 01186 assert_param(IS_TIM_CC4_INSTANCE(TIMx)); 01187 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity )); 01188 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput )); 01189 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler )); 01190 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter )); 01191 01192 /* Disable the Channel 4: Reset the CC4E Bit */ 01193 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; 01194 01195 /* Select the Input and set the filter and the prescaler value */ 01196 MODIFY_REG(TIMx->CCMR2, 01197 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), 01198 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler ) >> 8U); 01199 01200 /* Select the Polarity and set the CC2E Bit */ 01201 MODIFY_REG(TIMx->CCER, 01202 (TIM_CCER_CC4P | TIM_CCER_CC4NP), 01203 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E) ); 01204 01205 return SUCCESS; 01206 } 01207 01208 01209 /** 01210 * @} 01211 */ 01212 01213 /** 01214 * @} 01215 */ 01216 01217 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ 01218 01219 /** 01220 * @} 01221 */ 01222 01223 #endif /* USE_FULL_LL_DRIVER */ 01224 01225 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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