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stm32l4xx_ll_system.h

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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_system.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SYSTEM LL module.
00008   @verbatim
00009   ==============================================================================
00010                      ##### How to use this driver #####
00011   ==============================================================================
00012     [..]
00013     The LL SYSTEM driver contains a set of generic APIs that can be
00014     used by user:
00015       (+) Some of the FLASH features need to be handled in the SYSTEM file.
00016       (+) Access to DBGCMU registers
00017       (+) Access to SYSCFG registers
00018       (+) Access to VREFBUF registers
00019 
00020   @endverbatim
00021   ******************************************************************************
00022   * @attention
00023   *
00024   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00025   *
00026   * Redistribution and use in source and binary forms, with or without modification,
00027   * are permitted provided that the following conditions are met:
00028   *   1. Redistributions of source code must retain the above copyright notice,
00029   *      this list of conditions and the following disclaimer.
00030   *   2. Redistributions in binary form must reproduce the above copyright notice,
00031   *      this list of conditions and the following disclaimer in the documentation
00032   *      and/or other materials provided with the distribution.
00033   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00034   *      may be used to endorse or promote products derived from this software
00035   *      without specific prior written permission.
00036   *
00037   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00038   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00039   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00040   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00041   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00042   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00043   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00044   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00045   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00046   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00047   *
00048   ******************************************************************************
00049   */
00050 
00051 /* Define to prevent recursive inclusion -------------------------------------*/
00052 #ifndef __STM32L4xx_LL_SYSTEM_H
00053 #define __STM32L4xx_LL_SYSTEM_H
00054 
00055 #ifdef __cplusplus
00056 extern "C" {
00057 #endif
00058 
00059 /* Includes ------------------------------------------------------------------*/
00060 #include "stm32l4xx.h"
00061 
00062 /** @addtogroup STM32L4xx_LL_Driver
00063   * @{
00064   */
00065 
00066 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
00067 
00068 /** @defgroup SYSTEM_LL SYSTEM
00069   * @{
00070   */
00071 
00072 /* Private types -------------------------------------------------------------*/
00073 /* Private variables ---------------------------------------------------------*/
00074 
00075 /* Private constants ---------------------------------------------------------*/
00076 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
00077   * @{
00078   */
00079 
00080 /* Defines used for position in the register */
00081 #define DBGMCU_REVID_POSITION         (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
00082 
00083 /**
00084  * @brief Power-down in Run mode Flash key
00085  */
00086 #define FLASH_PDKEY1                  ((uint32_t)0x04152637U) /*!< Flash power down key1 */
00087 #define FLASH_PDKEY2                  ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
00088                                                                    to unlock the RUN_PD bit in FLASH_ACR */
00089 
00090 /**
00091   * @}
00092   */
00093 
00094 /* Private macros ------------------------------------------------------------*/
00095 
00096 /* Exported types ------------------------------------------------------------*/
00097 /* Exported constants --------------------------------------------------------*/
00098 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
00099   * @{
00100   */
00101 
00102 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
00103 * @{
00104 */
00105 #define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */
00106 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
00107 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
00108 #if defined(FMC_Bank1_R)
00109 #define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
00110 #endif /* FMC_Bank1_R */
00111 #define LL_SYSCFG_REMAP_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000                 */
00112 /**
00113   * @}
00114   */
00115 
00116 #if defined(SYSCFG_MEMRMP_FB_MODE)
00117 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
00118   * @{
00119   */
00120 #define LL_SYSCFG_BANKMODE_BANK1           (uint32_t)0x00000000      /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
00121                                                                       and Flash Bank2 mapped at 0x08080000 (and aliased at 0x00080000) */
00122 #define LL_SYSCFG_BANKMODE_BANK2           SYSCFG_MEMRMP_FB_MODE     /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
00123                                                                       and Flash Bank1 mapped at 0x08080000 (and aliased at 0x00080000) */
00124 /**
00125   * @}
00126   */
00127 
00128 #endif /* SYSCFG_MEMRMP_FB_MODE */
00129 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
00130   * @{
00131   */
00132 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6     SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
00133 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7     SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
00134 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
00135 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8     SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
00136 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
00137 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
00138 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9     SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
00139 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
00140 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1    SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
00141 #if defined(I2C2)
00142 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2    SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
00143 #endif /* I2C2 */
00144 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3    SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
00145 /**
00146   * @}
00147   */
00148 
00149 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
00150   * @{
00151   */
00152 #define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */
00153 #define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */
00154 #define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */
00155 #define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */
00156 #define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */
00157 #if defined(GPIOF)
00158 #define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */
00159 #endif /* GPIOF */
00160 #if defined(GPIOG)
00161 #define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */
00162 #endif /* GPIOG */
00163 #define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */
00164 /**
00165   * @}
00166   */
00167 
00168 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
00169   * @{
00170   */
00171 #define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /* !< EXTI_POSITION_0  | EXTICR[0] */
00172 #define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /* !< EXTI_POSITION_4  | EXTICR[0] */
00173 #define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /* !< EXTI_POSITION_8  | EXTICR[0] */
00174 #define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /* !< EXTI_POSITION_12 | EXTICR[0] */
00175 #define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /* !< EXTI_POSITION_0  | EXTICR[1] */
00176 #define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /* !< EXTI_POSITION_4  | EXTICR[1] */
00177 #define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /* !< EXTI_POSITION_8  | EXTICR[1] */
00178 #define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /* !< EXTI_POSITION_12 | EXTICR[1] */
00179 #define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /* !< EXTI_POSITION_0  | EXTICR[2] */
00180 #define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /* !< EXTI_POSITION_4  | EXTICR[2] */
00181 #define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /* !< EXTI_POSITION_8  | EXTICR[2] */
00182 #define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /* !< EXTI_POSITION_12 | EXTICR[2] */
00183 #define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /* !< EXTI_POSITION_0  | EXTICR[3] */
00184 #define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /* !< EXTI_POSITION_4  | EXTICR[3] */
00185 #define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /* !< EXTI_POSITION_8  | EXTICR[3] */
00186 #define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /* !< EXTI_POSITION_12 | EXTICR[3] */
00187 /**
00188   * @}
00189   */
00190 
00191 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
00192   * @{
00193   */
00194 #define LL_SYSCFG_TIMBREAK_ECC             SYSCFG_CFGR2_ECCL  /*!< Enables and locks the ECC error signal 
00195                                                                    with Break Input of TIM1/8/15/16/17                           */
00196 #define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVDL  /*!< Enables and locks the PVD connection 
00197                                                                    with TIM1/8/15/16/17 Break Input 
00198                                                                    and also the PVDE and PLS bits of the Power Control Interface */
00199 #define LL_SYSCFG_TIMBREAK_SRAM2_PARITY    SYSCFG_CFGR2_SPL   /*!< Enables and locks the SRAM2_PARITY error signal 
00200                                                                    with Break Input of TIM1/8/15/16/17                           */
00201 #define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_CLL   /*!< Enables and locks the LOCKUP output of CortexM4 
00202                                                                    with Break Input of TIM1/15/16/17                             */
00203 /**
00204   * @}
00205   */
00206 
00207 /** @defgroup SYSTEM_LL_EC_SRAM2WRP SYSCFG SRAM2 WRP
00208   * @{
00209   */
00210 #define LL_SYSCFG_SRAM2WRP_PAGE0           SYSCFG_SWPR_PAGE0  /*!< SRAM2 Write protection page 0  */
00211 #define LL_SYSCFG_SRAM2WRP_PAGE1           SYSCFG_SWPR_PAGE1  /*!< SRAM2 Write protection page 1  */
00212 #define LL_SYSCFG_SRAM2WRP_PAGE2           SYSCFG_SWPR_PAGE2  /*!< SRAM2 Write protection page 2  */
00213 #define LL_SYSCFG_SRAM2WRP_PAGE3           SYSCFG_SWPR_PAGE3  /*!< SRAM2 Write protection page 3  */
00214 #define LL_SYSCFG_SRAM2WRP_PAGE4           SYSCFG_SWPR_PAGE4  /*!< SRAM2 Write protection page 4  */
00215 #define LL_SYSCFG_SRAM2WRP_PAGE5           SYSCFG_SWPR_PAGE5  /*!< SRAM2 Write protection page 5  */
00216 #define LL_SYSCFG_SRAM2WRP_PAGE6           SYSCFG_SWPR_PAGE6  /*!< SRAM2 Write protection page 6  */
00217 #define LL_SYSCFG_SRAM2WRP_PAGE7           SYSCFG_SWPR_PAGE7  /*!< SRAM2 Write protection page 7  */
00218 #define LL_SYSCFG_SRAM2WRP_PAGE8           SYSCFG_SWPR_PAGE8  /*!< SRAM2 Write protection page 8  */
00219 #define LL_SYSCFG_SRAM2WRP_PAGE9           SYSCFG_SWPR_PAGE9  /*!< SRAM2 Write protection page 9  */
00220 #define LL_SYSCFG_SRAM2WRP_PAGE10          SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
00221 #define LL_SYSCFG_SRAM2WRP_PAGE11          SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
00222 #define LL_SYSCFG_SRAM2WRP_PAGE12          SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
00223 #define LL_SYSCFG_SRAM2WRP_PAGE13          SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
00224 #define LL_SYSCFG_SRAM2WRP_PAGE14          SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
00225 #define LL_SYSCFG_SRAM2WRP_PAGE15          SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
00226 #if defined(SYSCFG_SWPR_PAGE16)
00227 #define LL_SYSCFG_SRAM2WRP_PAGE16          SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
00228 #define LL_SYSCFG_SRAM2WRP_PAGE17          SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
00229 #define LL_SYSCFG_SRAM2WRP_PAGE18          SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
00230 #define LL_SYSCFG_SRAM2WRP_PAGE19          SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
00231 #define LL_SYSCFG_SRAM2WRP_PAGE20          SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
00232 #define LL_SYSCFG_SRAM2WRP_PAGE21          SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
00233 #define LL_SYSCFG_SRAM2WRP_PAGE22          SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
00234 #define LL_SYSCFG_SRAM2WRP_PAGE23          SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
00235 #define LL_SYSCFG_SRAM2WRP_PAGE24          SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
00236 #define LL_SYSCFG_SRAM2WRP_PAGE25          SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
00237 #define LL_SYSCFG_SRAM2WRP_PAGE26          SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
00238 #define LL_SYSCFG_SRAM2WRP_PAGE27          SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
00239 #define LL_SYSCFG_SRAM2WRP_PAGE28          SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
00240 #define LL_SYSCFG_SRAM2WRP_PAGE29          SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
00241 #define LL_SYSCFG_SRAM2WRP_PAGE30          SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
00242 #define LL_SYSCFG_SRAM2WRP_PAGE31          SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
00243 #endif /* SYSCFG_SWPR_PAGE16 */
00244 /**
00245   * @}
00246   */
00247 
00248 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
00249   * @{
00250   */
00251 #define LL_DBGMCU_TRACE_NONE               (uint32_t)0x00000000U                           /*!< TRACE pins not assigned (default state) */
00252 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
00253 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
00254 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
00255 #define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
00256 /**
00257   * @}
00258   */
00259 
00260 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
00261   * @{
00262   */
00263 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1FZR1_DBG_TIM2_STOP   /*!< The counter clock of TIM2 is stopped when the core is halted*/
00264 #if defined(TIM3)
00265 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1FZR1_DBG_TIM3_STOP   /*!< The counter clock of TIM3 is stopped when the core is halted*/
00266 #endif /* TIM3 */
00267 #if defined(TIM4)
00268 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1FZR1_DBG_TIM4_STOP   /*!< The counter clock of TIM4 is stopped when the core is halted*/
00269 #endif /* TIM4 */
00270 #if defined(TIM5)
00271 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1FZR1_DBG_TIM5_STOP   /*!< The counter clock of TIM5 is stopped when the core is halted*/
00272 #endif /* TIM5 */
00273 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1FZR1_DBG_TIM6_STOP   /*!< The counter clock of TIM6 is stopped when the core is halted*/
00274 #if defined(TIM7)
00275 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1FZR1_DBG_TIM7_STOP   /*!< The counter clock of TIM7 is stopped when the core is halted*/
00276 #endif /* TIM7 */
00277 #define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1FZR1_DBG_RTC_STOP    /*!< The clock of the RTC counter is stopped when the core is halted*/
00278 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1FZR1_DBG_WWDG_STOP   /*!< The window watchdog counter clock is stopped when the core is halted*/
00279 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1FZR1_DBG_IWDG_STOP   /*!< The independent watchdog counter clock is stopped when the core is halted*/
00280 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1FZR1_DBG_I2C1_STOP   /*!< The I2C1 SMBus timeout is frozen*/
00281 #if defined(I2C2)
00282 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1FZR1_DBG_I2C2_STOP   /*!< The I2C2 SMBus timeout is frozen*/
00283 #endif /* I2C2 */
00284 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1FZR1_DBG_I2C3_STOP   /*!< The I2C3 SMBus timeout is frozen*/
00285 #define LL_DBGMCU_APB1_GRP1_CAN_STOP       DBGMCU_APB1FZR1_DBG_CAN_STOP    /*!< The bxCAN receive registers are frozen*/
00286 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
00287 /**
00288   * @}
00289   */
00290 
00291 /** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
00292   * @{
00293   */
00294 #define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP    DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/
00295 /**
00296   * @}
00297   */
00298 
00299 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
00300   * @{
00301   */
00302 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ_DBG_TIM1_STOP     /*!< The counter clock of TIM1 is stopped when the core is halted*/
00303 #if defined(TIM8)
00304 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ_DBG_TIM8_STOP     /*!< The counter clock of TIM8 is stopped when the core is halted*/
00305 #endif /* TIM8 */
00306 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ_DBG_TIM15_STOP    /*!< The counter clock of TIM15 is stopped when the core is halted*/
00307 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ_DBG_TIM16_STOP    /*!< The counter clock of TIM16 is stopped when the core is halted*/
00308 #if defined(TIM17)
00309 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ_DBG_TIM17_STOP    /*!< The counter clock of TIM17 is stopped when the core is halted*/
00310 #endif /* TIM17 */
00311 /**
00312   * @}
00313   */
00314 
00315 #if defined(VREFBUF)
00316 /** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
00317   * @{
00318   */
00319 #define LL_VREFBUF_VOLTAGE_SCALE0          ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
00320 #define LL_VREFBUF_VOLTAGE_SCALE1          VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
00321 /**
00322   * @}
00323   */
00324 #endif /* VREFBUF */
00325 
00326 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
00327   * @{
00328   */
00329 #define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
00330 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
00331 #define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
00332 #define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
00333 #define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
00334 /**
00335   * @}
00336   */
00337 
00338 /**
00339   * @}
00340   */
00341 
00342 /* Exported macro ------------------------------------------------------------*/
00343 
00344 /* Exported functions --------------------------------------------------------*/
00345 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
00346   * @{
00347   */
00348 
00349 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
00350   * @{
00351   */
00352 
00353 /**
00354   * @brief  Set memory mapping at address 0x00000000
00355   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
00356   * @param  Memory This parameter can be one of the following values:
00357   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00358   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00359   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00360   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00361   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
00362   *
00363   *         (*) value not defined in all devices
00364   * @retval None
00365   */
00366 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
00367 {
00368   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
00369 }
00370 
00371 /**
00372   * @brief  Get memory mapping at address 0x00000000
00373   * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
00374   * @retval Returned value can be one of the following values:
00375   *         @arg @ref LL_SYSCFG_REMAP_FLASH
00376   *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
00377   *         @arg @ref LL_SYSCFG_REMAP_SRAM
00378   *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
00379   *         @arg @ref LL_SYSCFG_REMAP_QUADSPI
00380   *
00381   *         (*) value not defined in all devices
00382   */
00383 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
00384 {
00385   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
00386 }
00387 
00388 #if defined(SYSCFG_MEMRMP_FB_MODE)
00389 /**
00390   * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
00391   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_SetFlashBankMode
00392   * @param  Bank This parameter can be one of the following values:
00393   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
00394   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
00395   * @retval None
00396   */
00397 __STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
00398 {
00399   MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
00400 }
00401 
00402 /**
00403   * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
00404   * @rmtoll SYSCFG_MEMRMP FB_MODE       LL_SYSCFG_GetFlashBankMode
00405   * @retval Returned value can be one of the following values:
00406   *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
00407   *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
00408   */
00409 __STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
00410 {
00411   return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
00412 }
00413 #endif /* SYSCFG_MEMRMP_FB_MODE */
00414 
00415 /**
00416   * @brief  Firewall protection enabled
00417   * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_EnableFirewall
00418   * @retval None
00419   */
00420 __STATIC_INLINE void LL_SYSCFG_EnableFirewall(void)
00421 {
00422   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS);
00423 }
00424 
00425 /**
00426   * @brief  Check if Firewall protection is enabled or not
00427   * @rmtoll SYSCFG_CFGR1 FWDIS         LL_SYSCFG_IsEnabledFirewall
00428   * @retval State of bit (1 or 0).
00429   */
00430 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void)
00431 {
00432   return !(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FWDIS) == SYSCFG_CFGR1_FWDIS);
00433 }
00434 
00435 /**
00436   * @brief  Enable I/O analog switch voltage booster.
00437   * @note   When voltage booster is enabled, I/O analog switches are supplied
00438   *         by a dedicated voltage booster, from VDD power domain. This is
00439   *         the recommended configuration with low VDDA voltage operation.
00440   * @note   The I/O analog switch voltage booster is relevant for peripherals
00441   *         using I/O in analog input: ADC, COMP, OPAMP.
00442   *         However, COMP and OPAMP inputs have a high impedance and
00443   *         voltage booster do not impact performance significantly.
00444   *         Therefore, the voltage booster is mainly intended for
00445   *         usage with ADC.
00446   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_EnableAnalogBooster
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
00450 {
00451   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00452 }
00453 
00454 /**
00455   * @brief  Disable I/O analog switch voltage booster.
00456   * @note   When voltage booster is enabled, I/O analog switches are supplied
00457   *         by a dedicated voltage booster, from VDD power domain. This is
00458   *         the recommended configuration with low VDDA voltage operation.
00459   * @note   The I/O analog switch voltage booster is relevant for peripherals
00460   *         using I/O in analog input: ADC, COMP, OPAMP.
00461   *         However, COMP and OPAMP inputs have a high impedance and
00462   *         voltage booster do not impact performance significantly.
00463   *         Therefore, the voltage booster is mainly intended for
00464   *         usage with ADC.
00465   * @rmtoll SYSCFG_CFGR1 BOOSTEN       LL_SYSCFG_DisableAnalogBooster
00466   * @retval None
00467   */
00468 __STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
00469 {
00470   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
00471 }
00472 
00473 /**
00474   * @brief  Enable the I2C fast mode plus driving capability.
00475   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n
00476   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_EnableFastModePlus
00477   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00478   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00479   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00480   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00481   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00482   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00483   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00484   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00485   *
00486   *         (*) value not defined in all devices
00487   * @retval None
00488   */
00489 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
00490 {
00491   SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00492 }
00493 
00494 /**
00495   * @brief  Disable the I2C fast mode plus driving capability.
00496   * @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n
00497   *         SYSCFG_CFGR1 I2Cx_FMP      LL_SYSCFG_DisableFastModePlus
00498   * @param  ConfigFastModePlus This parameter can be a combination of the following values:
00499   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
00500   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
00501   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
00502   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
00503   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
00504   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
00505   *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
00506   *
00507   *         (*) value not defined in all devices
00508   * @retval None
00509   */
00510 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
00511 {
00512   CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
00513 }
00514 
00515 /**
00516   * @brief  Enable Floating Point Unit Invalid operation Interrupt
00517   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_EnableIT_FPU_IOC
00518   * @retval None
00519   */
00520 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
00521 {
00522   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00523 }
00524 
00525 /**
00526   * @brief  Enable Floating Point Unit Divide-by-zero Interrupt
00527   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_EnableIT_FPU_DZC
00528   * @retval None
00529   */
00530 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
00531 {
00532   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00533 }
00534 
00535 /**
00536   * @brief  Enable Floating Point Unit Underflow Interrupt
00537   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_EnableIT_FPU_UFC
00538   * @retval None
00539   */
00540 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
00541 {
00542   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00543 }
00544 
00545 /**
00546   * @brief  Enable Floating Point Unit Overflow Interrupt
00547   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_EnableIT_FPU_OFC
00548   * @retval None
00549   */
00550 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
00551 {
00552   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00553 }
00554 
00555 /**
00556   * @brief  Enable Floating Point Unit Input denormal Interrupt
00557   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_EnableIT_FPU_IDC
00558   * @retval None
00559   */
00560 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
00561 {
00562   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00563 }
00564 
00565 /**
00566   * @brief  Enable Floating Point Unit Inexact Interrupt
00567   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_EnableIT_FPU_IXC
00568   * @retval None
00569   */
00570 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
00571 {
00572   SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00573 }
00574 
00575 /**
00576   * @brief  Disable Floating Point Unit Invalid operation Interrupt
00577   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_DisableIT_FPU_IOC
00578   * @retval None
00579   */
00580 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
00581 {
00582   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
00583 }
00584 
00585 /**
00586   * @brief  Disable Floating Point Unit Divide-by-zero Interrupt
00587   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_DisableIT_FPU_DZC
00588   * @retval None
00589   */
00590 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
00591 {
00592   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
00593 }
00594 
00595 /**
00596   * @brief  Disable Floating Point Unit Underflow Interrupt
00597   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_DisableIT_FPU_UFC
00598   * @retval None
00599   */
00600 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
00601 {
00602   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
00603 }
00604 
00605 /**
00606   * @brief  Disable Floating Point Unit Overflow Interrupt
00607   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_DisableIT_FPU_OFC
00608   * @retval None
00609   */
00610 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
00611 {
00612   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
00613 }
00614 
00615 /**
00616   * @brief  Disable Floating Point Unit Input denormal Interrupt
00617   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_DisableIT_FPU_IDC
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
00621 {
00622   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
00623 }
00624 
00625 /**
00626   * @brief  Disable Floating Point Unit Inexact Interrupt
00627   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_DisableIT_FPU_IXC
00628   * @retval None
00629   */
00630 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
00631 {
00632   CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
00633 }
00634 
00635 /**
00636   * @brief  Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
00637   * @rmtoll SYSCFG_CFGR1 FPU_IE_0      LL_SYSCFG_IsEnabledIT_FPU_IOC
00638   * @retval State of bit (1 or 0).
00639   */
00640 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
00641 {
00642   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
00643 }
00644 
00645 /**
00646   * @brief  Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
00647   * @rmtoll SYSCFG_CFGR1 FPU_IE_1      LL_SYSCFG_IsEnabledIT_FPU_DZC
00648   * @retval State of bit (1 or 0).
00649   */
00650 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
00651 {
00652   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
00653 }
00654 
00655 /**
00656   * @brief  Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
00657   * @rmtoll SYSCFG_CFGR1 FPU_IE_2      LL_SYSCFG_IsEnabledIT_FPU_UFC
00658   * @retval State of bit (1 or 0).
00659   */
00660 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
00661 {
00662   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
00663 }
00664 
00665 /**
00666   * @brief  Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
00667   * @rmtoll SYSCFG_CFGR1 FPU_IE_3      LL_SYSCFG_IsEnabledIT_FPU_OFC
00668   * @retval State of bit (1 or 0).
00669   */
00670 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
00671 {
00672   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
00673 }
00674 
00675 /**
00676   * @brief  Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
00677   * @rmtoll SYSCFG_CFGR1 FPU_IE_4      LL_SYSCFG_IsEnabledIT_FPU_IDC
00678   * @retval State of bit (1 or 0).
00679   */
00680 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
00681 {
00682   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
00683 }
00684 
00685 /**
00686   * @brief  Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
00687   * @rmtoll SYSCFG_CFGR1 FPU_IE_5      LL_SYSCFG_IsEnabledIT_FPU_IXC
00688   * @retval State of bit (1 or 0).
00689   */
00690 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
00691 {
00692   return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
00693 }
00694 
00695 /**
00696   * @brief  Configure source input for the EXTI external interrupt.
00697   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
00698   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
00699   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
00700   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
00701   * @param  Port This parameter can be one of the following values:
00702   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00703   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00704   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00705   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00706   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00707   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
00708   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
00709   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00710   *
00711   *         (*) value not defined in all devices
00712   * @param  Line This parameter can be one of the following values:
00713   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00714   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00715   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00716   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00717   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00718   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00719   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00720   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00721   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00722   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00723   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00724   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00725   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00726   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00727   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00728   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00729   * @retval None
00730   */
00731 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
00732 {
00733   MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
00734 }
00735 
00736 /**
00737   * @brief  Get the configured defined for specific EXTI Line
00738   * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
00739   *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
00740   *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
00741   *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
00742   * @param  Line This parameter can be one of the following values:
00743   *         @arg @ref LL_SYSCFG_EXTI_LINE0
00744   *         @arg @ref LL_SYSCFG_EXTI_LINE1
00745   *         @arg @ref LL_SYSCFG_EXTI_LINE2
00746   *         @arg @ref LL_SYSCFG_EXTI_LINE3
00747   *         @arg @ref LL_SYSCFG_EXTI_LINE4
00748   *         @arg @ref LL_SYSCFG_EXTI_LINE5
00749   *         @arg @ref LL_SYSCFG_EXTI_LINE6
00750   *         @arg @ref LL_SYSCFG_EXTI_LINE7
00751   *         @arg @ref LL_SYSCFG_EXTI_LINE8
00752   *         @arg @ref LL_SYSCFG_EXTI_LINE9
00753   *         @arg @ref LL_SYSCFG_EXTI_LINE10
00754   *         @arg @ref LL_SYSCFG_EXTI_LINE11
00755   *         @arg @ref LL_SYSCFG_EXTI_LINE12
00756   *         @arg @ref LL_SYSCFG_EXTI_LINE13
00757   *         @arg @ref LL_SYSCFG_EXTI_LINE14
00758   *         @arg @ref LL_SYSCFG_EXTI_LINE15
00759   * @retval Returned value can be one of the following values:
00760   *         @arg @ref LL_SYSCFG_EXTI_PORTA
00761   *         @arg @ref LL_SYSCFG_EXTI_PORTB
00762   *         @arg @ref LL_SYSCFG_EXTI_PORTC
00763   *         @arg @ref LL_SYSCFG_EXTI_PORTD
00764   *         @arg @ref LL_SYSCFG_EXTI_PORTE
00765   *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
00766   *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
00767   *         @arg @ref LL_SYSCFG_EXTI_PORTH
00768   *
00769   *         (*) value not defined in all devices
00770   */
00771 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
00772 {
00773   return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
00774 }
00775 
00776 /**
00777   * @brief  Enable SRAM2 Erase (starts a hardware SRAM2 erase operation. This bit is
00778   * automatically cleared at the end of the SRAM2 erase operation.)
00779   * @note This bit is write-protected: setting this bit is possible only after the
00780   *       correct key sequence is written in the SYSCFG_SKR register.
00781   * @rmtoll SYSCFG_SCSR  SRAM2ER       LL_SYSCFG_EnableSRAM2Erase
00782   * @retval None
00783   */
00784 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2Erase(void)
00785 {
00786   /* unlock the write protection of the SRAM2ER bit */
00787   WRITE_REG(SYSCFG->SKR, 0xCA);
00788   WRITE_REG(SYSCFG->SKR, 0x53);
00789 
00790   /* Starts a hardware SRAM2 erase operation*/
00791   SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER);
00792 }
00793 
00794 /**
00795   * @brief  Check if SRAM2 erase operation is on going
00796   * @rmtoll SYSCFG_SCSR  SRAM2BSY      LL_SYSCFG_IsSRAM2EraseOngoing
00797   * @retval State of bit (1 or 0).
00798   */
00799 __STATIC_INLINE uint32_t LL_SYSCFG_IsSRAM2EraseOngoing(void)
00800 {
00801   return (READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2BSY) == (SYSCFG_SCSR_SRAM2BSY));
00802 }
00803 
00804 /**
00805   * @brief  Set connections to TIM1/8/15/16/17 Break inputs
00806   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_SetTIMBreakInputs\n
00807   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_SetTIMBreakInputs\n
00808   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_SetTIMBreakInputs\n
00809   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_SetTIMBreakInputs
00810   * @param  Break This parameter can be a combination of the following values:
00811   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00812   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00813   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
00814   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00815   * @retval None
00816   */
00817 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
00818 {
00819   MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
00820 }
00821 
00822 /**
00823   * @brief  Get connections to TIM1/8/15/16/17 Break inputs
00824   * @rmtoll SYSCFG_CFGR2 CLL           LL_SYSCFG_GetTIMBreakInputs\n
00825   *         SYSCFG_CFGR2 SPL           LL_SYSCFG_GetTIMBreakInputs\n
00826   *         SYSCFG_CFGR2 PVDL          LL_SYSCFG_GetTIMBreakInputs\n
00827   *         SYSCFG_CFGR2 ECCL          LL_SYSCFG_GetTIMBreakInputs
00828   * @retval Returned value can be can be a combination of the following values:
00829   *         @arg @ref LL_SYSCFG_TIMBREAK_ECC
00830   *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
00831   *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_PARITY
00832   *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
00833   */
00834 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
00835 {
00836   return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
00837 }
00838 
00839 /**
00840   * @brief  Check if SRAM2 parity error detected
00841   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_IsActiveFlag_SP
00842   * @retval State of bit (1 or 0).
00843   */
00844 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
00845 {
00846   return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF));
00847 }
00848 
00849 /**
00850   * @brief  Clear SRAM2 parity error flag
00851   * @rmtoll SYSCFG_CFGR2 SPF           LL_SYSCFG_ClearFlag_SP
00852   * @retval None
00853   */
00854 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
00855 {
00856   SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
00857 }
00858 
00859 /**
00860   * @brief  Enable SRAM2 page write protection
00861   * @note Write protection is cleared only by a system reset
00862   * @rmtoll SYSCFG_SWPR  PAGEx         LL_SYSCFG_EnableSRAM2PageWRP
00863   * @param  SRAM2WRP This parameter can be a combination of the following values:
00864   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE0
00865   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE1
00866   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE2
00867   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE3
00868   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE4
00869   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE5
00870   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE6
00871   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE7
00872   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE8
00873   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE9
00874   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE10
00875   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE11
00876   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE12
00877   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE13
00878   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE14
00879   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE15
00880   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE16 (*)
00881   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE17 (*)
00882   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE18 (*)
00883   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE19 (*)
00884   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE20 (*)
00885   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE21 (*)
00886   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE22 (*)
00887   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE23 (*)
00888   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE24 (*)
00889   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE25 (*)
00890   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE26 (*)
00891   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE27 (*)
00892   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE28 (*)
00893   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE29 (*)
00894   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE30 (*)
00895   *         @arg @ref LL_SYSCFG_SRAM2WRP_PAGE31 (*)
00896   *
00897   *         (*) value not defined in all devices
00898   * @retval None
00899   */
00900 __STATIC_INLINE void LL_SYSCFG_EnableSRAM2PageWRP(uint32_t SRAM2WRP)
00901 {
00902   SET_BIT(SYSCFG->SWPR, SRAM2WRP);
00903 }
00904 
00905 /**
00906   * @brief  SRAM2 page write protection lock prior to erase
00907   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_LockSRAM2WRP
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_SYSCFG_LockSRAM2WRP(void)
00911 {
00912   /* Writing a wrong key reactivates the write protection */
00913   WRITE_REG(SYSCFG->SKR, 0x00);
00914 }
00915 
00916 /**
00917   * @brief  SRAM2 page write protection unlock prior to erase
00918   * @rmtoll SYSCFG_SKR   KEY           LL_SYSCFG_UnlockSRAM2WRP
00919   * @retval None
00920   */
00921 __STATIC_INLINE void LL_SYSCFG_UnlockSRAM2WRP(void)
00922 {
00923   /* unlock the write protection of the SRAM2ER bit */
00924   WRITE_REG(SYSCFG->SKR, 0xCA);
00925   WRITE_REG(SYSCFG->SKR, 0x53);
00926 }
00927 
00928 /**
00929   * @}
00930   */
00931 
00932 
00933 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
00934   * @{
00935   */
00936 
00937 /**
00938   * @brief  Return the device identifier
00939   * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
00940   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415)
00941   */
00942 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
00943 {
00944   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
00945 }
00946 
00947 /**
00948   * @brief  Return the device revision identifier
00949   * @note This field indicates the revision of the device.
00950   * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
00951   * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
00952   */
00953 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
00954 {
00955   return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
00956 }
00957 
00958 /**
00959   * @brief  Enable the Debug Module during SLEEP mode
00960   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
00961   * @retval None
00962   */
00963 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
00964 {
00965   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00966 }
00967 
00968 /**
00969   * @brief  Disable the Debug Module during SLEEP mode
00970   * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
00971   * @retval None
00972   */
00973 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
00974 {
00975   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
00976 }
00977 
00978 /**
00979   * @brief  Enable the Debug Module during STOP mode
00980   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
00981   * @retval None
00982   */
00983 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
00984 {
00985   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00986 }
00987 
00988 /**
00989   * @brief  Disable the Debug Module during STOP mode
00990   * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
00991   * @retval None
00992   */
00993 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
00994 {
00995   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
00996 }
00997 
00998 /**
00999   * @brief  Enable the Debug Module during STANDBY mode
01000   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
01001   * @retval None
01002   */
01003 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
01004 {
01005   SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01006 }
01007 
01008 /**
01009   * @brief  Disable the Debug Module during STANDBY mode
01010   * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
01011   * @retval None
01012   */
01013 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
01014 {
01015   CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
01016 }
01017 
01018 /**
01019   * @brief  Set Trace pin assignment control
01020   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
01021   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
01022   * @param  PinAssignment This parameter can be one of the following values:
01023   *         @arg @ref LL_DBGMCU_TRACE_NONE
01024   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01025   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01026   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01027   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01028   * @retval None
01029   */
01030 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
01031 {
01032   MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
01033 }
01034 
01035 /**
01036   * @brief  Get Trace pin assignment control
01037   * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
01038   *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
01039   * @retval Returned value can be one of the following values:
01040   *         @arg @ref LL_DBGMCU_TRACE_NONE
01041   *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
01042   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
01043   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
01044   *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
01045   */
01046 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
01047 {
01048   return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
01049 }
01050 
01051 /**
01052   * @brief  Freeze APB1 peripherals (group1 peripherals)
01053   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_FreezePeriph
01054   * @param  Periphs This parameter can be a combination of the following values:
01055   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01056   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
01057   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01058   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01059   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01060   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01061   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01062   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01063   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01064   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01065   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01066   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01067   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
01068   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01069   *
01070   *         (*) value not defined in all devices.
01071   * @retval None
01072   */
01073 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
01074 {
01075   SET_BIT(DBGMCU->APB1FZR1, Periphs);
01076 }
01077 
01078 /**
01079   * @brief  Freeze APB1 peripherals (group2 peripherals)
01080   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_FreezePeriph
01081   * @param  Periphs This parameter can be a combination of the following values:
01082   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
01083   * @retval None
01084   */
01085 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
01086 {
01087   SET_BIT(DBGMCU->APB1FZR2, Periphs);
01088 }
01089 
01090 /**
01091   * @brief  Unfreeze APB1 peripherals (group1 peripherals)
01092   * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP1_UnFreezePeriph
01093   * @param  Periphs This parameter can be a combination of the following values:
01094   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
01095   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
01096   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
01097   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
01098   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
01099   *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
01100   *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
01101   *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
01102   *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
01103   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
01104   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
01105   *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
01106   *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP
01107   *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
01108   *
01109   *         (*) value not defined in all devices.
01110   * @retval None
01111   */
01112 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
01113 {
01114   CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
01115 }
01116 
01117 /**
01118   * @brief  Unfreeze APB1 peripherals (group2 peripherals)
01119   * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP  LL_DBGMCU_APB1_GRP2_UnFreezePeriph
01120   * @param  Periphs This parameter can be a combination of the following values:
01121   *         @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP
01122   * @retval None
01123   */
01124 __STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
01125 {
01126   CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
01127 }
01128 
01129 /**
01130   * @brief  Freeze APB2 peripherals
01131   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_FreezePeriph
01132   * @param  Periphs This parameter can be a combination of the following values:
01133   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01134   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
01135   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01136   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01137   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
01138   *
01139   *         (*) value not defined in all devices.
01140   * @retval None
01141   */
01142 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
01143 {
01144   SET_BIT(DBGMCU->APB2FZ, Periphs);
01145 }
01146 
01147 /**
01148   * @brief  Unfreeze APB2 peripherals
01149   * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP  LL_DBGMCU_APB2_GRP1_UnFreezePeriph
01150   * @param  Periphs This parameter can be a combination of the following values:
01151   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
01152   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
01153   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
01154   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
01155   *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
01156   *
01157   *         (*) value not defined in all devices.
01158   * @retval None
01159   */
01160 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
01161 {
01162   CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
01163 }
01164 
01165 /**
01166   * @}
01167   */
01168 
01169 #if defined(VREFBUF)
01170 /** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
01171   * @{
01172   */
01173 
01174 /**
01175   * @brief  Enable Internal voltage reference
01176   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Enable
01177   * @retval None
01178   */
01179 __STATIC_INLINE void LL_VREFBUF_Enable(void)
01180 {
01181   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01182 }
01183 
01184 /**
01185   * @brief  Disable Internal voltage reference
01186   * @rmtoll VREFBUF_CSR  ENVR          LL_VREFBUF_Disable
01187   * @retval None
01188   */
01189 __STATIC_INLINE void LL_VREFBUF_Disable(void)
01190 {
01191   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
01192 }
01193 
01194 /**
01195   * @brief  Enable high impedance (VREF+pin is high impedance)
01196   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_EnableHIZ
01197   * @retval None
01198   */
01199 __STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
01200 {
01201   SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01202 }
01203 
01204 /**
01205   * @brief  Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
01206   * @rmtoll VREFBUF_CSR  HIZ           LL_VREFBUF_DisableHIZ
01207   * @retval None
01208   */
01209 __STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
01210 {
01211   CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
01212 }
01213 
01214 /**
01215   * @brief  Set the Voltage reference scale
01216   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_SetVoltageScaling
01217   * @param  Scale This parameter can be one of the following values:
01218   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01219   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01220   * @retval None
01221   */
01222 __STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
01223 {
01224   MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
01225 }
01226 
01227 /**
01228   * @brief  Get the Voltage reference scale
01229   * @rmtoll VREFBUF_CSR  VRS           LL_VREFBUF_GetVoltageScaling
01230   * @retval Returned value can be one of the following values:
01231   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
01232   *         @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
01233   */
01234 __STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
01235 {
01236   return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
01237 }
01238 
01239 /**
01240   * @brief  Check if Voltage reference buffer is ready
01241   * @rmtoll VREFBUF_CSR  VRR           LL_VREFBUF_IsVREFReady
01242   * @retval State of bit (1 or 0).
01243   */
01244 __STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
01245 {
01246   return (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR));
01247 }
01248 
01249 /**
01250   * @brief  Get the trimming code for VREFBUF calibration
01251   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_GetTrimming
01252   * @retval Between 0 and 0x3F
01253   */
01254 __STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
01255 {
01256   return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
01257 }
01258 
01259 /**
01260   * @brief  Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
01261   * @rmtoll VREFBUF_CCR  TRIM          LL_VREFBUF_SetTrimming
01262   * @param  Value Between 0 and 0x3F
01263   * @retval None
01264   */
01265 __STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
01266 {
01267   WRITE_REG(VREFBUF->CCR, Value);
01268 }
01269 
01270 /**
01271   * @}
01272   */
01273 #endif /* VREFBUF */
01274 
01275 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
01276   * @{
01277   */
01278 
01279 /**
01280   * @brief  Set FLASH Latency
01281   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
01282   * @param  Latency This parameter can be one of the following values:
01283   *         @arg @ref LL_FLASH_LATENCY_0
01284   *         @arg @ref LL_FLASH_LATENCY_1
01285   *         @arg @ref LL_FLASH_LATENCY_2
01286   *         @arg @ref LL_FLASH_LATENCY_3
01287   *         @arg @ref LL_FLASH_LATENCY_4
01288   * @retval None
01289   */
01290 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
01291 {
01292   MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
01293 }
01294 
01295 /**
01296   * @brief  Get FLASH Latency
01297   * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
01298   * @retval Returned value can be one of the following values:
01299   *         @arg @ref LL_FLASH_LATENCY_0
01300   *         @arg @ref LL_FLASH_LATENCY_1
01301   *         @arg @ref LL_FLASH_LATENCY_2
01302   *         @arg @ref LL_FLASH_LATENCY_3
01303   *         @arg @ref LL_FLASH_LATENCY_4
01304   */
01305 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
01306 {
01307   return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
01308 }
01309 
01310 /**
01311   * @brief  Enable Prefetch
01312   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
01313   * @retval None
01314   */
01315 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
01316 {
01317   SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01318 }
01319 
01320 /**
01321   * @brief  Disable Prefetch
01322   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
01323   * @retval None
01324   */
01325 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
01326 {
01327   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
01328 }
01329 
01330 /**
01331   * @brief  Check if Prefetch buffer is enabled
01332   * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
01333   * @retval State of bit (1 or 0).
01334   */
01335 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
01336 {
01337   return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
01338 }
01339 
01340 /**
01341   * @brief  Enable Instruction cache
01342   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
01343   * @retval None
01344   */
01345 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
01346 {
01347   SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01348 }
01349 
01350 /**
01351   * @brief  Disable Instruction cache
01352   * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
01353   * @retval None
01354   */
01355 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
01356 {
01357   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
01358 }
01359 
01360 /**
01361   * @brief  Enable Data cache
01362   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
01363   * @retval None
01364   */
01365 __STATIC_INLINE void LL_FLASH_EnableDataCache(void)
01366 {
01367   SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
01368 }
01369 
01370 /**
01371   * @brief  Disable Data cache
01372   * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
01373   * @retval None
01374   */
01375 __STATIC_INLINE void LL_FLASH_DisableDataCache(void)
01376 {
01377   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
01378 }
01379 
01380 /**
01381   * @brief  Enable Instruction cache reset
01382   * @note  bit can be written only when the instruction cache is disabled
01383   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
01384   * @retval None
01385   */
01386 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
01387 {
01388   SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
01389 }
01390 
01391 /**
01392   * @brief  Disable Instruction cache reset
01393   * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
01394   * @retval None
01395   */
01396 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
01397 {
01398   CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
01399 }
01400 
01401 /**
01402   * @brief  Enable Data cache reset
01403   * @note bit can be written only when the data cache is disabled
01404   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
01408 {
01409   SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
01410 }
01411 
01412 /**
01413   * @brief  Disable Data cache reset
01414   * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
01415   * @retval None
01416   */
01417 __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
01418 {
01419   CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
01420 }
01421 
01422 /**
01423   * @brief  Enable Flash Power-down mode during run mode or Low-power run mode
01424   * @note Flash memory can be put in power-down mode only when the code is executed
01425   *       from RAM
01426   * @note Flash must not be accessed when power down is enabled
01427   * @note Flash must not be put in power-down while a program or an erase operation
01428   *       is on-going
01429   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_EnableRunPowerDown\n
01430   *         FLASH_PDKEYR PDKEY1        LL_FLASH_EnableRunPowerDown\n
01431   *         FLASH_PDKEYR PDKEY2        LL_FLASH_EnableRunPowerDown
01432   * @retval None
01433   */
01434 __STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
01435 {
01436   /* Following values must be written consecutively to unlock the RUN_PD bit in
01437      FLASH_ACR */
01438   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
01439   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
01440   SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
01441 }
01442 
01443 /**
01444   * @brief  Disable Flash Power-down mode during run mode or Low-power run mode
01445   * @rmtoll FLASH_ACR    RUN_PD        LL_FLASH_DisableRunPowerDown\n
01446   *         FLASH_PDKEYR PDKEY1        LL_FLASH_DisableRunPowerDown\n
01447   *         FLASH_PDKEYR PDKEY2        LL_FLASH_DisableRunPowerDown
01448   * @retval None
01449   */
01450 __STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
01451 {
01452   /* Following values must be written consecutively to unlock the RUN_PD bit in
01453      FLASH_ACR */
01454   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
01455   WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
01456   CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
01457 }
01458 
01459 /**
01460   * @brief  Enable Flash Power-down mode during Sleep or Low-power sleep mode
01461   * @note Flash must not be put in power-down while a program or an erase operation
01462   *       is on-going
01463   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_EnableSleepPowerDown
01464   * @retval None
01465   */
01466 __STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
01467 {
01468   SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
01469 }
01470 
01471 /**
01472   * @brief  Disable Flash Power-down mode during Sleep or Low-power sleep mode
01473   * @rmtoll FLASH_ACR    SLEEP_PD      LL_FLASH_DisableSleepPowerDown
01474   * @retval None
01475   */
01476 __STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
01477 {
01478   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
01479 }
01480 
01481 /**
01482   * @}
01483   */
01484 
01485 /**
01486   * @}
01487   */
01488 
01489 /**
01490   * @}
01491   */
01492 
01493 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
01494 
01495 /**
01496   * @}
01497   */
01498 
01499 #ifdef __cplusplus
01500 }
01501 #endif
01502 
01503 #endif /* __STM32L4xx_LL_SYSTEM_H */
01504 
01505 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/