stm32l4xx_ll_swpmi.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_swpmi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of SWPMI LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_SWPMI_H
00040 #define __STM32L4xx_LL_SWPMI_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (SWPMI1)
00054 
00055 /** @defgroup SWPMI_LL SWPMI
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 /* Private constants ---------------------------------------------------------*/
00062 /* Private macros ------------------------------------------------------------*/
00063 #if defined(USE_FULL_LL_DRIVER)
00064 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros
00065   * @{
00066   */
00067 /**
00068   * @}
00069   */
00070 #endif /*USE_FULL_LL_DRIVER*/
00071 
00072 /* Exported types ------------------------------------------------------------*/
00073 #if defined(USE_FULL_LL_DRIVER)
00074 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure
00075   * @{
00076   */
00077 
00078 /**
00079   * @brief  SWPMI Init structures definition
00080   */
00081 typedef struct
00082 {
00083   uint32_t VoltageClass;           /*!< Specifies the SWP Voltage Class.
00084                                         This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS
00085 
00086                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */
00087 
00088   uint32_t BitRatePrescaler;       /*!< Specifies the SWPMI bitrate prescaler.
00089                                         This parameter must be a number between Min_Data=0 and Max_Data=63.
00090 
00091                                         The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER
00092 
00093                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */
00094 
00095   uint32_t TxBufferingMode;        /*!< Specifies the transmission buffering mode.
00096                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX
00097 
00098                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */
00099 
00100   uint32_t RxBufferingMode;        /*!< Specifies the reception buffering mode.
00101                                         This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX
00102 
00103                                         This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */
00104 } LL_SWPMI_InitTypeDef;
00105 
00106 /**
00107   * @}
00108   */
00109 #endif /* USE_FULL_LL_DRIVER */
00110 
00111 /* Exported constants --------------------------------------------------------*/
00112 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants
00113   * @{
00114   */
00115 
00116 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines
00117   * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function
00118   * @{
00119   */
00120 #define LL_SWPMI_ICR_CRXBFF                SWPMI_ICR_CRXBFF  /*!< Clear receive buffer full flag     */
00121 #define LL_SWPMI_ICR_CTXBEF                SWPMI_ICR_CTXBEF  /*!< Clear transmit buffer empty flag   */
00122 #define LL_SWPMI_ICR_CRXBERF               SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag       */
00123 #define LL_SWPMI_ICR_CRXOVRF               SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag   */
00124 #define LL_SWPMI_ICR_CTXUNRF               SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */
00125 #define LL_SWPMI_ICR_CTCF                  SWPMI_ICR_CTCF    /*!< Clear transfer complete flag       */
00126 #define LL_SWPMI_ICR_CSRF                  SWPMI_ICR_CSRF    /*!< Clear slave resume flag            */
00127 /**
00128   * @}
00129   */
00130 
00131 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines
00132   * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function
00133   * @{
00134   */
00135 #define LL_SWPMI_ISR_RXBFF                 SWPMI_ISR_RXBFF   /*!< Receive buffer full flag           */
00136 #define LL_SWPMI_ISR_TXBEF                 SWPMI_ISR_TXBEF   /*!< Transmit buffer empty flag         */
00137 #define LL_SWPMI_ISR_RXBERF                SWPMI_ISR_RXBERF  /*!< Receive CRC error flag             */
00138 #define LL_SWPMI_ISR_RXOVRF                SWPMI_ISR_RXOVRF  /*!< Receive overrun error flag         */
00139 #define LL_SWPMI_ISR_TXUNRF                SWPMI_ISR_TXUNRF  /*!< Transmit underrun error flag       */
00140 #define LL_SWPMI_ISR_RXNE                  SWPMI_ISR_RXNE    /*!< Receive data register not empty    */
00141 #define LL_SWPMI_ISR_TXE                   SWPMI_ISR_TXE     /*!< Transmit data register empty       */
00142 #define LL_SWPMI_ISR_TCF                   SWPMI_ISR_TCF     /*!< Transfer complete flag             */
00143 #define LL_SWPMI_ISR_SRF                   SWPMI_ISR_SRF     /*!< Slave resume flag                  */
00144 #define LL_SWPMI_ISR_SUSP                  SWPMI_ISR_SUSP    /*!< SUSPEND flag                       */
00145 #define LL_SWPMI_ISR_DEACTF                SWPMI_ISR_DEACTF  /*!< DEACTIVATED flag                   */
00146 /**
00147   * @}
00148   */
00149 
00150 /** @defgroup SWPMI_LL_EC_IT IT Defines
00151   * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions
00152   * @{
00153   */
00154 #define LL_SWPMI_IER_SRIE                  SWPMI_IER_SRIE    /*!< Slave resume interrupt enable            */
00155 #define LL_SWPMI_IER_TCIE                  SWPMI_IER_TCIE    /*!< Transmit complete interrupt enable       */
00156 #define LL_SWPMI_IER_TIE                   SWPMI_IER_TIE     /*!< Transmit interrupt enable                */
00157 #define LL_SWPMI_IER_RIE                   SWPMI_IER_RIE     /*!< Receive interrupt enable                 */
00158 #define LL_SWPMI_IER_TXUNRIE               SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */
00159 #define LL_SWPMI_IER_RXOVRIE               SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable   */
00160 #define LL_SWPMI_IER_RXBERIE               SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable       */
00161 #define LL_SWPMI_IER_TXBEIE                SWPMI_IER_TXBEIE  /*!< Transmit buffer empty interrupt enable   */
00162 #define LL_SWPMI_IER_RXBFIE                SWPMI_IER_RXBFIE  /*!< Receive buffer full interrupt enable     */
00163 /**
00164   * @}
00165   */
00166 
00167 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX
00168   * @{
00169   */
00170 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for reception */
00171 #define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE         /*!< Multi software buffermode for reception   */
00172 /**
00173   * @}
00174   */
00175 
00176 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX
00177   * @{
00178   */
00179 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for transmission */
00180 #define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE         /*!< Multi software buffermode for transmission   */
00181 /**
00182   * @}
00183   */
00184 
00185 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS
00186   * @{
00187   */
00188 #define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000)  /*!< SWPMI_IO uses directly VDD voltage to operate in class C          */
00189 #define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS          /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */
00190 /**
00191   * @}
00192   */
00193 
00194 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data
00195   * @{
00196   */
00197 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0       /*!< Get address of data register used for transmission */
00198 #define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1       /*!< Get address of data register used for reception    */
00199 /**
00200   * @}
00201   */
00202 
00203 /**
00204   * @}
00205   */
00206 
00207 /* Exported macro ------------------------------------------------------------*/
00208 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros
00209   * @{
00210   */
00211 
00212 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros
00213   * @{
00214   */
00215 
00216 /**
00217   * @brief  Write a value in SWPMI register
00218   * @param  __INSTANCE__ SWPMI Instance
00219   * @param  __REG__ Register to be written
00220   * @param  __VALUE__ Value to be written in the register
00221   * @retval None
00222   */
00223 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00224 
00225 /**
00226   * @brief  Read a value in SWPMI register
00227   * @param  __INSTANCE__ SWPMI Instance
00228   * @param  __REG__ Register to be read
00229   * @retval Register value
00230   */
00231 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00232 /**
00233   * @}
00234   */
00235 
00236 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros
00237   * @{
00238   */
00239 
00240 /**
00241   * @brief  Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)
00242   * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);
00243   * @param  __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)
00244   * @param  __FSWPCLK__ PCLK or HSI frequency (in Hz)
00245   * @retval Bitrate prescaler (BRR register)
00246   */
00247 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))
00248 
00249 /**
00250   * @}
00251   */
00252 
00253 /**
00254   * @}
00255   */
00256 
00257 /* Exported functions --------------------------------------------------------*/
00258 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions
00259   * @{
00260   */
00261 
00262 /** @defgroup SWPMI_LL_EF_Configuration Configuration
00263   * @{
00264   */
00265 
00266 /**
00267   * @brief  Set Reception buffering mode
00268   * @note   If Multi software buffer mode is chosen, RXDMA bits must also be set.
00269   * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode
00270   * @param  SWPMIx SWPMI Instance
00271   * @param  RxBufferingMode This parameter can be one of the following values:
00272   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00273   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00274   * @retval None
00275   */
00276 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)
00277 {
00278   MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);
00279 }
00280 
00281 /**
00282   * @brief  Get Reception buffering mode
00283   * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode
00284   * @param  SWPMIx SWPMI Instance
00285   * @retval Returned value can be one of the following values:
00286   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE
00287   *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI
00288   */
00289 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)
00290 {
00291   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));
00292 }
00293 
00294 /**
00295   * @brief  Set Transmission buffering mode
00296   * @note   If Multi software buffer mode is chosen, TXDMA bits must also be set.
00297   * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode
00298   * @param  SWPMIx SWPMI Instance
00299   * @param  TxBufferingMode This parameter can be one of the following values:
00300   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00301   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00302   * @retval None
00303   */
00304 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)
00305 {
00306   MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);
00307 }
00308 
00309 /**
00310   * @brief  Get Transmission buffering mode
00311   * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode
00312   * @param  SWPMIx SWPMI Instance
00313   * @retval Returned value can be one of the following values:
00314   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE
00315   *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI
00316   */
00317 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)
00318 {
00319   return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));
00320 }
00321 
00322 /**
00323   * @brief  Enable loopback mode
00324   * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback
00325   * @param  SWPMIx SWPMI Instance
00326   * @retval None
00327   */
00328 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)
00329 {
00330   SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00331 }
00332 
00333 /**
00334   * @brief  Disable loopback mode
00335   * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback
00336   * @param  SWPMIx SWPMI Instance
00337   * @retval None
00338   */
00339 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)
00340 {
00341   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);
00342 }
00343 
00344 /**
00345   * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)
00346   * @note   SWP bus stays in the ACTIVATED state as long as there is a communication
00347   *         with the slave, either in transmission or in reception. The SWP bus switches back
00348   *         to the SUSPENDED state as soon as there is no more transmission or reception
00349   *         activity, after 7 idle bits.
00350   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00351   * @param  SWPMIx SWPMI Instance
00352   * @retval None
00353   */
00354 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)
00355 {
00356   /* In order to activate SWP again, the software must clear DEACT bit*/
00357   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00358 
00359   /* Set SWACT bit */
00360   SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00361 }
00362 
00363 /**
00364   * @brief  Check if Single wire protocol bus is in ACTIVATED state.
00365   * @rmtoll CR           SWPACT        LL_SWPMI_Activate
00366   * @param  SWPMIx SWPMI Instance
00367   * @retval State of bit (1 or 0).
00368   */
00369 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)
00370 {
00371   return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT));
00372 }
00373 
00374 /**
00375   * @brief  Deactivate immediately Single wire protocol bus (immediate transition to
00376   *         DEACTIVATED state)
00377   * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate
00378   * @param  SWPMIx SWPMI Instance
00379   * @retval None
00380   */
00381 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)
00382 {
00383   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);
00384 }
00385 
00386 /**
00387   * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED
00388   *         state if no resume from slave)
00389   * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation
00390   * @param  SWPMIx SWPMI Instance
00391   * @retval None
00392   */
00393 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)
00394 {
00395   SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);
00396 }
00397 
00398 /**
00399   * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)
00400   * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler
00401   * @param  SWPMIx SWPMI Instance
00402   * @param  BitRatePrescaler A number between Min_Data=0 and Max_Data=63
00403   * @retval None
00404   */
00405 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)
00406 {
00407   WRITE_REG(SWPMIx->BRR, BitRatePrescaler);
00408 }
00409 
00410 /**
00411   * @brief  Get Bitrate prescaler
00412   * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler
00413   * @param  SWPMIx SWPMI Instance
00414   * @retval A number between Min_Data=0 and Max_Data=63
00415   */
00416 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)
00417 {
00418   return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));
00419 }
00420 
00421 /**
00422   * @brief  Set SWP Voltage Class
00423   * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass
00424   * @param  SWPMIx SWPMI Instance
00425   * @param  VoltageClass This parameter can be one of the following values:
00426   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00427   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00428   * @retval None
00429   */
00430 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)
00431 {
00432   MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);
00433 }
00434 
00435 /**
00436   * @brief  Get SWP Voltage Class
00437   * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass
00438   * @param  SWPMIx SWPMI Instance
00439   * @retval Returned value can be one of the following values:
00440   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C
00441   *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B
00442   */
00443 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)
00444 {
00445   return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));
00446 }
00447 
00448 /**
00449   * @}
00450   */
00451 
00452 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management
00453   * @{
00454   */
00455 
00456 /**
00457   * @brief  Check if the last word of the frame under reception has arrived in SWPMI_RDR.
00458   * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF
00459   * @param  SWPMIx SWPMI Instance
00460   * @retval State of bit (1 or 0).
00461   */
00462 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00463 {
00464   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF));
00465 }
00466 
00467 /**
00468   * @brief  Check if Frame transmission buffer has been emptied
00469   * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE
00470   * @param  SWPMIx SWPMI Instance
00471   * @retval State of bit (1 or 0).
00472   */
00473 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00474 {
00475   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF));
00476 }
00477 
00478 /**
00479   * @brief  Check if CRC error in reception has been detected
00480   * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER
00481   * @param  SWPMIx SWPMI Instance
00482   * @retval State of bit (1 or 0).
00483   */
00484 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00485 {
00486   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF));
00487 }
00488 
00489 /**
00490   * @brief  Check if Overrun in reception has been detected
00491   * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR
00492   * @param  SWPMIx SWPMI Instance
00493   * @retval State of bit (1 or 0).
00494   */
00495 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00496 {
00497   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF));
00498 }
00499 
00500 /**
00501   * @brief  Check if underrun error in transmission has been detected
00502   * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR
00503   * @param  SWPMIx SWPMI Instance
00504   * @retval State of bit (1 or 0).
00505   */
00506 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00507 {
00508   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF));
00509 }
00510 
00511 /**
00512   * @brief  Check if Receive data register not empty (it means that Received data is ready
00513   *         to be read in the SWPMI_RDR register)
00514   * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE
00515   * @param  SWPMIx SWPMI Instance
00516   * @retval State of bit (1 or 0).
00517   */
00518 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)
00519 {
00520   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE));
00521 }
00522 
00523 /**
00524   * @brief  Check if Transmit data register is empty (it means that Data written in transmit
00525   *         data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)
00526   * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE
00527   * @param  SWPMIx SWPMI Instance
00528   * @retval State of bit (1 or 0).
00529   */
00530 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)
00531 {
00532   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE));
00533 }
00534 
00535 /**
00536   * @brief  Check if Both transmission and reception are completed and SWP is switched to
00537   *         the SUSPENDED state
00538   * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC
00539   * @param  SWPMIx SWPMI Instance
00540   * @retval State of bit (1 or 0).
00541   */
00542 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)
00543 {
00544   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF));
00545 }
00546 
00547 /**
00548   * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED
00549   *         state
00550   * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR
00551   * @param  SWPMIx SWPMI Instance
00552   * @retval State of bit (1 or 0).
00553   */
00554 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)
00555 {
00556   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF));
00557 }
00558 
00559 /**
00560   * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state
00561   * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP
00562   * @param  SWPMIx SWPMI Instance
00563   * @retval State of bit (1 or 0).
00564   */
00565 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)
00566 {
00567   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP));
00568 }
00569 
00570 /**
00571   * @brief  Check if SWP bus is in DEACTIVATED state
00572   * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT
00573   * @param  SWPMIx SWPMI Instance
00574   * @retval State of bit (1 or 0).
00575   */
00576 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)
00577 {
00578   return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF));
00579 }
00580 
00581 /**
00582   * @brief  Clear receive buffer full flag
00583   * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF
00584   * @param  SWPMIx SWPMI Instance
00585   * @retval None
00586   */
00587 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)
00588 {
00589   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);
00590 }
00591 
00592 /**
00593   * @brief  Clear transmit buffer empty flag
00594   * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE
00595   * @param  SWPMIx SWPMI Instance
00596   * @retval None
00597   */
00598 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)
00599 {
00600   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);
00601 }
00602 
00603 /**
00604   * @brief  Clear receive CRC error flag
00605   * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER
00606   * @param  SWPMIx SWPMI Instance
00607   * @retval None
00608   */
00609 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)
00610 {
00611   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);
00612 }
00613 
00614 /**
00615   * @brief  Clear receive overrun error flag
00616   * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR
00617   * @param  SWPMIx SWPMI Instance
00618   * @retval None
00619   */
00620 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)
00621 {
00622   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);
00623 }
00624 
00625 /**
00626   * @brief  Clear transmit underrun error flag
00627   * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR
00628   * @param  SWPMIx SWPMI Instance
00629   * @retval None
00630   */
00631 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)
00632 {
00633   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);
00634 }
00635 
00636 /**
00637   * @brief  Clear transfer complete flag
00638   * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC
00639   * @param  SWPMIx SWPMI Instance
00640   * @retval None
00641   */
00642 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)
00643 {
00644   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);
00645 }
00646 
00647 /**
00648   * @brief  Clear slave resume flag
00649   * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR
00650   * @param  SWPMIx SWPMI Instance
00651   * @retval None
00652   */
00653 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)
00654 {
00655   WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);
00656 }
00657 
00658 /**
00659   * @}
00660   */
00661 
00662 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management
00663   * @{
00664   */
00665 
00666 /**
00667   * @brief  Enable Slave resume interrupt
00668   * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR
00669   * @param  SWPMIx SWPMI Instance
00670   * @retval None
00671   */
00672 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)
00673 {
00674   SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00675 }
00676 
00677 /**
00678   * @brief  Enable Transmit complete interrupt
00679   * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC
00680   * @param  SWPMIx SWPMI Instance
00681   * @retval None
00682   */
00683 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)
00684 {
00685   SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00686 }
00687 
00688 /**
00689   * @brief  Enable Transmit interrupt
00690   * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX
00691   * @param  SWPMIx SWPMI Instance
00692   * @retval None
00693   */
00694 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)
00695 {
00696   SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00697 }
00698 
00699 /**
00700   * @brief  Enable Receive interrupt
00701   * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX
00702   * @param  SWPMIx SWPMI Instance
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)
00706 {
00707   SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00708 }
00709 
00710 /**
00711   * @brief  Enable Transmit underrun error interrupt
00712   * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR
00713   * @param  SWPMIx SWPMI Instance
00714   * @retval None
00715   */
00716 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00717 {
00718   SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00719 }
00720 
00721 /**
00722   * @brief  Enable Receive overrun error interrupt
00723   * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR
00724   * @param  SWPMIx SWPMI Instance
00725   * @retval None
00726   */
00727 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00728 {
00729   SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00730 }
00731 
00732 /**
00733   * @brief  Enable Receive CRC error interrupt
00734   * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER
00735   * @param  SWPMIx SWPMI Instance
00736   * @retval None
00737   */
00738 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00739 {
00740   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00741 }
00742 
00743 /**
00744   * @brief  Enable Transmit buffer empty interrupt
00745   * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE
00746   * @param  SWPMIx SWPMI Instance
00747   * @retval None
00748   */
00749 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00750 {
00751   SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00752 }
00753 
00754 /**
00755   * @brief  Enable Receive buffer full interrupt
00756   * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF
00757   * @param  SWPMIx SWPMI Instance
00758   * @retval None
00759   */
00760 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00761 {
00762   SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00763 }
00764 
00765 /**
00766   * @brief  Disable Slave resume interrupt
00767   * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR
00768   * @param  SWPMIx SWPMI Instance
00769   * @retval None
00770   */
00771 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)
00772 {
00773   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);
00774 }
00775 
00776 /**
00777   * @brief  Disable Transmit complete interrupt
00778   * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC
00779   * @param  SWPMIx SWPMI Instance
00780   * @retval None
00781   */
00782 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)
00783 {
00784   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);
00785 }
00786 
00787 /**
00788   * @brief  Disable Transmit interrupt
00789   * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX
00790   * @param  SWPMIx SWPMI Instance
00791   * @retval None
00792   */
00793 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)
00794 {
00795   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);
00796 }
00797 
00798 /**
00799   * @brief  Disable Receive interrupt
00800   * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX
00801   * @param  SWPMIx SWPMI Instance
00802   * @retval None
00803   */
00804 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)
00805 {
00806   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);
00807 }
00808 
00809 /**
00810   * @brief  Disable Transmit underrun error interrupt
00811   * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR
00812   * @param  SWPMIx SWPMI Instance
00813   * @retval None
00814   */
00815 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00816 {
00817   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);
00818 }
00819 
00820 /**
00821   * @brief  Disable Receive overrun error interrupt
00822   * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR
00823   * @param  SWPMIx SWPMI Instance
00824   * @retval None
00825   */
00826 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00827 {
00828   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);
00829 }
00830 
00831 /**
00832   * @brief  Disable Receive CRC error interrupt
00833   * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER
00834   * @param  SWPMIx SWPMI Instance
00835   * @retval None
00836   */
00837 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)
00838 {
00839   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);
00840 }
00841 
00842 /**
00843   * @brief  Disable Transmit buffer empty interrupt
00844   * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE
00845   * @param  SWPMIx SWPMI Instance
00846   * @retval None
00847   */
00848 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)
00849 {
00850   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);
00851 }
00852 
00853 /**
00854   * @brief  Disable Receive buffer full interrupt
00855   * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF
00856   * @param  SWPMIx SWPMI Instance
00857   * @retval None
00858   */
00859 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)
00860 {
00861   CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);
00862 }
00863 
00864 /**
00865   * @brief  Check if Slave resume interrupt is enabled
00866   * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR
00867   * @param  SWPMIx SWPMI Instance
00868   * @retval State of bit (1 or 0).
00869   */
00870 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)
00871 {
00872   return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE));
00873 }
00874 
00875 /**
00876   * @brief  Check if Transmit complete interrupt is enabled
00877   * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC
00878   * @param  SWPMIx SWPMI Instance
00879   * @retval State of bit (1 or 0).
00880   */
00881 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)
00882 {
00883   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE));
00884 }
00885 
00886 /**
00887   * @brief  Check if Transmit interrupt is enabled
00888   * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX
00889   * @param  SWPMIx SWPMI Instance
00890   * @retval State of bit (1 or 0).
00891   */
00892 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)
00893 {
00894   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE));
00895 }
00896 
00897 /**
00898   * @brief  Check if Receive interrupt is enabled
00899   * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX
00900   * @param  SWPMIx SWPMI Instance
00901   * @retval State of bit (1 or 0).
00902   */
00903 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)
00904 {
00905   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE));
00906 }
00907 
00908 /**
00909   * @brief  Check if Transmit underrun error interrupt is enabled
00910   * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR
00911   * @param  SWPMIx SWPMI Instance
00912   * @retval State of bit (1 or 0).
00913   */
00914 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)
00915 {
00916   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE));
00917 }
00918 
00919 /**
00920   * @brief  Check if Receive overrun error interrupt is enabled
00921   * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR
00922   * @param  SWPMIx SWPMI Instance
00923   * @retval State of bit (1 or 0).
00924   */
00925 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)
00926 {
00927   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE));
00928 }
00929 
00930 /**
00931   * @brief  Check if Receive CRC error interrupt is enabled
00932   * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER
00933   * @param  SWPMIx SWPMI Instance
00934   * @retval State of bit (1 or 0).
00935   */
00936 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)
00937 {
00938   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE));
00939 }
00940 
00941 /**
00942   * @brief  Check if Transmit buffer empty interrupt is enabled
00943   * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE
00944   * @param  SWPMIx SWPMI Instance
00945   * @retval State of bit (1 or 0).
00946   */
00947 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)
00948 {
00949   return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE));
00950 }
00951 
00952 /**
00953   * @brief  Check if Receive buffer full interrupt is enabled
00954   * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF
00955   * @param  SWPMIx SWPMI Instance
00956   * @retval State of bit (1 or 0).
00957   */
00958 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)
00959 {
00960   return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE));
00961 }
00962 
00963 /**
00964   * @}
00965   */
00966 
00967 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management
00968   * @{
00969   */
00970 
00971 /**
00972   * @brief  Enable DMA mode for reception
00973   * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX
00974   * @param  SWPMIx SWPMI Instance
00975   * @retval None
00976   */
00977 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00978 {
00979   SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
00980 }
00981 
00982 /**
00983   * @brief  Disable DMA mode for reception
00984   * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX
00985   * @param  SWPMIx SWPMI Instance
00986   * @retval None
00987   */
00988 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)
00989 {
00990   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);
00991 }
00992 
00993 /**
00994   * @brief  Check if DMA mode for reception is enabled
00995   * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX
00996   * @param  SWPMIx SWPMI Instance
00997   * @retval State of bit (1 or 0).
00998   */
00999 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)
01000 {
01001   return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA));
01002 }
01003 
01004 /**
01005   * @brief  Enable DMA mode for transmission
01006   * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX
01007   * @param  SWPMIx SWPMI Instance
01008   * @retval None
01009   */
01010 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01011 {
01012   SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
01013 }
01014 
01015 /**
01016   * @brief  Disable DMA mode for transmission
01017   * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX
01018   * @param  SWPMIx SWPMI Instance
01019   * @retval None
01020   */
01021 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01022 {
01023   CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);
01024 }
01025 
01026 /**
01027   * @brief  Check if DMA mode for transmission is enabled
01028   * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX
01029   * @param  SWPMIx SWPMI Instance
01030   * @retval State of bit (1 or 0).
01031   */
01032 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)
01033 {
01034   return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA));
01035 }
01036 
01037 /**
01038   * @brief  Get the data register address used for DMA transfer
01039   * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n
01040   *         RDR          RD            LL_SWPMI_DMA_GetRegAddr
01041   * @param  SWPMIx SWPMI Instance
01042   * @param  Direction This parameter can be one of the following values:
01043   *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT
01044   *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE
01045   * @retval Address of data register
01046   */
01047 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)
01048 {
01049   register uint32_t data_reg_addr = 0;
01050 
01051   if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)
01052   {
01053     /* return address of TDR register */
01054     data_reg_addr = (uint32_t)&(SWPMIx->TDR);
01055   }
01056   else
01057   {
01058     /* return address of RDR register */
01059     data_reg_addr = (uint32_t)&(SWPMIx->RDR);
01060   }
01061 
01062   return data_reg_addr;
01063 }
01064 
01065 /**
01066   * @}
01067   */
01068 
01069 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management
01070   * @{
01071   */
01072 
01073 /**
01074   * @brief  Retrieve number of data bytes present in payload of received frame
01075   * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength
01076   * @param  SWPMIx SWPMI Instance
01077   * @retval Value between Min_Data=0x00 and Max_Data=0x1F
01078   */
01079 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)
01080 {
01081   return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));
01082 }
01083 
01084 /**
01085   * @brief  Transmit Data Register
01086   * @rmtoll TDR          TD            LL_SWPMI_TransmitData32
01087   * @param  SWPMIx SWPMI Instance
01088   * @param  TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01089   * @retval None
01090   */
01091 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)
01092 {
01093   WRITE_REG(SWPMIx->TDR, TxData);
01094 }
01095 
01096 /**
01097   * @brief  Receive Data Register
01098   * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32
01099   * @param  SWPMIx SWPMI Instance
01100   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
01101   */
01102 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)
01103 {
01104   return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));
01105 }
01106 
01107 /**
01108   * @brief  Enable SWP Transceiver Bypass
01109   * @note   The external interface for SWPMI is SWPMI_IO
01110   *         (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)
01111   * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass
01112   * @param  SWPMIx SWPMI Instance
01113   * @retval None
01114   */
01115 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)
01116 {
01117   CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01118 }
01119 
01120 /**
01121   * @brief  Disable SWP Transceiver Bypass
01122   * @note   SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate
01123   *         function on GPIOs. This configuration is selected to connect an external transceiver
01124   * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass
01125   * @param  SWPMIx SWPMI Instance
01126   * @retval None
01127   */
01128 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)
01129 {
01130   SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);
01131 }
01132 
01133 /**
01134   * @}
01135   */
01136 
01137 #if defined(USE_FULL_LL_DRIVER)
01138 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions
01139   * @{
01140   */
01141 
01142 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);
01143 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
01144 void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);
01145 
01146 /**
01147   * @}
01148   */
01149 #endif /*USE_FULL_LL_DRIVER*/
01150 
01151 /**
01152   * @}
01153   */
01154 
01155 /**
01156   * @}
01157   */
01158 
01159 #endif /* defined (SWPMI1) */
01160 
01161 /**
01162   * @}
01163   */
01164 
01165 #ifdef __cplusplus
01166 }
01167 #endif
01168 
01169 #endif /* __STM32L4xx_LL_SWPMI_H */
01170 
01171 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/