stm32l4xx_ll_i2c.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_i2c.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of I2C LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_I2C_H
00040 #define __STM32L4xx_LL_I2C_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
00054 
00055 /** @defgroup I2C_LL I2C
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
00064   * @{
00065   */
00066 /* Defines used for the bit position in the register and perform offsets */
00067 #define I2C_POSITION_CR1_DNF            (uint32_t)POSITION_VAL(I2C_CR1_DNF)
00068 #define I2C_POSITION_CR2_NBYTES         (uint32_t)POSITION_VAL(I2C_CR2_NBYTES)
00069 #define I2C_POSITION_TIMINGR_PRESC      (uint32_t)POSITION_VAL(I2C_TIMINGR_PRESC)
00070 #define I2C_POSITION_TIMINGR_SCLDEL     (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLDEL)
00071 #define I2C_POSITION_TIMINGR_SDADEL     (uint32_t)POSITION_VAL(I2C_TIMINGR_SDADEL)
00072 #define I2C_POSITION_TIMINGR_SCLH       (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLH)
00073 #define I2C_POSITION_TIMINGR_SCLL       (uint32_t)POSITION_VAL(I2C_TIMINGR_SCLL)
00074 #define I2C_POSITION_ISR_ADDCODE        (uint32_t)POSITION_VAL(I2C_ISR_ADDCODE)
00075 #define I2C_POSITION_TIMEOUTR_TIMEOUTB  (uint32_t)POSITION_VAL(I2C_TIMEOUTR_TIMEOUTB)
00076 /**
00077   * @}
00078   */
00079 
00080 /* Private macros ------------------------------------------------------------*/
00081 #if defined(USE_FULL_LL_DRIVER)
00082 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
00083   * @{
00084   */
00085 /**
00086   * @}
00087   */
00088 #endif /*USE_FULL_LL_DRIVER*/
00089 
00090 /* Exported types ------------------------------------------------------------*/
00091 #if defined(USE_FULL_LL_DRIVER)
00092 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
00093   * @{
00094   */
00095 typedef struct
00096 {
00097   uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.
00098                                      This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
00099 
00100                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
00101 
00102   uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
00103                                      This parameter must be set by referring to the STM32CubeMX Tool and
00104                                      the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
00105 
00106                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
00107 
00108   uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.
00109                                      This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
00110 
00111                                      This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
00112 
00113   uint32_t DigitalFilter;       /*!< Configures the digital noise filter.
00114                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
00115 
00116                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
00117 
00118   uint32_t OwnAddress1;         /*!< Specifies the device own address 1.
00119                                      This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
00120 
00121                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00122 
00123   uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
00124                                      This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
00125 
00126                                      This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
00127 
00128   uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).
00129                                      This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
00130 
00131                                      This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
00132 } LL_I2C_InitTypeDef;
00133 /**
00134   * @}
00135   */
00136 #endif /*USE_FULL_LL_DRIVER*/
00137 
00138 /* Exported constants --------------------------------------------------------*/
00139 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
00140   * @{
00141   */
00142 
00143 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
00144   * @brief    Flags defines which can be used with LL_I2C_WriteReg function
00145   * @{
00146   */
00147 #define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */
00148 #define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */
00149 #define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */
00150 #define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */
00151 #define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */
00152 #define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */
00153 #define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */
00154 #define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */
00155 #define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */
00156 /**
00157   * @}
00158   */
00159 
00160 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
00161   * @brief    Flags defines which can be used with LL_I2C_ReadReg function
00162   * @{
00163   */
00164 #define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */
00165 #define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */
00166 #define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */
00167 #define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */
00168 #define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */
00169 #define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */
00170 #define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */
00171 #define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */
00172 #define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */
00173 #define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */
00174 #define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */
00175 #define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */
00176 #define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */
00177 #define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */
00178 #define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */
00179 /**
00180   * @}
00181   */
00182 
00183 /** @defgroup I2C_LL_EC_IT IT Defines
00184   * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions
00185   * @{
00186   */
00187 #define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */
00188 #define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */
00189 #define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */
00190 #define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */
00191 #define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */
00192 #define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */
00193 #define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */
00194 /**
00195   * @}
00196   */
00197 
00198 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
00199   * @{
00200   */
00201 #define LL_I2C_MODE_I2C                    ((uint32_t)0x00000000U)  /*!< I2C Master or Slave mode                                    */
00202 #define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */
00203 #define LL_I2C_MODE_SMBUS_DEVICE           ((uint32_t)0x00000000U)  /*!< SMBus Device default mode (Default address not acknowledge) */
00204 #define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */
00205 /**
00206   * @}
00207   */
00208 
00209 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
00210   * @{
00211   */
00212 #define LL_I2C_ANALOGFILTER_ENABLE          ((uint32_t)0x00000000U) /*!< Analog filter is enabled.  */
00213 #define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */
00214 /**
00215   * @}
00216   */
00217 
00218 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
00219   * @{
00220   */
00221 #define LL_I2C_ADDRESSING_MODE_7BIT         ((uint32_t) 0x00000000U) /*!< Master operates in 7-bit addressing mode. */
00222 #define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/
00223 /**
00224   * @}
00225   */
00226 
00227 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
00228   * @{
00229   */
00230 #define LL_I2C_OWNADDRESS1_7BIT             ((uint32_t)0x00000000U) /*!< Own address 1 is a 7-bit address. */
00231 #define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/
00232 /**
00233   * @}
00234   */
00235 
00236 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
00237   * @{
00238   */
00239 #define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */
00240 #define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */
00241 #define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */
00242 #define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */
00243 #define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */
00244 #define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */
00245 #define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */
00246 #define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/
00247 /**
00248   * @}
00249   */
00250 
00251 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
00252   * @{
00253   */
00254 #define LL_I2C_ACK                          ((uint32_t) 0x00000000U) /*!< ACK is sent after current received byte. */
00255 #define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/
00256 /**
00257   * @}
00258   */
00259 
00260 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
00261   * @{
00262   */
00263 #define LL_I2C_ADDRSLAVE_7BIT               ((uint32_t)0x00000000U)  /*!< Slave Address in 7-bit. */
00264 #define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/
00265 /**
00266   * @}
00267   */
00268 
00269 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
00270   * @{
00271   */
00272 #define LL_I2C_REQUEST_WRITE                ((uint32_t)0x00000000U)  /*!< Master request a write transfer. */
00273 #define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */
00274 /**
00275   * @}
00276   */
00277 
00278 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
00279   * @{
00280   */
00281 #define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */
00282 #define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */
00283 #define LL_I2C_MODE_SOFTEND                 ((uint32_t)0x00000000U)                             /*!< Enable I2C Software end mode with no HW PEC comparison.   */
00284 #define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00285 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00286 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00287 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */
00288 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */
00289 /**
00290   * @}
00291   */
00292 
00293 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
00294   * @{
00295   */
00296 #define LL_I2C_GENERATE_NOSTARTSTOP         ((uint32_t)0x00000000U)                                      /*!< Don't Generate Stop and Start condition.                */
00297 #define LL_I2C_GENERATE_STOP                I2C_CR2_STOP                                                 /*!< Generate Stop condition (Size should be set to 0).      */
00298 #define LL_I2C_GENERATE_START_READ          (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */
00299 #define LL_I2C_GENERATE_START_WRITE         I2C_CR2_START                                                /*!< Generate Start for write request.                       */
00300 #define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */
00301 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE  I2C_CR2_START                                                /*!< Generate Restart for write request, slave 7Bit address. */
00302 #define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
00303 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START                                                /*!< Generate Restart for write request, slave 10Bit address.*/
00304 /**
00305   * @}
00306   */
00307 
00308 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
00309   * @{
00310   */
00311 #define LL_I2C_DIRECTION_WRITE              ((uint32_t)0x00000000U)  /*!< Write transfer request by master, slave enters receiver mode.  */
00312 #define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/
00313 /**
00314   * @}
00315   */
00316 
00317 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
00318   * @{
00319   */
00320 #define LL_I2C_DMA_REG_DATA_TRANSMIT        ((uint32_t)0x00000000U)  /*!< Get address of data register used for transmission */
00321 #define LL_I2C_DMA_REG_DATA_RECEIVE         ((uint32_t)0x00000001U)  /*!< Get address of data register used for reception */
00322 /**
00323   * @}
00324   */
00325 
00326 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
00327   * @{
00328   */
00329 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW  ((uint32_t) 0x00000000U) /*!< TimeoutA is used to detect SCL low level timeout.              */
00330 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
00331 /**
00332   * @}
00333   */
00334 
00335 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
00336   * @{
00337   */
00338 #define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */
00339 #define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */
00340 #define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
00341 /**
00342   * @}
00343   */
00344 
00345 /**
00346   * @}
00347   */
00348 
00349 /* Exported macro ------------------------------------------------------------*/
00350 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
00351   * @{
00352   */
00353 
00354 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
00355   * @{
00356   */
00357 
00358 /**
00359   * @brief  Write a value in I2C register
00360   * @param  __INSTANCE__ I2C Instance
00361   * @param  __REG__ Register to be written
00362   * @param  __VALUE__ Value to be written in the register
00363   * @retval None
00364   */
00365 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00366 
00367 /**
00368   * @brief  Read a value in I2C register
00369   * @param  __INSTANCE__ I2C Instance
00370   * @param  __REG__ Register to be read
00371   * @retval Register value
00372   */
00373 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00374 /**
00375   * @}
00376   */
00377 
00378 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
00379   * @{
00380   */
00381 /**
00382   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00383   * @param  __PRESCALER__ This parameter must be a value between  0 and 0xF.
00384   * @param  __DATA_SETUP_TIME__ This parameter must be a value between 0 and 0xF. (tscldel = (SCLDEL+1)xtpresc)
00385   * @param  __DATA_HOLD_TIME__ This parameter must be a value between 0 and 0xF. (tsdadel = SDADELxtpresc)
00386   * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between 0 and 0xFF. (tsclh = (SCLH+1)xtpresc)
00387   * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  0 and 0xFF. (tscll = (SCLL+1)xtpresc)
00388   * @retval Value between 0 and 0xFFFFFFFF
00389   */
00390 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \
00391         ((((uint32_t)(__PRESCALER__)         << I2C_POSITION_TIMINGR_PRESC)  & I2C_TIMINGR_PRESC)   | \
00392          (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL)  | \
00393          (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL)  | \
00394          (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH)   & I2C_TIMINGR_SCLH)    | \
00395          (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_POSITION_TIMINGR_SCLL)   & I2C_TIMINGR_SCLL))
00396 /**
00397   * @}
00398   */
00399 
00400 /**
00401   * @}
00402   */
00403 
00404 /* Exported functions --------------------------------------------------------*/
00405 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
00406   * @{
00407   */
00408 
00409 /** @defgroup I2C_LL_EF_Configuration Configuration
00410   * @{
00411   */
00412 
00413 /**
00414   * @brief  Enable I2C peripheral (PE = 1).
00415   * @rmtoll CR1          PE            LL_I2C_Enable
00416   * @param  I2Cx I2C Instance.
00417   * @retval None
00418   */
00419 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
00420 {
00421   SET_BIT(I2Cx->CR1, I2C_CR1_PE);
00422 }
00423 
00424 /**
00425   * @brief  Disable I2C peripheral (PE = 0).
00426   * @note   When PE = 0, the I2C SCL and SDA lines are released.
00427   *         Internal state machines and status bits are put back to their reset value.
00428   *         When cleared, PE must be kept low for at least 3 APB clock cycles.
00429   * @rmtoll CR1          PE            LL_I2C_Disable
00430   * @param  I2Cx I2C Instance.
00431   * @retval None
00432   */
00433 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
00434 {
00435   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
00436 }
00437 
00438 /**
00439   * @brief  Check if the I2C peripheral is enabled or disabled.
00440   * @rmtoll CR1          PE            LL_I2C_IsEnabled
00441   * @param  I2Cx I2C Instance.
00442   * @retval State of bit (1 or 0).
00443   */
00444 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
00445 {
00446   return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
00447 }
00448 
00449 /**
00450   * @brief  Configure Noise Filters (Analog and Digital).
00451   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00452   *         The filters can only be programmed when the I2C is disabled (PE = 0).
00453   * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n
00454   *         CR1          DNF           LL_I2C_ConfigFilters
00455   * @param  I2Cx I2C Instance.
00456   * @param  AnalogFilter This parameter can be one of the following values:
00457   *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE
00458   *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE
00459   * @param  DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00460   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00461   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00462   * @retval None
00463   */
00464 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
00465 {
00466   MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_POSITION_CR1_DNF));
00467 }
00468 
00469 /**
00470   * @brief  Configure Digital Noise Filter.
00471   * @note   If the analog filter is also enabled, the digital filter is added to analog filter.
00472   *         This filter can only be programmed when the I2C is disabled (PE = 0).
00473   * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter
00474   * @param  I2Cx I2C Instance.
00475   * @param  DigitalFilter This parameter must be a value between 0x00 (Digital filter disabled) and 0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
00476   *         This parameter is used to configure the digital noise filter on SDA and SCL input.
00477   *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
00478   * @retval None
00479   */
00480 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
00481 {
00482   MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
00483 }
00484 
00485 /**
00486   * @brief  Get the current Digital Noise Filter configuration.
00487   * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter
00488   * @param  I2Cx I2C Instance.
00489   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00490   */
00491 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
00492 {
00493   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
00494 }
00495 
00496 /**
00497   * @brief  Enable Analog Noise Filter.
00498   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00499   * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter
00500   * @param  I2Cx I2C Instance.
00501   * @retval None
00502   */
00503 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
00504 {
00505   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00506 }
00507 
00508 /**
00509   * @brief  Disable Analog Noise Filter.
00510   * @note   This filter can only be programmed when the I2C is disabled (PE = 0).
00511   * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter
00512   * @param  I2Cx I2C Instance.
00513   * @retval None
00514   */
00515 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
00516 {
00517   SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
00518 }
00519 
00520 /**
00521   * @brief  Check if Analog Noise Filter is enabled or disabled.
00522   * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter
00523   * @param  I2Cx I2C Instance.
00524   * @retval State of bit (1 or 0).
00525   */
00526 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
00527 {
00528   return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
00529 }
00530 
00531 /**
00532   * @brief  Enable DMA transmission requests.
00533   * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX
00534   * @param  I2Cx I2C Instance.
00535   * @retval None
00536   */
00537 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
00538 {
00539   SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00540 }
00541 
00542 /**
00543   * @brief  Disable DMA transmission requests.
00544   * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX
00545   * @param  I2Cx I2C Instance.
00546   * @retval None
00547   */
00548 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
00549 {
00550   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
00551 }
00552 
00553 /**
00554   * @brief  Check if DMA transmission requests are enabled or disabled.
00555   * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX
00556   * @param  I2Cx I2C Instance.
00557   * @retval State of bit (1 or 0).
00558   */
00559 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
00560 {
00561   return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
00562 }
00563 
00564 /**
00565   * @brief  Enable DMA reception requests.
00566   * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX
00567   * @param  I2Cx I2C Instance.
00568   * @retval None
00569   */
00570 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
00571 {
00572   SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00573 }
00574 
00575 /**
00576   * @brief  Disable DMA reception requests.
00577   * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX
00578   * @param  I2Cx I2C Instance.
00579   * @retval None
00580   */
00581 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
00582 {
00583   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
00584 }
00585 
00586 /**
00587   * @brief  Check if DMA reception requests are enabled or disabled.
00588   * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX
00589   * @param  I2Cx I2C Instance.
00590   * @retval State of bit (1 or 0).
00591   */
00592 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
00593 {
00594   return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
00595 }
00596 
00597 /**
00598   * @brief  Get the data register address used for DMA transfer
00599   * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n
00600   *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr
00601   * @param  I2Cx I2C Instance
00602   * @param  Direction This parameter can be one of the following values:
00603   *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
00604   *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
00605   * @retval Address of data register
00606   */
00607 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
00608 {
00609   register uint32_t data_reg_addr = 0U;
00610 
00611   if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
00612   {
00613     /* return address of TXDR register */
00614     data_reg_addr = (uint32_t) & (I2Cx->TXDR);
00615   }
00616   else
00617   {
00618     /* return address of RXDR register */
00619     data_reg_addr = (uint32_t) & (I2Cx->RXDR);
00620   }
00621 
00622   return data_reg_addr;
00623 }
00624 
00625 /**
00626   * @brief  Enable Clock stretching.
00627   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00628   * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching
00629   * @param  I2Cx I2C Instance.
00630   * @retval None
00631   */
00632 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
00633 {
00634   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00635 }
00636 
00637 /**
00638   * @brief  Disable Clock stretching.
00639   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00640   * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching
00641   * @param  I2Cx I2C Instance.
00642   * @retval None
00643   */
00644 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
00645 {
00646   SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
00647 }
00648 
00649 /**
00650   * @brief  Check if Clock stretching is enabled or disabled.
00651   * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching
00652   * @param  I2Cx I2C Instance.
00653   * @retval State of bit (1 or 0).
00654   */
00655 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
00656 {
00657   return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
00658 }
00659 
00660 /**
00661   * @brief  Enable hardware byte control in slave mode.
00662   * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl
00663   * @param  I2Cx I2C Instance.
00664   * @retval None
00665   */
00666 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
00667 {
00668   SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
00669 }
00670 
00671 /**
00672   * @brief  Disable hardware byte control in slave mode.
00673   * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl
00674   * @param  I2Cx I2C Instance.
00675   * @retval None
00676   */
00677 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
00678 {
00679   CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
00680 }
00681 
00682 /**
00683   * @brief  Check if hardware byte control in slave mode is enabled or disabled.
00684   * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl
00685   * @param  I2Cx I2C Instance.
00686   * @retval State of bit (1 or 0).
00687   */
00688 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
00689 {
00690   return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
00691 }
00692 
00693 /**
00694   * @brief  Enable Wakeup from STOP.
00695   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00696   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00697   * @note   This bit can only be programmed when Digital Filter is disabled.
00698   * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop
00699   * @param  I2Cx I2C Instance.
00700   * @retval None
00701   */
00702 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
00703 {
00704   SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00705 }
00706 
00707 /**
00708   * @brief  Disable Wakeup from STOP.
00709   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00710   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00711   * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop
00712   * @param  I2Cx I2C Instance.
00713   * @retval None
00714   */
00715 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
00716 {
00717   CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
00718 }
00719 
00720 /**
00721   * @brief  Check if Wakeup from STOP is enabled or disabled.
00722   * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
00723   *         WakeUpFromStop feature is supported by the I2Cx Instance.
00724   * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop
00725   * @param  I2Cx I2C Instance.
00726   * @retval State of bit (1 or 0).
00727   */
00728 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
00729 {
00730   return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
00731 }
00732 
00733 /**
00734   * @brief  Enable General Call.
00735   * @note   When enabled the Address 0x00 is ACKed.
00736   * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall
00737   * @param  I2Cx I2C Instance.
00738   * @retval None
00739   */
00740 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
00741 {
00742   SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00743 }
00744 
00745 /**
00746   * @brief  Disable General Call.
00747   * @note   When disabled the Address 0x00 is NACKed.
00748   * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall
00749   * @param  I2Cx I2C Instance.
00750   * @retval None
00751   */
00752 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
00753 {
00754   CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
00755 }
00756 
00757 /**
00758   * @brief  Check if General Call is enabled or disabled.
00759   * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall
00760   * @param  I2Cx I2C Instance.
00761   * @retval State of bit (1 or 0).
00762   */
00763 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
00764 {
00765   return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
00766 }
00767 
00768 /**
00769   * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.
00770   * @note   Changing this bit is not allowed, when the START bit is set.
00771   * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode
00772   * @param  I2Cx I2C Instance.
00773   * @param  AddressingMode This parameter can be one of the following values:
00774   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00775   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00776   * @retval None
00777   */
00778 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
00779 {
00780   MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
00781 }
00782 
00783 /**
00784   * @brief  Get the Master addressing mode.
00785   * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode
00786   * @param  I2Cx I2C Instance.
00787   * @retval Returned value can be one of the following values:
00788   *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
00789   *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
00790   */
00791 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
00792 {
00793   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
00794 }
00795 
00796 /**
00797   * @brief  Set the Own Address1.
00798   * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n
00799   *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1
00800   * @param  I2Cx I2C Instance.
00801   * @param  OwnAddress1 This parameter must be a value between 0 and 0x3FF.
00802   * @param  OwnAddrSize This parameter can be one of the following values:
00803   *         @arg @ref LL_I2C_OWNADDRESS1_7BIT
00804   *         @arg @ref LL_I2C_OWNADDRESS1_10BIT
00805   * @retval None
00806   */
00807 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
00808 {
00809   MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
00810 }
00811 
00812 /**
00813   * @brief  Enable acknowledge on Own Address1 match address.
00814   * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1
00815   * @param  I2Cx I2C Instance.
00816   * @retval None
00817   */
00818 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
00819 {
00820   SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00821 }
00822 
00823 /**
00824   * @brief  Disable acknowledge on Own Address1 match address.
00825   * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1
00826   * @param  I2Cx I2C Instance.
00827   * @retval None
00828   */
00829 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
00830 {
00831   CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
00832 }
00833 
00834 /**
00835   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00836   * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1
00837   * @param  I2Cx I2C Instance.
00838   * @retval State of bit (1 or 0).
00839   */
00840 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
00841 {
00842   return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
00843 }
00844 
00845 /**
00846   * @brief  Set the 7bits Own Address2.
00847   * @note   This action has no effect if own address2 is enabled.
00848   * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n
00849   *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2
00850   * @param  I2Cx I2C Instance.
00851   * @param  OwnAddress2 Value between 0 and 0x7F.
00852   * @param  OwnAddrMask This parameter can be one of the following values:
00853   *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK
00854   *         @arg @ref LL_I2C_OWNADDRESS2_MASK01
00855   *         @arg @ref LL_I2C_OWNADDRESS2_MASK02
00856   *         @arg @ref LL_I2C_OWNADDRESS2_MASK03
00857   *         @arg @ref LL_I2C_OWNADDRESS2_MASK04
00858   *         @arg @ref LL_I2C_OWNADDRESS2_MASK05
00859   *         @arg @ref LL_I2C_OWNADDRESS2_MASK06
00860   *         @arg @ref LL_I2C_OWNADDRESS2_MASK07
00861   * @retval None
00862   */
00863 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
00864 {
00865   MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
00866 }
00867 
00868 /**
00869   * @brief  Enable acknowledge on Own Address2 match address.
00870   * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2
00871   * @param  I2Cx I2C Instance.
00872   * @retval None
00873   */
00874 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
00875 {
00876   SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00877 }
00878 
00879 /**
00880   * @brief  Disable  acknowledge on Own Address2 match address.
00881   * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2
00882   * @param  I2Cx I2C Instance.
00883   * @retval None
00884   */
00885 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
00886 {
00887   CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
00888 }
00889 
00890 /**
00891   * @brief  Check if Own Address1 acknowledge is enabled or disabled.
00892   * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2
00893   * @param  I2Cx I2C Instance.
00894   * @retval State of bit (1 or 0).
00895   */
00896 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
00897 {
00898   return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
00899 }
00900 
00901 /**
00902   * @brief  Configure the SDA setup, hold time and the SCL high, low period.
00903   * @note   This bit can only be programmed when the I2C is disabled (PE = 0).
00904   * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming
00905   * @param  I2Cx I2C Instance.
00906   * @param  Timing This parameter must be a value between  0 and 0xFFFFFFFF.
00907   * @note   This parameter is computed with the STM32CubeMX Tool.
00908   * @retval None
00909   */
00910 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
00911 {
00912   WRITE_REG(I2Cx->TIMINGR, Timing);
00913 }
00914 
00915 /**
00916   * @brief  Get the Timing Prescaler setting.
00917   * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler
00918   * @param  I2Cx I2C Instance.
00919   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00920   */
00921 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
00922 {
00923   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
00924 }
00925 
00926 /**
00927   * @brief  Get the SCL low period setting.
00928   * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod
00929   * @param  I2Cx I2C Instance.
00930   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00931   */
00932 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
00933 {
00934   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
00935 }
00936 
00937 /**
00938   * @brief  Get the SCL high period setting.
00939   * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod
00940   * @param  I2Cx I2C Instance.
00941   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
00942   */
00943 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
00944 {
00945   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
00946 }
00947 
00948 /**
00949   * @brief  Get the SDA hold time.
00950   * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime
00951   * @param  I2Cx I2C Instance.
00952   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00953   */
00954 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
00955 {
00956   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
00957 }
00958 
00959 /**
00960   * @brief  Get the SDA setup time.
00961   * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime
00962   * @param  I2Cx I2C Instance.
00963   * @retval Value between Min_Data=0x0 and Max_Data=0xF
00964   */
00965 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
00966 {
00967   return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
00968 }
00969 
00970 /**
00971   * @brief  Configure peripheral mode.
00972   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00973   *         SMBus feature is supported by the I2Cx Instance.
00974   * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n
00975   *         CR1          SMBDEN        LL_I2C_SetMode
00976   * @param  I2Cx I2C Instance.
00977   * @param  PeripheralMode This parameter can be one of the following values:
00978   *         @arg @ref LL_I2C_MODE_I2C
00979   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00980   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
00981   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
00982   * @retval None
00983   */
00984 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
00985 {
00986   MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
00987 }
00988 
00989 /**
00990   * @brief  Get peripheral mode.
00991   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
00992   *         SMBus feature is supported by the I2Cx Instance.
00993   * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n
00994   *         CR1          SMBDEN        LL_I2C_GetMode
00995   * @param  I2Cx I2C Instance.
00996   * @retval Returned value can be one of the following values:
00997   *         @arg @ref LL_I2C_MODE_I2C
00998   *         @arg @ref LL_I2C_MODE_SMBUS_HOST
00999   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE
01000   *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
01001   */
01002 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
01003 {
01004   return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
01005 }
01006 
01007 /**
01008   * @brief  Enable SMBus alert (Host or Device mode)
01009   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01010   *         SMBus feature is supported by the I2Cx Instance.
01011   * @note   SMBus Device mode:
01012   *         - SMBus Alert pin is drived low and
01013   *           Alert Response Address Header acknowledge is enabled.
01014   *         SMBus Host mode:
01015   *         - SMBus Alert pin management is supported.
01016   * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert
01017   * @param  I2Cx I2C Instance.
01018   * @retval None
01019   */
01020 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
01021 {
01022   SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01023 }
01024 
01025 /**
01026   * @brief  Disable SMBus alert (Host or Device mode)
01027   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01028   *         SMBus feature is supported by the I2Cx Instance.
01029   * @note   SMBus Device mode:
01030   *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and
01031   *           Alert Response Address Header acknowledge is disabled.
01032   *         SMBus Host mode:
01033   *         - SMBus Alert pin management is not supported.
01034   * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert
01035   * @param  I2Cx I2C Instance.
01036   * @retval None
01037   */
01038 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
01039 {
01040   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
01041 }
01042 
01043 /**
01044   * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.
01045   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01046   *         SMBus feature is supported by the I2Cx Instance.
01047   * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert
01048   * @param  I2Cx I2C Instance.
01049   * @retval State of bit (1 or 0).
01050   */
01051 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
01052 {
01053   return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
01054 }
01055 
01056 /**
01057   * @brief  Enable SMBus Packet Error Calculation (PEC).
01058   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01059   *         SMBus feature is supported by the I2Cx Instance.
01060   * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC
01061   * @param  I2Cx I2C Instance.
01062   * @retval None
01063   */
01064 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
01065 {
01066   SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01067 }
01068 
01069 /**
01070   * @brief  Disable SMBus Packet Error Calculation (PEC).
01071   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01072   *         SMBus feature is supported by the I2Cx Instance.
01073   * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC
01074   * @param  I2Cx I2C Instance.
01075   * @retval None
01076   */
01077 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
01078 {
01079   CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
01080 }
01081 
01082 /**
01083   * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
01084   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01085   *         SMBus feature is supported by the I2Cx Instance.
01086   * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC
01087   * @param  I2Cx I2C Instance.
01088   * @retval State of bit (1 or 0).
01089   */
01090 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
01091 {
01092   return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
01093 }
01094 
01095 /**
01096   * @brief  Configure the SMBus Clock Timeout.
01097   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01098   *         SMBus feature is supported by the I2Cx Instance.
01099   * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01100   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n
01101   *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n
01102   *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout
01103   * @param  I2Cx I2C Instance.
01104   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01105   * @param  TimeoutAMode This parameter can be one of the following values:
01106   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01107   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01108   * @param  TimeoutB
01109   *               @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
01110   * @retval None
01111   */
01112 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
01113                                                uint32_t TimeoutB)
01114 {
01115   MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
01116              TimeoutA | TimeoutAMode | (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
01117 }
01118 
01119 /**
01120   * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
01121   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01122   *         SMBus feature is supported by the I2Cx Instance.
01123   * @note   These bits can only be programmed when TimeoutA is disabled.
01124   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA
01125   * @param  I2Cx I2C Instance.
01126   * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01127   * @retval None
01128   */
01129 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
01130 {
01131   WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
01132 }
01133 
01134 /**
01135   * @brief  Get the SMBus Clock TimeoutA setting.
01136   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01137   *         SMBus feature is supported by the I2Cx Instance.
01138   * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA
01139   * @param  I2Cx I2C Instance.
01140   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01141   */
01142 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
01143 {
01144   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
01145 }
01146 
01147 /**
01148   * @brief  Set the SMBus Clock TimeoutA mode.
01149   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01150   *         SMBus feature is supported by the I2Cx Instance.
01151   * @note   This bit can only be programmed when TimeoutA is disabled.
01152   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode
01153   * @param  I2Cx I2C Instance.
01154   * @param  TimeoutAMode This parameter can be one of the following values:
01155   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01156   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01157   * @retval None
01158   */
01159 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
01160 {
01161   WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
01162 }
01163 
01164 /**
01165   * @brief  Get the SMBus Clock TimeoutA mode.
01166   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01167   *         SMBus feature is supported by the I2Cx Instance.
01168   * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode
01169   * @param  I2Cx I2C Instance.
01170   * @retval Returned value can be one of the following values:
01171   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
01172   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
01173   */
01174 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
01175 {
01176   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
01177 }
01178 
01179 /**
01180   * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
01181   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01182   *         SMBus feature is supported by the I2Cx Instance.
01183   * @note   These bits can only be programmed when TimeoutB is disabled.
01184   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB
01185   * @param  I2Cx I2C Instance.
01186   * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.
01187   * @retval None
01188   */
01189 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
01190 {
01191   WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
01192 }
01193 
01194 /**
01195   * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.
01196   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01197   *         SMBus feature is supported by the I2Cx Instance.
01198   * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB
01199   * @param  I2Cx I2C Instance.
01200   * @retval Value between Min_Data=0 and Max_Data=0xFFF
01201   */
01202 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
01203 {
01204   return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
01205 }
01206 
01207 /**
01208   * @brief  Enable the SMBus Clock Timeout.
01209   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01210   *         SMBus feature is supported by the I2Cx Instance.
01211   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n
01212   *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout
01213   * @param  I2Cx I2C Instance.
01214   * @param  ClockTimeout This parameter can be one of the following values:
01215   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01216   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01217   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01218   * @retval None
01219   */
01220 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01221 {
01222   SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01223 }
01224 
01225 /**
01226   * @brief  Disable the SMBus Clock Timeout.
01227   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01228   *         SMBus feature is supported by the I2Cx Instance.
01229   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n
01230   *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout
01231   * @param  I2Cx I2C Instance.
01232   * @param  ClockTimeout This parameter can be one of the following values:
01233   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01234   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01235   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01236   * @retval None
01237   */
01238 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01239 {
01240   CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
01241 }
01242 
01243 /**
01244   * @brief  Check if the SMBus Clock Timeout is enabled or disabled.
01245   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01246   *         SMBus feature is supported by the I2Cx Instance.
01247   * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n
01248   *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout
01249   * @param  I2Cx I2C Instance.
01250   * @param  ClockTimeout This parameter can be one of the following values:
01251   *         @arg @ref LL_I2C_SMBUS_TIMEOUTA
01252   *         @arg @ref LL_I2C_SMBUS_TIMEOUTB
01253   *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
01254   * @retval State of bit (1 or 0).
01255   */
01256 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
01257 {
01258   return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
01259 }
01260 
01261 /**
01262   * @}
01263   */
01264 
01265 /** @defgroup I2C_LL_EF_IT_Management IT_Management
01266   * @{
01267   */
01268 
01269 /**
01270   * @brief  Enable TXIS interrupt.
01271   * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX
01272   * @param  I2Cx I2C Instance.
01273   * @retval None
01274   */
01275 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
01276 {
01277   SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01278 }
01279 
01280 /**
01281   * @brief  Disable TXIS interrupt.
01282   * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX
01283   * @param  I2Cx I2C Instance.
01284   * @retval None
01285   */
01286 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
01287 {
01288   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
01289 }
01290 
01291 /**
01292   * @brief  Check if the TXIS Interrupt is enabled or disabled.
01293   * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX
01294   * @param  I2Cx I2C Instance.
01295   * @retval State of bit (1 or 0).
01296   */
01297 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
01298 {
01299   return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
01300 }
01301 
01302 /**
01303   * @brief  Enable RXNE interrupt.
01304   * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX
01305   * @param  I2Cx I2C Instance.
01306   * @retval None
01307   */
01308 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
01309 {
01310   SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01311 }
01312 
01313 /**
01314   * @brief  Disable RXNE interrupt.
01315   * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX
01316   * @param  I2Cx I2C Instance.
01317   * @retval None
01318   */
01319 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
01320 {
01321   CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
01322 }
01323 
01324 /**
01325   * @brief  Check if the RXNE Interrupt is enabled or disabled.
01326   * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX
01327   * @param  I2Cx I2C Instance.
01328   * @retval State of bit (1 or 0).
01329   */
01330 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
01331 {
01332   return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
01333 }
01334 
01335 /**
01336   * @brief  Enable Address match interrupt (slave mode only).
01337   * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR
01338   * @param  I2Cx I2C Instance.
01339   * @retval None
01340   */
01341 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
01342 {
01343   SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01344 }
01345 
01346 /**
01347   * @brief  Disable Address match interrupt (slave mode only).
01348   * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR
01349   * @param  I2Cx I2C Instance.
01350   * @retval None
01351   */
01352 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
01353 {
01354   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
01355 }
01356 
01357 /**
01358   * @brief  Check if Address match interrupt is enabled or disabled.
01359   * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR
01360   * @param  I2Cx I2C Instance.
01361   * @retval State of bit (1 or 0).
01362   */
01363 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
01364 {
01365   return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
01366 }
01367 
01368 /**
01369   * @brief  Enable Not acknowledge received interrupt.
01370   * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK
01371   * @param  I2Cx I2C Instance.
01372   * @retval None
01373   */
01374 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
01375 {
01376   SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01377 }
01378 
01379 /**
01380   * @brief  Disable Not acknowledge received interrupt.
01381   * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK
01382   * @param  I2Cx I2C Instance.
01383   * @retval None
01384   */
01385 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
01386 {
01387   CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
01388 }
01389 
01390 /**
01391   * @brief  Check if Not acknowledge received interrupt is enabled or disabled.
01392   * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK
01393   * @param  I2Cx I2C Instance.
01394   * @retval State of bit (1 or 0).
01395   */
01396 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
01397 {
01398   return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
01399 }
01400 
01401 /**
01402   * @brief  Enable STOP detection interrupt.
01403   * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP
01404   * @param  I2Cx I2C Instance.
01405   * @retval None
01406   */
01407 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
01408 {
01409   SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01410 }
01411 
01412 /**
01413   * @brief  Disable STOP detection interrupt.
01414   * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP
01415   * @param  I2Cx I2C Instance.
01416   * @retval None
01417   */
01418 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
01419 {
01420   CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
01421 }
01422 
01423 /**
01424   * @brief  Check if STOP detection interrupt is enabled or disabled.
01425   * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP
01426   * @param  I2Cx I2C Instance.
01427   * @retval State of bit (1 or 0).
01428   */
01429 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
01430 {
01431   return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
01432 }
01433 
01434 /**
01435   * @brief  Enable Transfer Complete interrupt.
01436   * @note   Any of these events will generate interrupt :
01437   *         Transfer Complete (TC)
01438   *         Transfer Complete Reload (TCR)
01439   * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC
01440   * @param  I2Cx I2C Instance.
01441   * @retval None
01442   */
01443 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
01444 {
01445   SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01446 }
01447 
01448 /**
01449   * @brief  Disable Transfer Complete interrupt.
01450   * @note   Any of these events will generate interrupt :
01451   *         Transfer Complete (TC)
01452   *         Transfer Complete Reload (TCR)
01453   * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC
01454   * @param  I2Cx I2C Instance.
01455   * @retval None
01456   */
01457 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
01458 {
01459   CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
01460 }
01461 
01462 /**
01463   * @brief  Check if Transfer Complete interrupt is enabled or disabled.
01464   * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC
01465   * @param  I2Cx I2C Instance.
01466   * @retval State of bit (1 or 0).
01467   */
01468 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
01469 {
01470   return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
01471 }
01472 
01473 /**
01474   * @brief  Enable Error interrupts.
01475   * @note   Any of these errors will generate interrupt :
01476   *         Arbitration Loss (ARLO)
01477   *         Bus Error detection (BERR)
01478   *         Overrun/Underrun (OVR)
01479   *         SMBus Timeout detection (TIMEOUT)
01480   *         SMBus PEC error detection (PECERR)
01481   *         SMBus Alert pin event detection (ALERT)
01482   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01483   *         SMBus feature is supported by the I2Cx Instance.
01484   * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR
01485   * @param  I2Cx I2C Instance.
01486   * @retval None
01487   */
01488 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
01489 {
01490   SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01491 }
01492 
01493 /**
01494   * @brief  Disable Error interrupts.
01495   * @note   Any of these errors will generate interrupt :
01496   *         Arbitration Loss (ARLO)
01497   *         Bus Error detection (BERR)
01498   *         Overrun/Underrun (OVR)
01499   *         SMBus Timeout detection (TIMEOUT)
01500   *         SMBus PEC error detection (PECERR)
01501   *         SMBus Alert pin event detection (ALERT)
01502   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01503   *         SMBus feature is supported by the I2Cx Instance.
01504   * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR
01505   * @param  I2Cx I2C Instance.
01506   * @retval None
01507   */
01508 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
01509 {
01510   CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
01511 }
01512 
01513 /**
01514   * @brief  Check if Error interrupts is enabled of disabled.
01515   * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR
01516   * @param  I2Cx I2C Instance.
01517   * @retval State of bit (1 or 0).
01518   */
01519 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
01520 {
01521   return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
01522 }
01523 
01524 /**
01525   * @}
01526   */
01527 
01528 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
01529   * @{
01530   */
01531 
01532 /**
01533   * @brief  Indicate the status of Transmit data register empty flag.
01534   * @note   RESET: When next data is written in Transmit data register.
01535   *         SET: When Transmit data register is empty.
01536   * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE
01537   * @param  I2Cx I2C Instance.
01538   * @retval State of bit (1 or 0).
01539   */
01540 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
01541 {
01542   return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
01543 }
01544 
01545 /**
01546   * @brief  Indicate the status of Transmit interrupt flag.
01547   * @note   RESET: When next data is written in Transmit data register.
01548   *         SET: When Transmit data register is empty.
01549   * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS
01550   * @param  I2Cx I2C Instance.
01551   * @retval State of bit (1 or 0).
01552   */
01553 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
01554 {
01555   return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
01556 }
01557 
01558 /**
01559   * @brief  Indicate the status of Receive data register not empty flag.
01560   * @note   RESET: When Receive data register is read.
01561   *         SET: When the received data is copied in Receive data register.
01562   * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE
01563   * @param  I2Cx I2C Instance.
01564   * @retval State of bit (1 or 0).
01565   */
01566 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
01567 {
01568   return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
01569 }
01570 
01571 /**
01572   * @brief  Indicate the status of Address matched flag (slave mode).
01573   * @note   RESET: Clear default value.
01574   *         SET: When the received slave address matched with one of the enabled slave address.
01575   * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR
01576   * @param  I2Cx I2C Instance.
01577   * @retval State of bit (1 or 0).
01578   */
01579 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
01580 {
01581   return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
01582 }
01583 
01584 /**
01585   * @brief  Indicate the status of Not Acknowledge received flag.
01586   * @note   RESET: Clear default value.
01587   *         SET: When a NACK is received after a byte transmission.
01588   * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK
01589   * @param  I2Cx I2C Instance.
01590   * @retval State of bit (1 or 0).
01591   */
01592 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
01593 {
01594   return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
01595 }
01596 
01597 /**
01598   * @brief  Indicate the status of Stop detection flag.
01599   * @note   RESET: Clear default value.
01600   *         SET: When a Stop condition is detected.
01601   * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP
01602   * @param  I2Cx I2C Instance.
01603   * @retval State of bit (1 or 0).
01604   */
01605 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
01606 {
01607   return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
01608 }
01609 
01610 /**
01611   * @brief  Indicate the status of Transfer complete flag (master mode).
01612   * @note   RESET: Clear default value.
01613   *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
01614   * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC
01615   * @param  I2Cx I2C Instance.
01616   * @retval State of bit (1 or 0).
01617   */
01618 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
01619 {
01620   return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
01621 }
01622 
01623 /**
01624   * @brief  Indicate the status of Transfer complete flag (master mode).
01625   * @note   RESET: Clear default value.
01626   *         SET: When RELOAD=1 and NBYTES date have been transferred.
01627   * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR
01628   * @param  I2Cx I2C Instance.
01629   * @retval State of bit (1 or 0).
01630   */
01631 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
01632 {
01633   return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
01634 }
01635 
01636 /**
01637   * @brief  Indicate the status of Bus error flag.
01638   * @note   RESET: Clear default value.
01639   *         SET: When a misplaced Start or Stop condition is detected.
01640   * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR
01641   * @param  I2Cx I2C Instance.
01642   * @retval State of bit (1 or 0).
01643   */
01644 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
01645 {
01646   return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
01647 }
01648 
01649 /**
01650   * @brief  Indicate the status of Arbitration lost flag.
01651   * @note   RESET: Clear default value.
01652   *         SET: When arbitration lost.
01653   * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO
01654   * @param  I2Cx I2C Instance.
01655   * @retval State of bit (1 or 0).
01656   */
01657 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
01658 {
01659   return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
01660 }
01661 
01662 /**
01663   * @brief  Indicate the status of Overrun/Underrun flag (slave mode).
01664   * @note   RESET: Clear default value.
01665   *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
01666   * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR
01667   * @param  I2Cx I2C Instance.
01668   * @retval State of bit (1 or 0).
01669   */
01670 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
01671 {
01672   return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
01673 }
01674 
01675 /**
01676   * @brief  Indicate the status of Bus Busy flag.
01677   * @note   RESET: Clear default value.
01678   *         SET: When a Start condition is detected.
01679   * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY
01680   * @param  I2Cx I2C Instance.
01681   * @retval State of bit (1 or 0).
01682   */
01683 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
01684 {
01685   return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
01686 }
01687 
01688 /**
01689   * @brief  Clear Address Matched flag.
01690   * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR
01691   * @param  I2Cx I2C Instance.
01692   * @retval None
01693   */
01694 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
01695 {
01696   SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
01697 }
01698 
01699 /**
01700   * @brief  Clear Not Acknowledge flag.
01701   * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK
01702   * @param  I2Cx I2C Instance.
01703   * @retval None
01704   */
01705 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
01706 {
01707   SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
01708 }
01709 
01710 /**
01711   * @brief  Clear Stop detection flag.
01712   * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP
01713   * @param  I2Cx I2C Instance.
01714   * @retval None
01715   */
01716 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
01717 {
01718   SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
01719 }
01720 
01721 /**
01722   * @brief  Clear Transmit data register empty flag (TXE).
01723   * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).
01724   * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE
01725   * @param  I2Cx I2C Instance.
01726   * @retval None
01727   */
01728 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
01729 {
01730   WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
01731 }
01732 
01733 /**
01734   * @brief  Clear Bus error flag.
01735   * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR
01736   * @param  I2Cx I2C Instance.
01737   * @retval None
01738   */
01739 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
01740 {
01741   SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
01742 }
01743 
01744 /**
01745   * @brief  Clear Arbitration lost flag.
01746   * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO
01747   * @param  I2Cx I2C Instance.
01748   * @retval None
01749   */
01750 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
01751 {
01752   SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
01753 }
01754 
01755 /**
01756   * @brief  Clear Overrun/Underrun flag.
01757   * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR
01758   * @param  I2Cx I2C Instance.
01759   * @retval None
01760   */
01761 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
01762 {
01763   SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
01764 }
01765 
01766 /**
01767   * @brief  Indicate the status of SMBus PEC error flag in reception.
01768   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01769   *         SMBus feature is supported by the I2Cx Instance.
01770   * @note   RESET: Clear default value.
01771   *         SET: When the received PEC does not match with the PEC register content.
01772   * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR
01773   * @param  I2Cx I2C Instance.
01774   * @retval State of bit (1 or 0).
01775   */
01776 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01777 {
01778   return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
01779 }
01780 
01781 /**
01782   * @brief  Indicate the status of SMBus Timeout detection flag.
01783   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01784   *         SMBus feature is supported by the I2Cx Instance.
01785   * @note   RESET: Clear default value.
01786   *         SET: When a timeout or extended clock timeout occurs.
01787   * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT
01788   * @param  I2Cx I2C Instance.
01789   * @retval State of bit (1 or 0).
01790   */
01791 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01792 {
01793   return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
01794 }
01795 
01796 /**
01797   * @brief  Indicate the status of SMBus alert flag.
01798   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01799   *         SMBus feature is supported by the I2Cx Instance.
01800   * @note   RESET: Clear default value.
01801   *         SET: When SMBus host configuration, SMBus alert enabled and
01802   *              a falling edge event occurs on SMBA pin.
01803   * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT
01804   * @param  I2Cx I2C Instance.
01805   * @retval State of bit (1 or 0).
01806   */
01807 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01808 {
01809   return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
01810 }
01811 
01812 /**
01813   * @brief  Clear SMBus PEC error flag.
01814   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01815   *         SMBus feature is supported by the I2Cx Instance.
01816   * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR
01817   * @param  I2Cx I2C Instance.
01818   * @retval None
01819   */
01820 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
01821 {
01822   SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
01823 }
01824 
01825 /**
01826   * @brief  Clear SMBus Timeout detection flag.
01827   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01828   *         SMBus feature is supported by the I2Cx Instance.
01829   * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT
01830   * @param  I2Cx I2C Instance.
01831   * @retval None
01832   */
01833 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
01834 {
01835   SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
01836 }
01837 
01838 /**
01839   * @brief  Clear SMBus Alert flag.
01840   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
01841   *         SMBus feature is supported by the I2Cx Instance.
01842   * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT
01843   * @param  I2Cx I2C Instance.
01844   * @retval None
01845   */
01846 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
01847 {
01848   SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
01849 }
01850 
01851 /**
01852   * @}
01853   */
01854 
01855 /** @defgroup I2C_LL_EF_Data_Management Data_Management
01856   * @{
01857   */
01858 
01859 /**
01860   * @brief  Enable automatic STOP condition generation (master mode).
01861   * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
01862   *         This bit has no effect in slave mode or when RELOAD bit is set.
01863   * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode
01864   * @param  I2Cx I2C Instance.
01865   * @retval None
01866   */
01867 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
01868 {
01869   SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01870 }
01871 
01872 /**
01873   * @brief  Disable automatic STOP condition generation (master mode).
01874   * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
01875   * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode
01876   * @param  I2Cx I2C Instance.
01877   * @retval None
01878   */
01879 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
01880 {
01881   CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
01882 }
01883 
01884 /**
01885   * @brief  Check if automatic STOP condition is enabled or disabled.
01886   * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode
01887   * @param  I2Cx I2C Instance.
01888   * @retval State of bit (1 or 0).
01889   */
01890 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
01891 {
01892   return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
01893 }
01894 
01895 /**
01896   * @brief  Enable reload mode (master mode).
01897   * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
01898   * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode
01899   * @param  I2Cx I2C Instance.
01900   * @retval None
01901   */
01902 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
01903 {
01904   SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01905 }
01906 
01907 /**
01908   * @brief  Disable reload mode (master mode).
01909   * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
01910   * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode
01911   * @param  I2Cx I2C Instance.
01912   * @retval None
01913   */
01914 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
01915 {
01916   CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
01917 }
01918 
01919 /**
01920   * @brief  Check if reload mode is enabled or disabled.
01921   * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode
01922   * @param  I2Cx I2C Instance.
01923   * @retval State of bit (1 or 0).
01924   */
01925 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
01926 {
01927   return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
01928 }
01929 
01930 /**
01931   * @brief  Configure the number of bytes for transfer.
01932   * @note   Changing these bits when START bit is set is not allowed.
01933   * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize
01934   * @param  I2Cx I2C Instance.
01935   * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
01936   * @retval None
01937   */
01938 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
01939 {
01940   MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
01941 }
01942 
01943 /**
01944   * @brief  Get the number of bytes configured for transfer.
01945   * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize
01946   * @param  I2Cx I2C Instance.
01947   * @retval Value between Min_Data=0x0 and Max_Data=0xFF
01948   */
01949 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
01950 {
01951   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
01952 }
01953 
01954 /**
01955   * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
01956   * @note   Usage in Slave mode only.
01957   * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData
01958   * @param  I2Cx I2C Instance.
01959   * @param  TypeAcknowledge This parameter can be one of the following values:
01960   *         @arg @ref LL_I2C_ACK
01961   *         @arg @ref LL_I2C_NACK
01962   * @retval None
01963   */
01964 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
01965 {
01966   MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
01967 }
01968 
01969 /**
01970   * @brief  Generate a STOP condition after the current byte transfer (master mode).
01971   * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition
01972   * @param  I2Cx I2C Instance.
01973   * @retval None
01974   */
01975 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
01976 {
01977   SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
01978 }
01979 
01980 /**
01981   * @brief  Generate a START or RESTART condition
01982   * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.
01983   *         This action has no effect when RELOAD is set.
01984   * @rmtoll CR2          START           LL_I2C_GenerateStartCondition
01985   * @param  I2Cx I2C Instance.
01986   * @retval None
01987   */
01988 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
01989 {
01990   SET_BIT(I2Cx->CR2, I2C_CR2_START);
01991 }
01992 
01993 /**
01994   * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).
01995   * @note   The master sends the complete 10bit slave address read sequence :
01996   *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
01997   * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead
01998   * @param  I2Cx I2C Instance.
01999   * @retval None
02000   */
02001 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
02002 {
02003   CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02004 }
02005 
02006 /**
02007   * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).
02008   * @note   The master only sends the first 7 bits of 10bit address in Read direction.
02009   * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead
02010   * @param  I2Cx I2C Instance.
02011   * @retval None
02012   */
02013 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
02014 {
02015   SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
02016 }
02017 
02018 /**
02019   * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
02020   * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead
02021   * @param  I2Cx I2C Instance.
02022   * @retval State of bit (1 or 0).
02023   */
02024 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
02025 {
02026   return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
02027 }
02028 
02029 /**
02030   * @brief  Configure the transfer direction (master mode).
02031   * @note   Changing these bits when START bit is set is not allowed.
02032   * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest
02033   * @param  I2Cx I2C Instance.
02034   * @param  TransferRequest This parameter can be one of the following values:
02035   *         @arg @ref LL_I2C_REQUEST_WRITE
02036   *         @arg @ref LL_I2C_REQUEST_READ
02037   * @retval None
02038   */
02039 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
02040 {
02041   MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
02042 }
02043 
02044 /**
02045   * @brief  Get the transfer direction requested (master mode).
02046   * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest
02047   * @param  I2Cx I2C Instance.
02048   * @retval Returned value can be one of the following values:
02049   *         @arg @ref LL_I2C_REQUEST_WRITE
02050   *         @arg @ref LL_I2C_REQUEST_READ
02051   */
02052 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
02053 {
02054   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
02055 }
02056 
02057 /**
02058   * @brief  Configure the slave address for transfer (master mode).
02059   * @note   Changing these bits when START bit is set is not allowed.
02060   * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr
02061   * @param  I2Cx I2C Instance.
02062   * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
02063   * @retval None
02064   */
02065 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
02066 {
02067   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
02068 }
02069 
02070 /**
02071   * @brief  Get the slave address programmed for transfer.
02072   * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr
02073   * @param  I2Cx I2C Instance.
02074   * @retval Value between Min_Data=0x0 and Max_Data=0x3F
02075   */
02076 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
02077 {
02078   return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
02079 }
02080 
02081 /**
02082   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
02083   * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n
02084   *         CR2          ADD10         LL_I2C_HandleTransfer\n
02085   *         CR2          RD_WRN        LL_I2C_HandleTransfer\n
02086   *         CR2          START         LL_I2C_HandleTransfer\n
02087   *         CR2          STOP          LL_I2C_HandleTransfer\n
02088   *         CR2          RELOAD        LL_I2C_HandleTransfer\n
02089   *         CR2          NBYTES        LL_I2C_HandleTransfer\n
02090   *         CR2          AUTOEND       LL_I2C_HandleTransfer\n
02091   *         CR2          HEAD10R       LL_I2C_HandleTransfer
02092   * @param  I2Cx I2C Instance.
02093   * @param  SlaveAddr Specifies the slave address to be programmed.
02094   * @param  SlaveAddrSize This parameter can be one of the following values:
02095   *         @arg @ref LL_I2C_ADDRSLAVE_7BIT
02096   *         @arg @ref LL_I2C_ADDRSLAVE_10BIT
02097   * @param  TransferSize Specifies the number of bytes to be programmed.
02098   *         This parameter must be a value between 0 and 255.
02099   * @param  EndMode This parameter can be one of the following values:
02100   *         @arg @ref LL_I2C_MODE_RELOAD
02101   *         @arg @ref LL_I2C_MODE_AUTOEND
02102   *         @arg @ref LL_I2C_MODE_SOFTEND
02103   *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD
02104   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
02105   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
02106   *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
02107   *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
02108   * @param  Request This parameter can be one of the following values:
02109   *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
02110   *         @arg @ref LL_I2C_GENERATE_STOP
02111   *         @arg @ref LL_I2C_GENERATE_START_READ
02112   *         @arg @ref LL_I2C_GENERATE_START_WRITE
02113   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
02114   *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
02115   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
02116   *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
02117   * @retval None
02118   */
02119 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
02120                                            uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
02121 {
02122   MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
02123              I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
02124              SlaveAddr | SlaveAddrSize | TransferSize << I2C_POSITION_CR2_NBYTES | EndMode | Request);
02125 }
02126 
02127 /**
02128   * @brief  Indicate the value of transfer direction (slave mode).
02129   * @note   RESET: Write transfer, Slave enters in receiver mode.
02130   *         SET: Read transfer, Slave enters in transmitter mode.
02131   * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection
02132   * @param  I2Cx I2C Instance.
02133   * @retval Returned value can be one of the following values:
02134   *         @arg @ref LL_I2C_DIRECTION_WRITE
02135   *         @arg @ref LL_I2C_DIRECTION_READ
02136   */
02137 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
02138 {
02139   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
02140 }
02141 
02142 /**
02143   * @brief  Return the slave matched address.
02144   * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode
02145   * @param  I2Cx I2C Instance.
02146   * @retval Value between Min_Data=0x00 and Max_Data=0x3F
02147   */
02148 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
02149 {
02150   return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
02151 }
02152 
02153 /**
02154   * @brief  Enable internal comparison of Packet Error byte (transmission or reception mode).
02155   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02156   *         SMBus feature is supported by the I2Cx Instance.
02157   * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
02158   *         This bit has no effect when RELOAD bit is set.
02159   *         This bit has no effect in device mode when SBC bit is not set.
02160   * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare
02161   * @param  I2Cx I2C Instance.
02162   * @retval None
02163   */
02164 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
02165 {
02166   SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
02167 }
02168 
02169 /**
02170   * @brief  Check if Packet Error byte internal comparison is requested or not.
02171   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02172   *         SMBus feature is supported by the I2Cx Instance.
02173   * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare
02174   * @param  I2Cx I2C Instance.
02175   * @retval State of bit (1 or 0).
02176   */
02177 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
02178 {
02179   return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
02180 }
02181 
02182 /**
02183   * @brief  Get the Packet Error byte calculated.
02184   * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
02185   *         SMBus feature is supported by the I2Cx Instance.
02186   * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC
02187   * @param  I2Cx I2C Instance.
02188   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02189 */
02190 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
02191 {
02192   return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
02193 }
02194 
02195 /**
02196   * @brief  Read Receive Data register.
02197   * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8
02198   * @param  I2Cx I2C Instance.
02199   * @retval Value between Min_Data=0x00 and Max_Data=0xFF
02200   */
02201 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
02202 {
02203   return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
02204 }
02205 
02206 /**
02207   * @brief  Write in Transmit Data Register .
02208   * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8
02209   * @param  I2Cx I2C Instance.
02210   * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
02211   * @retval None
02212   */
02213 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
02214 {
02215   WRITE_REG(I2Cx->TXDR, Data);
02216 }
02217 
02218 /**
02219   * @}
02220   */
02221 
02222 #if defined(USE_FULL_LL_DRIVER)
02223 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
02224   * @{
02225   */
02226 
02227 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
02228 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
02229 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
02230 
02231 
02232 /**
02233   * @}
02234   */
02235 #endif /* USE_FULL_LL_DRIVER */
02236 
02237 /**
02238   * @}
02239   */
02240 
02241 /**
02242   * @}
02243   */
02244 
02245 #endif /* I2C1 || I2C2 || I2C3 */
02246 
02247 /**
02248   * @}
02249   */
02250 
02251 #ifdef __cplusplus
02252 }
02253 #endif
02254 
02255 #endif /* __STM32L4xx_LL_I2C_H */
02256 
02257 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/