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stm32l4xx_ll_fmc.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_fmc.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief FMC Low Layer HAL module driver. 00008 * This file provides firmware functions to manage the following 00009 * functionalities of the Flexible Memory Controller (FMC) peripheral memories: 00010 * + Initialization/de-initialization functions 00011 * + Peripheral Control functions 00012 * + Peripheral State functions 00013 * 00014 @verbatim 00015 ============================================================================== 00016 ##### FMC peripheral features ##### 00017 ============================================================================== 00018 [..] The Flexible memory controller (FMC) includes following memory controllers: 00019 (+) The NOR/PSRAM memory controller 00020 (+) The NAND memory controller 00021 00022 [..] The FMC functional block makes the interface with synchronous and asynchronous static 00023 memories and 16-bit PC memory cards. Its main purposes are: 00024 (+) to translate AHB transactions into the appropriate external device protocol. 00025 (+) to meet the access time requirements of the external memory devices. 00026 00027 [..] All external memories share the addresses, data and control signals with the controller. 00028 Each external device is accessed by means of a unique Chip Select. The FMC performs 00029 only one access at a time to an external device. 00030 The main features of the FMC controller are the following: 00031 (+) Interface with static-memory mapped devices including: 00032 (++) Static random access memory (SRAM). 00033 (++) NOR Flash memory. 00034 (++) PSRAM (4 memory banks). 00035 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of 00036 data 00037 (+) Independent Chip Select control for each memory bank 00038 (+) Independent configuration for each memory bank 00039 00040 @endverbatim 00041 ****************************************************************************** 00042 * @attention 00043 * 00044 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00045 * 00046 * Redistribution and use in source and binary forms, with or without modification, 00047 * are permitted provided that the following conditions are met: 00048 * 1. Redistributions of source code must retain the above copyright notice, 00049 * this list of conditions and the following disclaimer. 00050 * 2. Redistributions in binary form must reproduce the above copyright notice, 00051 * this list of conditions and the following disclaimer in the documentation 00052 * and/or other materials provided with the distribution. 00053 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00054 * may be used to endorse or promote products derived from this software 00055 * without specific prior written permission. 00056 * 00057 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00058 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00059 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00060 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00061 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00062 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00063 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00064 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00065 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00066 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00067 * 00068 ****************************************************************************** 00069 */ 00070 00071 /* Includes ------------------------------------------------------------------*/ 00072 #include "stm32l4xx_hal.h" 00073 00074 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00075 00076 /** @addtogroup STM32L4xx_HAL_Driver 00077 * @{ 00078 */ 00079 00080 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) 00081 00082 /** @defgroup FMC_LL FMC Low Layer 00083 * @brief FMC driver modules 00084 * @{ 00085 */ 00086 00087 /* Private typedef -----------------------------------------------------------*/ 00088 /* Private define ------------------------------------------------------------*/ 00089 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants 00090 * @{ 00091 */ 00092 00093 /* ----------------------- FMC registers bit mask --------------------------- */ 00094 /* --- BCRx Register ---*/ 00095 /* BCRx register clear mask */ 00096 #define BCRx_CLEAR_MASK ((uint32_t)(FMC_BCRx_MBKEN | FMC_BCRx_MUXEN |\ 00097 FMC_BCRx_MTYP | FMC_BCRx_MWID |\ 00098 FMC_BCRx_FACCEN | FMC_BCRx_BURSTEN |\ 00099 FMC_BCRx_WAITPOL | FMC_BCRx_WAITCFG |\ 00100 FMC_BCRx_WREN | FMC_BCRx_WAITEN |\ 00101 FMC_BCRx_EXTMOD | FMC_BCRx_ASYNCWAIT |\ 00102 FMC_BCRx_CPSIZE | FMC_BCRx_CBURSTRW |\ 00103 FMC_BCR1_CCLKEN)) 00104 00105 /* --- BTRx Register ---*/ 00106 /* BTRx register clear mask */ 00107 #define BTRx_CLEAR_MASK ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD |\ 00108 FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\ 00109 FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT |\ 00110 FMC_BTRx_ACCMOD)) 00111 00112 /* --- BWTRx Register ---*/ 00113 /* BWTRx register clear mask */ 00114 #define BWTRx_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ 00115 FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ 00116 FMC_BWTRx_ACCMOD)) 00117 00118 /* --- PCR Register ---*/ 00119 /* PCR register clear mask */ 00120 #define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN |\ 00121 FMC_PCR_PTYP | FMC_PCR_PWID |\ 00122 FMC_PCR_ECCEN | FMC_PCR_TCLR |\ 00123 FMC_PCR_TAR | FMC_PCR_ECCPS)) 00124 00125 /* --- SR Register ---*/ 00126 /* SR register clear mask */ 00127 #define SR_CLEAR_MASK ((uint32_t)(FMC_SR_FEMPT)) 00128 00129 /* --- PMEM Register ---*/ 00130 /* PMEM register clear mask */ 00131 #define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET | FMC_PMEM_MEMWAIT |\ 00132 FMC_PMEM_MEMHOLD | FMC_PMEM_MEMHIZ)) 00133 00134 /* --- PATT Register ---*/ 00135 /* PATT register clear mask */ 00136 #define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET | FMC_PATT_ATTWAIT |\ 00137 FMC_PATT_ATTHOLD | FMC_PATT_ATTHIZ)) 00138 /** 00139 * @} 00140 */ 00141 00142 /* Private macro -------------------------------------------------------------*/ 00143 /** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros 00144 * @{ 00145 */ 00146 00147 /** 00148 * @} 00149 */ 00150 00151 /* Private variables ---------------------------------------------------------*/ 00152 /* Private function prototypes -----------------------------------------------*/ 00153 /* Exported functions --------------------------------------------------------*/ 00154 00155 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions 00156 * @{ 00157 */ 00158 00159 /** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions 00160 * @brief NORSRAM Controller functions 00161 * 00162 @verbatim 00163 ============================================================================== 00164 ##### How to use NORSRAM device driver ##### 00165 ============================================================================== 00166 00167 [..] 00168 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order 00169 to run the NORSRAM external devices. 00170 00171 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() 00172 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() 00173 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() 00174 (+) FMC NORSRAM bank extended timing configuration using the function 00175 FMC_NORSRAM_Extended_Timing_Init() 00176 (+) FMC NORSRAM bank enable/disable write operation using the functions 00177 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() 00178 00179 00180 @endverbatim 00181 * @{ 00182 */ 00183 00184 /** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00185 * @brief Initialization and Configuration functions 00186 * 00187 @verbatim 00188 ============================================================================== 00189 ##### Initialization and de-initialization functions ##### 00190 ============================================================================== 00191 [..] 00192 This section provides functions allowing to: 00193 (+) Initialize and configure the FMC NORSRAM interface 00194 (+) De-initialize the FMC NORSRAM interface 00195 (+) Configure the FMC clock and associated GPIOs 00196 00197 @endverbatim 00198 * @{ 00199 */ 00200 00201 /** 00202 * @brief Initialize the FMC_NORSRAM device according to the specified 00203 * control parameters in the FMC_NORSRAM_InitTypeDef 00204 * @param Device: Pointer to NORSRAM device instance 00205 * @param Init: Pointer to NORSRAM Initialization structure 00206 * @retval HAL status 00207 */ 00208 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) 00209 { 00210 uint32_t tmp; 00211 00212 /* Check the parameters */ 00213 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); 00214 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank )); 00215 assert_param(IS_FMC_MUX(Init->DataAddressMux )); 00216 assert_param(IS_FMC_MEMORY(Init->MemoryType )); 00217 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth )); 00218 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode )); 00219 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity )); 00220 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive )); 00221 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation )); 00222 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal )); 00223 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode )); 00224 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait )); 00225 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst )); 00226 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock )); 00227 assert_param(IS_FMC_PAGESIZE(Init->PageSize )); 00228 00229 tmp = (uint32_t)(Init->DataAddressMux |\ 00230 Init->MemoryType |\ 00231 Init->MemoryDataWidth |\ 00232 Init->BurstAccessMode |\ 00233 Init->WaitSignalPolarity |\ 00234 Init->WaitSignalActive |\ 00235 Init->WriteOperation |\ 00236 Init->WaitSignal |\ 00237 Init->ExtendedMode |\ 00238 Init->AsynchronousWait |\ 00239 Init->WriteBurst |\ 00240 Init->ContinuousClock |\ 00241 Init->PageSize ); 00242 00243 /* Set NORSRAM device control parameters */ 00244 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) 00245 { 00246 MODIFY_REG(Device->BTCR[Init->NSBank ], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE |\ 00247 tmp)); 00248 } 00249 else 00250 { 00251 MODIFY_REG(Device->BTCR[Init->NSBank ], BCRx_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE |\ 00252 tmp)); 00253 } 00254 00255 /* Specific bits on bank1 register for bank2..4 */ 00256 if(Init->NSBank != FMC_NORSRAM_BANK1) 00257 { 00258 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ 00259 if(Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) 00260 { 00261 Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; 00262 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCRx_BURSTEN | FMC_BCR1_CCLKEN, (uint32_t)(Init->BurstAccessMode |\ 00263 Init->ContinuousClock )); 00264 } 00265 } 00266 00267 return HAL_OK; 00268 } 00269 00270 00271 /** 00272 * @brief DeInitialize the FMC_NORSRAM peripheral 00273 * @param Device: Pointer to NORSRAM device instance 00274 * @param ExDevice: Pointer to NORSRAM extended mode device instance 00275 * @param Bank: NORSRAM bank number 00276 * @retval HAL status 00277 */ 00278 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) 00279 { 00280 /* Check the parameters */ 00281 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); 00282 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); 00283 assert_param(IS_FMC_NORSRAM_BANK(Bank)); 00284 00285 /* Disable the FMC_NORSRAM device */ 00286 __FMC_NORSRAM_DISABLE(Device, Bank); 00287 00288 /* De-initialize the FMC_NORSRAM device */ 00289 /* FMC_NORSRAM_BANK1 */ 00290 if(Bank == FMC_NORSRAM_BANK1) 00291 { 00292 Device->BTCR[Bank] = 0x000030DB; 00293 } 00294 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ 00295 else 00296 { 00297 Device->BTCR[Bank] = 0x000030D2; 00298 } 00299 00300 Device->BTCR[Bank + 1] = 0x0FFFFFFF; 00301 ExDevice->BWTR[Bank] = 0x0FFFFFFF; 00302 00303 return HAL_OK; 00304 } 00305 00306 00307 /** 00308 * @brief Initialize the FMC_NORSRAM Timing according to the specified 00309 * parameters in the FMC_NORSRAM_TimingTypeDef 00310 * @param Device: Pointer to NORSRAM device instance 00311 * @param Timing: Pointer to NORSRAM Timing structure 00312 * @param Bank: NORSRAM bank number 00313 * @retval HAL status 00314 */ 00315 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) 00316 { 00317 uint32_t tmpr = 0; 00318 00319 /* Check the parameters */ 00320 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); 00321 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime )); 00322 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime )); 00323 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime )); 00324 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration )); 00325 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision )); 00326 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency )); 00327 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode )); 00328 assert_param(IS_FMC_NORSRAM_BANK(Bank)); 00329 00330 /* Set FMC_NORSRAM device timing parameters */ 00331 MODIFY_REG(Device->BTCR[Bank + 1], \ 00332 BTRx_CLEAR_MASK, \ 00333 (uint32_t)(Timing->AddressSetupTime |\ 00334 ((Timing->AddressHoldTime ) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\ 00335 ((Timing->DataSetupTime ) << POSITION_VAL(FMC_BTRx_DATAST)) |\ 00336 ((Timing->BusTurnAroundDuration ) << POSITION_VAL(FMC_BTRx_BUSTURN)) |\ 00337 (((Timing->CLKDivision )-1) << POSITION_VAL(FMC_BTRx_CLKDIV)) |\ 00338 (((Timing->DataLatency )-2) << POSITION_VAL(FMC_BTRx_DATLAT)) |\ 00339 (Timing->AccessMode ))); 00340 00341 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ 00342 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) 00343 { 00344 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV))); 00345 tmpr |= (uint32_t)(((Timing->CLKDivision )-1) << POSITION_VAL(FMC_BTRx_CLKDIV)); 00346 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr); 00347 } 00348 00349 return HAL_OK; 00350 } 00351 00352 /** 00353 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified 00354 * parameters in the FMC_NORSRAM_TimingTypeDef 00355 * @param Device: Pointer to NORSRAM device instance 00356 * @param Timing: Pointer to NORSRAM Timing structure 00357 * @param Bank: NORSRAM bank number 00358 * @param ExtendedMode: FMC Extended Mode 00359 * This parameter can be one of the following values: 00360 * @arg FMC_EXTENDED_MODE_DISABLE 00361 * @arg FMC_EXTENDED_MODE_ENABLE 00362 * @retval HAL status 00363 */ 00364 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) 00365 { 00366 /* Check the parameters */ 00367 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); 00368 00369 /* Set NORSRAM device timing register for write configuration, if extended mode is used */ 00370 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) 00371 { 00372 /* Check the parameters */ 00373 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); 00374 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime )); 00375 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime )); 00376 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime )); 00377 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration )); 00378 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode )); 00379 assert_param(IS_FMC_NORSRAM_BANK(Bank)); 00380 00381 /* Set NORSRAM device timing register for write configuration, if extended mode is used */ 00382 MODIFY_REG(Device->BWTR[Bank], \ 00383 BWTRx_CLEAR_MASK, \ 00384 (uint32_t)(Timing->AddressSetupTime |\ 00385 ((Timing->AddressHoldTime ) << POSITION_VAL(FMC_BTRx_ADDHLD)) |\ 00386 ((Timing->DataSetupTime ) << POSITION_VAL(FMC_BTRx_DATAST)) |\ 00387 ((Timing->BusTurnAroundDuration ) << POSITION_VAL(FMC_BWTRx_BUSTURN)) | \ 00388 (Timing->AccessMode ))); 00389 } 00390 else 00391 { 00392 Device->BWTR[Bank] = 0x0FFFFFFF; 00393 } 00394 00395 return HAL_OK; 00396 } 00397 00398 00399 /** 00400 * @} 00401 */ 00402 00403 00404 /** @defgroup FMC_NORSRAM_Exported_Functions_Group2 Peripheral Control functions 00405 * @brief management functions 00406 * 00407 @verbatim 00408 ============================================================================== 00409 ##### FMC_NORSRAM Control functions ##### 00410 ============================================================================== 00411 [..] 00412 This subsection provides a set of functions allowing to control dynamically 00413 the FMC NORSRAM interface. 00414 00415 @endverbatim 00416 * @{ 00417 */ 00418 00419 /** 00420 * @brief Enables dynamically FMC_NORSRAM write operation. 00421 * @param Device: Pointer to NORSRAM device instance 00422 * @param Bank: NORSRAM bank number 00423 * @retval HAL status 00424 */ 00425 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) 00426 { 00427 /* Check the parameters */ 00428 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); 00429 assert_param(IS_FMC_NORSRAM_BANK(Bank)); 00430 00431 /* Enable write operation */ 00432 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); 00433 00434 return HAL_OK; 00435 } 00436 00437 /** 00438 * @brief Disables dynamically FMC_NORSRAM write operation. 00439 * @param Device: Pointer to NORSRAM device instance 00440 * @param Bank: NORSRAM bank number 00441 * @retval HAL status 00442 */ 00443 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) 00444 { 00445 /* Check the parameters */ 00446 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); 00447 assert_param(IS_FMC_NORSRAM_BANK(Bank)); 00448 00449 /* Disable write operation */ 00450 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); 00451 00452 return HAL_OK; 00453 } 00454 00455 /** 00456 * @} 00457 */ 00458 00459 /** 00460 * @} 00461 */ 00462 00463 /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions 00464 * @brief NAND Controller functions 00465 * 00466 @verbatim 00467 ============================================================================== 00468 ##### How to use NAND device driver ##### 00469 ============================================================================== 00470 [..] 00471 This driver contains a set of APIs to interface with the FMC NAND banks in order 00472 to run the NAND external devices. 00473 00474 (+) FMC NAND bank reset using the function FMC_NAND_DeInit() 00475 (+) FMC NAND bank control configuration using the function FMC_NAND_Init() 00476 (+) FMC NAND bank common space timing configuration using the function 00477 FMC_NAND_CommonSpace_Timing_Init() 00478 (+) FMC NAND bank attribute space timing configuration using the function 00479 FMC_NAND_AttributeSpace_Timing_Init() 00480 (+) FMC NAND bank enable/disable ECC correction feature using the functions 00481 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() 00482 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() 00483 00484 @endverbatim 00485 * @{ 00486 */ 00487 00488 /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00489 * @brief Initialization and Configuration functions 00490 * 00491 @verbatim 00492 ============================================================================== 00493 ##### Initialization and de-initialization functions ##### 00494 ============================================================================== 00495 [..] 00496 This section provides functions allowing to: 00497 (+) Initialize and configure the FMC NAND interface 00498 (+) De-initialize the FMC NAND interface 00499 (+) Configure the FMC clock and associated GPIOs 00500 00501 @endverbatim 00502 * @{ 00503 */ 00504 00505 /** 00506 * @brief Initializes the FMC_NAND device according to the specified 00507 * control parameters in the FMC_NAND_HandleTypeDef 00508 * @param Device: Pointer to NAND device instance 00509 * @param Init: Pointer to NAND Initialization structure 00510 * @retval HAL status 00511 */ 00512 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) 00513 { 00514 /* Check the parameters */ 00515 assert_param(IS_FMC_NAND_DEVICE(Device)); 00516 assert_param(IS_FMC_NAND_BANK(Init->NandBank )); 00517 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature )); 00518 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth )); 00519 assert_param(IS_FMC_ECC_STATE(Init->EccComputation )); 00520 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize )); 00521 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime )); 00522 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime )); 00523 00524 /* Set NAND device control parameters */ 00525 /* NAND bank 3 registers configuration */ 00526 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |\ 00527 FMC_PCR_MEMORY_TYPE_NAND |\ 00528 Init->MemoryDataWidth |\ 00529 Init->EccComputation |\ 00530 Init->ECCPageSize |\ 00531 ((Init->TCLRSetupTime ) << POSITION_VAL(FMC_PCR_TCLR)) |\ 00532 ((Init->TARSetupTime ) << POSITION_VAL(FMC_PCR_TAR)))); 00533 00534 return HAL_OK; 00535 00536 } 00537 00538 /** 00539 * @brief Initializes the FMC_NAND Common space Timing according to the specified 00540 * parameters in the FMC_NAND_PCC_TimingTypeDef 00541 * @param Device: Pointer to NAND device instance 00542 * @param Timing: Pointer to NAND timing structure 00543 * @param Bank: NAND bank number 00544 * @retval HAL status 00545 */ 00546 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) 00547 { 00548 /* Check the parameters */ 00549 assert_param(IS_FMC_NAND_DEVICE(Device)); 00550 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime )); 00551 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime )); 00552 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime )); 00553 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime )); 00554 assert_param(IS_FMC_NAND_BANK(Bank)); 00555 00556 /* Set FMC_NAND device timing parameters */ 00557 /* NAND bank 3 registers configuration */ 00558 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime |\ 00559 ((Timing->WaitSetupTime ) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\ 00560 ((Timing->HoldSetupTime ) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\ 00561 ((Timing->HiZSetupTime ) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); 00562 00563 return HAL_OK; 00564 } 00565 00566 /** 00567 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified 00568 * parameters in the FMC_NAND_PCC_TimingTypeDef 00569 * @param Device: Pointer to NAND device instance 00570 * @param Timing: Pointer to NAND timing structure 00571 * @param Bank: NAND bank number 00572 * @retval HAL status 00573 */ 00574 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) 00575 { 00576 /* Check the parameters */ 00577 assert_param(IS_FMC_NAND_DEVICE(Device)); 00578 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime )); 00579 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime )); 00580 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime )); 00581 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime )); 00582 assert_param(IS_FMC_NAND_BANK(Bank)); 00583 00584 /* Set FMC_NAND device timing parameters */ 00585 /* NAND bank 3 registers configuration */ 00586 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime |\ 00587 ((Timing->WaitSetupTime ) << POSITION_VAL(FMC_PMEM_MEMWAIT)) |\ 00588 ((Timing->HoldSetupTime ) << POSITION_VAL(FMC_PMEM_MEMHOLD)) |\ 00589 ((Timing->HiZSetupTime ) << POSITION_VAL(FMC_PMEM_MEMHIZ)))); 00590 00591 return HAL_OK; 00592 } 00593 00594 00595 /** 00596 * @brief DeInitialize the FMC_NAND device 00597 * @param Device: Pointer to NAND device instance 00598 * @param Bank: NAND bank number 00599 * @retval HAL status 00600 */ 00601 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) 00602 { 00603 /* Check the parameters */ 00604 assert_param(IS_FMC_NAND_DEVICE(Device)); 00605 assert_param(IS_FMC_NAND_BANK(Bank)); 00606 00607 /* Disable the NAND Bank */ 00608 __FMC_NAND_DISABLE(Device, Bank); 00609 00610 /* Set the FMC_NAND_BANK registers to their reset values */ 00611 WRITE_REG(Device->PCR, 0x00000018); 00612 WRITE_REG(Device->SR, 0x00000040); 00613 WRITE_REG(Device->PMEM, 0xFCFCFCFC); 00614 WRITE_REG(Device->PATT, 0xFCFCFCFC); 00615 00616 return HAL_OK; 00617 } 00618 00619 /** 00620 * @} 00621 */ 00622 00623 00624 /** @defgroup FMC_LL_NAND_Exported_Functions_Group2 FMC Low Layer Peripheral Control functions 00625 * @brief management functions 00626 * 00627 @verbatim 00628 ============================================================================== 00629 ##### FMC_NAND Control functions ##### 00630 ============================================================================== 00631 [..] 00632 This subsection provides a set of functions allowing to control dynamically 00633 the FMC NAND interface. 00634 00635 @endverbatim 00636 * @{ 00637 */ 00638 00639 00640 /** 00641 * @brief Enables dynamically FMC_NAND ECC feature. 00642 * @param Device: Pointer to NAND device instance 00643 * @param Bank: NAND bank number 00644 * @retval HAL status 00645 */ 00646 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) 00647 { 00648 /* Check the parameters */ 00649 assert_param(IS_FMC_NAND_DEVICE(Device)); 00650 assert_param(IS_FMC_NAND_BANK(Bank)); 00651 00652 /* Enable ECC feature */ 00653 SET_BIT(Device->PCR, FMC_PCR_ECCEN); 00654 00655 return HAL_OK; 00656 } 00657 00658 00659 /** 00660 * @brief Disables dynamically FMC_NAND ECC feature. 00661 * @param Device: Pointer to NAND device instance 00662 * @param Bank: NAND bank number 00663 * @retval HAL status 00664 */ 00665 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) 00666 { 00667 /* Check the parameters */ 00668 assert_param(IS_FMC_NAND_DEVICE(Device)); 00669 assert_param(IS_FMC_NAND_BANK(Bank)); 00670 00671 /* Disable ECC feature */ 00672 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); 00673 00674 return HAL_OK; 00675 } 00676 00677 /** 00678 * @brief Disables dynamically FMC_NAND ECC feature. 00679 * @param Device: Pointer to NAND device instance 00680 * @param ECCval: Pointer to ECC value 00681 * @param Bank: NAND bank number 00682 * @param Timeout: Timeout wait value 00683 * @retval HAL status 00684 */ 00685 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) 00686 { 00687 uint32_t tickstart = 0; 00688 00689 /* Check the parameters */ 00690 assert_param(IS_FMC_NAND_DEVICE(Device)); 00691 assert_param(IS_FMC_NAND_BANK(Bank)); 00692 00693 /* Get tick */ 00694 tickstart = HAL_GetTick(); 00695 00696 /* Wait until FIFO is empty */ 00697 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) 00698 { 00699 /* Check for the Timeout */ 00700 if(Timeout != HAL_MAX_DELAY) 00701 { 00702 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) 00703 { 00704 return HAL_TIMEOUT; 00705 } 00706 } 00707 } 00708 00709 /* Get the ECCR register value */ 00710 *ECCval = (uint32_t)Device->ECCR; 00711 00712 return HAL_OK; 00713 } 00714 00715 /** 00716 * @} 00717 */ 00718 00719 /** 00720 * @} 00721 */ 00722 00723 /** 00724 * @} 00725 */ 00726 00727 /** 00728 * @} 00729 */ 00730 00731 /** 00732 * @} 00733 */ 00734 00735 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED */ 00736 00737 /** 00738 * @} 00739 */ 00740 00741 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ 00742 00743 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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