stm32l4xx_ll_crs.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_ll_crs.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of CRS LL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_LL_CRS_H
00040 #define __STM32L4xx_LL_CRS_H
00041 
00042 #ifdef __cplusplus
00043 extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx.h"
00048 
00049 /** @addtogroup STM32L4xx_LL_Driver
00050   * @{
00051   */
00052 
00053 #if defined(CRS)
00054 
00055 /** @defgroup CRS_LL CRS
00056   * @{
00057   */
00058 
00059 /* Private types -------------------------------------------------------------*/
00060 /* Private variables ---------------------------------------------------------*/
00061 
00062 /* Private constants ---------------------------------------------------------*/
00063 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
00064   * @{
00065   */
00066 
00067 /* Defines used for the bit position in the register and perform offsets*/
00068 #define CRS_POSITION_TRIM        (uint32_t)POSITION_VAL(CRS_CR_TRIM)    /* bit position in CR reg */
00069 #define CRS_POSITION_FECAP       (uint32_t)POSITION_VAL(CRS_ISR_FECAP)  /* bit position in ISR reg */
00070 #define CRS_POSITION_FELIM       (uint32_t)POSITION_VAL(CRS_CFGR_FELIM) /* bit position in CFGR reg */
00071 
00072 
00073 /**
00074   * @}
00075   */
00076 
00077 /* Private macros ------------------------------------------------------------*/
00078 
00079 /* Exported types ------------------------------------------------------------*/
00080 /* Exported constants --------------------------------------------------------*/
00081 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
00082   * @{
00083   */
00084 
00085 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
00086   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
00087   * @{
00088   */
00089 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
00090 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
00091 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
00092 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
00093 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
00094 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
00095 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
00096 /**
00097   * @}
00098   */
00099 
00100 /** @defgroup CRS_LL_EC_IT IT Defines
00101   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
00102   * @{
00103   */
00104 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
00105 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
00106 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
00107 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
00108 /**
00109   * @}
00110   */
00111 
00112 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
00113   * @{
00114   */
00115 #define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
00116 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
00117 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
00118 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
00119 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
00120 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
00121 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
00122 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
00123 /**
00124   * @}
00125   */
00126 
00127 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
00128   * @{
00129   */
00130 #define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
00131 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
00132 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
00133 /**
00134   * @}
00135   */
00136 
00137 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
00138   * @{
00139   */
00140 #define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
00141 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
00142 /**
00143   * @}
00144   */
00145 
00146 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
00147   * @{
00148   */
00149 #define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
00150 #define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
00151 /**
00152   * @}
00153   */
00154 
00155 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
00156   * @{
00157   */
00158 /**
00159   * @brief Reset value of the RELOAD field
00160   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
00161   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
00162   */
00163 #define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)      
00164 
00165 /**
00166   * @brief Reset value of Frequency error limit.
00167   */
00168 #define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)      
00169 
00170 /**
00171   * @brief Reset value of the HSI48 Calibration field
00172   * @note The default value is 32, which corresponds to the middle of the trimming interval. 
00173   *       The trimming step is around 67 kHz between two consecutive TRIM steps. 
00174   *       A higher TRIM value corresponds to a higher output frequency
00175   */
00176 #define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20U)      
00177 /**
00178   * @}
00179   */ 
00180   
00181 /**
00182   * @}
00183   */
00184 
00185 /* Exported macro ------------------------------------------------------------*/
00186 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
00187   * @{
00188   */
00189 
00190 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
00191   * @{
00192   */
00193 
00194 /**
00195   * @brief  Write a value in CRS register
00196   * @param  __INSTANCE__ CRS Instance
00197   * @param  __REG__ Register to be written
00198   * @param  __VALUE__ Value to be written in the register
00199   * @retval None
00200   */
00201 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
00202 
00203 /**
00204   * @brief  Read a value in CRS register
00205   * @param  __INSTANCE__ CRS Instance
00206   * @param  __REG__ Register to be read
00207   * @retval Register value
00208   */
00209 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
00210 /**
00211   * @}
00212   */
00213 
00214 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
00215   * @{
00216   */
00217 
00218 /**
00219   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
00220   * @note   The RELOAD value should be selected according to the ratio between 
00221   *         the target frequency and the frequency of the synchronization source after
00222   *         prescaling. It is then decreased by one in order to reach the expected
00223   *         synchronization on the zero value. The formula is the following:
00224   *              RELOAD = (fTARGET / fSYNC) -1
00225   * @param  __FTARGET__ Target frequency (value in Hz)
00226   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
00227   * @retval Reload value (in Hz)
00228   */
00229 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
00230 
00231 /**
00232   * @}
00233   */
00234 
00235 /**
00236   * @}
00237   */
00238 
00239 /* Exported functions --------------------------------------------------------*/
00240 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
00241   * @{
00242   */
00243 
00244 /** @defgroup CRS_LL_EF_Configuration Configuration
00245   * @{
00246   */
00247 
00248 /**
00249   * @brief  Enable Frequency error counter
00250   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
00251   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
00252   * @retval None
00253   */
00254 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
00255 {
00256   SET_BIT(CRS->CR, CRS_CR_CEN);
00257 }
00258 
00259 /**
00260   * @brief  Disable Frequency error counter
00261   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
00262   * @retval None
00263   */
00264 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
00265 {
00266   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
00267 }
00268 
00269 /**
00270   * @brief  Check if Frequency error counter is enabled or not
00271   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
00272   * @retval State of bit (1 or 0).
00273   */
00274 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
00275 {
00276   return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
00277 }
00278 
00279 /**
00280   * @brief  Enable Automatic trimming counter
00281   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
00282   * @retval None
00283   */
00284 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
00285 {
00286   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00287 }
00288 
00289 /**
00290   * @brief  Disable Automatic trimming counter
00291   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
00292   * @retval None
00293   */
00294 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
00295 {
00296   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
00297 }
00298 
00299 /**
00300   * @brief  Check if Automatic trimming is enabled or not
00301   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
00302   * @retval State of bit (1 or 0).
00303   */
00304 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
00305 {
00306   return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
00307 }
00308 
00309 /**
00310   * @brief  Set HSI48 oscillator smooth trimming
00311   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
00312   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
00313   * @param  Value a number between Min_Data = 0 and Max_Data = 63
00314   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT 
00315   * @retval None
00316   */
00317 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
00318 {
00319   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
00320 }
00321 
00322 /**
00323   * @brief  Get HSI48 oscillator smooth trimming
00324   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
00325   * @retval a number between Min_Data = 0 and Max_Data = 63
00326   */
00327 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
00328 {
00329   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
00330 }
00331 
00332 /**
00333   * @brief  Set counter reload value
00334   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
00335   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
00336   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT 
00337   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
00338   * @retval None
00339   */
00340 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
00341 {
00342   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
00343 }
00344 
00345 /**
00346   * @brief  Get counter reload value
00347   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
00348   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
00349   */
00350 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
00351 {
00352   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
00353 }
00354 
00355 /**
00356   * @brief  Set frequency error limit
00357   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
00358   * @param  Value a number between Min_Data = 0 and Max_Data = 255
00359   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT 
00360   * @retval None
00361   */
00362 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
00363 {
00364   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
00365 }
00366 
00367 /**
00368   * @brief  Get frequency error limit
00369   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
00370   * @retval A number between Min_Data = 0 and Max_Data = 255
00371   */
00372 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
00373 {
00374   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
00375 }
00376 
00377 /**
00378   * @brief  Set division factor for SYNC signal
00379   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
00380   * @param  Divider This parameter can be one of the following values:
00381   *         @arg @ref LL_CRS_SYNC_DIV_1
00382   *         @arg @ref LL_CRS_SYNC_DIV_2
00383   *         @arg @ref LL_CRS_SYNC_DIV_4
00384   *         @arg @ref LL_CRS_SYNC_DIV_8
00385   *         @arg @ref LL_CRS_SYNC_DIV_16
00386   *         @arg @ref LL_CRS_SYNC_DIV_32
00387   *         @arg @ref LL_CRS_SYNC_DIV_64
00388   *         @arg @ref LL_CRS_SYNC_DIV_128
00389   * @retval None
00390   */
00391 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
00392 {
00393   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
00394 }
00395 
00396 /**
00397   * @brief  Get division factor for SYNC signal
00398   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
00399   * @retval Returned value can be one of the following values:
00400   *         @arg @ref LL_CRS_SYNC_DIV_1
00401   *         @arg @ref LL_CRS_SYNC_DIV_2
00402   *         @arg @ref LL_CRS_SYNC_DIV_4
00403   *         @arg @ref LL_CRS_SYNC_DIV_8
00404   *         @arg @ref LL_CRS_SYNC_DIV_16
00405   *         @arg @ref LL_CRS_SYNC_DIV_32
00406   *         @arg @ref LL_CRS_SYNC_DIV_64
00407   *         @arg @ref LL_CRS_SYNC_DIV_128
00408   */
00409 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
00410 {
00411   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
00412 }
00413 
00414 /**
00415   * @brief  Set SYNC signal source
00416   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
00417   * @param  Source This parameter can be one of the following values:
00418   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00419   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00420   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00421   * @retval None
00422   */
00423 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
00424 {
00425   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
00426 }
00427 
00428 /**
00429   * @brief  Get SYNC signal source
00430   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
00431   * @retval Returned value can be one of the following values:
00432   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
00433   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
00434   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
00435   */
00436 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
00437 {
00438   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
00439 }
00440 
00441 /**
00442   * @brief  Set input polarity for the SYNC signal source
00443   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
00444   * @param  Polarity This parameter can be one of the following values:
00445   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00446   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00447   * @retval None
00448   */
00449 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
00450 {
00451   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
00452 }
00453 
00454 /**
00455   * @brief  Get input polarity for the SYNC signal source
00456   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
00457   * @retval Returned value can be one of the following values:
00458   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
00459   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
00460   */
00461 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
00462 {
00463   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
00464 }
00465 
00466 /**
00467   * @brief  Configure CRS for the synchronization
00468   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
00469   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
00470   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
00471   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
00472   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
00473   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
00474   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
00475   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
00476   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
00477   * @param  Settings This parameter can be a combination of the following values:
00478   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
00479   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
00480   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
00481   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
00482   * @retval None
00483   */
00484 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
00485 {
00486   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
00487   MODIFY_REG(CRS->CFGR, 
00488              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 
00489              ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
00490 }
00491 
00492 /**
00493   * @}
00494   */
00495 
00496 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
00497   * @{
00498   */
00499 
00500 /**
00501   * @brief  Generate software SYNC event
00502   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
00503   * @retval None
00504   */
00505 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
00506 {
00507   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
00508 }
00509 
00510 /**
00511   * @brief  Get the frequency error direction latched in the time of the last 
00512   * SYNC event
00513   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
00514   * @retval Returned value can be one of the following values:
00515   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
00516   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
00517   */
00518 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
00519 {
00520   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
00521 }
00522 
00523 /**
00524   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
00525   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
00526   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
00527   */
00528 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
00529 {
00530   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
00531 }
00532 
00533 /**
00534   * @}
00535   */
00536 
00537 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
00538   * @{
00539   */
00540 
00541 /**
00542   * @brief  Check if SYNC event OK signal occurred or not
00543   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
00544   * @retval State of bit (1 or 0).
00545   */
00546 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
00547 {
00548   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
00549 }
00550 
00551 /**
00552   * @brief  Check if SYNC warning signal occurred or not
00553   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
00554   * @retval State of bit (1 or 0).
00555   */
00556 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
00557 {
00558   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
00559 }
00560 
00561 /**
00562   * @brief  Check if Synchronization or trimming error signal occurred or not
00563   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
00564   * @retval State of bit (1 or 0).
00565   */
00566 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
00567 {
00568   return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
00569 }
00570 
00571 /**
00572   * @brief  Check if Expected SYNC signal occurred or not
00573   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
00574   * @retval State of bit (1 or 0).
00575   */
00576 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
00577 {
00578   return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
00579 }
00580 
00581 /**
00582   * @brief  Check if SYNC error signal occurred or not
00583   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
00584   * @retval State of bit (1 or 0).
00585   */
00586 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
00587 {
00588   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
00589 }
00590 
00591 /**
00592   * @brief  Check if SYNC missed error signal occurred or not
00593   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
00594   * @retval State of bit (1 or 0).
00595   */
00596 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
00597 {
00598   return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
00599 }
00600 
00601 /**
00602   * @brief  Check if Trimming overflow or underflow occurred or not
00603   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
00604   * @retval State of bit (1 or 0).
00605   */
00606 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
00607 {
00608   return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
00609 }
00610 
00611 /**
00612   * @brief  Clear the SYNC event OK flag
00613   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
00614   * @retval None
00615   */
00616 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
00617 {
00618   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
00619 }
00620 
00621 /**
00622   * @brief  Clear the  SYNC warning flag
00623   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
00624   * @retval None
00625   */
00626 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
00627 {
00628   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
00629 }
00630 
00631 /**
00632   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also 
00633   * the ERR flag
00634   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
00635   * @retval None
00636   */
00637 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
00638 {
00639   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
00640 }
00641 
00642 /**
00643   * @brief  Clear Expected SYNC flag
00644   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
00645   * @retval None
00646   */
00647 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
00648 {
00649   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
00650 }
00651 
00652 /**
00653   * @}
00654   */
00655 
00656 /** @defgroup CRS_LL_EF_IT_Management IT_Management
00657   * @{
00658   */
00659 
00660 /**
00661   * @brief  Enable SYNC event OK interrupt
00662   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
00663   * @retval None
00664   */
00665 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
00666 {
00667   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00668 }
00669 
00670 /**
00671   * @brief  Disable SYNC event OK interrupt
00672   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
00673   * @retval None
00674   */
00675 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
00676 {
00677   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
00678 }
00679 
00680 /**
00681   * @brief  Check if SYNC event OK interrupt is enabled or not
00682   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
00683   * @retval State of bit (1 or 0).
00684   */
00685 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
00686 {
00687   return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
00688 }
00689 
00690 /**
00691   * @brief  Enable SYNC warning interrupt
00692   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
00693   * @retval None
00694   */
00695 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
00696 {
00697   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00698 }
00699 
00700 /**
00701   * @brief  Disable SYNC warning interrupt
00702   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
00703   * @retval None
00704   */
00705 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
00706 {
00707   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
00708 }
00709 
00710 /**
00711   * @brief  Check if SYNC warning interrupt is enabled or not
00712   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
00713   * @retval State of bit (1 or 0).
00714   */
00715 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
00716 {
00717   return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
00718 }
00719 
00720 /**
00721   * @brief  Enable Synchronization or trimming error interrupt
00722   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
00723   * @retval None
00724   */
00725 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
00726 {
00727   SET_BIT(CRS->CR, CRS_CR_ERRIE);
00728 }
00729 
00730 /**
00731   * @brief  Disable Synchronization or trimming error interrupt
00732   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
00733   * @retval None
00734   */
00735 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
00736 {
00737   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
00738 }
00739 
00740 /**
00741   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
00742   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
00743   * @retval State of bit (1 or 0).
00744   */
00745 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
00746 {
00747   return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
00748 }
00749 
00750 /**
00751   * @brief  Enable Expected SYNC interrupt
00752   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
00753   * @retval None
00754   */
00755 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
00756 {
00757   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
00758 }
00759 
00760 /**
00761   * @brief  Disable Expected SYNC interrupt
00762   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
00763   * @retval None
00764   */
00765 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
00766 {
00767   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
00768 }
00769 
00770 /**
00771   * @brief  Check if Expected SYNC interrupt is enabled or not
00772   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
00773   * @retval State of bit (1 or 0).
00774   */
00775 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
00776 {
00777   return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
00778 }
00779 
00780 /**
00781   * @}
00782   */
00783 
00784 #if defined(USE_FULL_LL_DRIVER)
00785 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
00786   * @{
00787   */
00788   
00789 ErrorStatus LL_CRS_DeInit(void);
00790 
00791 /**
00792   * @}
00793   */
00794 #endif /* USE_FULL_LL_DRIVER */
00795 
00796 /**
00797   * @}
00798   */
00799 
00800 /**
00801   * @}
00802   */
00803 
00804 #endif /* defined(CRS) */
00805 
00806 /**
00807   * @}
00808   */
00809 
00810 #ifdef __cplusplus
00811 }
00812 #endif
00813 
00814 #endif /* __STM32L4xx_LL_CRS_H */
00815 
00816 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/