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stm32l4xx_ll_bus.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of BUS LL module. 00008 00009 @verbatim 00010 ##### RCC Limitations ##### 00011 ============================================================================== 00012 [..] 00013 A delay between an RCC peripheral clock enable and the effective peripheral 00014 enabling should be taken into account in order to manage the peripheral read/write 00015 from/to registers. 00016 (+) This delay depends on the peripheral mapping. 00017 (++) AHB & APB peripherals, 1 dummy read is necessary 00018 00019 [..] 00020 Workarounds: 00021 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00022 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00023 00024 @endverbatim 00025 ****************************************************************************** 00026 * @attention 00027 * 00028 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00029 * 00030 * Redistribution and use in source and binary forms, with or without modification, 00031 * are permitted provided that the following conditions are met: 00032 * 1. Redistributions of source code must retain the above copyright notice, 00033 * this list of conditions and the following disclaimer. 00034 * 2. Redistributions in binary form must reproduce the above copyright notice, 00035 * this list of conditions and the following disclaimer in the documentation 00036 * and/or other materials provided with the distribution. 00037 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00038 * may be used to endorse or promote products derived from this software 00039 * without specific prior written permission. 00040 * 00041 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00042 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00043 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00044 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00045 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00046 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00047 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00048 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00049 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00050 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00051 * 00052 ****************************************************************************** 00053 */ 00054 00055 /* Define to prevent recursive inclusion -------------------------------------*/ 00056 #ifndef __STM32L4xx_LL_BUS_H 00057 #define __STM32L4xx_LL_BUS_H 00058 00059 #ifdef __cplusplus 00060 extern "C" { 00061 #endif 00062 00063 /* Includes ------------------------------------------------------------------*/ 00064 #include "stm32l4xx.h" 00065 00066 /** @addtogroup STM32L4xx_LL_Driver 00067 * @{ 00068 */ 00069 00070 #if defined(RCC) 00071 00072 /** @defgroup BUS_LL BUS 00073 * @{ 00074 */ 00075 00076 /* Private types -------------------------------------------------------------*/ 00077 /* Private variables ---------------------------------------------------------*/ 00078 00079 /* Private constants ---------------------------------------------------------*/ 00080 00081 /* Private macros ------------------------------------------------------------*/ 00082 00083 /* Exported types ------------------------------------------------------------*/ 00084 /* Exported constants --------------------------------------------------------*/ 00085 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00086 * @{ 00087 */ 00088 00089 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00090 * @{ 00091 */ 00092 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00093 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00094 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00095 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN 00096 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00097 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN 00098 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN 00099 /** 00100 * @} 00101 */ 00102 00103 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00104 * @{ 00105 */ 00106 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN 00107 #define LL_AHB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00108 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN 00109 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN 00110 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN 00111 #if defined(GPIOD) 00112 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN 00113 #endif /*GPIOD*/ 00114 #if defined(GPIOE) 00115 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN 00116 #endif /*GPIOE*/ 00117 #if defined(GPIOF) 00118 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN 00119 #endif /* GPIOF */ 00120 #if defined(GPIOG) 00121 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN 00122 #endif /* GPIOG */ 00123 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN 00124 #if defined(USB_OTG_FS) 00125 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 00126 #endif /* USB_OTG_FS */ 00127 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN 00128 #if defined(AES) 00129 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00130 #endif /* AES */ 00131 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00132 /** 00133 * @} 00134 */ 00135 00136 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00137 * @{ 00138 */ 00139 #define LL_AHB3_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00140 #if defined(FMC_Bank1_R) 00141 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00142 #endif /* FMC_Bank1_R */ 00143 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00149 * @{ 00150 */ 00151 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00152 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN 00153 #if defined(TIM3) 00154 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN 00155 #endif /* TIM3 */ 00156 #if defined(TIM4) 00157 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN 00158 #endif /* TIM4 */ 00159 #if defined(TIM5) 00160 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN 00161 #endif /* TIM5 */ 00162 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN 00163 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN 00164 #if defined(LCD) 00165 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN 00166 #endif /* LCD */ 00167 #if defined(RCC_APB1ENR1_RTCAPBEN) 00168 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN 00169 #endif /* RCC_APB1ENR1_RTCAPBEN */ 00170 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN 00171 #if defined(SPI2) 00172 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN 00173 #endif /* SPI2 */ 00174 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN 00175 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN 00176 #if defined(USART3) 00177 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN 00178 #endif /* USART3 */ 00179 #if defined(UART4) 00180 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN 00181 #endif /* UART4 */ 00182 #if defined(UART5) 00183 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN 00184 #endif /* UART5 */ 00185 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN 00186 #if defined(I2C2) 00187 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN 00188 #endif /* I2C2 */ 00189 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN 00190 #if defined(CRS) 00191 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN 00192 #endif /* CRS */ 00193 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN 00194 #if defined(USB) 00195 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN 00196 #endif /* USB */ 00197 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN 00198 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN 00199 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN 00200 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN 00201 /** 00202 * @} 00203 */ 00204 00205 00206 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH 00207 * @{ 00208 */ 00209 #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00210 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN 00211 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN 00212 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00218 * @{ 00219 */ 00220 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00221 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 00222 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN 00223 #if defined(SDMMC1) 00224 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 00225 #endif /* SDMMC1 */ 00226 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00227 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00228 #if defined(TIM8) 00229 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00230 #endif /* TIM8 */ 00231 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00232 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 00233 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 00234 #if defined(TIM17) 00235 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 00236 #endif /* TIM17 */ 00237 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00238 #if defined(SAI2) 00239 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00240 #endif /* SAI2 */ 00241 #if defined(DFSDM1_Channel0) 00242 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 00243 #endif /* DFSDM1_Channel0 */ 00244 /** 00245 * @} 00246 */ 00247 00248 /** Legacy definitions for compatibility purpose 00249 @cond 0 00250 */ 00251 #if defined(DFSDM1_Channel0) 00252 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1 00253 #endif /* DFSDM1_Channel0 */ 00254 /** 00255 @endcond 00256 */ 00257 00258 /** 00259 * @} 00260 */ 00261 00262 /* Exported macro ------------------------------------------------------------*/ 00263 /* Exported functions --------------------------------------------------------*/ 00264 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00265 * @{ 00266 */ 00267 00268 /** @defgroup BUS_LL_EF_AHB1 AHB1 00269 * @{ 00270 */ 00271 00272 /** 00273 * @brief Enable AHB1 peripherals clock. 00274 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00275 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00276 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n 00277 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 00278 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock 00279 * @param Periphs This parameter can be a combination of the following values: 00280 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00281 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00282 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00283 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00284 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00285 * 00286 * @retval None 00287 */ 00288 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00289 { 00290 __IO uint32_t tmpreg; 00291 SET_BIT(RCC->AHB1ENR, Periphs); 00292 /* Delay after an RCC peripheral clock enabling */ 00293 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 00294 (void)tmpreg; 00295 } 00296 00297 /** 00298 * @brief Check if AHB1 peripheral clock is enabled or not 00299 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00300 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00301 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n 00302 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00303 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock 00304 * @param Periphs This parameter can be a combination of the following values: 00305 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00306 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00307 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00308 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00309 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00310 * 00311 * @retval State of Periphs (1 or 0). 00312 */ 00313 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00314 { 00315 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 00316 } 00317 00318 /** 00319 * @brief Disable AHB1 peripherals clock. 00320 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00321 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00322 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n 00323 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 00324 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock 00325 * @param Periphs This parameter can be a combination of the following values: 00326 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00327 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00328 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00329 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00330 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00331 * 00332 * @retval None 00333 */ 00334 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00335 { 00336 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00337 } 00338 00339 /** 00340 * @brief Force AHB1 peripherals reset. 00341 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00342 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00343 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n 00344 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 00345 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset 00346 * @param Periphs This parameter can be a combination of the following values: 00347 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00348 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00349 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00351 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00352 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00353 * 00354 * @retval None 00355 */ 00356 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00357 { 00358 SET_BIT(RCC->AHB1RSTR, Periphs); 00359 } 00360 00361 /** 00362 * @brief Release AHB1 peripherals reset. 00363 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00364 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00365 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n 00366 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 00367 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset 00368 * @param Periphs This parameter can be a combination of the following values: 00369 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00370 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00371 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00372 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00373 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00374 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00375 * 00376 * @retval None 00377 */ 00378 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00379 { 00380 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 00381 } 00382 00383 /** 00384 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes 00385 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00386 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00387 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00388 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00389 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00390 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep 00391 * @param Periphs This parameter can be a combination of the following values: 00392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00393 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00394 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00395 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00396 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00397 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00398 * 00399 * @retval None 00400 */ 00401 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 00402 { 00403 __IO uint32_t tmpreg; 00404 SET_BIT(RCC->AHB1SMENR, Periphs); 00405 /* Delay after an RCC peripheral clock enabling */ 00406 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); 00407 (void)tmpreg; 00408 } 00409 00410 /** 00411 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes 00412 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00413 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00414 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00415 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00416 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00417 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep 00418 * @param Periphs This parameter can be a combination of the following values: 00419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00420 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00421 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00422 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00423 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00424 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00425 * 00426 * @retval None 00427 */ 00428 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 00429 { 00430 CLEAR_BIT(RCC->AHB1SMENR, Periphs); 00431 } 00432 00433 /** 00434 * @} 00435 */ 00436 00437 /** @defgroup BUS_LL_EF_AHB2 AHB2 00438 * @{ 00439 */ 00440 00441 /** 00442 * @brief Enable AHB2 peripherals clock. 00443 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n 00444 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n 00445 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n 00446 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n 00447 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n 00448 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n 00449 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n 00450 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n 00451 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n 00452 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n 00453 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 00454 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock 00455 * @param Periphs This parameter can be a combination of the following values: 00456 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00457 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00458 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00459 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00460 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00461 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00462 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00463 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00464 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00465 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00466 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00467 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00468 * 00469 * (*) value not defined in all devices. 00470 * @retval None 00471 */ 00472 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 00473 { 00474 __IO uint32_t tmpreg; 00475 SET_BIT(RCC->AHB2ENR, Periphs); 00476 /* Delay after an RCC peripheral clock enabling */ 00477 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 00478 (void)tmpreg; 00479 } 00480 00481 /** 00482 * @brief Check if AHB2 peripheral clock is enabled or not 00483 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n 00484 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n 00485 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n 00486 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n 00487 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n 00488 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n 00489 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n 00490 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n 00491 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n 00492 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n 00493 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 00494 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock 00495 * @param Periphs This parameter can be a combination of the following values: 00496 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00497 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00498 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00499 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00500 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00501 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00502 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00503 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00504 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00505 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00506 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00507 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00508 * 00509 * (*) value not defined in all devices. 00510 * @retval State of Periphs (1 or 0). 00511 */ 00512 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 00513 { 00514 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 00515 } 00516 00517 /** 00518 * @brief Disable AHB2 peripherals clock. 00519 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n 00520 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n 00521 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n 00522 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n 00523 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n 00524 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n 00525 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n 00526 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n 00527 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n 00528 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n 00529 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 00530 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock 00531 * @param Periphs This parameter can be a combination of the following values: 00532 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00533 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00534 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00535 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00536 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00537 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00538 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00539 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00540 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00541 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00542 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00543 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00544 * 00545 * (*) value not defined in all devices. 00546 * @retval None 00547 */ 00548 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 00549 { 00550 CLEAR_BIT(RCC->AHB2ENR, Periphs); 00551 } 00552 00553 /** 00554 * @brief Force AHB2 peripherals reset. 00555 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n 00556 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n 00557 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n 00558 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n 00559 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n 00560 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n 00561 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n 00562 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n 00563 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n 00564 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n 00565 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 00566 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset 00567 * @param Periphs This parameter can be a combination of the following values: 00568 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00569 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00570 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00571 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00572 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00573 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00574 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00575 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00576 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00577 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00578 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00579 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00580 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00581 * 00582 * (*) value not defined in all devices. 00583 * @retval None 00584 */ 00585 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 00586 { 00587 SET_BIT(RCC->AHB2RSTR, Periphs); 00588 } 00589 00590 /** 00591 * @brief Release AHB2 peripherals reset. 00592 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n 00593 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n 00594 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n 00595 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n 00596 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n 00597 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n 00598 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n 00599 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n 00600 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n 00601 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n 00602 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 00603 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset 00604 * @param Periphs This parameter can be a combination of the following values: 00605 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00606 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00607 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00611 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00612 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00613 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00614 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00615 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00616 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00617 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00618 * 00619 * (*) value not defined in all devices. 00620 * @retval None 00621 */ 00622 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 00623 { 00624 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 00625 } 00626 00627 /** 00628 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes 00629 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00630 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00631 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00632 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00633 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00634 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00635 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00636 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00637 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00638 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00639 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00640 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00641 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep 00642 * @param Periphs This parameter can be a combination of the following values: 00643 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00644 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00645 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00646 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00647 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00648 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00649 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00650 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00651 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00652 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00653 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00654 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00655 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00656 * 00657 * (*) value not defined in all devices. 00658 * @retval None 00659 */ 00660 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 00661 { 00662 __IO uint32_t tmpreg; 00663 SET_BIT(RCC->AHB2SMENR, Periphs); 00664 /* Delay after an RCC peripheral clock enabling */ 00665 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); 00666 (void)tmpreg; 00667 } 00668 00669 /** 00670 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes 00671 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00672 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00673 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00674 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00675 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00676 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00677 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00678 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00679 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00680 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00681 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00682 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00683 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep 00684 * @param Periphs This parameter can be a combination of the following values: 00685 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00686 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00687 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00688 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00689 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00690 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00691 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00692 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00693 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00694 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00695 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00696 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00697 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00698 * 00699 * (*) value not defined in all devices. 00700 * @retval None 00701 */ 00702 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 00703 { 00704 CLEAR_BIT(RCC->AHB2SMENR, Periphs); 00705 } 00706 00707 /** 00708 * @} 00709 */ 00710 00711 /** @defgroup BUS_LL_EF_AHB3 AHB3 00712 * @{ 00713 */ 00714 00715 /** 00716 * @brief Enable AHB3 peripherals clock. 00717 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00718 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock 00719 * @param Periphs This parameter can be a combination of the following values: 00720 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00721 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00722 * 00723 * (*) value not defined in all devices. 00724 * @retval None 00725 */ 00726 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 00727 { 00728 __IO uint32_t tmpreg; 00729 SET_BIT(RCC->AHB3ENR, Periphs); 00730 /* Delay after an RCC peripheral clock enabling */ 00731 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 00732 (void)tmpreg; 00733 } 00734 00735 /** 00736 * @brief Check if AHB3 peripheral clock is enabled or not 00737 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 00738 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock 00739 * @param Periphs This parameter can be a combination of the following values: 00740 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00741 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00742 * 00743 * (*) value not defined in all devices. 00744 * @retval State of Periphs (1 or 0). 00745 */ 00746 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 00747 { 00748 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 00749 } 00750 00751 /** 00752 * @brief Disable AHB3 peripherals clock. 00753 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 00754 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock 00755 * @param Periphs This parameter can be a combination of the following values: 00756 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00757 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00758 * 00759 * (*) value not defined in all devices. 00760 * @retval None 00761 */ 00762 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 00763 { 00764 CLEAR_BIT(RCC->AHB3ENR, Periphs); 00765 } 00766 00767 /** 00768 * @brief Force AHB3 peripherals reset. 00769 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 00770 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset 00771 * @param Periphs This parameter can be a combination of the following values: 00772 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 00773 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00774 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00775 * 00776 * (*) value not defined in all devices. 00777 * @retval None 00778 */ 00779 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 00780 { 00781 SET_BIT(RCC->AHB3RSTR, Periphs); 00782 } 00783 00784 /** 00785 * @brief Release AHB3 peripherals reset. 00786 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 00787 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset 00788 * @param Periphs This parameter can be a combination of the following values: 00789 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00790 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00791 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00792 * 00793 * (*) value not defined in all devices. 00794 * @retval None 00795 */ 00796 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 00797 { 00798 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 00799 } 00800 00801 /** 00802 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes 00803 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00804 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep 00805 * @param Periphs This parameter can be a combination of the following values: 00806 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00807 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00808 * 00809 * (*) value not defined in all devices. 00810 * @retval None 00811 */ 00812 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) 00813 { 00814 __IO uint32_t tmpreg; 00815 SET_BIT(RCC->AHB3SMENR, Periphs); 00816 /* Delay after an RCC peripheral clock enabling */ 00817 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); 00818 (void)tmpreg; 00819 } 00820 00821 /** 00822 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes 00823 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n 00824 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep 00825 * @param Periphs This parameter can be a combination of the following values: 00826 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00827 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI 00828 * 00829 * (*) value not defined in all devices. 00830 * @retval None 00831 */ 00832 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) 00833 { 00834 CLEAR_BIT(RCC->AHB3SMENR, Periphs); 00835 } 00836 00837 /** 00838 * @} 00839 */ 00840 00841 /** @defgroup BUS_LL_EF_APB1 APB1 00842 * @{ 00843 */ 00844 00845 /** 00846 * @brief Enable APB1 peripherals clock. 00847 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n 00848 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n 00849 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n 00850 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n 00851 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n 00852 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n 00853 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n 00854 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n 00855 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n 00856 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n 00857 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n 00858 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n 00859 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n 00860 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n 00861 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n 00862 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n 00863 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n 00864 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n 00865 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n 00866 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n 00867 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n 00868 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n 00869 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n 00870 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock 00871 * @param Periphs This parameter can be a combination of the following values: 00872 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00873 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 00874 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00875 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00876 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 00877 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 00878 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 00879 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 00880 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00881 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00882 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 00883 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00884 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00885 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00886 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00887 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00888 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00889 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 00890 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 00891 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 00892 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00893 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00894 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 00895 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 00896 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 00897 * 00898 * (*) value not defined in all devices. 00899 * @retval None 00900 */ 00901 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 00902 { 00903 __IO uint32_t tmpreg; 00904 SET_BIT(RCC->APB1ENR1, Periphs); 00905 /* Delay after an RCC peripheral clock enabling */ 00906 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 00907 (void)tmpreg; 00908 } 00909 00910 /** 00911 * @brief Enable APB1 peripherals clock. 00912 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n 00913 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n 00914 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock 00915 * @param Periphs This parameter can be a combination of the following values: 00916 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 00917 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 00918 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 00919 * @retval None 00920 */ 00921 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) 00922 { 00923 __IO uint32_t tmpreg; 00924 SET_BIT(RCC->APB1ENR2, Periphs); 00925 /* Delay after an RCC peripheral clock enabling */ 00926 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); 00927 (void)tmpreg; 00928 } 00929 00930 /** 00931 * @brief Check if APB1 peripheral clock is enabled or not 00932 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n 00933 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n 00934 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n 00935 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n 00936 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n 00937 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n 00938 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n 00939 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n 00940 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n 00941 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n 00942 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n 00943 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n 00944 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n 00945 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n 00946 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n 00947 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n 00948 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n 00949 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n 00950 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n 00951 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n 00952 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n 00953 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n 00954 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n 00955 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock 00956 * @param Periphs This parameter can be a combination of the following values: 00957 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00958 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 00959 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00960 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00961 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 00962 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 00963 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 00964 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 00965 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00966 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00967 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 00968 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00969 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00970 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00971 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00972 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00973 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00974 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 00975 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 00976 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 00977 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00978 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00979 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 00980 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 00981 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 00982 * 00983 * (*) value not defined in all devices. 00984 * @retval State of Periphs (1 or 0). 00985 */ 00986 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 00987 { 00988 return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs); 00989 } 00990 00991 /** 00992 * @brief Check if APB1 peripheral clock is enabled or not 00993 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n 00994 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n 00995 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock 00996 * @param Periphs This parameter can be a combination of the following values: 00997 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 00998 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 00999 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01000 * @retval State of Periphs (1 or 0). 01001 */ 01002 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 01003 { 01004 return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs); 01005 } 01006 01007 /** 01008 * @brief Disable APB1 peripherals clock. 01009 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n 01010 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n 01011 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n 01012 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n 01013 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n 01014 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n 01015 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n 01016 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n 01017 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n 01018 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n 01019 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n 01020 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n 01021 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n 01022 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n 01023 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n 01024 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n 01025 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n 01026 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n 01027 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n 01028 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n 01029 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n 01030 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n 01031 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n 01032 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock 01033 * @param Periphs This parameter can be a combination of the following values: 01034 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01035 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01036 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01037 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01038 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01039 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01040 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01041 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01042 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01043 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01044 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01045 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01046 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01047 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01048 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01049 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01050 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01051 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01052 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01053 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01054 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01055 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01056 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01057 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01058 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01059 * 01060 * (*) value not defined in all devices. 01061 * @retval None 01062 */ 01063 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 01064 { 01065 CLEAR_BIT(RCC->APB1ENR1, Periphs); 01066 } 01067 01068 /** 01069 * @brief Disable APB1 peripherals clock. 01070 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n 01071 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n 01072 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock 01073 * @param Periphs This parameter can be a combination of the following values: 01074 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01075 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01076 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01077 * @retval None 01078 */ 01079 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) 01080 { 01081 CLEAR_BIT(RCC->APB1ENR2, Periphs); 01082 } 01083 01084 /** 01085 * @brief Force APB1 peripherals reset. 01086 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n 01087 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n 01088 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n 01089 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n 01090 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n 01091 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n 01092 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n 01093 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n 01094 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n 01095 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n 01096 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n 01097 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n 01098 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n 01099 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n 01100 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n 01101 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n 01102 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n 01103 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n 01104 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n 01105 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n 01106 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n 01107 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset 01108 * @param Periphs This parameter can be a combination of the following values: 01109 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01110 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01111 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01112 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01113 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01114 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01115 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01116 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01117 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01118 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01119 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01120 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01121 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01122 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01123 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01124 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01125 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01126 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01127 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01128 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01129 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01130 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01131 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01132 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01133 * 01134 * (*) value not defined in all devices. 01135 * @retval None 01136 */ 01137 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 01138 { 01139 SET_BIT(RCC->APB1RSTR1, Periphs); 01140 } 01141 01142 /** 01143 * @brief Force APB1 peripherals reset. 01144 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n 01145 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n 01146 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset 01147 * @param Periphs This parameter can be a combination of the following values: 01148 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01149 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01150 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01151 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01152 * @retval None 01153 */ 01154 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) 01155 { 01156 SET_BIT(RCC->APB1RSTR2, Periphs); 01157 } 01158 01159 /** 01160 * @brief Release APB1 peripherals reset. 01161 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n 01162 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n 01163 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n 01164 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n 01165 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n 01166 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n 01167 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n 01168 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n 01169 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n 01170 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n 01171 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n 01172 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n 01173 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n 01174 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n 01175 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n 01176 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n 01177 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n 01178 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n 01179 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n 01180 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n 01181 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n 01182 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset 01183 * @param Periphs This parameter can be a combination of the following values: 01184 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01185 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01186 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01187 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01188 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01189 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01190 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01191 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01192 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01193 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01194 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01195 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01196 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01197 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01198 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01199 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01200 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01201 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01202 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01203 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01204 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01205 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01206 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01207 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01208 * 01209 * (*) value not defined in all devices. 01210 * @retval None 01211 */ 01212 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 01213 { 01214 CLEAR_BIT(RCC->APB1RSTR1, Periphs); 01215 } 01216 01217 /** 01218 * @brief Release APB1 peripherals reset. 01219 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n 01220 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n 01221 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset 01222 * @param Periphs This parameter can be a combination of the following values: 01223 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01224 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01225 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01226 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01227 * @retval None 01228 */ 01229 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) 01230 { 01231 CLEAR_BIT(RCC->APB1RSTR2, Periphs); 01232 } 01233 01234 /** 01235 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01236 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01237 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01238 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01239 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01240 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01241 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01242 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01243 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01244 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01245 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01246 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01247 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01248 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01249 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01250 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01251 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01252 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01253 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01254 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01255 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01256 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01257 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01258 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01259 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep 01260 * @param Periphs This parameter can be a combination of the following values: 01261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01265 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01266 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01267 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01268 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01269 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01270 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01271 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01272 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01273 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01274 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01275 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01276 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01277 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01278 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01279 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01280 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01281 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01282 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01283 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01284 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01285 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01286 * 01287 * (*) value not defined in all devices. 01288 * @retval None 01289 */ 01290 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 01291 { 01292 __IO uint32_t tmpreg; 01293 SET_BIT(RCC->APB1SMENR1, Periphs); 01294 /* Delay after an RCC peripheral clock enabling */ 01295 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); 01296 (void)tmpreg; 01297 } 01298 01299 /** 01300 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01301 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01302 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01303 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep 01304 * @param Periphs This parameter can be a combination of the following values: 01305 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01306 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01307 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01308 * @retval None 01309 */ 01310 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) 01311 { 01312 __IO uint32_t tmpreg; 01313 SET_BIT(RCC->APB1SMENR2, Periphs); 01314 /* Delay after an RCC peripheral clock enabling */ 01315 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); 01316 (void)tmpreg; 01317 } 01318 01319 /** 01320 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01321 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01322 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01323 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01324 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01325 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01326 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01327 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01328 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01329 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01330 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01331 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01332 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01333 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01334 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01335 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01336 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01337 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01338 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01339 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01340 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01341 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01342 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01343 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01344 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep 01345 * @param Periphs This parameter can be a combination of the following values: 01346 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01347 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01348 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01349 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01350 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01351 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01352 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01353 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01354 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01355 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01356 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01357 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01358 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01359 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01360 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01361 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01362 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01363 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01364 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01365 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01366 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01367 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01368 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01369 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01370 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01371 * 01372 * (*) value not defined in all devices. 01373 * @retval None 01374 */ 01375 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 01376 { 01377 CLEAR_BIT(RCC->APB1SMENR1, Periphs); 01378 } 01379 01380 /** 01381 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01382 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01383 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01384 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep 01385 * @param Periphs This parameter can be a combination of the following values: 01386 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01387 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 01388 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01389 * @retval None 01390 */ 01391 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) 01392 { 01393 CLEAR_BIT(RCC->APB1SMENR2, Periphs); 01394 } 01395 01396 /** 01397 * @} 01398 */ 01399 01400 /** @defgroup BUS_LL_EF_APB2 APB2 01401 * @{ 01402 */ 01403 01404 /** 01405 * @brief Enable APB2 peripherals clock. 01406 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 01407 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n 01408 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 01409 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 01410 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 01411 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 01412 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 01413 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 01414 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 01415 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 01416 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 01417 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 01418 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock 01419 * @param Periphs This parameter can be a combination of the following values: 01420 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01421 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01422 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01423 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01424 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01425 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01426 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01427 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01428 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01429 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01430 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01431 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01432 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01433 * 01434 * (*) value not defined in all devices. 01435 * @retval None 01436 */ 01437 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 01438 { 01439 __IO uint32_t tmpreg; 01440 SET_BIT(RCC->APB2ENR, Periphs); 01441 /* Delay after an RCC peripheral clock enabling */ 01442 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 01443 (void)tmpreg; 01444 } 01445 01446 /** 01447 * @brief Check if APB2 peripheral clock is enabled or not 01448 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n 01449 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n 01450 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n 01451 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 01452 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 01453 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 01454 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 01455 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 01456 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 01457 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 01458 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 01459 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 01460 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock 01461 * @param Periphs This parameter can be a combination of the following values: 01462 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01463 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01464 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01465 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01466 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01467 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01468 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01469 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01470 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01471 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01472 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01473 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01474 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01475 * 01476 * (*) value not defined in all devices. 01477 * @retval State of Periphs (1 or 0). 01478 */ 01479 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 01480 { 01481 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); 01482 } 01483 01484 /** 01485 * @brief Disable APB2 peripherals clock. 01486 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n 01487 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n 01488 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 01489 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 01490 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 01491 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 01492 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 01493 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 01494 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 01495 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 01496 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 01497 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock 01498 * @param Periphs This parameter can be a combination of the following values: 01499 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01500 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01501 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01502 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01503 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01504 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01505 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01506 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01507 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01508 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01509 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01510 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01511 * 01512 * (*) value not defined in all devices. 01513 * @retval None 01514 */ 01515 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 01516 { 01517 CLEAR_BIT(RCC->APB2ENR, Periphs); 01518 } 01519 01520 /** 01521 * @brief Force APB2 peripherals reset. 01522 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n 01523 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n 01524 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 01525 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 01526 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 01527 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 01528 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 01529 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 01530 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 01531 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 01532 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 01533 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset 01534 * @param Periphs This parameter can be a combination of the following values: 01535 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01536 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01537 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01538 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01539 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01540 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01541 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01542 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01543 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01544 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01545 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01546 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01547 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01548 * 01549 * (*) value not defined in all devices. 01550 * @retval None 01551 */ 01552 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 01553 { 01554 SET_BIT(RCC->APB2RSTR, Periphs); 01555 } 01556 01557 /** 01558 * @brief Release APB2 peripherals reset. 01559 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n 01560 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n 01561 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 01562 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 01563 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 01564 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 01565 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 01566 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 01567 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 01568 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 01569 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 01570 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset 01571 * @param Periphs This parameter can be a combination of the following values: 01572 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01573 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01574 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01575 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01576 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01577 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01578 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01579 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01580 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01581 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01582 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01583 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01584 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01585 * 01586 * (*) value not defined in all devices. 01587 * @retval None 01588 */ 01589 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 01590 { 01591 CLEAR_BIT(RCC->APB2RSTR, Periphs); 01592 } 01593 01594 /** 01595 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes 01596 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n 01597 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01598 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01599 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01600 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01601 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01602 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01603 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01604 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01605 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01606 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01607 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep 01608 * @param Periphs This parameter can be a combination of the following values: 01609 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01610 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01611 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01612 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01613 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01614 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01615 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01616 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01617 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01618 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01619 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01620 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01621 * 01622 * (*) value not defined in all devices. 01623 * @retval None 01624 */ 01625 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 01626 { 01627 __IO uint32_t tmpreg; 01628 SET_BIT(RCC->APB2SMENR, Periphs); 01629 /* Delay after an RCC peripheral clock enabling */ 01630 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); 01631 (void)tmpreg; 01632 } 01633 01634 /** 01635 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes 01636 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n 01637 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01638 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01639 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01640 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01641 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01642 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01643 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01644 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01645 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01646 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01647 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep 01648 * @param Periphs This parameter can be a combination of the following values: 01649 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01650 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01651 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01652 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01653 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01654 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01658 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01659 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01660 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01661 * 01662 * (*) value not defined in all devices. 01663 * @retval None 01664 */ 01665 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 01666 { 01667 CLEAR_BIT(RCC->APB2SMENR, Periphs); 01668 } 01669 01670 /** 01671 * @} 01672 */ 01673 01674 01675 /** 01676 * @} 01677 */ 01678 01679 /** 01680 * @} 01681 */ 01682 01683 #endif /* defined(RCC) */ 01684 01685 /** 01686 * @} 01687 */ 01688 01689 #ifdef __cplusplus 01690 } 01691 #endif 01692 01693 #endif /* __STM32L4xx_LL_BUS_H */ 01694 01695 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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