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stm32l4xx_ll_adc.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_adc.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief ADC LL module driver 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 #if defined(USE_FULL_LL_DRIVER) 00038 00039 /* Includes ------------------------------------------------------------------*/ 00040 #include "stm32l4xx_ll_adc.h" 00041 #include "stm32l4xx_ll_bus.h" 00042 00043 #ifdef USE_FULL_ASSERT 00044 #include "stm32_assert.h" 00045 #else 00046 #define assert_param(expr) ((void)0U) 00047 #endif 00048 00049 /** @addtogroup STM32L4xx_LL_Driver 00050 * @{ 00051 */ 00052 00053 #if defined (ADC1) || defined (ADC2) || defined (ADC3) 00054 00055 /** @addtogroup ADC_LL ADC 00056 * @{ 00057 */ 00058 00059 /* Private types -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /* Private constants ---------------------------------------------------------*/ 00062 /** @addtogroup ADC_LL_Private_Constants 00063 * @{ 00064 */ 00065 00066 /* Definitions of ADC hardware constraints delays */ 00067 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ 00068 /* not timeout values: */ 00069 /* Timeout values for ADC operations are dependent to device clock */ 00070 /* configuration (system clock versus ADC clock), */ 00071 /* and therefore must be defined in user application. */ 00072 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ 00073 /* values definition. */ 00074 /* Note: ADC timeout values are defined here in CPU cycles to be independent */ 00075 /* of device clock setting. */ 00076 /* In user application, ADC timeout values should be defined with */ 00077 /* temporal values, in function of device clock settings. */ 00078 /* Highest ratio CPU clock frequency vs ADC clock frequency: */ 00079 /* - ADC clock from synchronous clock with AHB prescaler 512, */ 00080 /* APB prescaler 16, ADC prescaler 4. */ 00081 /* - ADC clock from asynchronous clock (PLLSAI) with prescaler 1, */ 00082 /* with highest ratio CPU clock frequency vs HSI clock frequency: */ 00083 /* CPU clock frequency max 72MHz, PLLSAI freq min 26MHz: ratio 4. */ 00084 /* Unit: CPU cycles. */ 00085 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) 00086 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) 00087 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) 00088 00089 /** 00090 * @} 00091 */ 00092 00093 /* Private macros ------------------------------------------------------------*/ 00094 00095 /** @addtogroup ADC_LL_Private_Macros 00096 * @{ 00097 */ 00098 00099 /* Check of parameters for configuration of ADC hierarchical scope: */ 00100 /* common to several ADC instances. */ 00101 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ 00102 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ 00103 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ 00104 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ 00105 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ 00106 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ 00107 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ 00108 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \ 00109 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \ 00110 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \ 00111 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \ 00112 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \ 00113 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \ 00114 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \ 00115 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \ 00116 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \ 00117 ) 00118 00119 /* Check of parameters for configuration of ADC hierarchical scope: */ 00120 /* ADC instance. */ 00121 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ 00122 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ 00123 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ 00124 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ 00125 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ 00126 ) 00127 00128 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ 00129 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ 00130 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ 00131 ) 00132 00133 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ 00134 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ 00135 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ 00136 ) 00137 00138 /* Check of parameters for configuration of ADC hierarchical scope: */ 00139 /* ADC group regular */ 00140 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ 00141 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ 00142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ 00143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ 00144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ 00145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ 00146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ 00147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ 00148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ 00149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ 00150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ 00151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ 00152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ 00153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ 00154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ 00155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \ 00156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \ 00157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ 00158 ) 00159 00160 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ 00161 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ 00162 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ 00163 ) 00164 00165 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ 00166 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ 00167 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ 00168 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ 00169 ) 00170 00171 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ 00172 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ 00173 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ 00174 ) 00175 00176 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ 00177 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ 00178 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ 00179 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ 00180 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ 00181 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ 00182 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ 00183 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ 00184 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ 00185 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ 00186 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ 00187 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ 00188 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ 00189 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ 00190 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ 00191 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ 00192 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ 00193 ) 00194 00195 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ 00196 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ 00197 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ 00198 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ 00199 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ 00200 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ 00201 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ 00202 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ 00203 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ 00204 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ 00205 ) 00206 00207 /* Check of parameters for configuration of ADC hierarchical scope: */ 00208 /* ADC group injected */ 00209 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ 00210 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ 00211 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ 00212 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ 00213 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ 00214 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ 00215 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ 00216 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \ 00217 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ 00218 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ 00219 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ 00220 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ 00221 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ 00222 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ 00223 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ 00224 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ 00225 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \ 00226 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ 00227 ) 00228 00229 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ 00230 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ 00231 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ 00232 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ 00233 ) 00234 00235 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ 00236 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ 00237 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ 00238 ) 00239 00240 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ 00241 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ 00242 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ 00243 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ 00244 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ 00245 ) 00246 00247 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ 00248 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ 00249 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ 00250 ) 00251 00252 #if defined(ADC_MULTIMODE_SUPPORT) 00253 /* Check of parameters for configuration of ADC hierarchical scope: */ 00254 /* multimode. */ 00255 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ 00256 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ 00257 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ 00258 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ 00259 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ 00260 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ 00261 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ 00262 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ 00263 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ 00264 ) 00265 00266 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ 00267 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ 00268 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ 00269 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ 00270 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ 00271 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \ 00272 ) 00273 00274 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ 00275 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ 00276 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ 00277 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ 00278 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ 00279 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ 00280 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ 00281 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ 00282 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ 00283 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ 00284 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ 00285 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ 00286 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ 00287 ) 00288 00289 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ 00290 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ 00291 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ 00292 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ 00293 ) 00294 00295 #endif /* ADC_MULTIMODE_SUPPORT */ 00296 /** 00297 * @} 00298 */ 00299 00300 00301 /* Private function prototypes -----------------------------------------------*/ 00302 00303 /* Exported functions --------------------------------------------------------*/ 00304 /** @addtogroup ADC_LL_Exported_Functions 00305 * @{ 00306 */ 00307 00308 /** @addtogroup ADC_LL_EF_Init 00309 * @{ 00310 */ 00311 00312 /** 00313 * @brief De-initialize registers of all ADC instances belonging to 00314 * the same ADC common instance to their default reset values. 00315 * @note This function is performing a hard reset, using high level 00316 * clock source RCC ADC reset. 00317 * Caution: On this STM32 serie, if several ADC instances are available 00318 * on the selected device, RCC ADC reset will reset 00319 * all ADC instances belonging to the common ADC instance. 00320 * To de-initialize only 1 ADC instance, use 00321 * function @ref LL_ADC_DeInit(). 00322 * @param ADCxy_COMMON ADC common instance 00323 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00324 * @retval An ErrorStatus enumeration value: 00325 * - SUCCESS: ADC common registers are de-initialized 00326 * - ERROR: not applicable 00327 */ 00328 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) 00329 { 00330 /* Check the parameters */ 00331 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00332 00333 /* Force reset of ADC clock (core clock) */ 00334 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC); 00335 00336 /* Release reset of ADC clock (core clock) */ 00337 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC); 00338 00339 return SUCCESS; 00340 } 00341 00342 /** 00343 * @brief Initialize some features of ADC common parameters 00344 * (all ADC instances belonging to the same ADC common instance) 00345 * and multimode (for devices with several ADC instances available). 00346 * @note The setting of ADC common parameters is conditioned to 00347 * ADC instances state: 00348 * All ADC instances belonging to the same ADC common instance 00349 * must be disabled. 00350 * @param ADCxy_COMMON ADC common instance 00351 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 00352 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00353 * @retval An ErrorStatus enumeration value: 00354 * - SUCCESS: ADC common registers are initialized 00355 * - ERROR: ADC common registers are not initialized 00356 */ 00357 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00358 { 00359 ErrorStatus status = SUCCESS; 00360 00361 /* Check the parameters */ 00362 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); 00363 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock )); 00364 00365 #if defined(ADC_MULTIMODE_SUPPORT) 00366 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode )); 00367 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00368 { 00369 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer )); 00370 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay )); 00371 } 00372 #endif /* ADC_MULTIMODE_SUPPORT */ 00373 00374 /* Note: Hardware constraint (refer to description of functions */ 00375 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ 00376 /* On this STM32 serie, setting of these features is conditioned to */ 00377 /* ADC state: */ 00378 /* All ADC instances of the ADC common group must be disabled. */ 00379 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) 00380 { 00381 /* Configuration of ADC hierarchical scope: */ 00382 /* - common to several ADC */ 00383 /* (all ADC instances belonging to the same ADC common instance) */ 00384 /* - Set ADC clock (conversion clock) */ 00385 /* - multimode (if several ADC instances available on the */ 00386 /* selected device) */ 00387 /* - Set ADC multimode configuration */ 00388 /* - Set ADC multimode DMA transfer */ 00389 /* - Set ADC multimode: delay between 2 sampling phases */ 00390 #if defined(ADC_MULTIMODE_SUPPORT) 00391 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) 00392 { 00393 MODIFY_REG(ADCxy_COMMON->CCR, 00394 ADC_CCR_CKMODE 00395 | ADC_CCR_PRESC 00396 | ADC_CCR_DUAL 00397 | ADC_CCR_MDMA 00398 | ADC_CCR_DELAY 00399 , 00400 ADC_CommonInitStruct->CommonClock 00401 | ADC_CommonInitStruct->Multimode 00402 | ADC_CommonInitStruct->MultiDMATransfer 00403 | ADC_CommonInitStruct->MultiTwoSamplingDelay 00404 ); 00405 } 00406 else 00407 { 00408 MODIFY_REG(ADCxy_COMMON->CCR, 00409 ADC_CCR_CKMODE 00410 | ADC_CCR_PRESC 00411 | ADC_CCR_DUAL 00412 | ADC_CCR_MDMA 00413 | ADC_CCR_DELAY 00414 , 00415 ADC_CommonInitStruct->CommonClock 00416 | LL_ADC_MULTI_INDEPENDENT 00417 ); 00418 } 00419 #else 00420 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock ); 00421 #endif 00422 } 00423 else 00424 { 00425 /* Initialization error: One or several ADC instances belonging to */ 00426 /* the same ADC common instance are not disabled. */ 00427 status = ERROR; 00428 } 00429 00430 return status; 00431 } 00432 00433 /** 00434 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. 00435 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure 00436 * whose fields will be set to default values. 00437 * @retval None 00438 */ 00439 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) 00440 { 00441 /* Set ADC_CommonInitStruct fields to default values */ 00442 /* Set fields of ADC common */ 00443 /* (all ADC instances belonging to the same ADC common instance) */ 00444 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; 00445 00446 #if defined(ADC_MULTIMODE_SUPPORT) 00447 /* Set fields of ADC multimode */ 00448 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; 00449 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; 00450 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE; 00451 #endif /* ADC_MULTIMODE_SUPPORT */ 00452 } 00453 00454 /** 00455 * @brief De-initialize registers of the selected ADC instance 00456 * to their default reset values. 00457 * @note To reset all ADC instances quickly (perform a hard reset), 00458 * use function @ref LL_ADC_CommonDeInit(). 00459 * @note If this functions returns error status, it means that ADC instance 00460 * is in an unknown state. 00461 * In this case, perform a hard reset using high level 00462 * clock source RCC ADC reset. 00463 * Caution: On this STM32 serie, if several ADC instances are available 00464 * on the selected device, RCC ADC reset will reset 00465 * all ADC instances belonging to the common ADC instance. 00466 * Refer to function @ref LL_ADC_CommonDeInit(). 00467 * @param ADCx ADC instance 00468 * @retval An ErrorStatus enumeration value: 00469 * - SUCCESS: ADC registers are de-initialized 00470 * - ERROR: ADC registers are not de-initialized 00471 */ 00472 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) 00473 { 00474 ErrorStatus status = SUCCESS; 00475 00476 __IO uint32_t timeout_cpu_cycles = 0U; 00477 00478 /* Check the parameters */ 00479 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00480 00481 /* Disable ADC instance if not already disabled. */ 00482 if(LL_ADC_IsEnabled(ADCx) == 1U) 00483 { 00484 /* Set ADC group regular trigger source to SW start to ensure to not */ 00485 /* have an external trigger event occurring during the conversion stop */ 00486 /* ADC disable process. */ 00487 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); 00488 00489 /* Stop potential ADC conversion on going on ADC group regular. */ 00490 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) 00491 { 00492 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) 00493 { 00494 LL_ADC_REG_StopConversion(ADCx); 00495 } 00496 } 00497 00498 /* Set ADC group injected trigger source to SW start to ensure to not */ 00499 /* have an external trigger event occurring during the conversion stop */ 00500 /* ADC disable process. */ 00501 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); 00502 00503 /* Stop potential ADC conversion on going on ADC group injected. */ 00504 if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U) 00505 { 00506 if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U) 00507 { 00508 LL_ADC_INJ_StopConversion(ADCx); 00509 } 00510 } 00511 00512 /* Wait for ADC conversions are effectively stopped */ 00513 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; 00514 while (( LL_ADC_REG_IsStopConversionOngoing(ADCx) 00515 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U) 00516 { 00517 if(timeout_cpu_cycles-- == 0U) 00518 { 00519 /* Time-out error */ 00520 status = ERROR; 00521 } 00522 } 00523 00524 /* Flush group injected contexts queue (register JSQR): */ 00525 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */ 00526 /* contexts queue is maintained with the last active context). */ 00527 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY); 00528 00529 /* Disable the ADC instance */ 00530 LL_ADC_Disable(ADCx); 00531 00532 /* Wait for ADC instance is effectively disabled */ 00533 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; 00534 while (LL_ADC_IsDisableOngoing(ADCx) == 1U) 00535 { 00536 if(timeout_cpu_cycles-- == 0U) 00537 { 00538 /* Time-out error */ 00539 status = ERROR; 00540 } 00541 } 00542 } 00543 00544 /* Check whether ADC state is compliant with expected state */ 00545 if(READ_BIT(ADCx->CR, 00546 ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART 00547 | ADC_CR_ADDIS | ADC_CR_ADEN ) 00548 ) 00549 == 0U) 00550 { 00551 /* ========== Reset ADC registers ========== */ 00552 /* Reset register IER */ 00553 CLEAR_BIT(ADCx->IER, 00554 ( LL_ADC_IT_ADRDY 00555 | LL_ADC_IT_EOC 00556 | LL_ADC_IT_EOS 00557 | LL_ADC_IT_OVR 00558 | LL_ADC_IT_EOSMP 00559 | LL_ADC_IT_JEOC 00560 | LL_ADC_IT_JEOS 00561 | LL_ADC_IT_JQOVF 00562 | LL_ADC_IT_AWD1 00563 | LL_ADC_IT_AWD2 00564 | LL_ADC_IT_AWD3 ) 00565 ); 00566 00567 /* Reset register ISR */ 00568 SET_BIT(ADCx->ISR, 00569 ( LL_ADC_FLAG_ADRDY 00570 | LL_ADC_FLAG_EOC 00571 | LL_ADC_FLAG_EOS 00572 | LL_ADC_FLAG_OVR 00573 | LL_ADC_FLAG_EOSMP 00574 | LL_ADC_FLAG_JEOC 00575 | LL_ADC_FLAG_JEOS 00576 | LL_ADC_FLAG_JQOVF 00577 | LL_ADC_FLAG_AWD1 00578 | LL_ADC_FLAG_AWD2 00579 | LL_ADC_FLAG_AWD3 ) 00580 ); 00581 00582 /* Reset register CR */ 00583 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */ 00584 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */ 00585 /* access mode "read-set": no direct reset applicable. */ 00586 /* - Reset Calibration mode to default setting (single ended). */ 00587 /* - Disable ADC internal voltage regulator. */ 00588 /* - Enable ADC deep power down. */ 00589 /* Note: ADC internal voltage regulator disable and ADC deep power */ 00590 /* down enable are conditioned to ADC state disabled: */ 00591 /* already done above. */ 00592 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); 00593 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD); 00594 00595 /* Reset register CFGR */ 00596 MODIFY_REG(ADCx->CFGR, 00597 ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN 00598 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM 00599 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN 00600 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD 00601 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN 00602 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ), 00603 ADC_CFGR_JQDIS 00604 ); 00605 00606 /* Reset register CFGR2 */ 00607 CLEAR_BIT(ADCx->CFGR2, 00608 ( ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS 00609 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) 00610 ); 00611 00612 /* Reset register SMPR1 */ 00613 CLEAR_BIT(ADCx->SMPR1, 00614 ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 00615 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 00616 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1) 00617 ); 00618 00619 /* Reset register SMPR2 */ 00620 CLEAR_BIT(ADCx->SMPR2, 00621 ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 00622 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 00623 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10) 00624 ); 00625 00626 /* Reset register TR1 */ 00627 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1); 00628 00629 /* Reset register TR2 */ 00630 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2); 00631 00632 /* Reset register TR3 */ 00633 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3); 00634 00635 /* Reset register SQR1 */ 00636 CLEAR_BIT(ADCx->SQR1, 00637 ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 00638 | ADC_SQR1_SQ1 | ADC_SQR1_L) 00639 ); 00640 00641 /* Reset register SQR2 */ 00642 CLEAR_BIT(ADCx->SQR2, 00643 ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 00644 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5) 00645 ); 00646 00647 /* Reset register SQR3 */ 00648 CLEAR_BIT(ADCx->SQR3, 00649 ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 00650 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10) 00651 ); 00652 00653 /* Reset register SQR4 */ 00654 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); 00655 00656 /* Reset register JSQR */ 00657 CLEAR_BIT(ADCx->JSQR, 00658 ( ADC_JSQR_JL 00659 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN 00660 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 00661 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) 00662 ); 00663 00664 /* Reset register DR */ 00665 /* Note: bits in access mode read only, no direct reset applicable */ 00666 00667 /* Reset register OFR1 */ 00668 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); 00669 /* Reset register OFR2 */ 00670 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); 00671 /* Reset register OFR3 */ 00672 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); 00673 /* Reset register OFR4 */ 00674 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); 00675 00676 /* Reset registers JDR1, JDR2, JDR3, JDR4 */ 00677 /* Note: bits in access mode read only, no direct reset applicable */ 00678 00679 /* Reset register AWD2CR */ 00680 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH); 00681 00682 /* Reset register AWD3CR */ 00683 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH); 00684 00685 /* Reset register DIFSEL */ 00686 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL); 00687 00688 /* Reset register CALFACT */ 00689 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); 00690 } 00691 else 00692 { 00693 /* ADC instance is in an unknown state */ 00694 /* Need to performing a hard reset of ADC instance, using high level */ 00695 /* clock source RCC ADC reset. */ 00696 /* Caution: On this STM32 serie, if several ADC instances are available */ 00697 /* on the selected device, RCC ADC reset will reset */ 00698 /* all ADC instances belonging to the common ADC instance. */ 00699 /* Caution: On this STM32 serie, if several ADC instances are available */ 00700 /* on the selected device, RCC ADC reset will reset */ 00701 /* all ADC instances belonging to the common ADC instance. */ 00702 status = ERROR; 00703 } 00704 00705 return status; 00706 } 00707 00708 /** 00709 * @brief Initialize some features of ADC instance. 00710 * @note These parameters have an impact on ADC scope: ADC instance. 00711 * Affects both group regular and group injected (availability 00712 * of ADC group injected depends on STM32 families). 00713 * Refer to corresponding unitary functions into 00714 * @ref ADC_LL_EF_Configuration_ADC_Instance . 00715 * @note The setting of these parameters by function @ref LL_ADC_Init() 00716 * is conditioned to ADC state: 00717 * ADC instance must be disabled. 00718 * This condition is applied to all ADC features, for efficiency 00719 * and compatibility over all STM32 families. However, the different 00720 * features can be set under different ADC state conditions 00721 * (setting possible with ADC enabled without conversion on going, 00722 * ADC enabled with conversion on going, ...) 00723 * Each feature can be updated afterwards with a unitary function 00724 * and potentially with ADC in a different state than disabled, 00725 * refer to description of each function for setting 00726 * conditioned to ADC state. 00727 * @note After using this function, some other features must be configured 00728 * using LL unitary functions. 00729 * The minimum configuration remaining to be done is: 00730 * - Set ADC group regular or group injected sequencer: 00731 * map channel on the selected sequencer rank. 00732 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00733 * - Set ADC channel sampling time 00734 * Refer to function LL_ADC_SetChannelSamplingTime(); 00735 * @param ADCx ADC instance 00736 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00737 * @retval An ErrorStatus enumeration value: 00738 * - SUCCESS: ADC registers are initialized 00739 * - ERROR: ADC registers are not initialized 00740 */ 00741 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) 00742 { 00743 ErrorStatus status = SUCCESS; 00744 00745 /* Check the parameters */ 00746 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00747 00748 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution )); 00749 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment )); 00750 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode )); 00751 00752 /* Note: Hardware constraint (refer to description of this function): */ 00753 /* ADC instance must be disabled. */ 00754 if(LL_ADC_IsEnabled(ADCx) == 0U) 00755 { 00756 /* Configuration of ADC hierarchical scope: */ 00757 /* - ADC instance */ 00758 /* - Set ADC data resolution */ 00759 /* - Set ADC conversion data alignment */ 00760 /* - Set ADC low power mode */ 00761 MODIFY_REG(ADCx->CFGR, 00762 ADC_CFGR_RES 00763 | ADC_CFGR_ALIGN 00764 | ADC_CFGR_AUTDLY 00765 , 00766 ADC_InitStruct->Resolution 00767 | ADC_InitStruct->DataAlignment 00768 | ADC_InitStruct->LowPowerMode 00769 ); 00770 00771 } 00772 else 00773 { 00774 /* Initialization error: ADC instance is not disabled. */ 00775 status = ERROR; 00776 } 00777 return status; 00778 } 00779 00780 /** 00781 * @brief Set each @ref LL_ADC_InitTypeDef field to default value. 00782 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure 00783 * whose fields will be set to default values. 00784 * @retval None 00785 */ 00786 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) 00787 { 00788 /* Set ADC_InitStruct fields to default values */ 00789 /* Set fields of ADC instance */ 00790 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; 00791 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; 00792 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; 00793 00794 } 00795 00796 /** 00797 * @brief Initialize some features of ADC group regular. 00798 * @note These parameters have an impact on ADC scope: ADC group regular. 00799 * Refer to corresponding unitary functions into 00800 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00801 * (functions with prefix "REG"). 00802 * @note The setting of these parameters by function @ref LL_ADC_Init() 00803 * is conditioned to ADC state: 00804 * ADC instance must be disabled. 00805 * This condition is applied to all ADC features, for efficiency 00806 * and compatibility over all STM32 families. However, the different 00807 * features can be set under different ADC state conditions 00808 * (setting possible with ADC enabled without conversion on going, 00809 * ADC enabled with conversion on going, ...) 00810 * Each feature can be updated afterwards with a unitary function 00811 * and potentially with ADC in a different state than disabled, 00812 * refer to description of each function for setting 00813 * conditioned to ADC state. 00814 * @note After using this function, other features must be configured 00815 * using LL unitary functions. 00816 * The minimum configuration remaining to be done is: 00817 * - Set ADC group regular or group injected sequencer: 00818 * map channel on the selected sequencer rank. 00819 * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). 00820 * - Set ADC channel sampling time 00821 * Refer to function LL_ADC_SetChannelSamplingTime(); 00822 * @param ADCx ADC instance 00823 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00824 * @retval An ErrorStatus enumeration value: 00825 * - SUCCESS: ADC registers are initialized 00826 * - ERROR: ADC registers are not initialized 00827 */ 00828 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00829 { 00830 ErrorStatus status = SUCCESS; 00831 00832 /* Check the parameters */ 00833 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00834 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource )); 00835 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength )); 00836 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00837 { 00838 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont )); 00839 } 00840 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode )); 00841 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer )); 00842 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun )); 00843 00844 /* Note: Hardware constraint (refer to description of this function): */ 00845 /* ADC instance must be disabled. */ 00846 if(LL_ADC_IsEnabled(ADCx) == 0U) 00847 { 00848 /* Configuration of ADC hierarchical scope: */ 00849 /* - ADC group regular */ 00850 /* - Set ADC group regular trigger source */ 00851 /* - Set ADC group regular sequencer length */ 00852 /* - Set ADC group regular sequencer discontinuous mode */ 00853 /* - Set ADC group regular continuous mode */ 00854 /* - Set ADC group regular conversion data transfer: no transfer or */ 00855 /* transfer by DMA, and DMA requests mode */ 00856 /* - Set ADC group regular overrun behavior */ 00857 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ 00858 /* setting of trigger source to SW start. */ 00859 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00860 { 00861 MODIFY_REG(ADCx->CFGR, 00862 ADC_CFGR_EXTSEL 00863 | ADC_CFGR_EXTEN 00864 | ADC_CFGR_DISCEN 00865 | ADC_CFGR_DISCNUM 00866 | ADC_CFGR_CONT 00867 | ADC_CFGR_DMAEN 00868 | ADC_CFGR_DMACFG 00869 | ADC_CFGR_OVRMOD 00870 , 00871 ADC_REG_InitStruct->TriggerSource 00872 | ADC_REG_InitStruct->SequencerDiscont 00873 | ADC_REG_InitStruct->ContinuousMode 00874 | ADC_REG_InitStruct->DMATransfer 00875 | ADC_REG_InitStruct->Overrun 00876 ); 00877 } 00878 else 00879 { 00880 MODIFY_REG(ADCx->CFGR, 00881 ADC_CFGR_EXTSEL 00882 | ADC_CFGR_EXTEN 00883 | ADC_CFGR_DISCEN 00884 | ADC_CFGR_DISCNUM 00885 | ADC_CFGR_CONT 00886 | ADC_CFGR_DMAEN 00887 | ADC_CFGR_DMACFG 00888 | ADC_CFGR_OVRMOD 00889 , 00890 ADC_REG_InitStruct->TriggerSource 00891 | LL_ADC_REG_SEQ_DISCONT_DISABLE 00892 | ADC_REG_InitStruct->ContinuousMode 00893 | ADC_REG_InitStruct->DMATransfer 00894 | ADC_REG_InitStruct->Overrun 00895 ); 00896 } 00897 00898 /* Set ADC group regular sequencer length and scan direction */ 00899 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength ); 00900 } 00901 else 00902 { 00903 /* Initialization error: ADC instance is not disabled. */ 00904 status = ERROR; 00905 } 00906 return status; 00907 } 00908 00909 /** 00910 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. 00911 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure 00912 * whose fields will be set to default values. 00913 * @retval None 00914 */ 00915 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) 00916 { 00917 /* Set ADC_REG_InitStruct fields to default values */ 00918 /* Set fields of ADC group regular */ 00919 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ 00920 /* setting of trigger source to SW start. */ 00921 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; 00922 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; 00923 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; 00924 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; 00925 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; 00926 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; 00927 } 00928 00929 /** 00930 * @brief Initialize some features of ADC group injected. 00931 * @note These parameters have an impact on ADC scope: ADC group injected. 00932 * Refer to corresponding unitary functions into 00933 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular 00934 * (functions with prefix "INJ"). 00935 * @note The setting of these parameters by function @ref LL_ADC_Init() 00936 * is conditioned to ADC state: 00937 * ADC instance must be disabled. 00938 * This condition is applied to all ADC features, for efficiency 00939 * and compatibility over all STM32 families. However, the different 00940 * features can be set under different ADC state conditions 00941 * (setting possible with ADC enabled without conversion on going, 00942 * ADC enabled with conversion on going, ...) 00943 * Each feature can be updated afterwards with a unitary function 00944 * and potentially with ADC in a different state than disabled, 00945 * refer to description of each function for setting 00946 * conditioned to ADC state. 00947 * @note After using this function, other features must be configured 00948 * using LL unitary functions. 00949 * The minimum configuration remaining to be done is: 00950 * - Set ADC group injected sequencer: 00951 * map channel on the selected sequencer rank. 00952 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). 00953 * - Set ADC channel sampling time 00954 * Refer to function LL_ADC_SetChannelSamplingTime(); 00955 * @param ADCx ADC instance 00956 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 00957 * @retval An ErrorStatus enumeration value: 00958 * - SUCCESS: ADC registers are initialized 00959 * - ERROR: ADC registers are not initialized 00960 */ 00961 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 00962 { 00963 ErrorStatus status = SUCCESS; 00964 00965 /* Check the parameters */ 00966 assert_param(IS_ADC_ALL_INSTANCE(ADCx)); 00967 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource )); 00968 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength )); 00969 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) 00970 { 00971 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont )); 00972 } 00973 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto )); 00974 00975 /* Note: Hardware constraint (refer to description of this function): */ 00976 /* ADC instance must be disabled. */ 00977 if(LL_ADC_IsEnabled(ADCx) == 0U) 00978 { 00979 /* Configuration of ADC hierarchical scope: */ 00980 /* - ADC group injected */ 00981 /* - Set ADC group injected trigger source */ 00982 /* - Set ADC group injected sequencer length */ 00983 /* - Set ADC group injected sequencer discontinuous mode */ 00984 /* - Set ADC group injected conversion trigger: independent or */ 00985 /* from ADC group regular */ 00986 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ 00987 /* setting of trigger source to SW start. */ 00988 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) 00989 { 00990 MODIFY_REG(ADCx->CFGR, 00991 ADC_CFGR_JDISCEN 00992 | ADC_CFGR_JAUTO 00993 , 00994 ADC_INJ_InitStruct->SequencerDiscont 00995 | ADC_INJ_InitStruct->TrigAuto 00996 ); 00997 } 00998 else 00999 { 01000 MODIFY_REG(ADCx->CFGR, 01001 ADC_CFGR_JDISCEN 01002 | ADC_CFGR_JAUTO 01003 , 01004 LL_ADC_REG_SEQ_DISCONT_DISABLE 01005 | ADC_INJ_InitStruct->TrigAuto 01006 ); 01007 } 01008 01009 MODIFY_REG(ADCx->JSQR, 01010 ADC_JSQR_JEXTSEL 01011 | ADC_JSQR_JEXTEN 01012 | ADC_JSQR_JL 01013 , 01014 ADC_INJ_InitStruct->TriggerSource 01015 | ADC_INJ_InitStruct->SequencerLength 01016 ); 01017 } 01018 else 01019 { 01020 /* Initialization error: ADC instance is not disabled. */ 01021 status = ERROR; 01022 } 01023 return status; 01024 } 01025 01026 /** 01027 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. 01028 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure 01029 * whose fields will be set to default values. 01030 * @retval None 01031 */ 01032 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) 01033 { 01034 /* Set ADC_INJ_InitStruct fields to default values */ 01035 /* Set fields of ADC group injected */ 01036 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; 01037 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; 01038 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; 01039 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; 01040 } 01041 01042 /** 01043 * @} 01044 */ 01045 01046 /** 01047 * @} 01048 */ 01049 01050 /** 01051 * @} 01052 */ 01053 01054 #endif /* ADC1 || ADC2 || ADC3 */ 01055 01056 /** 01057 * @} 01058 */ 01059 01060 #endif /* USE_FULL_LL_DRIVER */ 01061 01062 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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