stm32l4xx_hal_tim_ex.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_tim_ex.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   TIM HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Timer Extended peripheral:
00010   *           + Time Hall Sensor Interface Initialization
00011   *           + Time Hall Sensor Interface Start
00012   *           + Time Complementary signal break and dead time configuration
00013   *           + Time Master and Slave synchronization configuration
00014   *           + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
00015   *           + Time OCRef clear configuration
00016   *           + Timer remapping capabilities configuration
00017   @verbatim
00018   ==============================================================================
00019                       ##### TIMER Extended features #####
00020   ==============================================================================
00021   [..]
00022     The Timer Extended features include:
00023     (#) Complementary outputs with programmable dead-time for :
00024         (++) Output Compare
00025         (++) PWM generation (Edge and Center-aligned Mode)
00026         (++) One-pulse mode output
00027     (#) Synchronization circuit to control the timer with external signals and to
00028         interconnect several timers together.
00029     (#) Break input to put the timer output signals in reset state or in a known state.
00030     (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
00031         positioning purposes
00032 
00033             ##### How to use this driver #####
00034   ==============================================================================
00035     [..]
00036      (#) Initialize the TIM low level resources by implementing the following functions
00037          depending on the selected feature:
00038            (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()
00039 
00040      (#) Initialize the TIM low level resources :
00041         (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
00042         (##) TIM pins configuration
00043             (+++) Enable the clock for the TIM GPIOs using the following function:
00044               __HAL_RCC_GPIOx_CLK_ENABLE();
00045             (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
00046 
00047      (#) The external Clock can be configured, if needed (the default clock is the
00048          internal clock from the APBx), using the following function:
00049          HAL_TIM_ConfigClockSource, the clock configuration should be done before
00050          any start function.
00051 
00052      (#) Configure the TIM in the desired functioning mode using one of the
00053          initialization function of this driver:
00054           (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutationEvent(): to use the
00055               Timer Hall Sensor Interface and the commutation event with the corresponding
00056               Interrupt and DMA request if needed (Note that One Timer is used to interface
00057              with the Hall sensor Interface and another Timer should be used to use
00058              the commutation event).
00059 
00060      (#) Activate the TIM peripheral using one of the start functions:
00061            (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
00062            (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
00063            (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
00064            (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
00065 
00066 
00067   @endverbatim
00068   ******************************************************************************
00069   * @attention
00070   *
00071   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00072   *
00073   * Redistribution and use in source and binary forms, with or without modification,
00074   * are permitted provided that the following conditions are met:
00075   *   1. Redistributions of source code must retain the above copyright notice,
00076   *      this list of conditions and the following disclaimer.
00077   *   2. Redistributions in binary form must reproduce the above copyright notice,
00078   *      this list of conditions and the following disclaimer in the documentation
00079   *      and/or other materials provided with the distribution.
00080   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00081   *      may be used to endorse or promote products derived from this software
00082   *      without specific prior written permission.
00083   *
00084   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00085   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00086   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00087   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00088   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00089   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00090   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00091   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00092   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00093   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00094   *
00095   ******************************************************************************
00096 */
00097 
00098 /* Includes ------------------------------------------------------------------*/
00099 #include "stm32l4xx_hal.h"
00100 
00101 /** @addtogroup STM32L4xx_HAL_Driver
00102   * @{
00103   */
00104 
00105 /** @defgroup TIMEx TIMEx
00106   * @brief TIM Extended HAL module driver
00107   * @{
00108   */
00109 
00110 #ifdef HAL_TIM_MODULE_ENABLED
00111 
00112 /* Private typedef -----------------------------------------------------------*/
00113 /* Private define ------------------------------------------------------------*/
00114 #define BDTR_BKF_SHIFT (16)
00115 #define BDTR_BK2F_SHIFT (20)
00116 #define TIMx_ETRSEL_MASK ((uint32_t)0x0001C000) 
00117 
00118 /* Private macro -------------------------------------------------------------*/
00119 /* Private variables ---------------------------------------------------------*/
00120 /* Private function prototypes -----------------------------------------------*/
00121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
00122 
00123 /* Private functions ---------------------------------------------------------*/
00124 
00125 /* Exported functions --------------------------------------------------------*/
00126 /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
00127   * @{
00128   */
00129 
00130 /** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
00131   * @brief    Timer Hall Sensor functions
00132   *
00133 @verbatim
00134   ==============================================================================
00135                       ##### Timer Hall Sensor functions #####
00136   ==============================================================================
00137   [..]
00138     This section provides functions allowing to:
00139     (+) Initialize and configure TIM HAL Sensor.
00140     (+) De-initialize TIM HAL Sensor.
00141     (+) Start the Hall Sensor Interface.
00142     (+) Stop the Hall Sensor Interface.
00143     (+) Start the Hall Sensor Interface and enable interrupts.
00144     (+) Stop the Hall Sensor Interface and disable interrupts.
00145     (+) Start the Hall Sensor Interface and enable DMA transfers.
00146     (+) Stop the Hall Sensor Interface and disable DMA transfers.
00147 
00148 @endverbatim
00149   * @{
00150   */
00151 /**
00152   * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
00153   * @param  htim: TIM Encoder Interface handle
00154   * @param  sConfig: TIM Hall Sensor configuration structure
00155   * @retval HAL status
00156   */
00157 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
00158 {
00159   TIM_OC_InitTypeDef OC_Config;
00160 
00161   /* Check the TIM handle allocation */
00162   if(htim == NULL)
00163   {
00164     return HAL_ERROR;
00165   }
00166 
00167   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00168   assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
00169   assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
00170   assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
00171   assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
00172   assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
00173 
00174   if(htim->State == HAL_TIM_STATE_RESET)
00175   {
00176     /* Allocate lock resource and initialize it */
00177     htim->Lock = HAL_UNLOCKED;
00178 
00179     /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
00180     HAL_TIMEx_HallSensor_MspInit(htim);
00181   }
00182 
00183   /* Set the TIM state */
00184   htim->State = HAL_TIM_STATE_BUSY;
00185 
00186   /* Configure the Time base in the Encoder Mode */
00187   TIM_Base_SetConfig(htim->Instance, &htim->Init);
00188 
00189   /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */
00190   TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
00191 
00192   /* Reset the IC1PSC Bits */
00193   htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
00194   /* Set the IC1PSC value */
00195   htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
00196 
00197   /* Enable the Hall sensor interface (XOR function of the three inputs) */
00198   htim->Instance->CR2 |= TIM_CR2_TI1S;
00199 
00200   /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
00201   htim->Instance->SMCR &= ~TIM_SMCR_TS;
00202   htim->Instance->SMCR |= TIM_TS_TI1F_ED;
00203 
00204   /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
00205   htim->Instance->SMCR &= ~TIM_SMCR_SMS;
00206   htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
00207 
00208   /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
00209   OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
00210   OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
00211   OC_Config.OCMode = TIM_OCMODE_PWM2;
00212   OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
00213   OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
00214   OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
00215   OC_Config.Pulse = sConfig->Commutation_Delay;
00216 
00217   TIM_OC2_SetConfig(htim->Instance, &OC_Config);
00218 
00219   /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
00220     register to 101 */
00221   htim->Instance->CR2 &= ~TIM_CR2_MMS;
00222   htim->Instance->CR2 |= TIM_TRGO_OC2REF;
00223 
00224   /* Initialize the TIM state*/
00225   htim->State= HAL_TIM_STATE_READY;
00226 
00227   return HAL_OK;
00228 }
00229 
00230 /**
00231   * @brief  DeInitialize the TIM Hall Sensor interface
00232   * @param  htim: TIM Hall Sensor handle
00233   * @retval HAL status
00234   */
00235 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
00236 {
00237   /* Check the parameters */
00238   assert_param(IS_TIM_INSTANCE(htim->Instance));
00239 
00240   htim->State = HAL_TIM_STATE_BUSY;
00241 
00242   /* Disable the TIM Peripheral Clock */
00243   __HAL_TIM_DISABLE(htim);
00244 
00245   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00246   HAL_TIMEx_HallSensor_MspDeInit(htim);
00247 
00248   /* Change TIM state */
00249   htim->State = HAL_TIM_STATE_RESET;
00250 
00251   /* Release Lock */
00252   __HAL_UNLOCK(htim);
00253 
00254   return HAL_OK;
00255 }
00256 
00257 /**
00258   * @brief  Initializes the TIM Hall Sensor MSP.
00259   * @param  htim: TIM handle
00260   * @retval None
00261   */
00262 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
00263 {
00264   /* Prevent unused argument(s) compilation warning */
00265   UNUSED(htim);
00266 
00267   /* NOTE : This function should not be modified, when the callback is needed,
00268             the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
00269    */
00270 }
00271 
00272 /**
00273   * @brief  DeInitialize TIM Hall Sensor MSP.
00274   * @param  htim: TIM handle
00275   * @retval None
00276   */
00277 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
00278 {
00279   /* Prevent unused argument(s) compilation warning */
00280   UNUSED(htim);
00281 
00282   /* NOTE : This function should not be modified, when the callback is needed,
00283             the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
00284    */
00285 }
00286 
00287 /**
00288   * @brief  Starts the TIM Hall Sensor Interface.
00289   * @param  htim : TIM Hall Sensor handle
00290   * @retval HAL status
00291   */
00292 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
00293 {
00294   /* Check the parameters */
00295   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00296 
00297   /* Enable the Input Capture channels 1
00298     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00299   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00300 
00301   /* Enable the Peripheral */
00302   __HAL_TIM_ENABLE(htim);
00303 
00304   /* Return function status */
00305   return HAL_OK;
00306 }
00307 
00308 /**
00309   * @brief  Stops the TIM Hall sensor Interface.
00310   * @param  htim : TIM Hall Sensor handle
00311   * @retval HAL status
00312   */
00313 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
00314 {
00315   /* Check the parameters */
00316   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00317 
00318   /* Disable the Input Capture channels 1, 2 and 3
00319     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00320   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00321 
00322   /* Disable the Peripheral */
00323   __HAL_TIM_DISABLE(htim);
00324 
00325   /* Return function status */
00326   return HAL_OK;
00327 }
00328 
00329 /**
00330   * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.
00331   * @param  htim : TIM Hall Sensor handle
00332   * @retval HAL status
00333   */
00334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
00335 {
00336   /* Check the parameters */
00337   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00338 
00339   /* Enable the capture compare Interrupts 1 event */
00340   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00341 
00342   /* Enable the Input Capture channels 1
00343     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00344   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00345 
00346   /* Enable the Peripheral */
00347   __HAL_TIM_ENABLE(htim);
00348 
00349   /* Return function status */
00350   return HAL_OK;
00351 }
00352 
00353 /**
00354   * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.
00355   * @param  htim : TIM handle
00356   * @retval HAL status
00357   */
00358 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
00359 {
00360   /* Check the parameters */
00361   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00362 
00363   /* Disable the Input Capture channels 1
00364     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00365   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00366 
00367   /* Disable the capture compare Interrupts event */
00368   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00369 
00370   /* Disable the Peripheral */
00371   __HAL_TIM_DISABLE(htim);
00372 
00373   /* Return function status */
00374   return HAL_OK;
00375 }
00376 
00377 /**
00378   * @brief  Starts the TIM Hall Sensor Interface in DMA mode.
00379   * @param  htim : TIM Hall Sensor handle
00380   * @param  pData: The destination Buffer address.
00381   * @param  Length: The length of data to be transferred from TIM peripheral to memory.
00382   * @retval HAL status
00383   */
00384 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
00385 {
00386   /* Check the parameters */
00387   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00388 
00389    if((htim->State == HAL_TIM_STATE_BUSY))
00390   {
00391      return HAL_BUSY;
00392   }
00393   else if((htim->State == HAL_TIM_STATE_READY))
00394   {
00395     if(((uint32_t)pData == 0 ) && (Length > 0))
00396     {
00397       return HAL_ERROR;
00398     }
00399     else
00400     {
00401       htim->State = HAL_TIM_STATE_BUSY;
00402     }
00403   }
00404   /* Enable the Input Capture channels 1
00405     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00406   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
00407 
00408   /* Set the DMA Input Capture 1 Callback */
00409   htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
00410   /* Set the DMA error callback */
00411   htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00412 
00413   /* Enable the DMA channel for Capture 1*/
00414   HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
00415 
00416   /* Enable the capture compare 1 Interrupt */
00417   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00418 
00419   /* Enable the Peripheral */
00420   __HAL_TIM_ENABLE(htim);
00421 
00422   /* Return function status */
00423   return HAL_OK;
00424 }
00425 
00426 /**
00427   * @brief  Stops the TIM Hall Sensor Interface in DMA mode.
00428   * @param  htim : TIM handle
00429   * @retval HAL status
00430   */
00431 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
00432 {
00433   /* Check the parameters */
00434   assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
00435 
00436   /* Disable the Input Capture channels 1
00437     (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
00438   TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
00439 
00440 
00441   /* Disable the capture compare Interrupts 1 event */
00442   __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00443 
00444   /* Disable the Peripheral */
00445   __HAL_TIM_DISABLE(htim);
00446 
00447   /* Return function status */
00448   return HAL_OK;
00449 }
00450 
00451 /**
00452   * @}
00453   */
00454 
00455 /** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
00456   *  @brief   Timer Complementary Output Compare functions
00457   *
00458 @verbatim
00459   ==============================================================================
00460               ##### Timer Complementary Output Compare functions #####
00461   ==============================================================================
00462   [..]
00463     This section provides functions allowing to:
00464     (+) Start the Complementary Output Compare/PWM.
00465     (+) Stop the Complementary Output Compare/PWM.
00466     (+) Start the Complementary Output Compare/PWM and enable interrupts.
00467     (+) Stop the Complementary Output Compare/PWM and disable interrupts.
00468     (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
00469     (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
00470 
00471 @endverbatim
00472   * @{
00473   */
00474 
00475 /**
00476   * @brief  Starts the TIM Output Compare signal generation on the complementary
00477   *         output.
00478   * @param  htim : TIM Output Compare handle
00479   * @param  Channel : TIM Channel to be enabled
00480   *          This parameter can be one of the following values:
00481   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00482   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00483   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00484   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00488 {
00489   /* Check the parameters */
00490   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00491 
00492   /* Enable the Capture compare channel N */
00493   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00494 
00495   /* Enable the Main Ouput */
00496   __HAL_TIM_MOE_ENABLE(htim);
00497 
00498   /* Enable the Peripheral */
00499   __HAL_TIM_ENABLE(htim);
00500 
00501   /* Return function status */
00502   return HAL_OK;
00503 }
00504 
00505 /**
00506   * @brief  Stops the TIM Output Compare signal generation on the complementary
00507   *         output.
00508   * @param  htim : TIM handle
00509   * @param  Channel : TIM Channel to be disabled
00510   *          This parameter can be one of the following values:
00511   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00512   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00513   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00514   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00518 {
00519   /* Check the parameters */
00520   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00521 
00522   /* Disable the Capture compare channel N */
00523   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00524 
00525   /* Disable the Main Ouput */
00526   __HAL_TIM_MOE_DISABLE(htim);
00527 
00528   /* Disable the Peripheral */
00529   __HAL_TIM_DISABLE(htim);
00530 
00531   /* Return function status */
00532   return HAL_OK;
00533 }
00534 
00535 /**
00536   * @brief  Starts the TIM Output Compare signal generation in interrupt mode
00537   *         on the complementary output.
00538   * @param  htim : TIM OC handle
00539   * @param  Channel : TIM Channel to be enabled
00540   *          This parameter can be one of the following values:
00541   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00542   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00543   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00544   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00545   * @retval HAL status
00546   */
00547 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00548 {
00549   /* Check the parameters */
00550   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00551 
00552   switch (Channel)
00553   {
00554     case TIM_CHANNEL_1:
00555     {
00556       /* Enable the TIM Output Compare interrupt */
00557       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00558     }
00559     break;
00560 
00561     case TIM_CHANNEL_2:
00562     {
00563       /* Enable the TIM Output Compare interrupt */
00564       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00565     }
00566     break;
00567 
00568     case TIM_CHANNEL_3:
00569     {
00570       /* Enable the TIM Output Compare interrupt */
00571       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00572     }
00573     break;
00574 
00575     case TIM_CHANNEL_4:
00576     {
00577       /* Enable the TIM Output Compare interrupt */
00578       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00579     }
00580     break;
00581 
00582     default:
00583     break;
00584   }
00585 
00586   /* Enable the TIM Break interrupt */
00587   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
00588   
00589   /* Enable the Capture compare channel N */
00590   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00591 
00592   /* Enable the Main Ouput */
00593   __HAL_TIM_MOE_ENABLE(htim);
00594 
00595   /* Enable the Peripheral */
00596   __HAL_TIM_ENABLE(htim);
00597 
00598   /* Return function status */
00599   return HAL_OK;
00600 }
00601 
00602 /**
00603   * @brief  Stops the TIM Output Compare signal generation in interrupt mode
00604   *         on the complementary output.
00605   * @param  htim : TIM Output Compare handle
00606   * @param  Channel : TIM Channel to be disabled
00607   *          This parameter can be one of the following values:
00608   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00609   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00610   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00611   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00612   * @retval HAL status
00613   */
00614 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00615 {
00616   uint32_t tmpccer = 0;
00617 
00618   /* Check the parameters */
00619   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00620 
00621   switch (Channel)
00622   {
00623     case TIM_CHANNEL_1:
00624     {
00625       /* Disable the TIM Output Compare interrupt */
00626       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
00627     }
00628     break;
00629 
00630     case TIM_CHANNEL_2:
00631     {
00632       /* Disable the TIM Output Compare interrupt */
00633       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
00634     }
00635     break;
00636 
00637     case TIM_CHANNEL_3:
00638     {
00639       /* Disable the TIM Output Compare interrupt */
00640       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
00641     }
00642     break;
00643 
00644     case TIM_CHANNEL_4:
00645     {
00646       /* Disable the TIM Output Compare interrupt */
00647       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
00648     }
00649     break;
00650 
00651     default:
00652     break;
00653   }
00654 
00655   /* Disable the Capture compare channel N */
00656   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00657 
00658   /* Disable the TIM Break interrupt (only if no more channel is active) */
00659   tmpccer = htim->Instance->CCER;
00660   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
00661   {
00662     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
00663   }
00664 
00665   /* Disable the Main Ouput */
00666   __HAL_TIM_MOE_DISABLE(htim);
00667 
00668   /* Disable the Peripheral */
00669   __HAL_TIM_DISABLE(htim);
00670 
00671   /* Return function status */
00672   return HAL_OK;
00673 }
00674 
00675 /**
00676   * @brief  Starts the TIM Output Compare signal generation in DMA mode
00677   *         on the complementary output.
00678   * @param  htim : TIM Output Compare handle
00679   * @param  Channel : TIM Channel to be enabled
00680   *          This parameter can be one of the following values:
00681   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00682   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00683   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00684   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00685   * @param  pData: The source Buffer address.
00686   * @param  Length: The length of data to be transferred from memory to TIM peripheral
00687   * @retval HAL status
00688   */
00689 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
00690 {
00691   /* Check the parameters */
00692   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00693 
00694   if((htim->State == HAL_TIM_STATE_BUSY))
00695   {
00696      return HAL_BUSY;
00697   }
00698   else if((htim->State == HAL_TIM_STATE_READY))
00699   {
00700     if(((uint32_t)pData == 0 ) && (Length > 0))
00701     {
00702       return HAL_ERROR;
00703     }
00704     else
00705     {
00706       htim->State = HAL_TIM_STATE_BUSY;
00707     }
00708   }
00709   switch (Channel)
00710   {
00711     case TIM_CHANNEL_1:
00712     {
00713       /* Set the DMA Period elapsed callback */
00714       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
00715 
00716       /* Set the DMA error callback */
00717       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
00718 
00719       /* Enable the DMA channel */
00720       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
00721 
00722       /* Enable the TIM Output Compare DMA request */
00723       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
00724     }
00725     break;
00726 
00727     case TIM_CHANNEL_2:
00728     {
00729       /* Set the DMA Period elapsed callback */
00730       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
00731 
00732       /* Set the DMA error callback */
00733       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
00734 
00735       /* Enable the DMA channel */
00736       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
00737 
00738       /* Enable the TIM Output Compare DMA request */
00739       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
00740     }
00741     break;
00742 
00743     case TIM_CHANNEL_3:
00744 {
00745       /* Set the DMA Period elapsed callback */
00746       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
00747 
00748       /* Set the DMA error callback */
00749       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
00750 
00751       /* Enable the DMA channel */
00752       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
00753 
00754       /* Enable the TIM Output Compare DMA request */
00755       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
00756     }
00757     break;
00758 
00759     case TIM_CHANNEL_4:
00760     {
00761      /* Set the DMA Period elapsed callback */
00762       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
00763 
00764       /* Set the DMA error callback */
00765       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
00766 
00767       /* Enable the DMA channel */
00768       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
00769 
00770       /* Enable the TIM Output Compare DMA request */
00771       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
00772     }
00773     break;
00774 
00775     default:
00776     break;
00777   }
00778 
00779   /* Enable the Capture compare channel N */
00780   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00781 
00782   /* Enable the Main Ouput */
00783   __HAL_TIM_MOE_ENABLE(htim);
00784 
00785   /* Enable the Peripheral */
00786   __HAL_TIM_ENABLE(htim);
00787 
00788   /* Return function status */
00789   return HAL_OK;
00790 }
00791 
00792 /**
00793   * @brief  Stops the TIM Output Compare signal generation in DMA mode
00794   *         on the complementary output.
00795   * @param  htim : TIM Output Compare handle
00796   * @param  Channel : TIM Channel to be disabled
00797   *          This parameter can be one of the following values:
00798   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00799   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00800   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00801   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00802   * @retval HAL status
00803   */
00804 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
00805 {
00806   /* Check the parameters */
00807   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00808 
00809   switch (Channel)
00810   {
00811     case TIM_CHANNEL_1:
00812     {
00813       /* Disable the TIM Output Compare DMA request */
00814       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
00815     }
00816     break;
00817 
00818     case TIM_CHANNEL_2:
00819     {
00820       /* Disable the TIM Output Compare DMA request */
00821       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
00822     }
00823     break;
00824 
00825     case TIM_CHANNEL_3:
00826     {
00827       /* Disable the TIM Output Compare DMA request */
00828       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
00829     }
00830     break;
00831 
00832     case TIM_CHANNEL_4:
00833     {
00834       /* Disable the TIM Output Compare interrupt */
00835       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
00836     }
00837     break;
00838 
00839     default:
00840     break;
00841   }
00842 
00843   /* Disable the Capture compare channel N */
00844   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00845 
00846   /* Disable the Main Ouput */
00847   __HAL_TIM_MOE_DISABLE(htim);
00848 
00849   /* Disable the Peripheral */
00850   __HAL_TIM_DISABLE(htim);
00851 
00852   /* Change the htim state */
00853   htim->State = HAL_TIM_STATE_READY;
00854 
00855   /* Return function status */
00856   return HAL_OK;
00857 }
00858 
00859 /**
00860   * @}
00861   */
00862 
00863 /** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
00864   * @brief    Timer Complementary PWM functions
00865   *
00866 @verbatim
00867   ==============================================================================
00868                  ##### Timer Complementary PWM functions #####
00869   ==============================================================================
00870   [..]
00871     This section provides functions allowing to:
00872     (+) Start the Complementary PWM.
00873     (+) Stop the Complementary PWM.
00874     (+) Start the Complementary PWM and enable interrupts.
00875     (+) Stop the Complementary PWM and disable interrupts.
00876     (+) Start the Complementary PWM and enable DMA transfers.
00877     (+) Stop the Complementary PWM and disable DMA transfers.
00878     (+) Start the Complementary Input Capture measurement.
00879     (+) Stop the Complementary Input Capture.
00880     (+) Start the Complementary Input Capture and enable interrupts.
00881     (+) Stop the Complementary Input Capture and disable interrupts.
00882     (+) Start the Complementary Input Capture and enable DMA transfers.
00883     (+) Stop the Complementary Input Capture and disable DMA transfers.
00884     (+) Start the Complementary One Pulse generation.
00885     (+) Stop the Complementary One Pulse.
00886     (+) Start the Complementary One Pulse and enable interrupts.
00887     (+) Stop the Complementary One Pulse and disable interrupts.
00888 
00889 @endverbatim
00890   * @{
00891   */
00892 
00893 /**
00894   * @brief  Starts the PWM signal generation on the complementary output.
00895   * @param  htim : TIM handle
00896   * @param  Channel : TIM Channel to be enabled
00897   *          This parameter can be one of the following values:
00898   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00899   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00900   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00901   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00902   * @retval HAL status
00903   */
00904 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
00905 {
00906   /* Check the parameters */
00907   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00908 
00909   /* Enable the complementary PWM output  */
00910   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
00911 
00912   /* Enable the Main Ouput */
00913   __HAL_TIM_MOE_ENABLE(htim);
00914 
00915   /* Enable the Peripheral */
00916   __HAL_TIM_ENABLE(htim);
00917 
00918   /* Return function status */
00919   return HAL_OK;
00920 }
00921 
00922 /**
00923   * @brief  Stops the PWM signal generation on the complementary output.
00924   * @param  htim : TIM handle
00925   * @param  Channel : TIM Channel to be disabled
00926   *          This parameter can be one of the following values:
00927   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00928   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00929   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00930   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00931   * @retval HAL status
00932   */
00933 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
00934 {
00935   /* Check the parameters */
00936   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00937 
00938   /* Disable the complementary PWM output  */
00939   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
00940 
00941   /* Disable the Main Ouput */
00942   __HAL_TIM_MOE_DISABLE(htim);
00943 
00944   /* Disable the Peripheral */
00945   __HAL_TIM_DISABLE(htim);
00946 
00947   /* Return function status */
00948   return HAL_OK;
00949 }
00950 
00951 /**
00952   * @brief  Starts the PWM signal generation in interrupt mode on the
00953   *         complementary output.
00954   * @param  htim : TIM handle
00955   * @param  Channel : TIM Channel to be disabled
00956   *          This parameter can be one of the following values:
00957   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
00958   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
00959   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
00960   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
00961   * @retval HAL status
00962   */
00963 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
00964 {
00965   /* Check the parameters */
00966   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
00967 
00968   switch (Channel)
00969   {
00970     case TIM_CHANNEL_1:
00971     {
00972       /* Enable the TIM Capture/Compare 1 interrupt */
00973       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
00974     }
00975     break;
00976 
00977     case TIM_CHANNEL_2:
00978     {
00979       /* Enable the TIM Capture/Compare 2 interrupt */
00980       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
00981     }
00982     break;
00983 
00984     case TIM_CHANNEL_3:
00985     {
00986       /* Enable the TIM Capture/Compare 3 interrupt */
00987       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
00988     }
00989     break;
00990 
00991     case TIM_CHANNEL_4:
00992     {
00993       /* Enable the TIM Capture/Compare 4 interrupt */
00994       __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
00995     }
00996     break;
00997 
00998     default:
00999     break;
01000   }
01001 
01002   /* Enable the TIM Break interrupt */
01003   __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
01004 
01005   /* Enable the complementary PWM output  */
01006   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01007 
01008   /* Enable the Main Ouput */
01009   __HAL_TIM_MOE_ENABLE(htim);
01010 
01011   /* Enable the Peripheral */
01012   __HAL_TIM_ENABLE(htim);
01013 
01014   /* Return function status */
01015   return HAL_OK;
01016 }
01017 
01018 /**
01019   * @brief  Stops the PWM signal generation in interrupt mode on the
01020   *         complementary output.
01021   * @param  htim : TIM handle
01022   * @param  Channel : TIM Channel to be disabled
01023   *          This parameter can be one of the following values:
01024   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01025   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01026   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01027   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01028   * @retval HAL status
01029   */
01030 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
01031 {
01032   uint32_t tmpccer = 0;
01033 
01034   /* Check the parameters */
01035   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01036 
01037   switch (Channel)
01038   {
01039     case TIM_CHANNEL_1:
01040     {
01041       /* Disable the TIM Capture/Compare 1 interrupt */
01042       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01043     }
01044     break;
01045 
01046     case TIM_CHANNEL_2:
01047     {
01048       /* Disable the TIM Capture/Compare 2 interrupt */
01049       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01050     }
01051     break;
01052 
01053     case TIM_CHANNEL_3:
01054     {
01055       /* Disable the TIM Capture/Compare 3 interrupt */
01056       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
01057     }
01058     break;
01059 
01060     case TIM_CHANNEL_4:
01061     {
01062       /* Disable the TIM Capture/Compare 3 interrupt */
01063       __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
01064     }
01065     break;
01066 
01067     default:
01068     break;
01069   }
01070 
01071   /* Disable the complementary PWM output  */
01072   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01073 
01074   
01075   /* Disable the TIM Break interrupt (only if no more channel is active) */
01076   tmpccer = htim->Instance->CCER;
01077   if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
01078   {
01079     __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
01080   }
01081 
01082   /* Disable the Main Ouput */
01083   __HAL_TIM_MOE_DISABLE(htim);
01084 
01085   /* Disable the Peripheral */
01086   __HAL_TIM_DISABLE(htim);
01087 
01088   /* Return function status */
01089   return HAL_OK;
01090 }
01091 
01092 /**
01093   * @brief  Starts the TIM PWM signal generation in DMA mode on the
01094   *         complementary output
01095   * @param  htim : TIM handle
01096   * @param  Channel : TIM Channel to be enabled
01097   *          This parameter can be one of the following values:
01098   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01099   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01100   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01101   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01102   * @param  pData: The source Buffer address.
01103   * @param  Length: The length of data to be transferred from memory to TIM peripheral
01104   * @retval HAL status
01105   */
01106 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
01107 {
01108   /* Check the parameters */
01109   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01110 
01111   if((htim->State == HAL_TIM_STATE_BUSY))
01112   {
01113      return HAL_BUSY;
01114   }
01115   else if((htim->State == HAL_TIM_STATE_READY))
01116   {
01117     if(((uint32_t)pData == 0 ) && (Length > 0))
01118     {
01119       return HAL_ERROR;
01120     }
01121     else
01122     {
01123       htim->State = HAL_TIM_STATE_BUSY;
01124     }
01125   }
01126   switch (Channel)
01127   {
01128     case TIM_CHANNEL_1:
01129     {
01130       /* Set the DMA Period elapsed callback */
01131       htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
01132 
01133       /* Set the DMA error callback */
01134       htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
01135 
01136       /* Enable the DMA channel */
01137       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
01138 
01139       /* Enable the TIM Capture/Compare 1 DMA request */
01140       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
01141     }
01142     break;
01143 
01144     case TIM_CHANNEL_2:
01145     {
01146       /* Set the DMA Period elapsed callback */
01147       htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
01148 
01149       /* Set the DMA error callback */
01150       htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
01151 
01152       /* Enable the DMA channel */
01153       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
01154 
01155       /* Enable the TIM Capture/Compare 2 DMA request */
01156       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
01157     }
01158     break;
01159 
01160     case TIM_CHANNEL_3:
01161     {
01162       /* Set the DMA Period elapsed callback */
01163       htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
01164 
01165       /* Set the DMA error callback */
01166       htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
01167 
01168       /* Enable the DMA channel */
01169       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
01170 
01171       /* Enable the TIM Capture/Compare 3 DMA request */
01172       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
01173     }
01174     break;
01175 
01176     case TIM_CHANNEL_4:
01177     {
01178      /* Set the DMA Period elapsed callback */
01179       htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
01180 
01181       /* Set the DMA error callback */
01182       htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
01183 
01184       /* Enable the DMA channel */
01185       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
01186 
01187       /* Enable the TIM Capture/Compare 4 DMA request */
01188       __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
01189     }
01190     break;
01191 
01192     default:
01193     break;
01194   }
01195 
01196   /* Enable the complementary PWM output  */
01197   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
01198 
01199   /* Enable the Main Ouput */
01200   __HAL_TIM_MOE_ENABLE(htim);
01201 
01202   /* Enable the Peripheral */
01203   __HAL_TIM_ENABLE(htim);
01204 
01205   /* Return function status */
01206   return HAL_OK;
01207 }
01208 
01209 /**
01210   * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
01211   *         output
01212   * @param  htim : TIM handle
01213   * @param  Channel : TIM Channel to be disabled
01214   *          This parameter can be one of the following values:
01215   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01216   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01217   *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
01218   *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
01219   * @retval HAL status
01220   */
01221 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
01222 {
01223   /* Check the parameters */
01224   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
01225 
01226   switch (Channel)
01227   {
01228     case TIM_CHANNEL_1:
01229     {
01230       /* Disable the TIM Capture/Compare 1 DMA request */
01231       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
01232     }
01233     break;
01234 
01235     case TIM_CHANNEL_2:
01236     {
01237       /* Disable the TIM Capture/Compare 2 DMA request */
01238       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
01239     }
01240     break;
01241 
01242     case TIM_CHANNEL_3:
01243     {
01244       /* Disable the TIM Capture/Compare 3 DMA request */
01245       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
01246     }
01247     break;
01248 
01249     case TIM_CHANNEL_4:
01250     {
01251       /* Disable the TIM Capture/Compare 4 DMA request */
01252       __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
01253     }
01254     break;
01255 
01256     default:
01257     break;
01258   }
01259 
01260   /* Disable the complementary PWM output */
01261   TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
01262 
01263   /* Disable the Main Ouput */
01264   __HAL_TIM_MOE_DISABLE(htim);
01265 
01266   /* Disable the Peripheral */
01267   __HAL_TIM_DISABLE(htim);
01268 
01269   /* Change the htim state */
01270   htim->State = HAL_TIM_STATE_READY;
01271 
01272   /* Return function status */
01273   return HAL_OK;
01274 }
01275 
01276 /**
01277   * @}
01278   */
01279 
01280 /** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
01281   * @brief    Timer Complementary One Pulse functions
01282   *
01283 @verbatim
01284   ==============================================================================
01285                 ##### Timer Complementary One Pulse functions #####
01286   ==============================================================================
01287   [..]
01288     This section provides functions allowing to:
01289     (+) Start the Complementary One Pulse generation.
01290     (+) Stop the Complementary One Pulse.
01291     (+) Start the Complementary One Pulse and enable interrupts.
01292     (+) Stop the Complementary One Pulse and disable interrupts.
01293 
01294 @endverbatim
01295   * @{
01296   */
01297 
01298 /**
01299   * @brief  Starts the TIM One Pulse signal generation on the complementary
01300   *         output.
01301   * @param  htim : TIM One Pulse handle
01302   * @param  OutputChannel : TIM Channel to be enabled
01303   *          This parameter can be one of the following values:
01304   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01305   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01306   * @retval HAL status
01307   */
01308 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01309   {
01310   /* Check the parameters */
01311   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01312 
01313   /* Enable the complementary One Pulse output */
01314   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01315 
01316   /* Enable the Main Ouput */
01317   __HAL_TIM_MOE_ENABLE(htim);
01318 
01319   /* Return function status */
01320   return HAL_OK;
01321 }
01322 
01323 /**
01324   * @brief  Stops the TIM One Pulse signal generation on the complementary
01325   *         output.
01326   * @param  htim : TIM One Pulse handle
01327   * @param  OutputChannel : TIM Channel to be disabled
01328   *          This parameter can be one of the following values:
01329   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01330   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01331   * @retval HAL status
01332   */
01333 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01334 {
01335 
01336   /* Check the parameters */
01337   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01338 
01339   /* Disable the complementary One Pulse output */
01340   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01341 
01342   /* Disable the Main Ouput */
01343   __HAL_TIM_MOE_DISABLE(htim);
01344 
01345   /* Disable the Peripheral */
01346   __HAL_TIM_DISABLE(htim);
01347 
01348   /* Return function status */
01349   return HAL_OK;
01350 }
01351 
01352 /**
01353   * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
01354   *         complementary channel.
01355   * @param  htim : TIM One Pulse handle
01356   * @param  OutputChannel : TIM Channel to be enabled
01357   *          This parameter can be one of the following values:
01358   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01359   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01360   * @retval HAL status
01361   */
01362 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01363 {
01364   /* Check the parameters */
01365   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01366 
01367   /* Enable the TIM Capture/Compare 1 interrupt */
01368   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
01369 
01370   /* Enable the TIM Capture/Compare 2 interrupt */
01371   __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
01372 
01373   /* Enable the complementary One Pulse output */
01374   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
01375 
01376   /* Enable the Main Ouput */
01377   __HAL_TIM_MOE_ENABLE(htim);
01378 
01379   /* Return function status */
01380   return HAL_OK;
01381 }
01382 
01383 /**
01384   * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
01385   *         complementary channel.
01386   * @param  htim : TIM One Pulse handle
01387   * @param  OutputChannel : TIM Channel to be disabled
01388   *          This parameter can be one of the following values:
01389   *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
01390   *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
01391   * @retval HAL status
01392   */
01393 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
01394 {
01395   /* Check the parameters */
01396   assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
01397 
01398   /* Disable the TIM Capture/Compare 1 interrupt */
01399   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
01400 
01401   /* Disable the TIM Capture/Compare 2 interrupt */
01402   __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
01403 
01404   /* Disable the complementary One Pulse output */
01405   TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
01406 
01407   /* Disable the Main Ouput */
01408   __HAL_TIM_MOE_DISABLE(htim);
01409 
01410   /* Disable the Peripheral */
01411   __HAL_TIM_DISABLE(htim);
01412 
01413   /* Return function status */
01414   return HAL_OK;
01415 }
01416 
01417 /**
01418   * @}
01419   */
01420 
01421 /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
01422   * @brief    Peripheral Control functions
01423   *
01424 @verbatim
01425   ==============================================================================
01426                     ##### Peripheral Control functions #####
01427   ==============================================================================
01428   [..]
01429     This section provides functions allowing to:
01430     (+) Configure the commutation event in case of use of the Hall sensor interface.
01431       (+) Configure Output channels for OC and PWM mode.
01432 
01433       (+) Configure Complementary channels, break features and dead time.
01434       (+) Configure Master synchronization.
01435       (+) Configure timer remapping capabilities.
01436       (+) Enable or disable channel grouping
01437 
01438 @endverbatim
01439   * @{
01440   */
01441 
01442 /**
01443   * @brief  Configure the TIM commutation event sequence.
01444   * @note  This function is mandatory to use the commutation event in order to
01445   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01446   *        the typical use of this feature is with the use of another Timer(interface Timer)
01447   *        configured in Hall sensor interface, this interface Timer will generate the
01448   *        commutation at its TRGO output (connected to Timer used in this function) each time
01449   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01450   * @param  htim: TIM handle
01451   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01452   *          This parameter can be one of the following values:
01453   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01454   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01455   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01456   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01457   *            @arg TIM_TS_NONE: No trigger is needed
01458   * @param  CommutationSource : the Commutation Event source
01459   *          This parameter can be one of the following values:
01460   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01461   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01462   * @retval HAL status
01463   */
01464 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01465 {
01466   /* Check the parameters */
01467   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01468   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01469 
01470   __HAL_LOCK(htim);
01471 
01472   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01473       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01474   {
01475     /* Select the Input trigger */
01476     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01477     htim->Instance->SMCR |= InputTrigger;
01478   }
01479 
01480   /* Select the Capture Compare preload feature */
01481   htim->Instance->CR2 |= TIM_CR2_CCPC;
01482   /* Select the Commutation event source */
01483   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01484   htim->Instance->CR2 |= CommutationSource;
01485 
01486   __HAL_UNLOCK(htim);
01487 
01488   return HAL_OK;
01489 }
01490 
01491 /**
01492   * @brief  Configure the TIM commutation event sequence with interrupt.
01493   * @note  This function is mandatory to use the commutation event in order to
01494   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01495   *        the typical use of this feature is with the use of another Timer(interface Timer)
01496   *        configured in Hall sensor interface, this interface Timer will generate the
01497   *        commutation at its TRGO output (connected to Timer used in this function) each time
01498   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01499   * @param  htim: TIM handle
01500   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01501   *          This parameter can be one of the following values:
01502   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01503   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01504   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01505   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01506   *            @arg TIM_TS_NONE: No trigger is needed
01507   * @param  CommutationSource : the Commutation Event source
01508   *          This parameter can be one of the following values:
01509   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01510   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01511   * @retval HAL status
01512   */
01513 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01514 {
01515   /* Check the parameters */
01516   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01517   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01518 
01519   __HAL_LOCK(htim);
01520 
01521   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01522       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01523   {
01524     /* Select the Input trigger */
01525     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01526     htim->Instance->SMCR |= InputTrigger;
01527   }
01528 
01529   /* Select the Capture Compare preload feature */
01530   htim->Instance->CR2 |= TIM_CR2_CCPC;
01531   /* Select the Commutation event source */
01532   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01533   htim->Instance->CR2 |= CommutationSource;
01534 
01535   /* Enable the Commutation Interrupt Request */
01536   __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
01537 
01538   __HAL_UNLOCK(htim);
01539 
01540   return HAL_OK;
01541 }
01542 
01543 /**
01544   * @brief  Configure the TIM commutation event sequence with DMA.
01545   * @note  This function is mandatory to use the commutation event in order to
01546   *        update the configuration at each commutation detection on the TRGI input of the Timer,
01547   *        the typical use of this feature is with the use of another Timer(interface Timer)
01548   *        configured in Hall sensor interface, this interface Timer will generate the
01549   *        commutation at its TRGO output (connected to Timer used in this function) each time
01550   *        the TI1 of the Interface Timer detect a commutation at its input TI1.
01551   * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set
01552   * @param  htim: TIM handle
01553   * @param  InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
01554   *          This parameter can be one of the following values:
01555   *            @arg TIM_TS_ITR0: Internal trigger 0 selected
01556   *            @arg TIM_TS_ITR1: Internal trigger 1 selected
01557   *            @arg TIM_TS_ITR2: Internal trigger 2 selected
01558   *            @arg TIM_TS_ITR3: Internal trigger 3 selected
01559   *            @arg TIM_TS_NONE: No trigger is needed
01560   * @param  CommutationSource : the Commutation Event source
01561   *          This parameter can be one of the following values:
01562   *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
01563   *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit
01564   * @retval HAL status
01565   */
01566 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
01567 {
01568   /* Check the parameters */
01569   assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
01570   assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
01571 
01572   __HAL_LOCK(htim);
01573 
01574   if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
01575       (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
01576   {
01577     /* Select the Input trigger */
01578     htim->Instance->SMCR &= ~TIM_SMCR_TS;
01579     htim->Instance->SMCR |= InputTrigger;
01580   }
01581 
01582   /* Select the Capture Compare preload feature */
01583   htim->Instance->CR2 |= TIM_CR2_CCPC;
01584   /* Select the Commutation event source */
01585   htim->Instance->CR2 &= ~TIM_CR2_CCUS;
01586   htim->Instance->CR2 |= CommutationSource;
01587 
01588   /* Enable the Commutation DMA Request */
01589   /* Set the DMA Commutation Callback */
01590   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
01591   /* Set the DMA error callback */
01592   htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
01593 
01594   /* Enable the Commutation DMA Request */
01595   __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
01596 
01597   __HAL_UNLOCK(htim);
01598 
01599   return HAL_OK;
01600 }
01601 
01602 /**
01603   * @brief  Configures the TIM in master mode.
01604   * @param  htim: TIM handle.
01605   * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
01606   *         contains the selected trigger output (TRGO) and the Master/Slave
01607   *         mode.
01608   * @retval HAL status
01609   */
01610 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
01611                                                       TIM_MasterConfigTypeDef * sMasterConfig)
01612 {
01613   uint32_t tmpcr2;
01614   uint32_t tmpsmcr;
01615 
01616   /* Check the parameters */
01617   assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
01618   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
01619   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
01620 
01621   /* Check input state */
01622   __HAL_LOCK(htim);
01623 
01624  /* Get the TIMx CR2 register value */
01625   tmpcr2 = htim->Instance->CR2;
01626 
01627   /* Get the TIMx SMCR register value */
01628   tmpsmcr = htim->Instance->SMCR;
01629 
01630   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
01631   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
01632   {
01633     /* Check the parameters */
01634     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
01635 
01636     /* Clear the MMS2 bits */
01637     tmpcr2 &= ~TIM_CR2_MMS2;
01638     /* Select the TRGO2 source*/
01639     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
01640   }
01641 
01642   /* Reset the MMS Bits */
01643   tmpcr2 &= ~TIM_CR2_MMS;
01644   /* Select the TRGO source */
01645   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
01646 
01647   /* Reset the MSM Bit */
01648   tmpsmcr &= ~TIM_SMCR_MSM;
01649   /* Set master mode */
01650   tmpsmcr |= sMasterConfig->MasterSlaveMode;
01651 
01652   /* Update TIMx CR2 */
01653   htim->Instance->CR2 = tmpcr2;
01654 
01655   /* Update TIMx SMCR */
01656   htim->Instance->SMCR = tmpsmcr;
01657 
01658   __HAL_UNLOCK(htim);
01659 
01660   return HAL_OK;
01661 }
01662 
01663 /**
01664   * @brief   Configures the Break feature, dead time, Lock level, OSSI/OSSR State
01665   *         and the AOE(automatic output enable).
01666   * @param  htim: TIM handle
01667   * @param  sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
01668   *         contains the BDTR Register configuration  information for the TIM peripheral.
01669   * @retval HAL status
01670   */
01671 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
01672                                                 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
01673 {
01674   uint32_t tmpbdtr = 0;
01675 
01676   /* Check the parameters */
01677   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01678   assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
01679   assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
01680   assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
01681   assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
01682   assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
01683   assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
01684   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
01685   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
01686 
01687   /* Check input state */
01688   __HAL_LOCK(htim);
01689 
01690   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
01691      the OSSI State, the dead time value and the Automatic Output Enable Bit */
01692   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
01693   {
01694     assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
01695     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
01696     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
01697 
01698     /* Clear the BDTR bits */
01699     tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
01700                  TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
01701                  TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF |
01702                  TIM_BDTR_BK2F | TIM_BDTR_BK2E | TIM_BDTR_BK2P);
01703 
01704     /* Set the BDTR bits */
01705     tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
01706     tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
01707     tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
01708     tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
01709     tmpbdtr |= sBreakDeadTimeConfig->BreakState;
01710     tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
01711     tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
01712     tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
01713     tmpbdtr |= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
01714     tmpbdtr |= sBreakDeadTimeConfig->Break2State;
01715     tmpbdtr |= sBreakDeadTimeConfig->Break2Polarity;
01716   }
01717   else
01718   {
01719     /* Clear the BDTR bits */
01720     tmpbdtr &= ~(TIM_BDTR_DTG | TIM_BDTR_LOCK |  TIM_BDTR_OSSI |
01721                  TIM_BDTR_OSSR | TIM_BDTR_BKE | TIM_BDTR_BKP |
01722                  TIM_BDTR_AOE | TIM_BDTR_MOE | TIM_BDTR_BKF);
01723 
01724     /* Set the BDTR bits */
01725     tmpbdtr |= sBreakDeadTimeConfig->DeadTime;
01726     tmpbdtr |= sBreakDeadTimeConfig->LockLevel;
01727     tmpbdtr |= sBreakDeadTimeConfig->OffStateIDLEMode;
01728     tmpbdtr |= sBreakDeadTimeConfig->OffStateRunMode;
01729     tmpbdtr |= sBreakDeadTimeConfig->BreakState;
01730     tmpbdtr |= sBreakDeadTimeConfig->BreakPolarity;
01731     tmpbdtr |= sBreakDeadTimeConfig->AutomaticOutput;
01732     tmpbdtr |= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
01733   }
01734 
01735   /* Set TIMx_BDTR */
01736   htim->Instance->BDTR = tmpbdtr;
01737 
01738   __HAL_UNLOCK(htim);
01739 
01740   return HAL_OK;
01741 }
01742 
01743 /**
01744   * @brief  Configures the break input source.
01745   * @param  htim: TIM handle.
01746   * @param  BreakInput: Break input to configure
01747   *          This parameter can be one of the following values:
01748   *            @arg TIM_BREAKINPUT_BRK: Timer break input
01749   *            @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
01750   * @param  sBreakInputConfig: Break input source configuration
01751   * @retval HAL status
01752   */
01753 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
01754                                              uint32_t BreakInput,
01755                                              TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
01756 
01757 {
01758   uint32_t tmporx = 0;
01759   uint32_t bkin_enable_mask = 0;
01760   uint32_t bkin_polarity_mask = 0;
01761   uint32_t bkin_enable_bitpos = 0;
01762   uint32_t bkin_polarity_bitpos = 0;
01763 
01764   /* Check the parameters */
01765   assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
01766   assert_param(IS_TIM_BREAKINPUT(BreakInput));
01767   assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
01768   assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
01769 
01770 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01771   if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01772   {
01773     assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01774   }
01775 #else
01776    assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
01777 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01778   
01779   /* Check input state */
01780   __HAL_LOCK(htim);
01781   
01782   switch(sBreakInputConfig->Source)
01783   {
01784   case TIM_BREAKINPUTSOURCE_BKIN:
01785     {
01786       bkin_enable_mask = TIM1_OR2_BKINE;
01787       bkin_enable_bitpos = 0;
01788       bkin_polarity_mask = TIM1_OR2_BKINP;
01789       bkin_polarity_bitpos = 9;
01790     }
01791     break;
01792   case TIM_BREAKINPUTSOURCE_COMP1:
01793     {
01794       bkin_enable_mask = TIM1_OR2_BKCMP1E;
01795       bkin_enable_bitpos = 1;
01796       bkin_polarity_mask = TIM1_OR2_BKCMP1P;
01797       bkin_polarity_bitpos = 10;
01798     }
01799     break;
01800   case TIM_BREAKINPUTSOURCE_COMP2:
01801     {
01802       bkin_enable_mask = TIM1_OR2_BKCMP2E;
01803       bkin_enable_bitpos = 2;
01804       bkin_polarity_mask = TIM1_OR2_BKCMP2P;
01805       bkin_polarity_bitpos = 11;
01806     }
01807     break;
01808 
01809 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01810   case TIM_BREAKINPUTSOURCE_DFSDM1:
01811     {
01812       bkin_enable_mask = TIM1_OR2_BKDF1BK0E;
01813       bkin_enable_bitpos = 8;
01814     }
01815     break;    
01816 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01817 
01818   default:
01819     break;
01820   }
01821   
01822   switch(BreakInput)
01823   {
01824     case TIM_BREAKINPUT_BRK:
01825       {
01826         /* Get the TIMx_OR2 register value */
01827         tmporx = htim->Instance->OR2;
01828         
01829         /* Enable the break input */
01830         tmporx &= ~bkin_enable_mask;
01831         tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01832         
01833         /* Set the break input polarity */
01834 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01835         if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01836 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01837         {
01838           tmporx &= ~bkin_polarity_mask;
01839           tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01840         }
01841         
01842         /* Set TIMx_OR2 */
01843         htim->Instance->OR2 = tmporx;        
01844       }
01845         break;
01846     case TIM_BREAKINPUT_BRK2:
01847       {
01848         /* Get the TIMx_OR3 register value */
01849         tmporx = htim->Instance->OR3;
01850         
01851         /* Enable the break input */
01852         tmporx &= ~bkin_enable_mask;
01853         tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
01854         
01855         /* Set the break input polarity */
01856 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
01857         if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
01858 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
01859         {
01860           tmporx &= ~bkin_polarity_mask;
01861           tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
01862         }
01863         
01864         /* Set TIMx_OR3 */
01865         htim->Instance->OR3 = tmporx;        
01866       }
01867       break;    
01868   default:
01869     break;
01870   }
01871   
01872   __HAL_UNLOCK(htim);
01873 
01874   return HAL_OK;
01875 }
01876 
01877 /**
01878   * @brief  Configures the TIMx Remapping input capabilities.
01879   * @param  htim: TIM handle.
01880   * @param  Remap: specifies the TIM remapping source.
01881   *
01882   @if STM32L486xx
01883   *         For TIM1, the parameter is a combination of 4 fields (field1 | field2 | field3 | field4):
01884   *
01885   *                   field1 can have the following values:
01886   *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
01887   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
01888   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
01889   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
01890   *
01891   *                   field2 can have the following values:
01892   *            @arg TIM_TIM1_ETR_ADC3_NONE:           TIM1_ETR is not connected to any ADC3 AWD (analog watchdog)
01893   *            @arg TIM_TIM1_ETR_ADC3_AWD1:           TIM1_ETR is connected to ADC3 AWD1
01894   *            @arg TIM_TIM1_ETR_ADC3_AWD2:           TIM1_ETR is connected to ADC3 AWD2
01895   *            @arg TIM_TIM1_ETR_ADC3_AWD3:           TIM1_ETR is connected to ADC3 AWD3
01896   *
01897   *                   field3 can have the following values:
01898   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
01899   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
01900   *
01901   *                   field4 can have the following values:
01902   *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
01903   *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
01904   *            @note  When field4 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 and field2 values are not significant 
01905   @endif
01906   @if STM32L443xx
01907   *         For TIM1, the parameter is a combination of 3 fields (field1 | field2 | field3):
01908   *
01909   *                   field1 can have the following values:
01910   *            @arg TIM_TIM1_ETR_ADC1_NONE:           TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
01911   *            @arg TIM_TIM1_ETR_ADC1_AWD1:           TIM1_ETR is connected to ADC1 AWD1
01912   *            @arg TIM_TIM1_ETR_ADC1_AWD2:           TIM1_ETR is connected to ADC1 AWD2
01913   *            @arg TIM_TIM1_ETR_ADC1_AWD3:           TIM1_ETR is connected to ADC1 AWD3
01914   *
01915   *                   field2 can have the following values:
01916   *            @arg TIM_TIM1_TI1_GPIO:                TIM1 TI1 is connected to GPIO
01917   *            @arg TIM_TIM1_TI1_COMP1:               TIM1 TI1 is connected to COMP1 output
01918   *
01919   *                   field3 can have the following values:
01920   *            @arg TIM_TIM1_ETR_COMP1:               TIM1_ETR is connected to COMP1 output
01921   *            @arg TIM_TIM1_ETR_COMP2:               TIM1_ETR is connected to COMP2 output
01922   *
01923   *            @note  When field3 is set to TIM_TIM1_ETR_COMP1 or TIM_TIM1_ETR_COMP2 field1 values is not significant 
01924   *
01925   @endif
01926   @if STM32L486xx
01927   *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
01928   *
01929   *                   field1 can have the following values:
01930   *            @arg TIM_TIM2_ITR1_TIM8_TRGO:          TIM2_ITR1 is connected to TIM8_TRGO
01931   *            @arg TIM_TIM2_ITR1_OTG_FS_SOF:         TIM2_ITR1 is connected to OTG_FS SOF
01932   *
01933   *                   field2 can have the following values:
01934   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
01935   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
01936   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
01937   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
01938   *
01939   *                   field3 can have the following values:
01940   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
01941   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
01942   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
01943   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
01944   @endif
01945   @if STM32L443xx
01946   *         For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
01947   *
01948   *                   field1 can have the following values:
01949   *            @arg TIM_TIM2_ITR1_NONE:               No internal trigger on TIM2_ITR1
01950   *            @arg TIM_TIM2_ITR1_USB_SOF:            TIM2_ITR1 is connected to USB SOF
01951   *
01952   *                   field2 can have the following values:
01953   *            @arg TIM_TIM2_ETR_GPIO:                TIM2_ETR is connected to GPIO
01954   *            @arg TIM_TIM2_ETR_LSE:                 TIM2_ETR is connected to LSE
01955   *            @arg TIM_TIM2_ETR_COMP1:               TIM2_ETR is connected to COMP1 output
01956   *            @arg TIM_TIM2_ETR_COMP2:               TIM2_ETR is connected to COMP2 output
01957   *
01958   *                   field3 can have the following values:
01959   *            @arg TIM_TIM2_TI4_GPIO:                TIM2 TI4 is connected to GPIO
01960   *            @arg TIM_TIM2_TI4_COMP1:               TIM2 TI4 is connected to COMP1 output
01961   *            @arg TIM_TIM2_TI4_COMP2:               TIM2 TI4 is connected to COMP2 output
01962   *            @arg TIM_TIM2_TI4_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output
01963   *
01964   @endif
01965   @if STM32L486xx
01966   *         For TIM3, the parameter is a combination 2 fields(field1 | field2):
01967   *
01968   *                   field1 can have the following values:
01969   *            @arg TIM_TIM3_TI1_GPIO:                TIM3 TI1 is connected to GPIO
01970   *            @arg TIM_TIM3_TI1_COMP1:               TIM3 TI1 is connected to COMP1 output
01971   *            @arg TIM_TIM3_TI1_COMP2:               TIM3 TI1 is connected to COMP2 output
01972   *            @arg TIM_TIM3_TI1_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output
01973   *
01974   *                   field2 can have the following values:
01975   *            @arg TIM_TIM3_ETR_GPIO:                TIM3_ETR is connected to GPIO
01976   *            @arg TIM_TIM3_ETR_COMP1:               TIM3_ETR is connected to COMP1 output
01977   *
01978   @endif
01979   @if STM32L486xx
01980   *         For TIM8, the parameter is a combination of 3 fields (field1 | field2 | field3):
01981   *
01982   *                   field1 can have the following values:
01983   *            @arg TIM_TIM8_ETR_ADC2_NONE:          TIM8_ETR is not connected to any ADC2 AWD (analog watchdog)
01984   *            @arg TIM_TIM8_ETR_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1
01985   *            @arg TIM_TIM8_ETR_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2
01986   *            @arg TIM_TIM8_ETR_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3
01987   *
01988   *                   field2 can have the following values:
01989   *            @arg TIM_TIM8_ETR_ADC3_NONE:          TIM8_ETR is not connected to any ADC3 AWD (analog watchdog)
01990   *            @arg TIM_TIM8_ETR_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1
01991   *            @arg TIM_TIM8_ETR_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2
01992   *            @arg TIM_TIM8_ETR_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3
01993   *
01994   *                   field3 can have the following values:
01995   *            @arg TIM_TIM8_TI1_GPIO:               TIM8 TI1 is connected to GPIO
01996   *            @arg TIM_TIM8_TI1_COMP2:              TIM8 TI1 is connected to COMP2 output
01997   *
01998   *                   field4 can have the following values:
01999   *            @arg TIM_TIM8_ETR_COMP1:               TIM8_ETR is connected to COMP1 output
02000   *            @arg TIM_TIM8_ETR_COMP2:               TIM8_ETR is connected to COMP2 output
02001   *            @note  When field4 is set to TIM_TIM8_ETR_COMP1 or TIM_TIM8_ETR_COMP2 field1 and field2 values are not significant 
02002   *
02003   @endif
02004   *         For TIM15, the parameter is a combination of 3 fields (field1 | field2):
02005   *
02006   *                   field1 can have the following values:
02007   *            @arg TIM_TIM15_TI1_GPIO:              TIM15 TI1 is connected to GPIO
02008   *            @arg TIM_TIM15_TI1_LSE:               TIM15 TI1 is connected to LSE
02009   *
02010   *                   field2 can have the following values:
02011   *            @arg TIM_TIM15_ENCODERMODE_NONE:      No redirection 
02012   *            @arg TIM_TIM15_ENCODERMODE_TIM2:      TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
02013   *            @arg TIM_TIM15_ENCODERMODE_TIM3:      TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
02014   *            @arg TIM_TIM15_ENCODERMODE_TIM4:      TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
02015   *
02016   @if STM32L486xx
02017   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
02018   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
02019   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
02020   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
02021   *
02022   @endif
02023   @if STM32L443xx
02024   *         For TIM16, the parameter can have the following values:
02025   *            @arg TIM_TIM16_TI1_GPIO:              TIM16 TI1 is connected to GPIO
02026   *            @arg TIM_TIM16_TI1_LSI:               TIM16 TI1 is connected to LSI
02027   *            @arg TIM_TIM16_TI1_LSE:               TIM16 TI1 is connected to LSE
02028   *            @arg TIM_TIM16_TI1_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt
02029   *            @arg TIM_TIM16_TI1_MSI:               TIM16 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
02030   *            @arg TIM_TIM16_TI1_HSE_32:            TIM16 TI1 is connected to HSE div 32  (note that HSE div 32 must be selected as RTC clock source)
02031   *            @arg TIM_TIM16_TI1_MCO:               TIM16 TI1 is connected to MCO
02032   *
02033   @endif
02034   @if STM32L486xx
02035   *         For TIM17, the parameter can have the following values:
02036   *            @arg TIM_TIM17_TI1_GPIO:              TIM17 TI1 is connected to GPIO
02037   *            @arg TIM_TIM17_TI1_MSI:               TIM17 TI1 is connected to MSI  (contraints: MSI clock < 1/4 TIM APB clock)
02038   *            @arg TIM_TIM17_TI1_HSE_32:            TIM17 TI1 is connected to HSE div 32
02039   *            @arg TIM_TIM17_TI1_MCO:               TIM17 TI1 is connected to MCO
02040   @endif
02041   *
02042   * @retval HAL status
02043   */
02044 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
02045 {
02046   uint32_t tmpor1 = 0;
02047   uint32_t tmpor2 = 0;
02048   
02049   __HAL_LOCK(htim);
02050 
02051   /* Check parameters */
02052   assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
02053   assert_param(IS_TIM_REMAP(Remap));
02054   
02055   /* Set ETR_SEL bit field (if required) */
02056   if (IS_TIM_ETRSEL_INSTANCE(htim->Instance))
02057   {
02058     tmpor2 = htim->Instance->OR2;
02059     tmpor2 &= ~TIMx_ETRSEL_MASK;
02060     tmpor2 |= (Remap & TIMx_ETRSEL_MASK);
02061     
02062     /* Set TIMx_OR2 */
02063     htim->Instance->OR2 = tmpor2;        
02064   }
02065   
02066   /* Set other remapping capabilities */
02067   tmpor1 = Remap;
02068   tmpor1 &= ~TIMx_ETRSEL_MASK;
02069 
02070   /* Set TIMx_OR1 */
02071   htim->Instance->OR1 = Remap;
02072   
02073   /* Set TIMx_OR1 */
02074   htim->Instance->OR1 = tmpor1;        
02075   
02076   htim->State = HAL_TIM_STATE_READY;
02077 
02078   __HAL_UNLOCK(htim);
02079 
02080   return HAL_OK;
02081 }
02082 
02083 /**
02084   * @brief  Group channel 5 and channel 1, 2 or 3
02085   * @param  htim: TIM handle.
02086   * @param  Channels: specifies the reference signal(s) the OC5REF is combined with.
02087   *         This parameter can be any combination of the following values:
02088   *         TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
02089   *         TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
02090   *         TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
02091   *         TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
02092   * @retval HAL status
02093   */
02094 HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
02095 {
02096   /* Check parameters */
02097   assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
02098   assert_param(IS_TIM_GROUPCH5(Channels));
02099 
02100   /* Process Locked */
02101   __HAL_LOCK(htim);
02102 
02103   htim->State = HAL_TIM_STATE_BUSY;
02104 
02105   /* Clear GC5Cx bit fields */
02106   htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3|TIM_CCR5_GC5C2|TIM_CCR5_GC5C1);
02107 
02108   /* Set GC5Cx bit fields */
02109   htim->Instance->CCR5 |= Channels;
02110 
02111   htim->State = HAL_TIM_STATE_READY;
02112 
02113   __HAL_UNLOCK(htim);
02114 
02115   return HAL_OK;
02116 }
02117 
02118 /**
02119   * @}
02120   */
02121 
02122 /** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
02123   * @brief    Extended Callbacks functions
02124   *
02125 @verbatim
02126   ==============================================================================
02127                     ##### Extended Callbacks functions #####
02128   ==============================================================================
02129   [..]
02130     This section provides Extended TIM callback functions:
02131     (+) Timer Commutation callback
02132     (+) Timer Break callback
02133 
02134 @endverbatim
02135   * @{
02136   */
02137 
02138 /**
02139   * @brief  Hall commutation changed callback in non-blocking mode
02140   * @param  htim : TIM handle
02141   * @retval None
02142   */
02143 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
02144 {
02145   /* Prevent unused argument(s) compilation warning */
02146   UNUSED(htim);
02147 
02148   /* NOTE : This function should not be modified, when the callback is needed,
02149             the HAL_TIMEx_CommutationCallback could be implemented in the user file
02150    */
02151 }
02152 
02153 /**
02154   * @brief  Hall Break detection callback in non-blocking mode
02155   * @param  htim : TIM handle
02156   * @retval None
02157   */
02158 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
02159 {
02160   /* Prevent unused argument(s) compilation warning */
02161   UNUSED(htim);
02162 
02163   /* NOTE : This function should not be modified, when the callback is needed,
02164             the HAL_TIMEx_BreakCallback could be implemented in the user file
02165    */
02166 }
02167 
02168 /**
02169   * @}
02170   */
02171 
02172 /** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
02173   * @brief    Extended Peripheral State functions
02174   *
02175 @verbatim
02176   ==============================================================================
02177                 ##### Extended Peripheral State functions #####
02178   ==============================================================================
02179   [..]
02180     This subsection permits to get in run-time the status of the peripheral
02181     and the data flow.
02182 
02183 @endverbatim
02184   * @{
02185   */
02186 
02187 /**
02188   * @brief  Return the TIM Hall Sensor interface handle state.
02189   * @param  htim: TIM Hall Sensor handle
02190   * @retval HAL state
02191   */
02192 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
02193 {
02194   return htim->State;
02195 }
02196 
02197 /**
02198   * @}
02199   */
02200 
02201 /**
02202   * @brief  TIM DMA Commutation callback.
02203   * @param  hdma : pointer to DMA handle.
02204   * @retval None
02205   */
02206 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
02207 {
02208   TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02209 
02210   htim->State= HAL_TIM_STATE_READY;
02211 
02212   HAL_TIMEx_CommutationCallback(htim);
02213 }
02214 
02215 /**
02216   * @brief  Enables or disables the TIM Capture Compare Channel xN.
02217   * @param  TIMx to select the TIM peripheral
02218   * @param  Channel: specifies the TIM Channel
02219   *          This parameter can be one of the following values:
02220   *            @arg TIM_Channel_1: TIM Channel 1
02221   *            @arg TIM_Channel_2: TIM Channel 2
02222   *            @arg TIM_Channel_3: TIM Channel 3
02223   * @param  ChannelNState: specifies the TIM Channel CCxNE bit new state.
02224   *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
02225   * @retval None
02226   */
02227 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
02228 {
02229   uint32_t tmp = 0;
02230 
02231   tmp = TIM_CCER_CC1NE << Channel;
02232 
02233   /* Reset the CCxNE Bit */
02234   TIMx->CCER &=  ~tmp;
02235 
02236   /* Set or reset the CCxNE Bit */
02237   TIMx->CCER |=  (uint32_t)(ChannelNState << Channel);
02238 }
02239 
02240 /**
02241   * @}
02242   */
02243 
02244 #endif /* HAL_TIM_MODULE_ENABLED */
02245 /**
02246   * @}
02247   */
02248 
02249 /**
02250   * @}
02251   */
02252 
02253 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/