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stm32l4xx_hal_tim.c
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_tim.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief TIM HAL module driver. 00008 * This file provides firmware functions to manage the following 00009 * functionalities of the Timer (TIM) peripheral: 00010 * + Time Base Initialization 00011 * + Time Base Start 00012 * + Time Base Start Interruption 00013 * + Time Base Start DMA 00014 * + Time Output Compare/PWM Initialization 00015 * + Time Output Compare/PWM Channel Configuration 00016 * + Time Output Compare/PWM Start 00017 * + Time Output Compare/PWM Start Interruption 00018 * + Time Output Compare/PWM Start DMA 00019 * + Time Input Capture Initialization 00020 * + Time Input Capture Channel Configuration 00021 * + Time Input Capture Start 00022 * + Time Input Capture Start Interruption 00023 * + Time Input Capture Start DMA 00024 * + Time One Pulse Initialization 00025 * + Time One Pulse Channel Configuration 00026 * + Time One Pulse Start 00027 * + Time Encoder Interface Initialization 00028 * + Time Encoder Interface Start 00029 * + Time Encoder Interface Start Interruption 00030 * + Time Encoder Interface Start DMA 00031 * + Commutation Event configuration with Interruption and DMA 00032 * + Time OCRef clear configuration 00033 * + Time External Clock configuration 00034 @verbatim 00035 ============================================================================== 00036 ##### TIMER Generic features ##### 00037 ============================================================================== 00038 [..] The Timer features include: 00039 (#) 16-bit up, down, up/down auto-reload counter. 00040 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the 00041 counter clock frequency either by any factor between 1 and 65536. 00042 (#) Up to 4 independent channels for: 00043 (++) Input Capture 00044 (++) Output Compare 00045 (++) PWM generation (Edge and Center-aligned Mode) 00046 (++) One-pulse mode output 00047 00048 ##### How to use this driver ##### 00049 ============================================================================== 00050 [..] 00051 (#) Initialize the TIM low level resources by implementing the following functions 00052 depending on the selected feature: 00053 (++) Time Base : HAL_TIM_Base_MspInit() 00054 (++) Input Capture : HAL_TIM_IC_MspInit() 00055 (++) Output Compare : HAL_TIM_OC_MspInit() 00056 (++) PWM generation : HAL_TIM_PWM_MspInit() 00057 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() 00058 (++) Encoder mode output : HAL_TIM_Encoder_MspInit() 00059 00060 (#) Initialize the TIM low level resources : 00061 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); 00062 (##) TIM pins configuration 00063 (+++) Enable the clock for the TIM GPIOs using the following function: 00064 __HAL_RCC_GPIOx_CLK_ENABLE(); 00065 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); 00066 00067 (#) The external Clock can be configured, if needed (the default clock is the 00068 internal clock from the APBx), using the following function: 00069 HAL_TIM_ConfigClockSource, the clock configuration should be done before 00070 any start function. 00071 00072 (#) Configure the TIM in the desired functioning mode using one of the 00073 Initialization function of this driver: 00074 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base 00075 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an 00076 Output Compare signal. 00077 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a 00078 PWM signal. 00079 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an 00080 external signal. 00081 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer 00082 in One Pulse Mode. 00083 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. 00084 00085 (#) Activate the TIM peripheral using one of the start functions depending from the feature used: 00086 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() 00087 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() 00088 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() 00089 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() 00090 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() 00091 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). 00092 00093 (#) The DMA Burst is managed with the two following functions: 00094 HAL_TIM_DMABurst_WriteStart() 00095 HAL_TIM_DMABurst_ReadStart() 00096 00097 @endverbatim 00098 ****************************************************************************** 00099 * @attention 00100 * 00101 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00102 * 00103 * Redistribution and use in source and binary forms, with or without modification, 00104 * are permitted provided that the following conditions are met: 00105 * 1. Redistributions of source code must retain the above copyright notice, 00106 * this list of conditions and the following disclaimer. 00107 * 2. Redistributions in binary form must reproduce the above copyright notice, 00108 * this list of conditions and the following disclaimer in the documentation 00109 * and/or other materials provided with the distribution. 00110 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00111 * may be used to endorse or promote products derived from this software 00112 * without specific prior written permission. 00113 * 00114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00124 * 00125 ****************************************************************************** 00126 */ 00127 00128 /* Includes ------------------------------------------------------------------*/ 00129 #include "stm32l4xx_hal.h" 00130 00131 /** @addtogroup STM32L4xx_HAL_Driver 00132 * @{ 00133 */ 00134 00135 /** @defgroup TIM TIM 00136 * @brief TIM HAL module driver 00137 * @{ 00138 */ 00139 00140 #ifdef HAL_TIM_MODULE_ENABLED 00141 00142 /* Private typedef -----------------------------------------------------------*/ 00143 /* Private define ------------------------------------------------------------*/ 00144 /* Private macro -------------------------------------------------------------*/ 00145 /* Private variables ---------------------------------------------------------*/ 00146 /* Private function prototypes -----------------------------------------------*/ 00147 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00148 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00149 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00150 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00151 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); 00152 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); 00153 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00154 uint32_t TIM_ICFilter); 00155 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); 00156 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00157 uint32_t TIM_ICFilter); 00158 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 00159 uint32_t TIM_ICFilter); 00160 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); 00161 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); 00162 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); 00163 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, 00164 TIM_SlaveConfigTypeDef * sSlaveConfig); 00165 /* Exported functions --------------------------------------------------------*/ 00166 00167 /** @defgroup TIM_Exported_Functions TIM Exported Functions 00168 * @{ 00169 */ 00170 00171 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions 00172 * @brief Time Base functions 00173 * 00174 @verbatim 00175 ============================================================================== 00176 ##### Time Base functions ##### 00177 ============================================================================== 00178 [..] 00179 This section provides functions allowing to: 00180 (+) Initialize and configure the TIM base. 00181 (+) De-initialize the TIM base. 00182 (+) Start the Time Base. 00183 (+) Stop the Time Base. 00184 (+) Start the Time Base and enable interrupt. 00185 (+) Stop the Time Base and disable interrupt. 00186 (+) Start the Time Base and enable DMA transfer. 00187 (+) Stop the Time Base and disable DMA transfer. 00188 00189 @endverbatim 00190 * @{ 00191 */ 00192 /** 00193 * @brief Initializes the TIM Time base Unit according to the specified 00194 * parameters in the TIM_HandleTypeDef and initialize the associated handle. 00195 * @param htim: TIM Base handle 00196 * @retval HAL status 00197 */ 00198 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) 00199 { 00200 /* Check the TIM handle allocation */ 00201 if(htim == NULL) 00202 { 00203 return HAL_ERROR; 00204 } 00205 00206 /* Check the parameters */ 00207 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00208 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00209 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00210 00211 if(htim->State == HAL_TIM_STATE_RESET) 00212 { 00213 /* Allocate lock resource and initialize it */ 00214 htim->Lock = HAL_UNLOCKED; 00215 00216 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00217 HAL_TIM_Base_MspInit(htim); 00218 } 00219 00220 /* Set the TIM state */ 00221 htim->State= HAL_TIM_STATE_BUSY; 00222 00223 /* Set the Time Base configuration */ 00224 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00225 00226 /* Initialize the TIM state*/ 00227 htim->State= HAL_TIM_STATE_READY; 00228 00229 return HAL_OK; 00230 } 00231 00232 /** 00233 * @brief DeInitialize the TIM Base peripheral 00234 * @param htim: TIM Base handle 00235 * @retval HAL status 00236 */ 00237 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) 00238 { 00239 /* Check the parameters */ 00240 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00241 00242 htim->State = HAL_TIM_STATE_BUSY; 00243 00244 /* Disable the TIM Peripheral Clock */ 00245 __HAL_TIM_DISABLE(htim); 00246 00247 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 00248 HAL_TIM_Base_MspDeInit(htim); 00249 00250 /* Change TIM state */ 00251 htim->State = HAL_TIM_STATE_RESET; 00252 00253 /* Release Lock */ 00254 __HAL_UNLOCK(htim); 00255 00256 return HAL_OK; 00257 } 00258 00259 /** 00260 * @brief Initializes the TIM Base MSP. 00261 * @param htim: TIM handle 00262 * @retval None 00263 */ 00264 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) 00265 { 00266 /* Prevent unused argument(s) compilation warning */ 00267 UNUSED(htim); 00268 00269 /* NOTE : This function should not be modified, when the callback is needed, 00270 the HAL_TIM_Base_MspInit could be implemented in the user file 00271 */ 00272 } 00273 00274 /** 00275 * @brief DeInitialize TIM Base MSP. 00276 * @param htim: TIM handle 00277 * @retval None 00278 */ 00279 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) 00280 { 00281 /* Prevent unused argument(s) compilation warning */ 00282 UNUSED(htim); 00283 00284 /* NOTE : This function should not be modified, when the callback is needed, 00285 the HAL_TIM_Base_MspDeInit could be implemented in the user file 00286 */ 00287 } 00288 00289 00290 /** 00291 * @brief Starts the TIM Base generation. 00292 * @param htim : TIM handle 00293 * @retval HAL status 00294 */ 00295 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) 00296 { 00297 /* Check the parameters */ 00298 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00299 00300 /* Set the TIM state */ 00301 htim->State= HAL_TIM_STATE_BUSY; 00302 00303 /* Enable the Peripheral */ 00304 __HAL_TIM_ENABLE(htim); 00305 00306 /* Change the TIM state*/ 00307 htim->State= HAL_TIM_STATE_READY; 00308 00309 /* Return function status */ 00310 return HAL_OK; 00311 } 00312 00313 /** 00314 * @brief Stops the TIM Base generation. 00315 * @param htim : TIM handle 00316 * @retval HAL status 00317 */ 00318 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) 00319 { 00320 /* Check the parameters */ 00321 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00322 00323 /* Set the TIM state */ 00324 htim->State= HAL_TIM_STATE_BUSY; 00325 00326 /* Disable the Peripheral */ 00327 __HAL_TIM_DISABLE(htim); 00328 00329 /* Change the TIM state*/ 00330 htim->State= HAL_TIM_STATE_READY; 00331 00332 /* Return function status */ 00333 return HAL_OK; 00334 } 00335 00336 /** 00337 * @brief Starts the TIM Base generation in interrupt mode. 00338 * @param htim : TIM handle 00339 * @retval HAL status 00340 */ 00341 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) 00342 { 00343 /* Check the parameters */ 00344 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00345 00346 /* Enable the TIM Update interrupt */ 00347 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 00348 00349 /* Enable the Peripheral */ 00350 __HAL_TIM_ENABLE(htim); 00351 00352 /* Return function status */ 00353 return HAL_OK; 00354 } 00355 00356 /** 00357 * @brief Stops the TIM Base generation in interrupt mode. 00358 * @param htim : TIM handle 00359 * @retval HAL status 00360 */ 00361 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) 00362 { 00363 /* Check the parameters */ 00364 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00365 /* Disable the TIM Update interrupt */ 00366 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); 00367 00368 /* Disable the Peripheral */ 00369 __HAL_TIM_DISABLE(htim); 00370 00371 /* Return function status */ 00372 return HAL_OK; 00373 } 00374 00375 /** 00376 * @brief Starts the TIM Base generation in DMA mode. 00377 * @param htim : TIM handle 00378 * @param pData: The source Buffer address. 00379 * @param Length: The length of data to be transferred from memory to peripheral. 00380 * @retval HAL status 00381 */ 00382 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) 00383 { 00384 /* Check the parameters */ 00385 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 00386 00387 if((htim->State == HAL_TIM_STATE_BUSY)) 00388 { 00389 return HAL_BUSY; 00390 } 00391 else if((htim->State == HAL_TIM_STATE_READY)) 00392 { 00393 if((pData == 0 ) && (Length > 0)) 00394 { 00395 return HAL_ERROR; 00396 } 00397 else 00398 { 00399 htim->State = HAL_TIM_STATE_BUSY; 00400 } 00401 } 00402 /* Set the DMA Period elapsed callback */ 00403 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 00404 00405 /* Set the DMA error callback */ 00406 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 00407 00408 /* Enable the DMA channel */ 00409 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); 00410 00411 /* Enable the TIM Update DMA request */ 00412 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); 00413 00414 /* Enable the Peripheral */ 00415 __HAL_TIM_ENABLE(htim); 00416 00417 /* Return function status */ 00418 return HAL_OK; 00419 } 00420 00421 /** 00422 * @brief Stops the TIM Base generation in DMA mode. 00423 * @param htim : TIM handle 00424 * @retval HAL status 00425 */ 00426 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) 00427 { 00428 /* Check the parameters */ 00429 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); 00430 00431 /* Disable the TIM Update DMA request */ 00432 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); 00433 00434 /* Disable the Peripheral */ 00435 __HAL_TIM_DISABLE(htim); 00436 00437 /* Change the htim state */ 00438 htim->State = HAL_TIM_STATE_READY; 00439 00440 /* Return function status */ 00441 return HAL_OK; 00442 } 00443 00444 /** 00445 * @} 00446 */ 00447 00448 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions 00449 * @brief Time Output Compare functions 00450 * 00451 @verbatim 00452 ============================================================================== 00453 ##### Time Output Compare functions ##### 00454 ============================================================================== 00455 [..] 00456 This section provides functions allowing to: 00457 (+) Initialize and configure the TIM Output Compare. 00458 (+) De-initialize the TIM Output Compare. 00459 (+) Start the Time Output Compare. 00460 (+) Stop the Time Output Compare. 00461 (+) Start the Time Output Compare and enable interrupt. 00462 (+) Stop the Time Output Compare and disable interrupt. 00463 (+) Start the Time Output Compare and enable DMA transfer. 00464 (+) Stop the Time Output Compare and disable DMA transfer. 00465 00466 @endverbatim 00467 * @{ 00468 */ 00469 /** 00470 * @brief Initializes the TIM Output Compare according to the specified 00471 * parameters in the TIM_HandleTypeDef and initialize the associated handle. 00472 * @param htim: TIM Output Compare handle 00473 * @retval HAL status 00474 */ 00475 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) 00476 { 00477 /* Check the TIM handle allocation */ 00478 if(htim == NULL) 00479 { 00480 return HAL_ERROR; 00481 } 00482 00483 /* Check the parameters */ 00484 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00485 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 00486 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 00487 00488 if(htim->State == HAL_TIM_STATE_RESET) 00489 { 00490 /* Allocate lock resource and initialize it */ 00491 htim->Lock = HAL_UNLOCKED; 00492 00493 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 00494 HAL_TIM_OC_MspInit(htim); 00495 } 00496 00497 /* Set the TIM state */ 00498 htim->State= HAL_TIM_STATE_BUSY; 00499 00500 /* Init the base time for the Output Compare */ 00501 TIM_Base_SetConfig(htim->Instance, &htim->Init); 00502 00503 /* Initialize the TIM state*/ 00504 htim->State= HAL_TIM_STATE_READY; 00505 00506 return HAL_OK; 00507 } 00508 00509 /** 00510 * @brief DeInitialize the TIM peripheral 00511 * @param htim: TIM Output Compare handle 00512 * @retval HAL status 00513 */ 00514 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) 00515 { 00516 /* Check the parameters */ 00517 assert_param(IS_TIM_INSTANCE(htim->Instance)); 00518 00519 htim->State = HAL_TIM_STATE_BUSY; 00520 00521 /* Disable the TIM Peripheral Clock */ 00522 __HAL_TIM_DISABLE(htim); 00523 00524 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 00525 HAL_TIM_OC_MspDeInit(htim); 00526 00527 /* Change TIM state */ 00528 htim->State = HAL_TIM_STATE_RESET; 00529 00530 /* Release Lock */ 00531 __HAL_UNLOCK(htim); 00532 00533 return HAL_OK; 00534 } 00535 00536 /** 00537 * @brief Initializes the TIM Output Compare MSP. 00538 * @param htim: TIM handle 00539 * @retval None 00540 */ 00541 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) 00542 { 00543 /* Prevent unused argument(s) compilation warning */ 00544 UNUSED(htim); 00545 00546 /* NOTE : This function should not be modified, when the callback is needed, 00547 the HAL_TIM_OC_MspInit could be implemented in the user file 00548 */ 00549 } 00550 00551 /** 00552 * @brief DeInitialize TIM Output Compare MSP. 00553 * @param htim: TIM handle 00554 * @retval None 00555 */ 00556 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) 00557 { 00558 /* Prevent unused argument(s) compilation warning */ 00559 UNUSED(htim); 00560 00561 /* NOTE : This function should not be modified, when the callback is needed, 00562 the HAL_TIM_OC_MspDeInit could be implemented in the user file 00563 */ 00564 } 00565 00566 /** 00567 * @brief Starts the TIM Output Compare signal generation. 00568 * @param htim : TIM Output Compare handle 00569 * @param Channel : TIM Channel to be enabled 00570 * This parameter can be one of the following values: 00571 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00572 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00573 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00574 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00575 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00576 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00577 * @retval HAL status 00578 */ 00579 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 00580 { 00581 /* Check the parameters */ 00582 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00583 00584 /* Enable the Output compare channel */ 00585 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00586 00587 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00588 { 00589 /* Enable the main output */ 00590 __HAL_TIM_MOE_ENABLE(htim); 00591 } 00592 00593 /* Enable the Peripheral */ 00594 __HAL_TIM_ENABLE(htim); 00595 00596 /* Return function status */ 00597 return HAL_OK; 00598 } 00599 00600 /** 00601 * @brief Stops the TIM Output Compare signal generation. 00602 * @param htim : TIM handle 00603 * @param Channel : TIM Channel to be disabled 00604 * This parameter can be one of the following values: 00605 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00606 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00607 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00608 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00609 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00610 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00611 * @retval HAL status 00612 */ 00613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 00614 { 00615 /* Check the parameters */ 00616 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00617 00618 /* Disable the Output compare channel */ 00619 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00620 00621 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00622 { 00623 /* Disable the Main Ouput */ 00624 __HAL_TIM_MOE_DISABLE(htim); 00625 } 00626 00627 /* Disable the Peripheral */ 00628 __HAL_TIM_DISABLE(htim); 00629 00630 /* Return function status */ 00631 return HAL_OK; 00632 } 00633 00634 /** 00635 * @brief Starts the TIM Output Compare signal generation in interrupt mode. 00636 * @param htim : TIM OC handle 00637 * @param Channel : TIM Channel to be enabled 00638 * This parameter can be one of the following values: 00639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00643 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00644 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00645 * @retval HAL status 00646 */ 00647 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00648 { 00649 /* Check the parameters */ 00650 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00651 00652 switch (Channel) 00653 { 00654 case TIM_CHANNEL_1: 00655 { 00656 /* Enable the TIM Capture/Compare 1 interrupt */ 00657 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 00658 } 00659 break; 00660 00661 case TIM_CHANNEL_2: 00662 { 00663 /* Enable the TIM Capture/Compare 2 interrupt */ 00664 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 00665 } 00666 break; 00667 00668 case TIM_CHANNEL_3: 00669 { 00670 /* Enable the TIM Capture/Compare 3 interrupt */ 00671 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 00672 } 00673 break; 00674 00675 case TIM_CHANNEL_4: 00676 { 00677 /* Enable the TIM Capture/Compare 4 interrupt */ 00678 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 00679 } 00680 break; 00681 00682 default: 00683 break; 00684 } 00685 00686 /* Enable the Output compare channel */ 00687 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00688 00689 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00690 { 00691 /* Enable the main output */ 00692 __HAL_TIM_MOE_ENABLE(htim); 00693 } 00694 00695 /* Enable the Peripheral */ 00696 __HAL_TIM_ENABLE(htim); 00697 00698 /* Return function status */ 00699 return HAL_OK; 00700 } 00701 00702 /** 00703 * @brief Stops the TIM Output Compare signal generation in interrupt mode. 00704 * @param htim : TIM Output Compare handle 00705 * @param Channel : TIM Channel to be disabled 00706 * This parameter can be one of the following values: 00707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00709 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00710 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00711 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00712 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00713 * @retval HAL status 00714 */ 00715 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 00716 { 00717 /* Check the parameters */ 00718 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00719 00720 switch (Channel) 00721 { 00722 case TIM_CHANNEL_1: 00723 { 00724 /* Disable the TIM Capture/Compare 1 interrupt */ 00725 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 00726 } 00727 break; 00728 00729 case TIM_CHANNEL_2: 00730 { 00731 /* Disable the TIM Capture/Compare 2 interrupt */ 00732 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 00733 } 00734 break; 00735 00736 case TIM_CHANNEL_3: 00737 { 00738 /* Disable the TIM Capture/Compare 3 interrupt */ 00739 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 00740 } 00741 break; 00742 00743 case TIM_CHANNEL_4: 00744 { 00745 /* Disable the TIM Capture/Compare 4 interrupt */ 00746 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 00747 } 00748 break; 00749 00750 default: 00751 break; 00752 } 00753 00754 /* Disable the Output compare channel */ 00755 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00756 00757 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00758 { 00759 /* Disable the Main Ouput */ 00760 __HAL_TIM_MOE_DISABLE(htim); 00761 } 00762 00763 /* Disable the Peripheral */ 00764 __HAL_TIM_DISABLE(htim); 00765 00766 /* Return function status */ 00767 return HAL_OK; 00768 } 00769 00770 /** 00771 * @brief Starts the TIM Output Compare signal generation in DMA mode. 00772 * @param htim : TIM Output Compare handle 00773 * @param Channel : TIM Channel to be enabled 00774 * This parameter can be one of the following values: 00775 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00776 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00777 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00778 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00779 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00780 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00781 * @param pData: The source Buffer address. 00782 * @param Length: The length of data to be transferred from memory to TIM peripheral 00783 * @retval HAL status 00784 */ 00785 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 00786 { 00787 /* Check the parameters */ 00788 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00789 00790 if((htim->State == HAL_TIM_STATE_BUSY)) 00791 { 00792 return HAL_BUSY; 00793 } 00794 else if((htim->State == HAL_TIM_STATE_READY)) 00795 { 00796 if(((uint32_t)pData == 0 ) && (Length > 0)) 00797 { 00798 return HAL_ERROR; 00799 } 00800 else 00801 { 00802 htim->State = HAL_TIM_STATE_BUSY; 00803 } 00804 } 00805 switch (Channel) 00806 { 00807 case TIM_CHANNEL_1: 00808 { 00809 /* Set the DMA Period elapsed callback */ 00810 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 00811 00812 /* Set the DMA error callback */ 00813 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 00814 00815 /* Enable the DMA channel */ 00816 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); 00817 00818 /* Enable the TIM Capture/Compare 1 DMA request */ 00819 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 00820 } 00821 break; 00822 00823 case TIM_CHANNEL_2: 00824 { 00825 /* Set the DMA Period elapsed callback */ 00826 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 00827 00828 /* Set the DMA error callback */ 00829 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 00830 00831 /* Enable the DMA channel */ 00832 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); 00833 00834 /* Enable the TIM Capture/Compare 2 DMA request */ 00835 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 00836 } 00837 break; 00838 00839 case TIM_CHANNEL_3: 00840 { 00841 /* Set the DMA Period elapsed callback */ 00842 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 00843 00844 /* Set the DMA error callback */ 00845 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 00846 00847 /* Enable the DMA channel */ 00848 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); 00849 00850 /* Enable the TIM Capture/Compare 3 DMA request */ 00851 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 00852 } 00853 break; 00854 00855 case TIM_CHANNEL_4: 00856 { 00857 /* Set the DMA Period elapsed callback */ 00858 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 00859 00860 /* Set the DMA error callback */ 00861 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 00862 00863 /* Enable the DMA channel */ 00864 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); 00865 00866 /* Enable the TIM Capture/Compare 4 DMA request */ 00867 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 00868 } 00869 break; 00870 00871 default: 00872 break; 00873 } 00874 00875 /* Enable the Output compare channel */ 00876 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 00877 00878 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00879 { 00880 /* Enable the main output */ 00881 __HAL_TIM_MOE_ENABLE(htim); 00882 } 00883 00884 /* Enable the Peripheral */ 00885 __HAL_TIM_ENABLE(htim); 00886 00887 /* Return function status */ 00888 return HAL_OK; 00889 } 00890 00891 /** 00892 * @brief Stops the TIM Output Compare signal generation in DMA mode. 00893 * @param htim : TIM Output Compare handle 00894 * @param Channel : TIM Channel to be disabled 00895 * This parameter can be one of the following values: 00896 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 00897 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 00898 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 00899 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 00900 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 00901 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 00902 * @retval HAL status 00903 */ 00904 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 00905 { 00906 /* Check the parameters */ 00907 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 00908 00909 switch (Channel) 00910 { 00911 case TIM_CHANNEL_1: 00912 { 00913 /* Disable the TIM Capture/Compare 1 DMA request */ 00914 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 00915 } 00916 break; 00917 00918 case TIM_CHANNEL_2: 00919 { 00920 /* Disable the TIM Capture/Compare 2 DMA request */ 00921 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 00922 } 00923 break; 00924 00925 case TIM_CHANNEL_3: 00926 { 00927 /* Disable the TIM Capture/Compare 3 DMA request */ 00928 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 00929 } 00930 break; 00931 00932 case TIM_CHANNEL_4: 00933 { 00934 /* Disable the TIM Capture/Compare 4 interrupt */ 00935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 00936 } 00937 break; 00938 00939 default: 00940 break; 00941 } 00942 00943 /* Disable the Output compare channel */ 00944 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 00945 00946 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 00947 { 00948 /* Disable the Main Ouput */ 00949 __HAL_TIM_MOE_DISABLE(htim); 00950 } 00951 00952 /* Disable the Peripheral */ 00953 __HAL_TIM_DISABLE(htim); 00954 00955 /* Change the htim state */ 00956 htim->State = HAL_TIM_STATE_READY; 00957 00958 /* Return function status */ 00959 return HAL_OK; 00960 } 00961 00962 /** 00963 * @} 00964 */ 00965 00966 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions 00967 * @brief Time PWM functions 00968 * 00969 @verbatim 00970 ============================================================================== 00971 ##### Time PWM functions ##### 00972 ============================================================================== 00973 [..] 00974 This section provides functions allowing to: 00975 (+) Initialize and configure the TIM OPWM. 00976 (+) De-initialize the TIM PWM. 00977 (+) Start the Time PWM. 00978 (+) Stop the Time PWM. 00979 (+) Start the Time PWM and enable interrupt. 00980 (+) Stop the Time PWM and disable interrupt. 00981 (+) Start the Time PWM and enable DMA transfer. 00982 (+) Stop the Time PWM and disable DMA transfer. 00983 00984 @endverbatim 00985 * @{ 00986 */ 00987 /** 00988 * @brief Initializes the TIM PWM Time Base according to the specified 00989 * parameters in the TIM_HandleTypeDef and initialize the associated handle. 00990 * @param htim: TIM handle 00991 * @retval HAL status 00992 */ 00993 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) 00994 { 00995 /* Check the TIM handle allocation */ 00996 if(htim == NULL) 00997 { 00998 return HAL_ERROR; 00999 } 01000 01001 /* Check the parameters */ 01002 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01003 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01004 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01005 01006 if(htim->State == HAL_TIM_STATE_RESET) 01007 { 01008 /* Allocate lock resource and initialize it */ 01009 htim->Lock = HAL_UNLOCKED; 01010 01011 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 01012 HAL_TIM_PWM_MspInit(htim); 01013 } 01014 01015 /* Set the TIM state */ 01016 htim->State= HAL_TIM_STATE_BUSY; 01017 01018 /* Init the base time for the PWM */ 01019 TIM_Base_SetConfig(htim->Instance, &htim->Init); 01020 01021 /* Initialize the TIM state*/ 01022 htim->State= HAL_TIM_STATE_READY; 01023 01024 return HAL_OK; 01025 } 01026 01027 /** 01028 * @brief DeInitialize the TIM peripheral 01029 * @param htim: TIM handle 01030 * @retval HAL status 01031 */ 01032 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) 01033 { 01034 /* Check the parameters */ 01035 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01036 01037 htim->State = HAL_TIM_STATE_BUSY; 01038 01039 /* Disable the TIM Peripheral Clock */ 01040 __HAL_TIM_DISABLE(htim); 01041 01042 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 01043 HAL_TIM_PWM_MspDeInit(htim); 01044 01045 /* Change TIM state */ 01046 htim->State = HAL_TIM_STATE_RESET; 01047 01048 /* Release Lock */ 01049 __HAL_UNLOCK(htim); 01050 01051 return HAL_OK; 01052 } 01053 01054 /** 01055 * @brief Initializes the TIM PWM MSP. 01056 * @param htim: TIM handle 01057 * @retval None 01058 */ 01059 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) 01060 { 01061 /* Prevent unused argument(s) compilation warning */ 01062 UNUSED(htim); 01063 01064 /* NOTE : This function should not be modified, when the callback is needed, 01065 the HAL_TIM_PWM_MspInit could be implemented in the user file 01066 */ 01067 } 01068 01069 /** 01070 * @brief DeInitialize TIM PWM MSP. 01071 * @param htim: TIM handle 01072 * @retval None 01073 */ 01074 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) 01075 { 01076 /* Prevent unused argument(s) compilation warning */ 01077 UNUSED(htim); 01078 01079 /* NOTE : This function should not be modified, when the callback is needed, 01080 the HAL_TIM_PWM_MspDeInit could be implemented in the user file 01081 */ 01082 } 01083 01084 /** 01085 * @brief Starts the PWM signal generation. 01086 * @param htim : TIM handle 01087 * @param Channel : TIM Channels to be enabled 01088 * This parameter can be one of the following values: 01089 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01090 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01091 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01092 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01093 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01094 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01095 * @retval HAL status 01096 */ 01097 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 01098 { 01099 /* Check the parameters */ 01100 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01101 01102 /* Enable the Capture compare channel */ 01103 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01104 01105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01106 { 01107 /* Enable the main output */ 01108 __HAL_TIM_MOE_ENABLE(htim); 01109 } 01110 01111 /* Enable the Peripheral */ 01112 __HAL_TIM_ENABLE(htim); 01113 01114 /* Return function status */ 01115 return HAL_OK; 01116 } 01117 01118 /** 01119 * @brief Stops the PWM signal generation. 01120 * @param htim : TIM handle 01121 * @param Channel : TIM Channels to be disabled 01122 * This parameter can be one of the following values: 01123 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01124 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01125 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01126 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01127 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 01128 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 01129 * @retval HAL status 01130 */ 01131 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 01132 { 01133 /* Check the parameters */ 01134 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01135 01136 /* Disable the Capture compare channel */ 01137 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01138 01139 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01140 { 01141 /* Disable the Main Ouput */ 01142 __HAL_TIM_MOE_DISABLE(htim); 01143 } 01144 01145 /* Disable the Peripheral */ 01146 __HAL_TIM_DISABLE(htim); 01147 01148 /* Change the htim state */ 01149 htim->State = HAL_TIM_STATE_READY; 01150 01151 /* Return function status */ 01152 return HAL_OK; 01153 } 01154 01155 /** 01156 * @brief Starts the PWM signal generation in interrupt mode. 01157 * @param htim : TIM handle 01158 * @param Channel : TIM Channel to be enabled 01159 * This parameter can be one of the following values: 01160 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01161 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01162 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01163 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01164 * @retval HAL status 01165 */ 01166 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01167 { 01168 /* Check the parameters */ 01169 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01170 01171 switch (Channel) 01172 { 01173 case TIM_CHANNEL_1: 01174 { 01175 /* Enable the TIM Capture/Compare 1 interrupt */ 01176 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01177 } 01178 break; 01179 01180 case TIM_CHANNEL_2: 01181 { 01182 /* Enable the TIM Capture/Compare 2 interrupt */ 01183 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01184 } 01185 break; 01186 01187 case TIM_CHANNEL_3: 01188 { 01189 /* Enable the TIM Capture/Compare 3 interrupt */ 01190 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 01191 } 01192 break; 01193 01194 case TIM_CHANNEL_4: 01195 { 01196 /* Enable the TIM Capture/Compare 4 interrupt */ 01197 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 01198 } 01199 break; 01200 01201 default: 01202 break; 01203 } 01204 01205 /* Enable the Capture compare channel */ 01206 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01207 01208 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01209 { 01210 /* Enable the main output */ 01211 __HAL_TIM_MOE_ENABLE(htim); 01212 } 01213 01214 /* Enable the Peripheral */ 01215 __HAL_TIM_ENABLE(htim); 01216 01217 /* Return function status */ 01218 return HAL_OK; 01219 } 01220 01221 /** 01222 * @brief Stops the PWM signal generation in interrupt mode. 01223 * @param htim : TIM handle 01224 * @param Channel : TIM Channels to be disabled 01225 * This parameter can be one of the following values: 01226 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01227 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01228 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01229 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01230 * @retval HAL status 01231 */ 01232 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) 01233 { 01234 /* Check the parameters */ 01235 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01236 01237 switch (Channel) 01238 { 01239 case TIM_CHANNEL_1: 01240 { 01241 /* Disable the TIM Capture/Compare 1 interrupt */ 01242 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01243 } 01244 break; 01245 01246 case TIM_CHANNEL_2: 01247 { 01248 /* Disable the TIM Capture/Compare 2 interrupt */ 01249 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01250 } 01251 break; 01252 01253 case TIM_CHANNEL_3: 01254 { 01255 /* Disable the TIM Capture/Compare 3 interrupt */ 01256 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01257 } 01258 break; 01259 01260 case TIM_CHANNEL_4: 01261 { 01262 /* Disable the TIM Capture/Compare 4 interrupt */ 01263 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 01264 } 01265 break; 01266 01267 default: 01268 break; 01269 } 01270 01271 /* Disable the Capture compare channel */ 01272 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01273 01274 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01275 { 01276 /* Disable the Main Ouput */ 01277 __HAL_TIM_MOE_DISABLE(htim); 01278 } 01279 01280 /* Disable the Peripheral */ 01281 __HAL_TIM_DISABLE(htim); 01282 01283 /* Return function status */ 01284 return HAL_OK; 01285 } 01286 01287 /** 01288 * @brief Starts the TIM PWM signal generation in DMA mode. 01289 * @param htim : TIM handle 01290 * @param Channel : TIM Channels to be enabled 01291 * This parameter can be one of the following values: 01292 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01293 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01294 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01295 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01296 * @param pData: The source Buffer address. 01297 * @param Length: The length of data to be transferred from memory to TIM peripheral 01298 * @retval HAL status 01299 */ 01300 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 01301 { 01302 /* Check the parameters */ 01303 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01304 01305 if((htim->State == HAL_TIM_STATE_BUSY)) 01306 { 01307 return HAL_BUSY; 01308 } 01309 else if((htim->State == HAL_TIM_STATE_READY)) 01310 { 01311 if(((uint32_t)pData == 0 ) && (Length > 0)) 01312 { 01313 return HAL_ERROR; 01314 } 01315 else 01316 { 01317 htim->State = HAL_TIM_STATE_BUSY; 01318 } 01319 } 01320 switch (Channel) 01321 { 01322 case TIM_CHANNEL_1: 01323 { 01324 /* Set the DMA Period elapsed callback */ 01325 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 01326 01327 /* Set the DMA error callback */ 01328 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 01329 01330 /* Enable the DMA channel */ 01331 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); 01332 01333 /* Enable the TIM Capture/Compare 1 DMA request */ 01334 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 01335 } 01336 break; 01337 01338 case TIM_CHANNEL_2: 01339 { 01340 /* Set the DMA Period elapsed callback */ 01341 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 01342 01343 /* Set the DMA error callback */ 01344 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 01345 01346 /* Enable the DMA channel */ 01347 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); 01348 01349 /* Enable the TIM Capture/Compare 2 DMA request */ 01350 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 01351 } 01352 break; 01353 01354 case TIM_CHANNEL_3: 01355 { 01356 /* Set the DMA Period elapsed callback */ 01357 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 01358 01359 /* Set the DMA error callback */ 01360 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 01361 01362 /* Enable the DMA channel */ 01363 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); 01364 01365 /* Enable the TIM Output Capture/Compare 3 request */ 01366 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 01367 } 01368 break; 01369 01370 case TIM_CHANNEL_4: 01371 { 01372 /* Set the DMA Period elapsed callback */ 01373 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 01374 01375 /* Set the DMA error callback */ 01376 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 01377 01378 /* Enable the DMA channel */ 01379 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); 01380 01381 /* Enable the TIM Capture/Compare 4 DMA request */ 01382 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 01383 } 01384 break; 01385 01386 default: 01387 break; 01388 } 01389 01390 /* Enable the Capture compare channel */ 01391 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01392 01393 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01394 { 01395 /* Enable the main output */ 01396 __HAL_TIM_MOE_ENABLE(htim); 01397 } 01398 01399 /* Enable the Peripheral */ 01400 __HAL_TIM_ENABLE(htim); 01401 01402 /* Return function status */ 01403 return HAL_OK; 01404 } 01405 01406 /** 01407 * @brief Stops the TIM PWM signal generation in DMA mode. 01408 * @param htim : TIM handle 01409 * @param Channel : TIM Channels to be disabled 01410 * This parameter can be one of the following values: 01411 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01412 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01413 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01414 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01415 * @retval HAL status 01416 */ 01417 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01418 { 01419 /* Check the parameters */ 01420 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01421 01422 switch (Channel) 01423 { 01424 case TIM_CHANNEL_1: 01425 { 01426 /* Disable the TIM Capture/Compare 1 DMA request */ 01427 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01428 } 01429 break; 01430 01431 case TIM_CHANNEL_2: 01432 { 01433 /* Disable the TIM Capture/Compare 2 DMA request */ 01434 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01435 } 01436 break; 01437 01438 case TIM_CHANNEL_3: 01439 { 01440 /* Disable the TIM Capture/Compare 3 DMA request */ 01441 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01442 } 01443 break; 01444 01445 case TIM_CHANNEL_4: 01446 { 01447 /* Disable the TIM Capture/Compare 4 interrupt */ 01448 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 01449 } 01450 break; 01451 01452 default: 01453 break; 01454 } 01455 01456 /* Disable the Capture compare channel */ 01457 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01458 01459 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 01460 { 01461 /* Disable the Main Ouput */ 01462 __HAL_TIM_MOE_DISABLE(htim); 01463 } 01464 01465 /* Disable the Peripheral */ 01466 __HAL_TIM_DISABLE(htim); 01467 01468 /* Change the htim state */ 01469 htim->State = HAL_TIM_STATE_READY; 01470 01471 /* Return function status */ 01472 return HAL_OK; 01473 } 01474 01475 /** 01476 * @} 01477 */ 01478 01479 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions 01480 * @brief Time Input Capture functions 01481 * 01482 @verbatim 01483 ============================================================================== 01484 ##### Time Input Capture functions ##### 01485 ============================================================================== 01486 [..] 01487 This section provides functions allowing to: 01488 (+) Initialize and configure the TIM Input Capture. 01489 (+) De-initialize the TIM Input Capture. 01490 (+) Start the Time Input Capture. 01491 (+) Stop the Time Input Capture. 01492 (+) Start the Time Input Capture and enable interrupt. 01493 (+) Stop the Time Input Capture and disable interrupt. 01494 (+) Start the Time Input Capture and enable DMA transfer. 01495 (+) Stop the Time Input Capture and disable DMA transfer. 01496 01497 @endverbatim 01498 * @{ 01499 */ 01500 /** 01501 * @brief Initializes the TIM Input Capture Time base according to the specified 01502 * parameters in the TIM_HandleTypeDef and initialize the associated handle. 01503 * @param htim: TIM Input Capture handle 01504 * @retval HAL status 01505 */ 01506 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) 01507 { 01508 /* Check the TIM handle allocation */ 01509 if(htim == NULL) 01510 { 01511 return HAL_ERROR; 01512 } 01513 01514 /* Check the parameters */ 01515 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01516 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01517 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01518 01519 if(htim->State == HAL_TIM_STATE_RESET) 01520 { 01521 /* Allocate lock resource and initialize it */ 01522 htim->Lock = HAL_UNLOCKED; 01523 01524 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 01525 HAL_TIM_IC_MspInit(htim); 01526 } 01527 01528 /* Set the TIM state */ 01529 htim->State= HAL_TIM_STATE_BUSY; 01530 01531 /* Init the base time for the input capture */ 01532 TIM_Base_SetConfig(htim->Instance, &htim->Init); 01533 01534 /* Initialize the TIM state*/ 01535 htim->State= HAL_TIM_STATE_READY; 01536 01537 return HAL_OK; 01538 } 01539 01540 /** 01541 * @brief DeInitialize the TIM peripheral 01542 * @param htim: TIM Input Capture handle 01543 * @retval HAL status 01544 */ 01545 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) 01546 { 01547 /* Check the parameters */ 01548 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01549 01550 htim->State = HAL_TIM_STATE_BUSY; 01551 01552 /* Disable the TIM Peripheral Clock */ 01553 __HAL_TIM_DISABLE(htim); 01554 01555 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ 01556 HAL_TIM_IC_MspDeInit(htim); 01557 01558 /* Change TIM state */ 01559 htim->State = HAL_TIM_STATE_RESET; 01560 01561 /* Release Lock */ 01562 __HAL_UNLOCK(htim); 01563 01564 return HAL_OK; 01565 } 01566 01567 /** 01568 * @brief Initializes the TIM INput Capture MSP. 01569 * @param htim: TIM handle 01570 * @retval None 01571 */ 01572 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) 01573 { 01574 /* Prevent unused argument(s) compilation warning */ 01575 UNUSED(htim); 01576 01577 /* NOTE : This function should not be modified, when the callback is needed, 01578 the HAL_TIM_IC_MspInit could be implemented in the user file 01579 */ 01580 } 01581 01582 /** 01583 * @brief DeInitialize TIM Input Capture MSP. 01584 * @param htim: TIM handle 01585 * @retval None 01586 */ 01587 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) 01588 { 01589 /* Prevent unused argument(s) compilation warning */ 01590 UNUSED(htim); 01591 01592 /* NOTE : This function should not be modified, when the callback is needed, 01593 the HAL_TIM_IC_MspDeInit could be implemented in the user file 01594 */ 01595 } 01596 01597 /** 01598 * @brief Starts the TIM Input Capture measurement. 01599 * @param htim : TIM Input Capture handle 01600 * @param Channel : TIM Channels to be enabled 01601 * This parameter can be one of the following values: 01602 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01603 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01604 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01605 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01606 * @retval HAL status 01607 */ 01608 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) 01609 { 01610 /* Check the parameters */ 01611 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01612 01613 /* Enable the Input Capture channel */ 01614 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01615 01616 /* Enable the Peripheral */ 01617 __HAL_TIM_ENABLE(htim); 01618 01619 /* Return function status */ 01620 return HAL_OK; 01621 } 01622 01623 /** 01624 * @brief Stops the TIM Input Capture measurement. 01625 * @param htim : TIM handle 01626 * @param Channel : TIM Channels to be disabled 01627 * This parameter can be one of the following values: 01628 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01629 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01630 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01631 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01632 * @retval HAL status 01633 */ 01634 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 01635 { 01636 /* Check the parameters */ 01637 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01638 01639 /* Disable the Input Capture channel */ 01640 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01641 01642 /* Disable the Peripheral */ 01643 __HAL_TIM_DISABLE(htim); 01644 01645 /* Return function status */ 01646 return HAL_OK; 01647 } 01648 01649 /** 01650 * @brief Starts the TIM Input Capture measurement in interrupt mode. 01651 * @param htim : TIM Input Capture handle 01652 * @param Channel : TIM Channels to be enabled 01653 * This parameter can be one of the following values: 01654 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01655 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01656 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01657 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01658 * @retval HAL status 01659 */ 01660 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) 01661 { 01662 /* Check the parameters */ 01663 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01664 01665 switch (Channel) 01666 { 01667 case TIM_CHANNEL_1: 01668 { 01669 /* Enable the TIM Capture/Compare 1 interrupt */ 01670 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 01671 } 01672 break; 01673 01674 case TIM_CHANNEL_2: 01675 { 01676 /* Enable the TIM Capture/Compare 2 interrupt */ 01677 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 01678 } 01679 break; 01680 01681 case TIM_CHANNEL_3: 01682 { 01683 /* Enable the TIM Capture/Compare 3 interrupt */ 01684 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); 01685 } 01686 break; 01687 01688 case TIM_CHANNEL_4: 01689 { 01690 /* Enable the TIM Capture/Compare 4 interrupt */ 01691 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); 01692 } 01693 break; 01694 01695 default: 01696 break; 01697 } 01698 /* Enable the Input Capture channel */ 01699 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01700 01701 /* Enable the Peripheral */ 01702 __HAL_TIM_ENABLE(htim); 01703 01704 /* Return function status */ 01705 return HAL_OK; 01706 } 01707 01708 /** 01709 * @brief Stops the TIM Input Capture measurement in interrupt mode. 01710 * @param htim : TIM handle 01711 * @param Channel : TIM Channels to be disabled 01712 * This parameter can be one of the following values: 01713 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01714 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01715 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01716 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01717 * @retval HAL status 01718 */ 01719 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 01720 { 01721 /* Check the parameters */ 01722 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01723 01724 switch (Channel) 01725 { 01726 case TIM_CHANNEL_1: 01727 { 01728 /* Disable the TIM Capture/Compare 1 interrupt */ 01729 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 01730 } 01731 break; 01732 01733 case TIM_CHANNEL_2: 01734 { 01735 /* Disable the TIM Capture/Compare 2 interrupt */ 01736 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 01737 } 01738 break; 01739 01740 case TIM_CHANNEL_3: 01741 { 01742 /* Disable the TIM Capture/Compare 3 interrupt */ 01743 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); 01744 } 01745 break; 01746 01747 case TIM_CHANNEL_4: 01748 { 01749 /* Disable the TIM Capture/Compare 4 interrupt */ 01750 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); 01751 } 01752 break; 01753 01754 default: 01755 break; 01756 } 01757 01758 /* Disable the Input Capture channel */ 01759 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01760 01761 /* Disable the Peripheral */ 01762 __HAL_TIM_DISABLE(htim); 01763 01764 /* Return function status */ 01765 return HAL_OK; 01766 } 01767 01768 /** 01769 * @brief Starts the TIM Input Capture measurement on in DMA mode. 01770 * @param htim : TIM Input Capture handle 01771 * @param Channel : TIM Channels to be enabled 01772 * This parameter can be one of the following values: 01773 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01774 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01775 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01776 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01777 * @param pData: The destination Buffer address. 01778 * @param Length: The length of data to be transferred from TIM peripheral to memory. 01779 * @retval HAL status 01780 */ 01781 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) 01782 { 01783 /* Check the parameters */ 01784 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01785 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 01786 01787 if((htim->State == HAL_TIM_STATE_BUSY)) 01788 { 01789 return HAL_BUSY; 01790 } 01791 else if((htim->State == HAL_TIM_STATE_READY)) 01792 { 01793 if((pData == 0 ) && (Length > 0)) 01794 { 01795 return HAL_ERROR; 01796 } 01797 else 01798 { 01799 htim->State = HAL_TIM_STATE_BUSY; 01800 } 01801 } 01802 01803 switch (Channel) 01804 { 01805 case TIM_CHANNEL_1: 01806 { 01807 /* Set the DMA Period elapsed callback */ 01808 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 01809 01810 /* Set the DMA error callback */ 01811 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 01812 01813 /* Enable the DMA channel */ 01814 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); 01815 01816 /* Enable the TIM Capture/Compare 1 DMA request */ 01817 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 01818 } 01819 break; 01820 01821 case TIM_CHANNEL_2: 01822 { 01823 /* Set the DMA Period elapsed callback */ 01824 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 01825 01826 /* Set the DMA error callback */ 01827 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 01828 01829 /* Enable the DMA channel */ 01830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); 01831 01832 /* Enable the TIM Capture/Compare 2 DMA request */ 01833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 01834 } 01835 break; 01836 01837 case TIM_CHANNEL_3: 01838 { 01839 /* Set the DMA Period elapsed callback */ 01840 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; 01841 01842 /* Set the DMA error callback */ 01843 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 01844 01845 /* Enable the DMA channel */ 01846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); 01847 01848 /* Enable the TIM Capture/Compare 3 DMA request */ 01849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); 01850 } 01851 break; 01852 01853 case TIM_CHANNEL_4: 01854 { 01855 /* Set the DMA Period elapsed callback */ 01856 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; 01857 01858 /* Set the DMA error callback */ 01859 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 01860 01861 /* Enable the DMA channel */ 01862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); 01863 01864 /* Enable the TIM Capture/Compare 4 DMA request */ 01865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); 01866 } 01867 break; 01868 01869 default: 01870 break; 01871 } 01872 01873 /* Enable the Input Capture channel */ 01874 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 01875 01876 /* Enable the Peripheral */ 01877 __HAL_TIM_ENABLE(htim); 01878 01879 /* Return function status */ 01880 return HAL_OK; 01881 } 01882 01883 /** 01884 * @brief Stops the TIM Input Capture measurement on in DMA mode. 01885 * @param htim : TIM Input Capture handle 01886 * @param Channel : TIM Channels to be disabled 01887 * This parameter can be one of the following values: 01888 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 01889 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 01890 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 01891 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 01892 * @retval HAL status 01893 */ 01894 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 01895 { 01896 /* Check the parameters */ 01897 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); 01898 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 01899 01900 switch (Channel) 01901 { 01902 case TIM_CHANNEL_1: 01903 { 01904 /* Disable the TIM Capture/Compare 1 DMA request */ 01905 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 01906 } 01907 break; 01908 01909 case TIM_CHANNEL_2: 01910 { 01911 /* Disable the TIM Capture/Compare 2 DMA request */ 01912 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 01913 } 01914 break; 01915 01916 case TIM_CHANNEL_3: 01917 { 01918 /* Disable the TIM Capture/Compare 3 DMA request */ 01919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); 01920 } 01921 break; 01922 01923 case TIM_CHANNEL_4: 01924 { 01925 /* Disable the TIM Capture/Compare 4 DMA request */ 01926 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); 01927 } 01928 break; 01929 01930 default: 01931 break; 01932 } 01933 01934 /* Disable the Input Capture channel */ 01935 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); 01936 01937 /* Disable the Peripheral */ 01938 __HAL_TIM_DISABLE(htim); 01939 01940 /* Change the htim state */ 01941 htim->State = HAL_TIM_STATE_READY; 01942 01943 /* Return function status */ 01944 return HAL_OK; 01945 } 01946 /** 01947 * @} 01948 */ 01949 01950 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions 01951 * @brief Time One Pulse functions 01952 * 01953 @verbatim 01954 ============================================================================== 01955 ##### Time One Pulse functions ##### 01956 ============================================================================== 01957 [..] 01958 This section provides functions allowing to: 01959 (+) Initialize and configure the TIM One Pulse. 01960 (+) De-initialize the TIM One Pulse. 01961 (+) Start the Time One Pulse. 01962 (+) Stop the Time One Pulse. 01963 (+) Start the Time One Pulse and enable interrupt. 01964 (+) Stop the Time One Pulse and disable interrupt. 01965 (+) Start the Time One Pulse and enable DMA transfer. 01966 (+) Stop the Time One Pulse and disable DMA transfer. 01967 01968 @endverbatim 01969 * @{ 01970 */ 01971 /** 01972 * @brief Initializes the TIM One Pulse Time Base according to the specified 01973 * parameters in the TIM_HandleTypeDef and initialize the associated handle. 01974 * @param htim: TIM OnePulse handle 01975 * @param OnePulseMode: Select the One pulse mode. 01976 * This parameter can be one of the following values: 01977 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. 01978 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. 01979 * @retval HAL status 01980 */ 01981 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) 01982 { 01983 /* Check the TIM handle allocation */ 01984 if(htim == NULL) 01985 { 01986 return HAL_ERROR; 01987 } 01988 01989 /* Check the parameters */ 01990 assert_param(IS_TIM_INSTANCE(htim->Instance)); 01991 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); 01992 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); 01993 assert_param(IS_TIM_OPM_MODE(OnePulseMode)); 01994 01995 if(htim->State == HAL_TIM_STATE_RESET) 01996 { 01997 /* Allocate lock resource and initialize it */ 01998 htim->Lock = HAL_UNLOCKED; 01999 02000 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 02001 HAL_TIM_OnePulse_MspInit(htim); 02002 } 02003 02004 /* Set the TIM state */ 02005 htim->State= HAL_TIM_STATE_BUSY; 02006 02007 /* Configure the Time base in the One Pulse Mode */ 02008 TIM_Base_SetConfig(htim->Instance, &htim->Init); 02009 02010 /* Reset the OPM Bit */ 02011 htim->Instance->CR1 &= ~TIM_CR1_OPM; 02012 02013 /* Configure the OPM Mode */ 02014 htim->Instance->CR1 |= OnePulseMode; 02015 02016 /* Initialize the TIM state*/ 02017 htim->State= HAL_TIM_STATE_READY; 02018 02019 return HAL_OK; 02020 } 02021 02022 /** 02023 * @brief DeInitialize the TIM One Pulse 02024 * @param htim: TIM One Pulse handle 02025 * @retval HAL status 02026 */ 02027 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) 02028 { 02029 /* Check the parameters */ 02030 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02031 02032 htim->State = HAL_TIM_STATE_BUSY; 02033 02034 /* Disable the TIM Peripheral Clock */ 02035 __HAL_TIM_DISABLE(htim); 02036 02037 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 02038 HAL_TIM_OnePulse_MspDeInit(htim); 02039 02040 /* Change TIM state */ 02041 htim->State = HAL_TIM_STATE_RESET; 02042 02043 /* Release Lock */ 02044 __HAL_UNLOCK(htim); 02045 02046 return HAL_OK; 02047 } 02048 02049 /** 02050 * @brief Initializes the TIM One Pulse MSP. 02051 * @param htim: TIM handle 02052 * @retval None 02053 */ 02054 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) 02055 { 02056 /* Prevent unused argument(s) compilation warning */ 02057 UNUSED(htim); 02058 02059 /* NOTE : This function should not be modified, when the callback is needed, 02060 the HAL_TIM_OnePulse_MspInit could be implemented in the user file 02061 */ 02062 } 02063 02064 /** 02065 * @brief DeInitialize TIM One Pulse MSP. 02066 * @param htim: TIM handle 02067 * @retval None 02068 */ 02069 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) 02070 { 02071 /* Prevent unused argument(s) compilation warning */ 02072 UNUSED(htim); 02073 02074 /* NOTE : This function should not be modified, when the callback is needed, 02075 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file 02076 */ 02077 } 02078 02079 /** 02080 * @brief Starts the TIM One Pulse signal generation. 02081 * @param htim : TIM One Pulse handle 02082 * @param OutputChannel : TIM Channels to be enabled 02083 * This parameter can be one of the following values: 02084 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02085 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02086 * @retval HAL status 02087 */ 02088 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02089 { 02090 /* Prevent unused argument(s) compilation warning */ 02091 UNUSED(OutputChannel); 02092 02093 /* Enable the Capture compare and the Input Capture channels 02094 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02095 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02096 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02097 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 02098 02099 No need to enable the counter, it's enabled automatically by hardware 02100 (the counter starts in response to a stimulus and generate a pulse */ 02101 02102 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02103 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02104 02105 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02106 { 02107 /* Enable the main output */ 02108 __HAL_TIM_MOE_ENABLE(htim); 02109 } 02110 02111 /* Return function status */ 02112 return HAL_OK; 02113 } 02114 02115 /** 02116 * @brief Stops the TIM One Pulse signal generation. 02117 * @param htim : TIM One Pulse handle 02118 * @param OutputChannel : TIM Channels to be disable 02119 * This parameter can be one of the following values: 02120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02122 * @retval HAL status 02123 */ 02124 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02125 { 02126 /* Prevent unused argument(s) compilation warning */ 02127 UNUSED(OutputChannel); 02128 02129 /* Disable the Capture compare and the Input Capture channels 02130 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02131 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02132 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02133 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ 02134 02135 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02136 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02137 02138 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02139 { 02140 /* Disable the Main Ouput */ 02141 __HAL_TIM_MOE_DISABLE(htim); 02142 } 02143 02144 /* Disable the Peripheral */ 02145 __HAL_TIM_DISABLE(htim); 02146 02147 /* Return function status */ 02148 return HAL_OK; 02149 } 02150 02151 /** 02152 * @brief Starts the TIM One Pulse signal generation in interrupt mode. 02153 * @param htim : TIM One Pulse handle 02154 * @param OutputChannel : TIM Channels to be enabled 02155 * This parameter can be one of the following values: 02156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02158 * @retval HAL status 02159 */ 02160 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02161 { 02162 /* Prevent unused argument(s) compilation warning */ 02163 UNUSED(OutputChannel); 02164 02165 /* Enable the Capture compare and the Input Capture channels 02166 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02167 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02168 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02169 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together 02170 02171 No need to enable the counter, it's enabled automatically by hardware 02172 (the counter starts in response to a stimulus and generate a pulse */ 02173 02174 /* Enable the TIM Capture/Compare 1 interrupt */ 02175 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02176 02177 /* Enable the TIM Capture/Compare 2 interrupt */ 02178 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02179 02180 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02181 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02182 02183 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02184 { 02185 /* Enable the main output */ 02186 __HAL_TIM_MOE_ENABLE(htim); 02187 } 02188 02189 /* Return function status */ 02190 return HAL_OK; 02191 } 02192 02193 /** 02194 * @brief Stops the TIM One Pulse signal generation in interrupt mode. 02195 * @param htim : TIM One Pulse handle 02196 * @param OutputChannel : TIM Channels to be enabled 02197 * This parameter can be one of the following values: 02198 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02199 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02200 * @retval HAL status 02201 */ 02202 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) 02203 { 02204 /* Prevent unused argument(s) compilation warning */ 02205 UNUSED(OutputChannel); 02206 02207 /* Disable the TIM Capture/Compare 1 interrupt */ 02208 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02209 02210 /* Disable the TIM Capture/Compare 2 interrupt */ 02211 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02212 02213 /* Disable the Capture compare and the Input Capture channels 02214 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) 02215 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and 02216 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output 02217 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ 02218 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02219 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02220 02221 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 02222 { 02223 /* Disable the Main Ouput */ 02224 __HAL_TIM_MOE_DISABLE(htim); 02225 } 02226 02227 /* Disable the Peripheral */ 02228 __HAL_TIM_DISABLE(htim); 02229 02230 /* Return function status */ 02231 return HAL_OK; 02232 } 02233 02234 /** 02235 * @} 02236 */ 02237 02238 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions 02239 * @brief Time Encoder functions 02240 * 02241 @verbatim 02242 ============================================================================== 02243 ##### Time Encoder functions ##### 02244 ============================================================================== 02245 [..] 02246 This section provides functions allowing to: 02247 (+) Initialize and configure the TIM Encoder. 02248 (+) De-initialize the TIM Encoder. 02249 (+) Start the Time Encoder. 02250 (+) Stop the Time Encoder. 02251 (+) Start the Time Encoder and enable interrupt. 02252 (+) Stop the Time Encoder and disable interrupt. 02253 (+) Start the Time Encoder and enable DMA transfer. 02254 (+) Stop the Time Encoder and disable DMA transfer. 02255 02256 @endverbatim 02257 * @{ 02258 */ 02259 /** 02260 * @brief Initializes the TIM Encoder Interface and initialize the associated handle. 02261 * @param htim: TIM Encoder Interface handle 02262 * @param sConfig: TIM Encoder Interface configuration structure 02263 * @retval HAL status 02264 */ 02265 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) 02266 { 02267 uint32_t tmpsmcr = 0; 02268 uint32_t tmpccmr1 = 0; 02269 uint32_t tmpccer = 0; 02270 02271 /* Check the TIM handle allocation */ 02272 if(htim == NULL) 02273 { 02274 return HAL_ERROR; 02275 } 02276 02277 /* Check the parameters */ 02278 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02279 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); 02280 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); 02281 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); 02282 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); 02283 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); 02284 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); 02285 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); 02286 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); 02287 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); 02288 02289 if(htim->State == HAL_TIM_STATE_RESET) 02290 { 02291 /* Allocate lock resource and initialize it */ 02292 htim->Lock = HAL_UNLOCKED; 02293 02294 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ 02295 HAL_TIM_Encoder_MspInit(htim); 02296 } 02297 02298 /* Set the TIM state */ 02299 htim->State= HAL_TIM_STATE_BUSY; 02300 02301 /* Reset the SMS bits */ 02302 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 02303 02304 /* Configure the Time base in the Encoder Mode */ 02305 TIM_Base_SetConfig(htim->Instance, &htim->Init); 02306 02307 /* Get the TIMx SMCR register value */ 02308 tmpsmcr = htim->Instance->SMCR; 02309 02310 /* Get the TIMx CCMR1 register value */ 02311 tmpccmr1 = htim->Instance->CCMR1; 02312 02313 /* Get the TIMx CCER register value */ 02314 tmpccer = htim->Instance->CCER; 02315 02316 /* Set the encoder Mode */ 02317 tmpsmcr |= sConfig->EncoderMode; 02318 02319 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 02320 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 02321 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); 02322 02323 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ 02324 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 02325 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 02326 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); 02327 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); 02328 02329 /* Set the TI1 and the TI2 Polarities */ 02330 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 02331 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 02332 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); 02333 02334 /* Write to TIMx SMCR */ 02335 htim->Instance->SMCR = tmpsmcr; 02336 02337 /* Write to TIMx CCMR1 */ 02338 htim->Instance->CCMR1 = tmpccmr1; 02339 02340 /* Write to TIMx CCER */ 02341 htim->Instance->CCER = tmpccer; 02342 02343 /* Initialize the TIM state*/ 02344 htim->State= HAL_TIM_STATE_READY; 02345 02346 return HAL_OK; 02347 } 02348 02349 02350 /** 02351 * @brief DeInitialize the TIM Encoder interface 02352 * @param htim: TIM Encoder handle 02353 * @retval HAL status 02354 */ 02355 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) 02356 { 02357 /* Check the parameters */ 02358 assert_param(IS_TIM_INSTANCE(htim->Instance)); 02359 02360 htim->State = HAL_TIM_STATE_BUSY; 02361 02362 /* Disable the TIM Peripheral Clock */ 02363 __HAL_TIM_DISABLE(htim); 02364 02365 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 02366 HAL_TIM_Encoder_MspDeInit(htim); 02367 02368 /* Change TIM state */ 02369 htim->State = HAL_TIM_STATE_RESET; 02370 02371 /* Release Lock */ 02372 __HAL_UNLOCK(htim); 02373 02374 return HAL_OK; 02375 } 02376 02377 /** 02378 * @brief Initializes the TIM Encoder Interface MSP. 02379 * @param htim: TIM handle 02380 * @retval None 02381 */ 02382 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) 02383 { 02384 /* Prevent unused argument(s) compilation warning */ 02385 UNUSED(htim); 02386 02387 /* NOTE : This function should not be modified, when the callback is needed, 02388 the HAL_TIM_Encoder_MspInit could be implemented in the user file 02389 */ 02390 } 02391 02392 /** 02393 * @brief DeInitialize TIM Encoder Interface MSP. 02394 * @param htim: TIM handle 02395 * @retval None 02396 */ 02397 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) 02398 { 02399 /* Prevent unused argument(s) compilation warning */ 02400 UNUSED(htim); 02401 02402 /* NOTE : This function should not be modified, when the callback is needed, 02403 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file 02404 */ 02405 } 02406 02407 /** 02408 * @brief Starts the TIM Encoder Interface. 02409 * @param htim : TIM Encoder Interface handle 02410 * @param Channel : TIM Channels to be enabled 02411 * This parameter can be one of the following values: 02412 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02413 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02414 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02415 * @retval HAL status 02416 */ 02417 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) 02418 { 02419 /* Check the parameters */ 02420 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02421 02422 /* Enable the encoder interface channels */ 02423 switch (Channel) 02424 { 02425 case TIM_CHANNEL_1: 02426 { 02427 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02428 } 02429 break; 02430 02431 case TIM_CHANNEL_2: 02432 { 02433 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02434 } 02435 break; 02436 02437 default : 02438 { 02439 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02440 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02441 } 02442 break; 02443 } 02444 /* Enable the Peripheral */ 02445 __HAL_TIM_ENABLE(htim); 02446 02447 /* Return function status */ 02448 return HAL_OK; 02449 } 02450 02451 /** 02452 * @brief Stops the TIM Encoder Interface. 02453 * @param htim : TIM Encoder Interface handle 02454 * @param Channel : TIM Channels to be disabled 02455 * This parameter can be one of the following values: 02456 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02457 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02458 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02459 * @retval HAL status 02460 */ 02461 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) 02462 { 02463 /* Check the parameters */ 02464 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02465 02466 /* Disable the Input Capture channels 1 and 2 02467 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02468 switch (Channel) 02469 { 02470 case TIM_CHANNEL_1: 02471 { 02472 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02473 } 02474 break; 02475 02476 case TIM_CHANNEL_2: 02477 { 02478 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02479 } 02480 break; 02481 02482 default : 02483 { 02484 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02485 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02486 } 02487 break; 02488 } 02489 02490 /* Disable the Peripheral */ 02491 __HAL_TIM_DISABLE(htim); 02492 02493 /* Return function status */ 02494 return HAL_OK; 02495 } 02496 02497 /** 02498 * @brief Starts the TIM Encoder Interface in interrupt mode. 02499 * @param htim : TIM Encoder Interface handle 02500 * @param Channel : TIM Channels to be enabled 02501 * This parameter can be one of the following values: 02502 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02503 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02504 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02505 * @retval HAL status 02506 */ 02507 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 02508 { 02509 /* Check the parameters */ 02510 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02511 02512 /* Enable the encoder interface channels */ 02513 /* Enable the capture compare Interrupts 1 and/or 2 */ 02514 switch (Channel) 02515 { 02516 case TIM_CHANNEL_1: 02517 { 02518 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02519 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02520 } 02521 break; 02522 02523 case TIM_CHANNEL_2: 02524 { 02525 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02526 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02527 } 02528 break; 02529 02530 default : 02531 { 02532 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02533 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02534 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); 02535 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); 02536 } 02537 break; 02538 } 02539 02540 /* Enable the Peripheral */ 02541 __HAL_TIM_ENABLE(htim); 02542 02543 /* Return function status */ 02544 return HAL_OK; 02545 } 02546 02547 /** 02548 * @brief Stops the TIM Encoder Interface in interrupt mode. 02549 * @param htim : TIM Encoder Interface handle 02550 * @param Channel : TIM Channels to be disabled 02551 * This parameter can be one of the following values: 02552 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02553 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02554 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02555 * @retval HAL status 02556 */ 02557 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) 02558 { 02559 /* Check the parameters */ 02560 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02561 02562 /* Disable the Input Capture channels 1 and 2 02563 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02564 if(Channel == TIM_CHANNEL_1) 02565 { 02566 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02567 02568 /* Disable the capture compare Interrupts 1 */ 02569 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02570 } 02571 else if(Channel == TIM_CHANNEL_2) 02572 { 02573 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02574 02575 /* Disable the capture compare Interrupts 2 */ 02576 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02577 } 02578 else 02579 { 02580 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02581 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02582 02583 /* Disable the capture compare Interrupts 1 and 2 */ 02584 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); 02585 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); 02586 } 02587 02588 /* Disable the Peripheral */ 02589 __HAL_TIM_DISABLE(htim); 02590 02591 /* Change the htim state */ 02592 htim->State = HAL_TIM_STATE_READY; 02593 02594 /* Return function status */ 02595 return HAL_OK; 02596 } 02597 02598 /** 02599 * @brief Starts the TIM Encoder Interface in DMA mode. 02600 * @param htim : TIM Encoder Interface handle 02601 * @param Channel : TIM Channels to be enabled 02602 * This parameter can be one of the following values: 02603 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02604 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02605 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02606 * @param pData1: The destination Buffer address for IC1. 02607 * @param pData2: The destination Buffer address for IC2. 02608 * @param Length: The length of data to be transferred from TIM peripheral to memory. 02609 * @retval HAL status 02610 */ 02611 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) 02612 { 02613 /* Check the parameters */ 02614 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02615 02616 if((htim->State == HAL_TIM_STATE_BUSY)) 02617 { 02618 return HAL_BUSY; 02619 } 02620 else if((htim->State == HAL_TIM_STATE_READY)) 02621 { 02622 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) 02623 { 02624 return HAL_ERROR; 02625 } 02626 else 02627 { 02628 htim->State = HAL_TIM_STATE_BUSY; 02629 } 02630 } 02631 02632 switch (Channel) 02633 { 02634 case TIM_CHANNEL_1: 02635 { 02636 /* Set the DMA Period elapsed callback */ 02637 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02638 02639 /* Set the DMA error callback */ 02640 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02641 02642 /* Enable the DMA channel */ 02643 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); 02644 02645 /* Enable the TIM Input Capture DMA request */ 02646 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 02647 02648 /* Enable the Peripheral */ 02649 __HAL_TIM_ENABLE(htim); 02650 02651 /* Enable the Capture compare channel */ 02652 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02653 } 02654 break; 02655 02656 case TIM_CHANNEL_2: 02657 { 02658 /* Set the DMA Period elapsed callback */ 02659 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02660 02661 /* Set the DMA error callback */ 02662 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; 02663 /* Enable the DMA channel */ 02664 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); 02665 02666 /* Enable the TIM Input Capture DMA request */ 02667 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 02668 02669 /* Enable the Peripheral */ 02670 __HAL_TIM_ENABLE(htim); 02671 02672 /* Enable the Capture compare channel */ 02673 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02674 } 02675 break; 02676 02677 case TIM_CHANNEL_ALL: 02678 { 02679 /* Set the DMA Period elapsed callback */ 02680 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 02681 02682 /* Set the DMA error callback */ 02683 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 02684 02685 /* Enable the DMA channel */ 02686 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); 02687 02688 /* Set the DMA Period elapsed callback */ 02689 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 02690 02691 /* Set the DMA error callback */ 02692 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 02693 02694 /* Enable the DMA channel */ 02695 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); 02696 02697 /* Enable the Peripheral */ 02698 __HAL_TIM_ENABLE(htim); 02699 02700 /* Enable the Capture compare channel */ 02701 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 02702 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 02703 02704 /* Enable the TIM Input Capture DMA request */ 02705 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); 02706 /* Enable the TIM Input Capture DMA request */ 02707 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); 02708 } 02709 break; 02710 02711 default: 02712 break; 02713 } 02714 /* Return function status */ 02715 return HAL_OK; 02716 } 02717 02718 /** 02719 * @brief Stops the TIM Encoder Interface in DMA mode. 02720 * @param htim : TIM Encoder Interface handle 02721 * @param Channel : TIM Channels to be enabled 02722 * This parameter can be one of the following values: 02723 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02724 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02725 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected 02726 * @retval HAL status 02727 */ 02728 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) 02729 { 02730 /* Check the parameters */ 02731 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); 02732 02733 /* Disable the Input Capture channels 1 and 2 02734 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ 02735 if(Channel == TIM_CHANNEL_1) 02736 { 02737 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02738 02739 /* Disable the capture compare DMA Request 1 */ 02740 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 02741 } 02742 else if(Channel == TIM_CHANNEL_2) 02743 { 02744 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02745 02746 /* Disable the capture compare DMA Request 2 */ 02747 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 02748 } 02749 else 02750 { 02751 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); 02752 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); 02753 02754 /* Disable the capture compare DMA Request 1 and 2 */ 02755 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); 02756 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); 02757 } 02758 02759 /* Disable the Peripheral */ 02760 __HAL_TIM_DISABLE(htim); 02761 02762 /* Change the htim state */ 02763 htim->State = HAL_TIM_STATE_READY; 02764 02765 /* Return function status */ 02766 return HAL_OK; 02767 } 02768 02769 /** 02770 * @} 02771 */ 02772 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management 02773 * @brief IRQ handler management 02774 * 02775 @verbatim 02776 ============================================================================== 02777 ##### IRQ handler management ##### 02778 ============================================================================== 02779 [..] 02780 This section provides Timer IRQ handler function. 02781 02782 @endverbatim 02783 * @{ 02784 */ 02785 /** 02786 * @brief This function handles TIM interrupts requests. 02787 * @param htim: TIM handle 02788 * @retval None 02789 */ 02790 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) 02791 { 02792 /* Capture compare 1 event */ 02793 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) 02794 { 02795 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) 02796 { 02797 { 02798 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); 02799 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 02800 02801 /* Input capture event */ 02802 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) 02803 { 02804 HAL_TIM_IC_CaptureCallback(htim); 02805 } 02806 /* Output compare event */ 02807 else 02808 { 02809 HAL_TIM_OC_DelayElapsedCallback(htim); 02810 HAL_TIM_PWM_PulseFinishedCallback(htim); 02811 } 02812 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02813 } 02814 } 02815 } 02816 /* Capture compare 2 event */ 02817 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) 02818 { 02819 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) 02820 { 02821 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); 02822 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 02823 /* Input capture event */ 02824 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) 02825 { 02826 HAL_TIM_IC_CaptureCallback(htim); 02827 } 02828 /* Output compare event */ 02829 else 02830 { 02831 HAL_TIM_OC_DelayElapsedCallback(htim); 02832 HAL_TIM_PWM_PulseFinishedCallback(htim); 02833 } 02834 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02835 } 02836 } 02837 /* Capture compare 3 event */ 02838 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) 02839 { 02840 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) 02841 { 02842 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); 02843 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 02844 /* Input capture event */ 02845 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) 02846 { 02847 HAL_TIM_IC_CaptureCallback(htim); 02848 } 02849 /* Output compare event */ 02850 else 02851 { 02852 HAL_TIM_OC_DelayElapsedCallback(htim); 02853 HAL_TIM_PWM_PulseFinishedCallback(htim); 02854 } 02855 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02856 } 02857 } 02858 /* Capture compare 4 event */ 02859 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) 02860 { 02861 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) 02862 { 02863 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); 02864 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 02865 /* Input capture event */ 02866 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) 02867 { 02868 HAL_TIM_IC_CaptureCallback(htim); 02869 } 02870 /* Output compare event */ 02871 else 02872 { 02873 HAL_TIM_OC_DelayElapsedCallback(htim); 02874 HAL_TIM_PWM_PulseFinishedCallback(htim); 02875 } 02876 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 02877 } 02878 } 02879 /* TIM Update event */ 02880 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) 02881 { 02882 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) 02883 { 02884 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); 02885 HAL_TIM_PeriodElapsedCallback(htim); 02886 } 02887 } 02888 /* TIM Break input event */ 02889 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) 02890 { 02891 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET) 02892 { 02893 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); 02894 HAL_TIMEx_BreakCallback(htim); 02895 } 02896 } 02897 /* TIM Trigger detection event */ 02898 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) 02899 { 02900 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) 02901 { 02902 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); 02903 HAL_TIM_TriggerCallback(htim); 02904 } 02905 } 02906 /* TIM commutation event */ 02907 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) 02908 { 02909 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET) 02910 { 02911 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); 02912 HAL_TIMEx_CommutationCallback(htim); 02913 } 02914 } 02915 } 02916 02917 /** 02918 * @} 02919 */ 02920 02921 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions 02922 * @brief Peripheral Control functions 02923 * 02924 @verbatim 02925 ============================================================================== 02926 ##### Peripheral Control functions ##### 02927 ============================================================================== 02928 [..] 02929 This section provides functions allowing to: 02930 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. 02931 (+) Configure External Clock source. 02932 (+) Configure Complementary channels, break features and dead time. 02933 (+) Configure Master and the Slave synchronization. 02934 (+) Configure the DMA Burst Mode. 02935 02936 @endverbatim 02937 * @{ 02938 */ 02939 02940 /** 02941 * @brief Initializes the TIM Output Compare Channels according to the specified 02942 * parameters in the TIM_OC_InitTypeDef. 02943 * @param htim: TIM Output Compare handle 02944 * @param sConfig: TIM Output Compare configuration structure 02945 * @param Channel : TIM Channels to configure 02946 * This parameter can be one of the following values: 02947 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 02948 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 02949 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 02950 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 02951 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 02952 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 02953 * @retval HAL status 02954 */ 02955 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, 02956 TIM_OC_InitTypeDef* sConfig, 02957 uint32_t Channel) 02958 { 02959 /* Check the parameters */ 02960 assert_param(IS_TIM_CHANNELS(Channel)); 02961 assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); 02962 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); 02963 02964 /* Process Locked */ 02965 __HAL_LOCK(htim); 02966 02967 htim->State = HAL_TIM_STATE_BUSY; 02968 02969 switch (Channel) 02970 { 02971 case TIM_CHANNEL_1: 02972 { 02973 /* Check the parameters */ 02974 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 02975 02976 /* Configure the TIM Channel 1 in Output Compare */ 02977 TIM_OC1_SetConfig(htim->Instance, sConfig); 02978 } 02979 break; 02980 02981 case TIM_CHANNEL_2: 02982 { 02983 /* Check the parameters */ 02984 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 02985 02986 /* Configure the TIM Channel 2 in Output Compare */ 02987 TIM_OC2_SetConfig(htim->Instance, sConfig); 02988 } 02989 break; 02990 02991 case TIM_CHANNEL_3: 02992 { 02993 /* Check the parameters */ 02994 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 02995 02996 /* Configure the TIM Channel 3 in Output Compare */ 02997 TIM_OC3_SetConfig(htim->Instance, sConfig); 02998 } 02999 break; 03000 03001 case TIM_CHANNEL_4: 03002 { 03003 /* Check the parameters */ 03004 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03005 03006 /* Configure the TIM Channel 4 in Output Compare */ 03007 TIM_OC4_SetConfig(htim->Instance, sConfig); 03008 } 03009 break; 03010 03011 case TIM_CHANNEL_5: 03012 { 03013 /* Check the parameters */ 03014 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); 03015 03016 /* Configure the TIM Channel 5 in Output Compare */ 03017 TIM_OC5_SetConfig(htim->Instance, sConfig); 03018 } 03019 break; 03020 03021 case TIM_CHANNEL_6: 03022 { 03023 /* Check the parameters */ 03024 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); 03025 03026 /* Configure the TIM Channel 6 in Output Compare */ 03027 TIM_OC6_SetConfig(htim->Instance, sConfig); 03028 } 03029 break; 03030 03031 default: 03032 break; 03033 } 03034 03035 htim->State = HAL_TIM_STATE_READY; 03036 03037 __HAL_UNLOCK(htim); 03038 03039 return HAL_OK; 03040 } 03041 03042 /** 03043 * @brief Initializes the TIM Input Capture Channels according to the specified 03044 * parameters in the TIM_IC_InitTypeDef. 03045 * @param htim: TIM IC handle 03046 * @param sConfig: TIM Input Capture configuration structure 03047 * @param Channel : TIM Channels to be enabled 03048 * This parameter can be one of the following values: 03049 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03050 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03051 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03052 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03053 * @retval HAL status 03054 */ 03055 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) 03056 { 03057 /* Check the parameters */ 03058 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03059 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); 03060 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); 03061 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); 03062 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); 03063 03064 /* Process Locked */ 03065 __HAL_LOCK(htim); 03066 03067 htim->State = HAL_TIM_STATE_BUSY; 03068 03069 if (Channel == TIM_CHANNEL_1) 03070 { 03071 /* TI1 Configuration */ 03072 TIM_TI1_SetConfig(htim->Instance, 03073 sConfig->ICPolarity, 03074 sConfig->ICSelection, 03075 sConfig->ICFilter); 03076 03077 /* Reset the IC1PSC Bits */ 03078 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 03079 03080 /* Set the IC1PSC value */ 03081 htim->Instance->CCMR1 |= sConfig->ICPrescaler; 03082 } 03083 else if (Channel == TIM_CHANNEL_2) 03084 { 03085 /* TI2 Configuration */ 03086 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03087 03088 TIM_TI2_SetConfig(htim->Instance, 03089 sConfig->ICPolarity, 03090 sConfig->ICSelection, 03091 sConfig->ICFilter); 03092 03093 /* Reset the IC2PSC Bits */ 03094 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 03095 03096 /* Set the IC2PSC value */ 03097 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); 03098 } 03099 else if (Channel == TIM_CHANNEL_3) 03100 { 03101 /* TI3 Configuration */ 03102 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03103 03104 TIM_TI3_SetConfig(htim->Instance, 03105 sConfig->ICPolarity, 03106 sConfig->ICSelection, 03107 sConfig->ICFilter); 03108 03109 /* Reset the IC3PSC Bits */ 03110 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; 03111 03112 /* Set the IC3PSC value */ 03113 htim->Instance->CCMR2 |= sConfig->ICPrescaler; 03114 } 03115 else 03116 { 03117 /* TI4 Configuration */ 03118 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03119 03120 TIM_TI4_SetConfig(htim->Instance, 03121 sConfig->ICPolarity, 03122 sConfig->ICSelection, 03123 sConfig->ICFilter); 03124 03125 /* Reset the IC4PSC Bits */ 03126 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; 03127 03128 /* Set the IC4PSC value */ 03129 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); 03130 } 03131 03132 htim->State = HAL_TIM_STATE_READY; 03133 03134 __HAL_UNLOCK(htim); 03135 03136 return HAL_OK; 03137 } 03138 03139 /** 03140 * @brief Initializes the TIM PWM channels according to the specified 03141 * parameters in the TIM_OC_InitTypeDef. 03142 * @param htim: TIM PWM handle 03143 * @param sConfig: TIM PWM configuration structure 03144 * @param Channel : TIM Channels to be configured 03145 * This parameter can be one of the following values: 03146 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03147 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03148 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 03149 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 03150 * @arg TIM_CHANNEL_5: TIM Channel 5 selected 03151 * @arg TIM_CHANNEL_6: TIM Channel 6 selected 03152 * @retval HAL status 03153 */ 03154 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, 03155 TIM_OC_InitTypeDef* sConfig, 03156 uint32_t Channel) 03157 { 03158 /* Check the parameters */ 03159 assert_param(IS_TIM_CHANNELS(Channel)); 03160 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); 03161 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); 03162 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); 03163 03164 /* Process Locked */ 03165 __HAL_LOCK(htim); 03166 03167 htim->State = HAL_TIM_STATE_BUSY; 03168 03169 switch (Channel) 03170 { 03171 case TIM_CHANNEL_1: 03172 { 03173 /* Check the parameters */ 03174 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03175 03176 /* Configure the Channel 1 in PWM mode */ 03177 TIM_OC1_SetConfig(htim->Instance, sConfig); 03178 03179 /* Set the Preload enable bit for channel1 */ 03180 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 03181 03182 /* Configure the Output Fast mode */ 03183 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 03184 htim->Instance->CCMR1 |= sConfig->OCFastMode; 03185 } 03186 break; 03187 03188 case TIM_CHANNEL_2: 03189 { 03190 /* Check the parameters */ 03191 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03192 03193 /* Configure the Channel 2 in PWM mode */ 03194 TIM_OC2_SetConfig(htim->Instance, sConfig); 03195 03196 /* Set the Preload enable bit for channel2 */ 03197 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 03198 03199 /* Configure the Output Fast mode */ 03200 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 03201 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; 03202 } 03203 break; 03204 03205 case TIM_CHANNEL_3: 03206 { 03207 /* Check the parameters */ 03208 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 03209 03210 /* Configure the Channel 3 in PWM mode */ 03211 TIM_OC3_SetConfig(htim->Instance, sConfig); 03212 03213 /* Set the Preload enable bit for channel3 */ 03214 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 03215 03216 /* Configure the Output Fast mode */ 03217 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 03218 htim->Instance->CCMR2 |= sConfig->OCFastMode; 03219 } 03220 break; 03221 03222 case TIM_CHANNEL_4: 03223 { 03224 /* Check the parameters */ 03225 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 03226 03227 /* Configure the Channel 4 in PWM mode */ 03228 TIM_OC4_SetConfig(htim->Instance, sConfig); 03229 03230 /* Set the Preload enable bit for channel4 */ 03231 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 03232 03233 /* Configure the Output Fast mode */ 03234 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 03235 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; 03236 } 03237 break; 03238 03239 case TIM_CHANNEL_5: 03240 { 03241 /* Check the parameters */ 03242 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); 03243 03244 /* Configure the Channel 5 in PWM mode */ 03245 TIM_OC5_SetConfig(htim->Instance, sConfig); 03246 03247 /* Set the Preload enable bit for channel5*/ 03248 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 03249 03250 /* Configure the Output Fast mode */ 03251 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 03252 htim->Instance->CCMR3 |= sConfig->OCFastMode; 03253 } 03254 break; 03255 03256 case TIM_CHANNEL_6: 03257 { 03258 /* Check the parameters */ 03259 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); 03260 03261 /* Configure the Channel 5 in PWM mode */ 03262 TIM_OC6_SetConfig(htim->Instance, sConfig); 03263 03264 /* Set the Preload enable bit for channel6 */ 03265 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 03266 03267 /* Configure the Output Fast mode */ 03268 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 03269 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8; 03270 } 03271 break; 03272 03273 default: 03274 break; 03275 } 03276 03277 htim->State = HAL_TIM_STATE_READY; 03278 03279 __HAL_UNLOCK(htim); 03280 03281 return HAL_OK; 03282 } 03283 03284 /** 03285 * @brief Initializes the TIM One Pulse Channels according to the specified 03286 * parameters in the TIM_OnePulse_InitTypeDef. 03287 * @param htim: TIM One Pulse handle 03288 * @param sConfig: TIM One Pulse configuration structure 03289 * @param OutputChannel : TIM Channels to be enabled 03290 * This parameter can be one of the following values: 03291 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03292 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03293 * @param InputChannel : TIM Channels to be enabled 03294 * This parameter can be one of the following values: 03295 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 03296 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 03297 * @retval HAL status 03298 */ 03299 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) 03300 { 03301 TIM_OC_InitTypeDef temp1; 03302 03303 /* Check the parameters */ 03304 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); 03305 assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); 03306 03307 if(OutputChannel != InputChannel) 03308 { 03309 /* Process Locked */ 03310 __HAL_LOCK(htim); 03311 03312 htim->State = HAL_TIM_STATE_BUSY; 03313 03314 /* Extract the Ouput compare configuration from sConfig structure */ 03315 temp1.OCMode = sConfig->OCMode; 03316 temp1.Pulse = sConfig->Pulse; 03317 temp1.OCPolarity = sConfig->OCPolarity; 03318 temp1.OCNPolarity = sConfig->OCNPolarity; 03319 temp1.OCIdleState = sConfig->OCIdleState; 03320 temp1.OCNIdleState = sConfig->OCNIdleState; 03321 03322 switch (OutputChannel) 03323 { 03324 case TIM_CHANNEL_1: 03325 { 03326 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03327 03328 TIM_OC1_SetConfig(htim->Instance, &temp1); 03329 } 03330 break; 03331 case TIM_CHANNEL_2: 03332 { 03333 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03334 03335 TIM_OC2_SetConfig(htim->Instance, &temp1); 03336 } 03337 break; 03338 default: 03339 break; 03340 } 03341 switch (InputChannel) 03342 { 03343 case TIM_CHANNEL_1: 03344 { 03345 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 03346 03347 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, 03348 sConfig->ICSelection, sConfig->ICFilter); 03349 03350 /* Reset the IC1PSC Bits */ 03351 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; 03352 03353 /* Select the Trigger source */ 03354 htim->Instance->SMCR &= ~TIM_SMCR_TS; 03355 htim->Instance->SMCR |= TIM_TS_TI1FP1; 03356 03357 /* Select the Slave Mode */ 03358 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03359 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; 03360 } 03361 break; 03362 case TIM_CHANNEL_2: 03363 { 03364 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 03365 03366 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, 03367 sConfig->ICSelection, sConfig->ICFilter); 03368 03369 /* Reset the IC2PSC Bits */ 03370 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; 03371 03372 /* Select the Trigger source */ 03373 htim->Instance->SMCR &= ~TIM_SMCR_TS; 03374 htim->Instance->SMCR |= TIM_TS_TI2FP2; 03375 03376 /* Select the Slave Mode */ 03377 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 03378 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; 03379 } 03380 break; 03381 03382 default: 03383 break; 03384 } 03385 03386 htim->State = HAL_TIM_STATE_READY; 03387 03388 __HAL_UNLOCK(htim); 03389 03390 return HAL_OK; 03391 } 03392 else 03393 { 03394 return HAL_ERROR; 03395 } 03396 } 03397 03398 /** 03399 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral 03400 * @param htim: TIM handle 03401 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write 03402 * This parameters can be on of the following values: 03403 * @arg TIM_DMABASE_CR1 03404 * @arg TIM_DMABASE_CR2 03405 * @arg TIM_DMABASE_SMCR 03406 * @arg TIM_DMABASE_DIER 03407 * @arg TIM_DMABASE_SR 03408 * @arg TIM_DMABASE_EGR 03409 * @arg TIM_DMABASE_CCMR1 03410 * @arg TIM_DMABASE_CCMR2 03411 * @arg TIM_DMABASE_CCER 03412 * @arg TIM_DMABASE_CNT 03413 * @arg TIM_DMABASE_PSC 03414 * @arg TIM_DMABASE_ARR 03415 * @arg TIM_DMABASE_RCR 03416 * @arg TIM_DMABASE_CCR1 03417 * @arg TIM_DMABASE_CCR2 03418 * @arg TIM_DMABASE_CCR3 03419 * @arg TIM_DMABASE_CCR4 03420 * @arg TIM_DMABASE_BDTR 03421 * @arg TIM_DMABASE_DCR 03422 * @param BurstRequestSrc: TIM DMA Request sources 03423 * This parameters can be on of the following values: 03424 * @arg TIM_DMA_UPDATE: TIM update Interrupt source 03425 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 03426 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 03427 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 03428 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 03429 * @arg TIM_DMA_COM: TIM Commutation DMA source 03430 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source 03431 * @param BurstBuffer: The Buffer address. 03432 * @param BurstLength: DMA Burst length. This parameter can be one value 03433 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. 03434 * @retval HAL status 03435 */ 03436 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, 03437 uint32_t* BurstBuffer, uint32_t BurstLength) 03438 { 03439 /* Check the parameters */ 03440 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); 03441 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); 03442 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03443 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); 03444 03445 if((htim->State == HAL_TIM_STATE_BUSY)) 03446 { 03447 return HAL_BUSY; 03448 } 03449 else if((htim->State == HAL_TIM_STATE_READY)) 03450 { 03451 if((BurstBuffer == 0 ) && (BurstLength > 0)) 03452 { 03453 return HAL_ERROR; 03454 } 03455 else 03456 { 03457 htim->State = HAL_TIM_STATE_BUSY; 03458 } 03459 } 03460 switch(BurstRequestSrc) 03461 { 03462 case TIM_DMA_UPDATE: 03463 { 03464 /* Set the DMA Period elapsed callback */ 03465 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 03466 03467 /* Set the DMA error callback */ 03468 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 03469 03470 /* Enable the DMA channel */ 03471 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03472 } 03473 break; 03474 case TIM_DMA_CC1: 03475 { 03476 /* Set the DMA Period elapsed callback */ 03477 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; 03478 03479 /* Set the DMA error callback */ 03480 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 03481 03482 /* Enable the DMA channel */ 03483 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03484 } 03485 break; 03486 case TIM_DMA_CC2: 03487 { 03488 /* Set the DMA Period elapsed callback */ 03489 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; 03490 03491 /* Set the DMA error callback */ 03492 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 03493 03494 /* Enable the DMA channel */ 03495 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03496 } 03497 break; 03498 case TIM_DMA_CC3: 03499 { 03500 /* Set the DMA Period elapsed callback */ 03501 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; 03502 03503 /* Set the DMA error callback */ 03504 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 03505 03506 /* Enable the DMA channel */ 03507 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03508 } 03509 break; 03510 case TIM_DMA_CC4: 03511 { 03512 /* Set the DMA Period elapsed callback */ 03513 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; 03514 03515 /* Set the DMA error callback */ 03516 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 03517 03518 /* Enable the DMA channel */ 03519 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03520 } 03521 break; 03522 case TIM_DMA_COM: 03523 { 03524 /* Set the DMA Period elapsed callback */ 03525 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 03526 03527 /* Set the DMA error callback */ 03528 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; 03529 03530 /* Enable the DMA channel */ 03531 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03532 } 03533 break; 03534 case TIM_DMA_TRIGGER: 03535 { 03536 /* Set the DMA Period elapsed callback */ 03537 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; 03538 03539 /* Set the DMA error callback */ 03540 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; 03541 03542 /* Enable the DMA channel */ 03543 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); 03544 } 03545 break; 03546 default: 03547 break; 03548 } 03549 /* configure the DMA Burst Mode */ 03550 htim->Instance->DCR = BurstBaseAddress | BurstLength; 03551 03552 /* Enable the TIM DMA Request */ 03553 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); 03554 03555 htim->State = HAL_TIM_STATE_READY; 03556 03557 /* Return function status */ 03558 return HAL_OK; 03559 } 03560 03561 /** 03562 * @brief Stops the TIM DMA Burst mode 03563 * @param htim: TIM handle 03564 * @param BurstRequestSrc: TIM DMA Request sources to disable 03565 * @retval HAL status 03566 */ 03567 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) 03568 { 03569 /* Check the parameters */ 03570 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03571 03572 /* Abort the DMA transfer (at least disable the DMA channel) */ 03573 switch(BurstRequestSrc) 03574 { 03575 case TIM_DMA_UPDATE: 03576 { 03577 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); 03578 } 03579 break; 03580 case TIM_DMA_CC1: 03581 { 03582 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); 03583 } 03584 break; 03585 case TIM_DMA_CC2: 03586 { 03587 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); 03588 } 03589 break; 03590 case TIM_DMA_CC3: 03591 { 03592 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); 03593 } 03594 break; 03595 case TIM_DMA_CC4: 03596 { 03597 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); 03598 } 03599 break; 03600 case TIM_DMA_COM: 03601 { 03602 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); 03603 } 03604 break; 03605 case TIM_DMA_TRIGGER: 03606 { 03607 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); 03608 } 03609 break; 03610 default: 03611 break; 03612 } 03613 03614 /* Disable the TIM Update DMA request */ 03615 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); 03616 03617 /* Return function status */ 03618 return HAL_OK; 03619 } 03620 03621 /** 03622 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory 03623 * @param htim: TIM handle 03624 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read 03625 * This parameters can be on of the following values: 03626 * @arg TIM_DMABASE_CR1 03627 * @arg TIM_DMABASE_CR2 03628 * @arg TIM_DMABASE_SMCR 03629 * @arg TIM_DMABASE_DIER 03630 * @arg TIM_DMABASE_SR 03631 * @arg TIM_DMABASE_EGR 03632 * @arg TIM_DMABASE_CCMR1 03633 * @arg TIM_DMABASE_CCMR2 03634 * @arg TIM_DMABASE_CCER 03635 * @arg TIM_DMABASE_CNT 03636 * @arg TIM_DMABASE_PSC 03637 * @arg TIM_DMABASE_ARR 03638 * @arg TIM_DMABASE_RCR 03639 * @arg TIM_DMABASE_CCR1 03640 * @arg TIM_DMABASE_CCR2 03641 * @arg TIM_DMABASE_CCR3 03642 * @arg TIM_DMABASE_CCR4 03643 * @arg TIM_DMABASE_BDTR 03644 * @arg TIM_DMABASE_DCR 03645 * @param BurstRequestSrc: TIM DMA Request sources 03646 * This parameters can be on of the following values: 03647 * @arg TIM_DMA_UPDATE: TIM update Interrupt source 03648 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 03649 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 03650 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 03651 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 03652 * @arg TIM_DMA_COM: TIM Commutation DMA source 03653 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source 03654 * @param BurstBuffer: The Buffer address. 03655 * @param BurstLength: DMA Burst length. This parameter can be one value 03656 * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. 03657 * @retval HAL status 03658 */ 03659 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, 03660 uint32_t *BurstBuffer, uint32_t BurstLength) 03661 { 03662 /* Check the parameters */ 03663 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); 03664 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); 03665 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03666 assert_param(IS_TIM_DMA_LENGTH(BurstLength)); 03667 03668 if((htim->State == HAL_TIM_STATE_BUSY)) 03669 { 03670 return HAL_BUSY; 03671 } 03672 else if((htim->State == HAL_TIM_STATE_READY)) 03673 { 03674 if((BurstBuffer == 0 ) && (BurstLength > 0)) 03675 { 03676 return HAL_ERROR; 03677 } 03678 else 03679 { 03680 htim->State = HAL_TIM_STATE_BUSY; 03681 } 03682 } 03683 switch(BurstRequestSrc) 03684 { 03685 case TIM_DMA_UPDATE: 03686 { 03687 /* Set the DMA Period elapsed callback */ 03688 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; 03689 03690 /* Set the DMA error callback */ 03691 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; 03692 03693 /* Enable the DMA channel */ 03694 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03695 } 03696 break; 03697 case TIM_DMA_CC1: 03698 { 03699 /* Set the DMA Period elapsed callback */ 03700 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; 03701 03702 /* Set the DMA error callback */ 03703 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; 03704 03705 /* Enable the DMA channel */ 03706 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03707 } 03708 break; 03709 case TIM_DMA_CC2: 03710 { 03711 /* Set the DMA Period elapsed callback */ 03712 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; 03713 03714 /* Set the DMA error callback */ 03715 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; 03716 03717 /* Enable the DMA channel */ 03718 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03719 } 03720 break; 03721 case TIM_DMA_CC3: 03722 { 03723 /* Set the DMA Period elapsed callback */ 03724 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; 03725 03726 /* Set the DMA error callback */ 03727 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; 03728 03729 /* Enable the DMA channel */ 03730 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03731 } 03732 break; 03733 case TIM_DMA_CC4: 03734 { 03735 /* Set the DMA Period elapsed callback */ 03736 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; 03737 03738 /* Set the DMA error callback */ 03739 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; 03740 03741 /* Enable the DMA channel */ 03742 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03743 } 03744 break; 03745 case TIM_DMA_COM: 03746 { 03747 /* Set the DMA Period elapsed callback */ 03748 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; 03749 03750 /* Set the DMA error callback */ 03751 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; 03752 03753 /* Enable the DMA channel */ 03754 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03755 } 03756 break; 03757 case TIM_DMA_TRIGGER: 03758 { 03759 /* Set the DMA Period elapsed callback */ 03760 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; 03761 03762 /* Set the DMA error callback */ 03763 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; 03764 03765 /* Enable the DMA channel */ 03766 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); 03767 } 03768 break; 03769 default: 03770 break; 03771 } 03772 03773 /* configure the DMA Burst Mode */ 03774 htim->Instance->DCR = BurstBaseAddress | BurstLength; 03775 03776 /* Enable the TIM DMA Request */ 03777 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); 03778 03779 htim->State = HAL_TIM_STATE_READY; 03780 03781 /* Return function status */ 03782 return HAL_OK; 03783 } 03784 03785 /** 03786 * @brief Stop the DMA burst reading 03787 * @param htim: TIM handle 03788 * @param BurstRequestSrc: TIM DMA Request sources to disable. 03789 * @retval HAL status 03790 */ 03791 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) 03792 { 03793 /* Check the parameters */ 03794 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); 03795 03796 /* Abort the DMA transfer (at least disable the DMA channel) */ 03797 switch(BurstRequestSrc) 03798 { 03799 case TIM_DMA_UPDATE: 03800 { 03801 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); 03802 } 03803 break; 03804 case TIM_DMA_CC1: 03805 { 03806 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); 03807 } 03808 break; 03809 case TIM_DMA_CC2: 03810 { 03811 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); 03812 } 03813 break; 03814 case TIM_DMA_CC3: 03815 { 03816 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); 03817 } 03818 break; 03819 case TIM_DMA_CC4: 03820 { 03821 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); 03822 } 03823 break; 03824 case TIM_DMA_COM: 03825 { 03826 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]); 03827 } 03828 break; 03829 case TIM_DMA_TRIGGER: 03830 { 03831 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); 03832 } 03833 break; 03834 default: 03835 break; 03836 } 03837 03838 /* Disable the TIM Update DMA request */ 03839 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); 03840 03841 /* Return function status */ 03842 return HAL_OK; 03843 } 03844 03845 /** 03846 * @brief Generate a software event 03847 * @param htim: TIM handle 03848 * @param EventSource: specifies the event source. 03849 * This parameter can be one of the following values: 03850 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source 03851 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source 03852 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source 03853 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source 03854 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source 03855 * @arg TIM_EVENTSOURCE_COM: Timer COM event source 03856 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source 03857 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source 03858 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source 03859 * @retval None 03860 */ 03861 03862 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) 03863 { 03864 /* Check the parameters */ 03865 assert_param(IS_TIM_INSTANCE(htim->Instance)); 03866 assert_param(IS_TIM_EVENT_SOURCE(EventSource)); 03867 03868 /* Process Locked */ 03869 __HAL_LOCK(htim); 03870 03871 /* Change the TIM state */ 03872 htim->State = HAL_TIM_STATE_BUSY; 03873 03874 /* Set the event sources */ 03875 htim->Instance->EGR = EventSource; 03876 03877 /* Change the TIM state */ 03878 htim->State = HAL_TIM_STATE_READY; 03879 03880 __HAL_UNLOCK(htim); 03881 03882 /* Return function status */ 03883 return HAL_OK; 03884 } 03885 03886 /** 03887 * @brief Configures the OCRef clear feature 03888 * @param htim: TIM handle 03889 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that 03890 * contains the OCREF clear feature and parameters for the TIM peripheral. 03891 * @param Channel: specifies the TIM Channel 03892 * This parameter can be one of the following values: 03893 * @arg TIM_Channel_1: TIM Channel 1 03894 * @arg TIM_Channel_2: TIM Channel 2 03895 * @arg TIM_Channel_3: TIM Channel 3 03896 * @arg TIM_Channel_4: TIM Channel 4 03897 * @arg TIM_Channel_5: TIM Channel 5 03898 * @arg TIM_Channel_6: TIM Channel 6 03899 * @retval None 03900 */ 03901 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, 03902 TIM_ClearInputConfigTypeDef *sClearInputConfig, 03903 uint32_t Channel) 03904 { 03905 uint32_t tmpsmcr = 0; 03906 03907 /* Check the parameters */ 03908 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); 03909 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); 03910 03911 /* Process Locked */ 03912 __HAL_LOCK(htim); 03913 03914 switch (sClearInputConfig->ClearInputSource) 03915 { 03916 case TIM_CLEARINPUTSOURCE_NONE: 03917 { 03918 /* Get the TIMx SMCR register value */ 03919 tmpsmcr = htim->Instance->SMCR; 03920 03921 /* Clear the OCREF clear selection bit */ 03922 tmpsmcr &= ~TIM_SMCR_OCCS; 03923 03924 /* Clear the ETR Bits */ 03925 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 03926 03927 /* Set TIMx_SMCR */ 03928 htim->Instance->SMCR = tmpsmcr; 03929 } 03930 break; 03931 03932 case TIM_CLEARINPUTSOURCE_OCREFCLR: 03933 { 03934 /* Clear the OCREF clear selection bit */ 03935 htim->Instance->SMCR &= ~TIM_SMCR_OCCS; 03936 } 03937 break; 03938 03939 case TIM_CLEARINPUTSOURCE_ETR: 03940 { 03941 /* Check the parameters */ 03942 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); 03943 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); 03944 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); 03945 03946 TIM_ETR_SetConfig(htim->Instance, 03947 sClearInputConfig->ClearInputPrescaler, 03948 sClearInputConfig->ClearInputPolarity, 03949 sClearInputConfig->ClearInputFilter); 03950 03951 /* Set the OCREF clear selection bit */ 03952 htim->Instance->SMCR |= TIM_SMCR_OCCS; 03953 } 03954 break; 03955 03956 default: 03957 break; 03958 } 03959 03960 switch (Channel) 03961 { 03962 case TIM_CHANNEL_1: 03963 { 03964 if(sClearInputConfig->ClearInputState != RESET) 03965 { 03966 /* Enable the OCREF clear feature for Channel 1 */ 03967 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; 03968 } 03969 else 03970 { 03971 /* Disable the OCREF clear feature for Channel 1 */ 03972 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; 03973 } 03974 } 03975 break; 03976 case TIM_CHANNEL_2: 03977 { 03978 if(sClearInputConfig->ClearInputState != RESET) 03979 { 03980 /* Enable the OCREF clear feature for Channel 2 */ 03981 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; 03982 } 03983 else 03984 { 03985 /* Disable the OCREF clear feature for Channel 2 */ 03986 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; 03987 } 03988 } 03989 break; 03990 case TIM_CHANNEL_3: 03991 { 03992 if(sClearInputConfig->ClearInputState != RESET) 03993 { 03994 /* Enable the OCREF clear feature for Channel 3 */ 03995 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; 03996 } 03997 else 03998 { 03999 /* Disable the OCREF clear feature for Channel 3 */ 04000 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; 04001 } 04002 } 04003 break; 04004 case TIM_CHANNEL_4: 04005 { 04006 if(sClearInputConfig->ClearInputState != RESET) 04007 { 04008 /* Enable the OCREF clear feature for Channel 4 */ 04009 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; 04010 } 04011 else 04012 { 04013 /* Disable the OCREF clear feature for Channel 4 */ 04014 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; 04015 } 04016 } 04017 break; 04018 case TIM_CHANNEL_5: 04019 { 04020 if(sClearInputConfig->ClearInputState != RESET) 04021 { 04022 /* Enable the OCREF clear feature for Channel 1 */ 04023 htim->Instance->CCMR3 |= TIM_CCMR3_OC5CE; 04024 } 04025 else 04026 { 04027 /* Disable the OCREF clear feature for Channel 1 */ 04028 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE; 04029 } 04030 } 04031 break; 04032 case TIM_CHANNEL_6: 04033 { 04034 if(sClearInputConfig->ClearInputState != RESET) 04035 { 04036 /* Enable the OCREF clear feature for Channel 1 */ 04037 htim->Instance->CCMR3 |= TIM_CCMR3_OC6CE; 04038 } 04039 else 04040 { 04041 /* Disable the OCREF clear feature for Channel 1 */ 04042 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE; 04043 } 04044 } 04045 break; 04046 default: 04047 break; 04048 } 04049 04050 __HAL_UNLOCK(htim); 04051 04052 return HAL_OK; 04053 } 04054 04055 /** 04056 * @brief Configures the clock source to be used 04057 * @param htim: TIM handle 04058 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that 04059 * contains the clock source information for the TIM peripheral. 04060 * @retval HAL status 04061 */ 04062 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) 04063 { 04064 uint32_t tmpsmcr = 0; 04065 04066 /* Process Locked */ 04067 __HAL_LOCK(htim); 04068 04069 htim->State = HAL_TIM_STATE_BUSY; 04070 04071 /* Check the parameters */ 04072 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); 04073 04074 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ 04075 tmpsmcr = htim->Instance->SMCR; 04076 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 04077 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 04078 htim->Instance->SMCR = tmpsmcr; 04079 04080 switch (sClockSourceConfig->ClockSource) 04081 { 04082 case TIM_CLOCKSOURCE_INTERNAL: 04083 { 04084 assert_param(IS_TIM_INSTANCE(htim->Instance)); 04085 /* Disable slave mode to clock the prescaler directly with the internal clock */ 04086 htim->Instance->SMCR &= ~TIM_SMCR_SMS; 04087 } 04088 break; 04089 04090 case TIM_CLOCKSOURCE_ETRMODE1: 04091 { 04092 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ 04093 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); 04094 04095 /* Check ETR input conditioning related parameters */ 04096 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); 04097 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04098 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04099 04100 /* Configure the ETR Clock source */ 04101 TIM_ETR_SetConfig(htim->Instance, 04102 sClockSourceConfig->ClockPrescaler, 04103 sClockSourceConfig->ClockPolarity, 04104 sClockSourceConfig->ClockFilter); 04105 /* Get the TIMx SMCR register value */ 04106 tmpsmcr = htim->Instance->SMCR; 04107 /* Reset the SMS and TS Bits */ 04108 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 04109 /* Select the External clock mode1 and the ETRF trigger */ 04110 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 04111 /* Write to TIMx SMCR */ 04112 htim->Instance->SMCR = tmpsmcr; 04113 } 04114 break; 04115 04116 case TIM_CLOCKSOURCE_ETRMODE2: 04117 { 04118 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ 04119 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); 04120 04121 /* Check ETR input conditioning related parameters */ 04122 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); 04123 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04124 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04125 04126 /* Configure the ETR Clock source */ 04127 TIM_ETR_SetConfig(htim->Instance, 04128 sClockSourceConfig->ClockPrescaler, 04129 sClockSourceConfig->ClockPolarity, 04130 sClockSourceConfig->ClockFilter); 04131 /* Enable the External clock mode2 */ 04132 htim->Instance->SMCR |= TIM_SMCR_ECE; 04133 } 04134 break; 04135 04136 case TIM_CLOCKSOURCE_TI1: 04137 { 04138 /* Check whether or not the timer instance supports external clock mode 1 */ 04139 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); 04140 04141 /* Check TI1 input conditioning related parameters */ 04142 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04143 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04144 04145 TIM_TI1_ConfigInputStage(htim->Instance, 04146 sClockSourceConfig->ClockPolarity, 04147 sClockSourceConfig->ClockFilter); 04148 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 04149 } 04150 break; 04151 04152 case TIM_CLOCKSOURCE_TI2: 04153 { 04154 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ 04155 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); 04156 04157 /* Check TI2 input conditioning related parameters */ 04158 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04159 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04160 04161 TIM_TI2_ConfigInputStage(htim->Instance, 04162 sClockSourceConfig->ClockPolarity, 04163 sClockSourceConfig->ClockFilter); 04164 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 04165 } 04166 break; 04167 04168 case TIM_CLOCKSOURCE_TI1ED: 04169 { 04170 /* Check whether or not the timer instance supports external clock mode 1 */ 04171 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); 04172 04173 /* Check TI1 input conditioning related parameters */ 04174 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); 04175 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); 04176 04177 TIM_TI1_ConfigInputStage(htim->Instance, 04178 sClockSourceConfig->ClockPolarity, 04179 sClockSourceConfig->ClockFilter); 04180 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 04181 } 04182 break; 04183 04184 case TIM_CLOCKSOURCE_ITR0: 04185 { 04186 /* Check whether or not the timer instance supports internal trigger input */ 04187 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); 04188 04189 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); 04190 } 04191 break; 04192 04193 case TIM_CLOCKSOURCE_ITR1: 04194 { 04195 /* Check whether or not the timer instance supports internal trigger input */ 04196 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); 04197 04198 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); 04199 } 04200 break; 04201 04202 case TIM_CLOCKSOURCE_ITR2: 04203 { 04204 /* Check whether or not the timer instance supports internal trigger input */ 04205 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); 04206 04207 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); 04208 } 04209 break; 04210 04211 case TIM_CLOCKSOURCE_ITR3: 04212 { 04213 /* Check whether or not the timer instance supports internal trigger input */ 04214 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); 04215 04216 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); 04217 } 04218 break; 04219 04220 default: 04221 break; 04222 } 04223 htim->State = HAL_TIM_STATE_READY; 04224 04225 __HAL_UNLOCK(htim); 04226 04227 return HAL_OK; 04228 } 04229 04230 /** 04231 * @brief Selects the signal connected to the TI1 input: direct from CH1_input 04232 * or a XOR combination between CH1_input, CH2_input & CH3_input 04233 * @param htim: TIM handle. 04234 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the 04235 * output of a XOR gate. 04236 * This parameter can be one of the following values: 04237 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input 04238 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 04239 * pins are connected to the TI1 input (XOR combination) 04240 * @retval HAL status 04241 */ 04242 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) 04243 { 04244 uint32_t tmpcr2 = 0; 04245 04246 /* Check the parameters */ 04247 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); 04248 assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); 04249 04250 /* Get the TIMx CR2 register value */ 04251 tmpcr2 = htim->Instance->CR2; 04252 04253 /* Reset the TI1 selection */ 04254 tmpcr2 &= ~TIM_CR2_TI1S; 04255 04256 /* Set the TI1 selection */ 04257 tmpcr2 |= TI1_Selection; 04258 04259 /* Write to TIMxCR2 */ 04260 htim->Instance->CR2 = tmpcr2; 04261 04262 return HAL_OK; 04263 } 04264 04265 /** 04266 * @brief Configures the TIM in Slave mode 04267 * @param htim: TIM handle. 04268 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that 04269 * contains the selected trigger (internal trigger input, filtered 04270 * timer input or external trigger input) and the ) and the Slave 04271 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). 04272 * @retval HAL status 04273 */ 04274 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) 04275 { 04276 /* Check the parameters */ 04277 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); 04278 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); 04279 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); 04280 04281 __HAL_LOCK(htim); 04282 04283 htim->State = HAL_TIM_STATE_BUSY; 04284 04285 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); 04286 04287 /* Disable Trigger Interrupt */ 04288 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); 04289 04290 /* Disable Trigger DMA request */ 04291 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 04292 04293 htim->State = HAL_TIM_STATE_READY; 04294 04295 __HAL_UNLOCK(htim); 04296 04297 return HAL_OK; 04298 } 04299 04300 /** 04301 * @brief Configures the TIM in Slave mode in interrupt mode 04302 * @param htim: TIM handle. 04303 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that 04304 * contains the selected trigger (internal trigger input, filtered 04305 * timer input or external trigger input) and the ) and the Slave 04306 * mode (Disable, Reset, Gated, Trigger, External clock mode 1). 04307 * @retval HAL status 04308 */ 04309 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, 04310 TIM_SlaveConfigTypeDef * sSlaveConfig) 04311 { 04312 /* Check the parameters */ 04313 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); 04314 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); 04315 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); 04316 04317 __HAL_LOCK(htim); 04318 04319 htim->State = HAL_TIM_STATE_BUSY; 04320 04321 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); 04322 04323 /* Enable Trigger Interrupt */ 04324 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); 04325 04326 /* Disable Trigger DMA request */ 04327 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); 04328 04329 htim->State = HAL_TIM_STATE_READY; 04330 04331 __HAL_UNLOCK(htim); 04332 04333 return HAL_OK; 04334 } 04335 04336 /** 04337 * @brief Read the captured value from Capture Compare unit 04338 * @param htim: TIM handle. 04339 * @param Channel : TIM Channels to be enabled 04340 * This parameter can be one of the following values: 04341 * @arg TIM_CHANNEL_1: TIM Channel 1 selected 04342 * @arg TIM_CHANNEL_2: TIM Channel 2 selected 04343 * @arg TIM_CHANNEL_3: TIM Channel 3 selected 04344 * @arg TIM_CHANNEL_4: TIM Channel 4 selected 04345 * @retval Captured value 04346 */ 04347 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) 04348 { 04349 uint32_t tmpreg = 0; 04350 04351 __HAL_LOCK(htim); 04352 04353 switch (Channel) 04354 { 04355 case TIM_CHANNEL_1: 04356 { 04357 /* Check the parameters */ 04358 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 04359 04360 /* Return the capture 1 value */ 04361 tmpreg = htim->Instance->CCR1; 04362 04363 break; 04364 } 04365 case TIM_CHANNEL_2: 04366 { 04367 /* Check the parameters */ 04368 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 04369 04370 /* Return the capture 2 value */ 04371 tmpreg = htim->Instance->CCR2; 04372 04373 break; 04374 } 04375 04376 case TIM_CHANNEL_3: 04377 { 04378 /* Check the parameters */ 04379 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); 04380 04381 /* Return the capture 3 value */ 04382 tmpreg = htim->Instance->CCR3; 04383 04384 break; 04385 } 04386 04387 case TIM_CHANNEL_4: 04388 { 04389 /* Check the parameters */ 04390 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); 04391 04392 /* Return the capture 4 value */ 04393 tmpreg = htim->Instance->CCR4; 04394 04395 break; 04396 } 04397 04398 default: 04399 break; 04400 } 04401 04402 __HAL_UNLOCK(htim); 04403 return tmpreg; 04404 } 04405 04406 /** 04407 * @} 04408 */ 04409 04410 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions 04411 * @brief TIM Callbacks functions 04412 * 04413 @verbatim 04414 ============================================================================== 04415 ##### TIM Callbacks functions ##### 04416 ============================================================================== 04417 [..] 04418 This section provides TIM callback functions: 04419 (+) Timer Period elapsed callback 04420 (+) Timer Output Compare callback 04421 (+) Timer Input capture callback 04422 (+) Timer Trigger callback 04423 (+) Timer Error callback 04424 04425 @endverbatim 04426 * @{ 04427 */ 04428 04429 /** 04430 * @brief Period elapsed callback in non-blocking mode 04431 * @param htim : TIM handle 04432 * @retval None 04433 */ 04434 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) 04435 { 04436 /* Prevent unused argument(s) compilation warning */ 04437 UNUSED(htim); 04438 04439 /* NOTE : This function should not be modified, when the callback is needed, 04440 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file 04441 */ 04442 04443 } 04444 /** 04445 * @brief Output Compare callback in non-blocking mode 04446 * @param htim : TIM OC handle 04447 * @retval None 04448 */ 04449 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) 04450 { 04451 /* Prevent unused argument(s) compilation warning */ 04452 UNUSED(htim); 04453 04454 /* NOTE : This function should not be modified, when the callback is needed, 04455 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file 04456 */ 04457 } 04458 /** 04459 * @brief Input Capture callback in non-blocking mode 04460 * @param htim : TIM IC handle 04461 * @retval None 04462 */ 04463 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) 04464 { 04465 /* Prevent unused argument(s) compilation warning */ 04466 UNUSED(htim); 04467 04468 /* NOTE : This function should not be modified, when the callback is needed, 04469 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file 04470 */ 04471 } 04472 04473 /** 04474 * @brief PWM Pulse finished callback in non-blocking mode 04475 * @param htim : TIM handle 04476 * @retval None 04477 */ 04478 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) 04479 { 04480 /* Prevent unused argument(s) compilation warning */ 04481 UNUSED(htim); 04482 04483 /* NOTE : This function should not be modified, when the callback is needed, 04484 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file 04485 */ 04486 } 04487 04488 /** 04489 * @brief Hall Trigger detection callback in non-blocking mode 04490 * @param htim : TIM handle 04491 * @retval None 04492 */ 04493 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) 04494 { 04495 /* Prevent unused argument(s) compilation warning */ 04496 UNUSED(htim); 04497 04498 /* NOTE : This function should not be modified, when the callback is needed, 04499 the HAL_TIM_TriggerCallback could be implemented in the user file 04500 */ 04501 } 04502 04503 /** 04504 * @brief Timer error callback in non-blocking mode 04505 * @param htim : TIM handle 04506 * @retval None 04507 */ 04508 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) 04509 { 04510 /* Prevent unused argument(s) compilation warning */ 04511 UNUSED(htim); 04512 04513 /* NOTE : This function should not be modified, when the callback is needed, 04514 the HAL_TIM_ErrorCallback could be implemented in the user file 04515 */ 04516 } 04517 04518 /** 04519 * @} 04520 */ 04521 04522 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions 04523 * @brief Peripheral State functions 04524 * 04525 @verbatim 04526 ============================================================================== 04527 ##### Peripheral State functions ##### 04528 ============================================================================== 04529 [..] 04530 This subsection permits to get in run-time the status of the peripheral 04531 and the data flow. 04532 04533 @endverbatim 04534 * @{ 04535 */ 04536 04537 /** 04538 * @brief Return the TIM Base handle state. 04539 * @param htim: TIM Base handle 04540 * @retval HAL state 04541 */ 04542 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) 04543 { 04544 return htim->State; 04545 } 04546 04547 /** 04548 * @brief Return the TIM OC handle state. 04549 * @param htim: TIM Ouput Compare handle 04550 * @retval HAL state 04551 */ 04552 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) 04553 { 04554 return htim->State; 04555 } 04556 04557 /** 04558 * @brief Return the TIM PWM handle state. 04559 * @param htim: TIM handle 04560 * @retval HAL state 04561 */ 04562 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) 04563 { 04564 return htim->State; 04565 } 04566 04567 /** 04568 * @brief Return the TIM Input Capture handle state. 04569 * @param htim: TIM IC handle 04570 * @retval HAL state 04571 */ 04572 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) 04573 { 04574 return htim->State; 04575 } 04576 04577 /** 04578 * @brief Return the TIM One Pulse Mode handle state. 04579 * @param htim: TIM OPM handle 04580 * @retval HAL state 04581 */ 04582 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) 04583 { 04584 return htim->State; 04585 } 04586 04587 /** 04588 * @brief Return the TIM Encoder Mode handle state. 04589 * @param htim: TIM Encoder handle 04590 * @retval HAL state 04591 */ 04592 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) 04593 { 04594 return htim->State; 04595 } 04596 04597 /** 04598 * @} 04599 */ 04600 04601 /** 04602 * @brief TIM DMA error callback 04603 * @param hdma : pointer to DMA handle. 04604 * @retval None 04605 */ 04606 void TIM_DMAError(DMA_HandleTypeDef *hdma) 04607 { 04608 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04609 04610 htim->State= HAL_TIM_STATE_READY; 04611 04612 HAL_TIM_ErrorCallback(htim); 04613 } 04614 04615 /** 04616 * @brief TIM DMA Delay Pulse complete callback. 04617 * @param hdma : pointer to DMA handle. 04618 * @retval None 04619 */ 04620 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) 04621 { 04622 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04623 04624 htim->State= HAL_TIM_STATE_READY; 04625 04626 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 04627 { 04628 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 04629 } 04630 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 04631 { 04632 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 04633 } 04634 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 04635 { 04636 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 04637 } 04638 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 04639 { 04640 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 04641 } 04642 04643 HAL_TIM_PWM_PulseFinishedCallback(htim); 04644 04645 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 04646 } 04647 /** 04648 * @brief TIM DMA Capture complete callback. 04649 * @param hdma : pointer to DMA handle. 04650 * @retval None 04651 */ 04652 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) 04653 { 04654 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04655 04656 htim->State= HAL_TIM_STATE_READY; 04657 04658 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) 04659 { 04660 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 04661 } 04662 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) 04663 { 04664 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 04665 } 04666 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) 04667 { 04668 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 04669 } 04670 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) 04671 { 04672 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 04673 } 04674 04675 HAL_TIM_IC_CaptureCallback(htim); 04676 04677 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 04678 } 04679 04680 /** 04681 * @brief TIM DMA Period Elapse complete callback. 04682 * @param hdma : pointer to DMA handle. 04683 * @retval None 04684 */ 04685 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) 04686 { 04687 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04688 04689 htim->State= HAL_TIM_STATE_READY; 04690 04691 HAL_TIM_PeriodElapsedCallback(htim); 04692 } 04693 04694 /** 04695 * @brief TIM DMA Trigger callback. 04696 * @param hdma : pointer to DMA handle. 04697 * @retval None 04698 */ 04699 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) 04700 { 04701 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 04702 04703 htim->State= HAL_TIM_STATE_READY; 04704 04705 HAL_TIM_TriggerCallback(htim); 04706 } 04707 04708 /** 04709 * @brief Time Base configuration 04710 * @param TIMx: TIM peripheral 04711 * @param Structure: TIM Base configuration structure 04712 * @retval None 04713 */ 04714 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) 04715 { 04716 uint32_t tmpcr1 = 0; 04717 tmpcr1 = TIMx->CR1; 04718 04719 /* Set TIM Time Base Unit parameters ---------------------------------------*/ 04720 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 04721 { 04722 /* Select the Counter Mode */ 04723 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 04724 tmpcr1 |= Structure->CounterMode; 04725 } 04726 04727 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 04728 { 04729 /* Set the clock division */ 04730 tmpcr1 &= ~TIM_CR1_CKD; 04731 tmpcr1 |= (uint32_t)Structure->ClockDivision; 04732 } 04733 04734 TIMx->CR1 = tmpcr1; 04735 04736 /* Set the Autoreload value */ 04737 TIMx->ARR = (uint32_t)Structure->Period ; 04738 04739 /* Set the Prescaler value */ 04740 TIMx->PSC = (uint32_t)Structure->Prescaler; 04741 04742 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 04743 { 04744 /* Set the Repetition Counter value */ 04745 TIMx->RCR = Structure->RepetitionCounter; 04746 } 04747 04748 /* Generate an update event to reload the Prescaler 04749 and the repetition counter(only for TIM1 and TIM8) value immediately */ 04750 TIMx->EGR = TIM_EGR_UG; 04751 } 04752 04753 /** 04754 * @brief Time Ouput Compare 1 configuration 04755 * @param TIMx to select the TIM peripheral 04756 * @param OC_Config: The ouput configuration structure 04757 * @retval None 04758 */ 04759 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04760 { 04761 uint32_t tmpccmrx = 0; 04762 uint32_t tmpccer = 0; 04763 uint32_t tmpcr2 = 0; 04764 04765 /* Disable the Channel 1: Reset the CC1E Bit */ 04766 TIMx->CCER &= ~TIM_CCER_CC1E; 04767 04768 /* Get the TIMx CCER register value */ 04769 tmpccer = TIMx->CCER; 04770 /* Get the TIMx CR2 register value */ 04771 tmpcr2 = TIMx->CR2; 04772 04773 /* Get the TIMx CCMR1 register value */ 04774 tmpccmrx = TIMx->CCMR1; 04775 04776 /* Reset the Output Compare Mode Bits */ 04777 tmpccmrx &= ~TIM_CCMR1_OC1M; 04778 tmpccmrx &= ~TIM_CCMR1_CC1S; 04779 /* Select the Output Compare Mode */ 04780 tmpccmrx |= OC_Config->OCMode; 04781 04782 /* Reset the Output Polarity level */ 04783 tmpccer &= ~TIM_CCER_CC1P; 04784 /* Set the Output Compare Polarity */ 04785 tmpccer |= OC_Config->OCPolarity; 04786 04787 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 04788 { 04789 /* Check parameters */ 04790 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 04791 04792 /* Reset the Output N Polarity level */ 04793 tmpccer &= ~TIM_CCER_CC1NP; 04794 /* Set the Output N Polarity */ 04795 tmpccer |= OC_Config->OCNPolarity; 04796 /* Reset the Output N State */ 04797 tmpccer &= ~TIM_CCER_CC1NE; 04798 } 04799 04800 if(IS_TIM_BREAK_INSTANCE(TIMx)) 04801 { 04802 /* Check parameters */ 04803 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 04804 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 04805 04806 /* Reset the Output Compare and Output Compare N IDLE State */ 04807 tmpcr2 &= ~TIM_CR2_OIS1; 04808 tmpcr2 &= ~TIM_CR2_OIS1N; 04809 /* Set the Output Idle state */ 04810 tmpcr2 |= OC_Config->OCIdleState; 04811 /* Set the Output N Idle state */ 04812 tmpcr2 |= OC_Config->OCNIdleState; 04813 } 04814 /* Write to TIMx CR2 */ 04815 TIMx->CR2 = tmpcr2; 04816 04817 /* Write to TIMx CCMR1 */ 04818 TIMx->CCMR1 = tmpccmrx; 04819 04820 /* Set the Capture Compare Register value */ 04821 TIMx->CCR1 = OC_Config->Pulse; 04822 04823 /* Write to TIMx CCER */ 04824 TIMx->CCER = tmpccer; 04825 } 04826 04827 /** 04828 * @brief Time Ouput Compare 2 configuration 04829 * @param TIMx to select the TIM peripheral 04830 * @param OC_Config: The ouput configuration structure 04831 * @retval None 04832 */ 04833 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04834 { 04835 uint32_t tmpccmrx = 0; 04836 uint32_t tmpccer = 0; 04837 uint32_t tmpcr2 = 0; 04838 04839 /* Disable the Channel 2: Reset the CC2E Bit */ 04840 TIMx->CCER &= ~TIM_CCER_CC2E; 04841 04842 /* Get the TIMx CCER register value */ 04843 tmpccer = TIMx->CCER; 04844 /* Get the TIMx CR2 register value */ 04845 tmpcr2 = TIMx->CR2; 04846 04847 /* Get the TIMx CCMR1 register value */ 04848 tmpccmrx = TIMx->CCMR1; 04849 04850 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 04851 tmpccmrx &= ~TIM_CCMR1_OC2M; 04852 tmpccmrx &= ~TIM_CCMR1_CC2S; 04853 04854 /* Select the Output Compare Mode */ 04855 tmpccmrx |= (OC_Config->OCMode << 8); 04856 04857 /* Reset the Output Polarity level */ 04858 tmpccer &= ~TIM_CCER_CC2P; 04859 /* Set the Output Compare Polarity */ 04860 tmpccer |= (OC_Config->OCPolarity << 4); 04861 04862 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 04863 { 04864 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 04865 04866 /* Reset the Output N Polarity level */ 04867 tmpccer &= ~TIM_CCER_CC2NP; 04868 /* Set the Output N Polarity */ 04869 tmpccer |= (OC_Config->OCNPolarity << 4); 04870 /* Reset the Output N State */ 04871 tmpccer &= ~TIM_CCER_CC2NE; 04872 04873 } 04874 04875 if(IS_TIM_BREAK_INSTANCE(TIMx)) 04876 { 04877 /* Check parameters */ 04878 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 04879 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 04880 04881 /* Reset the Output Compare and Output Compare N IDLE State */ 04882 tmpcr2 &= ~TIM_CR2_OIS2; 04883 tmpcr2 &= ~TIM_CR2_OIS2N; 04884 /* Set the Output Idle state */ 04885 tmpcr2 |= (OC_Config->OCIdleState << 2); 04886 /* Set the Output N Idle state */ 04887 tmpcr2 |= (OC_Config->OCNIdleState << 2); 04888 } 04889 04890 /* Write to TIMx CR2 */ 04891 TIMx->CR2 = tmpcr2; 04892 04893 /* Write to TIMx CCMR1 */ 04894 TIMx->CCMR1 = tmpccmrx; 04895 04896 /* Set the Capture Compare Register value */ 04897 TIMx->CCR2 = OC_Config->Pulse; 04898 04899 /* Write to TIMx CCER */ 04900 TIMx->CCER = tmpccer; 04901 } 04902 04903 /** 04904 * @brief Time Ouput Compare 3 configuration 04905 * @param TIMx to select the TIM peripheral 04906 * @param OC_Config: The ouput configuration structure 04907 * @retval None 04908 */ 04909 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04910 { 04911 uint32_t tmpccmrx = 0; 04912 uint32_t tmpccer = 0; 04913 uint32_t tmpcr2 = 0; 04914 04915 /* Disable the Channel 3: Reset the CC2E Bit */ 04916 TIMx->CCER &= ~TIM_CCER_CC3E; 04917 04918 /* Get the TIMx CCER register value */ 04919 tmpccer = TIMx->CCER; 04920 /* Get the TIMx CR2 register value */ 04921 tmpcr2 = TIMx->CR2; 04922 04923 /* Get the TIMx CCMR2 register value */ 04924 tmpccmrx = TIMx->CCMR2; 04925 04926 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 04927 tmpccmrx &= ~TIM_CCMR2_OC3M; 04928 tmpccmrx &= ~TIM_CCMR2_CC3S; 04929 /* Select the Output Compare Mode */ 04930 tmpccmrx |= OC_Config->OCMode; 04931 04932 /* Reset the Output Polarity level */ 04933 tmpccer &= ~TIM_CCER_CC3P; 04934 /* Set the Output Compare Polarity */ 04935 tmpccer |= (OC_Config->OCPolarity << 8); 04936 04937 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 04938 { 04939 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); 04940 04941 /* Reset the Output N Polarity level */ 04942 tmpccer &= ~TIM_CCER_CC3NP; 04943 /* Set the Output N Polarity */ 04944 tmpccer |= (OC_Config->OCNPolarity << 8); 04945 /* Reset the Output N State */ 04946 tmpccer &= ~TIM_CCER_CC3NE; 04947 } 04948 04949 if(IS_TIM_BREAK_INSTANCE(TIMx)) 04950 { 04951 /* Check parameters */ 04952 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); 04953 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 04954 04955 /* Reset the Output Compare and Output Compare N IDLE State */ 04956 tmpcr2 &= ~TIM_CR2_OIS3; 04957 tmpcr2 &= ~TIM_CR2_OIS3N; 04958 /* Set the Output Idle state */ 04959 tmpcr2 |= (OC_Config->OCIdleState << 4); 04960 /* Set the Output N Idle state */ 04961 tmpcr2 |= (OC_Config->OCNIdleState << 4); 04962 } 04963 04964 /* Write to TIMx CR2 */ 04965 TIMx->CR2 = tmpcr2; 04966 04967 /* Write to TIMx CCMR2 */ 04968 TIMx->CCMR2 = tmpccmrx; 04969 04970 /* Set the Capture Compare Register value */ 04971 TIMx->CCR3 = OC_Config->Pulse; 04972 04973 /* Write to TIMx CCER */ 04974 TIMx->CCER = tmpccer; 04975 } 04976 04977 /** 04978 * @brief Time Ouput Compare 4 configuration 04979 * @param TIMx to select the TIM peripheral 04980 * @param OC_Config: The ouput configuration structure 04981 * @retval None 04982 */ 04983 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) 04984 { 04985 uint32_t tmpccmrx = 0; 04986 uint32_t tmpccer = 0; 04987 uint32_t tmpcr2 = 0; 04988 04989 /* Disable the Channel 4: Reset the CC4E Bit */ 04990 TIMx->CCER &= ~TIM_CCER_CC4E; 04991 04992 /* Get the TIMx CCER register value */ 04993 tmpccer = TIMx->CCER; 04994 /* Get the TIMx CR2 register value */ 04995 tmpcr2 = TIMx->CR2; 04996 04997 /* Get the TIMx CCMR2 register value */ 04998 tmpccmrx = TIMx->CCMR2; 04999 05000 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 05001 tmpccmrx &= ~TIM_CCMR2_OC4M; 05002 tmpccmrx &= ~TIM_CCMR2_CC4S; 05003 05004 /* Select the Output Compare Mode */ 05005 tmpccmrx |= (OC_Config->OCMode << 8); 05006 05007 /* Reset the Output Polarity level */ 05008 tmpccer &= ~TIM_CCER_CC4P; 05009 /* Set the Output Compare Polarity */ 05010 tmpccer |= (OC_Config->OCPolarity << 12); 05011 05012 if(IS_TIM_BREAK_INSTANCE(TIMx)) 05013 { 05014 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); 05015 05016 /* Reset the Output Compare IDLE State */ 05017 tmpcr2 &= ~TIM_CR2_OIS4; 05018 /* Set the Output Idle state */ 05019 tmpcr2 |= (OC_Config->OCIdleState << 6); 05020 } 05021 05022 /* Write to TIMx CR2 */ 05023 TIMx->CR2 = tmpcr2; 05024 05025 /* Write to TIMx CCMR2 */ 05026 TIMx->CCMR2 = tmpccmrx; 05027 05028 /* Set the Capture Compare Register value */ 05029 TIMx->CCR4 = OC_Config->Pulse; 05030 05031 /* Write to TIMx CCER */ 05032 TIMx->CCER = tmpccer; 05033 } 05034 05035 /** 05036 * @brief Timer Ouput Compare 5 configuration 05037 * @param TIMx to select the TIM peripheral 05038 * @param OC_Config: The ouput configuration structure 05039 * @retval None 05040 */ 05041 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, 05042 TIM_OC_InitTypeDef *OC_Config) 05043 { 05044 uint32_t tmpccmrx = 0; 05045 uint32_t tmpccer = 0; 05046 uint32_t tmpcr2 = 0; 05047 05048 /* Disable the output: Reset the CCxE Bit */ 05049 TIMx->CCER &= ~TIM_CCER_CC5E; 05050 05051 /* Get the TIMx CCER register value */ 05052 tmpccer = TIMx->CCER; 05053 /* Get the TIMx CR2 register value */ 05054 tmpcr2 = TIMx->CR2; 05055 /* Get the TIMx CCMR1 register value */ 05056 tmpccmrx = TIMx->CCMR3; 05057 05058 /* Reset the Output Compare Mode Bits */ 05059 tmpccmrx &= ~(TIM_CCMR3_OC5M); 05060 /* Select the Output Compare Mode */ 05061 tmpccmrx |= OC_Config->OCMode; 05062 05063 /* Reset the Output Polarity level */ 05064 tmpccer &= ~TIM_CCER_CC5P; 05065 /* Set the Output Compare Polarity */ 05066 tmpccer |= (OC_Config->OCPolarity << 16); 05067 05068 if(IS_TIM_BREAK_INSTANCE(TIMx)) 05069 { 05070 /* Reset the Output Compare IDLE State */ 05071 tmpcr2 &= ~TIM_CR2_OIS5; 05072 /* Set the Output Idle state */ 05073 tmpcr2 |= (OC_Config->OCIdleState << 8); 05074 } 05075 /* Write to TIMx CR2 */ 05076 TIMx->CR2 = tmpcr2; 05077 05078 /* Write to TIMx CCMR3 */ 05079 TIMx->CCMR3 = tmpccmrx; 05080 05081 /* Set the Capture Compare Register value */ 05082 TIMx->CCR5 = OC_Config->Pulse; 05083 05084 /* Write to TIMx CCER */ 05085 TIMx->CCER = tmpccer; 05086 } 05087 05088 /** 05089 * @brief Timer Ouput Compare 6 configuration 05090 * @param TIMx to select the TIM peripheral 05091 * @param OC_Config: The ouput configuration structure 05092 * @retval None 05093 */ 05094 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, 05095 TIM_OC_InitTypeDef *OC_Config) 05096 { 05097 uint32_t tmpccmrx = 0; 05098 uint32_t tmpccer = 0; 05099 uint32_t tmpcr2 = 0; 05100 05101 /* Disable the output: Reset the CCxE Bit */ 05102 TIMx->CCER &= ~TIM_CCER_CC6E; 05103 05104 /* Get the TIMx CCER register value */ 05105 tmpccer = TIMx->CCER; 05106 /* Get the TIMx CR2 register value */ 05107 tmpcr2 = TIMx->CR2; 05108 /* Get the TIMx CCMR1 register value */ 05109 tmpccmrx = TIMx->CCMR3; 05110 05111 /* Reset the Output Compare Mode Bits */ 05112 tmpccmrx &= ~(TIM_CCMR3_OC6M); 05113 /* Select the Output Compare Mode */ 05114 tmpccmrx |= (OC_Config->OCMode << 8); 05115 05116 /* Reset the Output Polarity level */ 05117 tmpccer &= (uint32_t)~TIM_CCER_CC6P; 05118 /* Set the Output Compare Polarity */ 05119 tmpccer |= (OC_Config->OCPolarity << 20); 05120 05121 if(IS_TIM_BREAK_INSTANCE(TIMx)) 05122 { 05123 /* Reset the Output Compare IDLE State */ 05124 tmpcr2 &= ~TIM_CR2_OIS6; 05125 /* Set the Output Idle state */ 05126 tmpcr2 |= (OC_Config->OCIdleState << 10); 05127 } 05128 05129 /* Write to TIMx CR2 */ 05130 TIMx->CR2 = tmpcr2; 05131 05132 /* Write to TIMx CCMR3 */ 05133 TIMx->CCMR3 = tmpccmrx; 05134 05135 /* Set the Capture Compare Register value */ 05136 TIMx->CCR6 = OC_Config->Pulse; 05137 05138 /* Write to TIMx CCER */ 05139 TIMx->CCER = tmpccer; 05140 } 05141 05142 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, 05143 TIM_SlaveConfigTypeDef * sSlaveConfig) 05144 { 05145 uint32_t tmpsmcr = 0; 05146 uint32_t tmpccmr1 = 0; 05147 uint32_t tmpccer = 0; 05148 05149 /* Get the TIMx SMCR register value */ 05150 tmpsmcr = htim->Instance->SMCR; 05151 05152 /* Reset the Trigger Selection Bits */ 05153 tmpsmcr &= ~TIM_SMCR_TS; 05154 /* Set the Input Trigger source */ 05155 tmpsmcr |= sSlaveConfig->InputTrigger; 05156 05157 /* Reset the slave mode Bits */ 05158 tmpsmcr &= ~TIM_SMCR_SMS; 05159 /* Set the slave mode */ 05160 tmpsmcr |= sSlaveConfig->SlaveMode; 05161 05162 /* Write to TIMx SMCR */ 05163 htim->Instance->SMCR = tmpsmcr; 05164 05165 /* Configure the trigger prescaler, filter, and polarity */ 05166 switch (sSlaveConfig->InputTrigger) 05167 { 05168 case TIM_TS_ETRF: 05169 { 05170 /* Check the parameters */ 05171 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); 05172 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); 05173 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 05174 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05175 /* Configure the ETR Trigger source */ 05176 TIM_ETR_SetConfig(htim->Instance, 05177 sSlaveConfig->TriggerPrescaler, 05178 sSlaveConfig->TriggerPolarity, 05179 sSlaveConfig->TriggerFilter); 05180 } 05181 break; 05182 05183 case TIM_TS_TI1F_ED: 05184 { 05185 /* Check the parameters */ 05186 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 05187 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05188 05189 /* Disable the Channel 1: Reset the CC1E Bit */ 05190 tmpccer = htim->Instance->CCER; 05191 htim->Instance->CCER &= ~TIM_CCER_CC1E; 05192 tmpccmr1 = htim->Instance->CCMR1; 05193 05194 /* Set the filter */ 05195 tmpccmr1 &= ~TIM_CCMR1_IC1F; 05196 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); 05197 05198 /* Write to TIMx CCMR1 and CCER registers */ 05199 htim->Instance->CCMR1 = tmpccmr1; 05200 htim->Instance->CCER = tmpccer; 05201 05202 } 05203 break; 05204 05205 case TIM_TS_TI1FP1: 05206 { 05207 /* Check the parameters */ 05208 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); 05209 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 05210 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05211 05212 /* Configure TI1 Filter and Polarity */ 05213 TIM_TI1_ConfigInputStage(htim->Instance, 05214 sSlaveConfig->TriggerPolarity, 05215 sSlaveConfig->TriggerFilter); 05216 } 05217 break; 05218 05219 case TIM_TS_TI2FP2: 05220 { 05221 /* Check the parameters */ 05222 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05223 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); 05224 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); 05225 05226 /* Configure TI2 Filter and Polarity */ 05227 TIM_TI2_ConfigInputStage(htim->Instance, 05228 sSlaveConfig->TriggerPolarity, 05229 sSlaveConfig->TriggerFilter); 05230 } 05231 break; 05232 05233 case TIM_TS_ITR0: 05234 { 05235 /* Check the parameter */ 05236 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05237 } 05238 break; 05239 05240 case TIM_TS_ITR1: 05241 { 05242 /* Check the parameter */ 05243 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05244 } 05245 break; 05246 05247 case TIM_TS_ITR2: 05248 { 05249 /* Check the parameter */ 05250 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05251 } 05252 break; 05253 05254 case TIM_TS_ITR3: 05255 { 05256 /* Check the parameter */ 05257 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); 05258 } 05259 break; 05260 05261 default: 05262 break; 05263 } 05264 } 05265 05266 /** 05267 * @brief Configure the TI1 as Input. 05268 * @param TIMx to select the TIM peripheral. 05269 * @param TIM_ICPolarity : The Input Polarity. 05270 * This parameter can be one of the following values: 05271 * @arg TIM_ICPolarity_Rising 05272 * @arg TIM_ICPolarity_Falling 05273 * @arg TIM_ICPolarity_BothEdge 05274 * @param TIM_ICSelection: specifies the input to be used. 05275 * This parameter can be one of the following values: 05276 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. 05277 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. 05278 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. 05279 * @param TIM_ICFilter: Specifies the Input Capture Filter. 05280 * This parameter must be a value between 0x00 and 0x0F. 05281 * @retval None 05282 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 05283 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be 05284 * protected against un-initialized filter and polarity values. 05285 */ 05286 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05287 uint32_t TIM_ICFilter) 05288 { 05289 uint32_t tmpccmr1 = 0; 05290 uint32_t tmpccer = 0; 05291 05292 /* Disable the Channel 1: Reset the CC1E Bit */ 05293 TIMx->CCER &= ~TIM_CCER_CC1E; 05294 tmpccmr1 = TIMx->CCMR1; 05295 tmpccer = TIMx->CCER; 05296 05297 /* Select the Input */ 05298 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) 05299 { 05300 tmpccmr1 &= ~TIM_CCMR1_CC1S; 05301 tmpccmr1 |= TIM_ICSelection; 05302 } 05303 else 05304 { 05305 tmpccmr1 |= TIM_CCMR1_CC1S_0; 05306 } 05307 05308 /* Set the filter */ 05309 tmpccmr1 &= ~TIM_CCMR1_IC1F; 05310 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); 05311 05312 /* Select the Polarity and set the CC1E Bit */ 05313 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 05314 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); 05315 05316 /* Write to TIMx CCMR1 and CCER registers */ 05317 TIMx->CCMR1 = tmpccmr1; 05318 TIMx->CCER = tmpccer; 05319 } 05320 05321 /** 05322 * @brief Configure the Polarity and Filter for TI1. 05323 * @param TIMx to select the TIM peripheral. 05324 * @param TIM_ICPolarity : The Input Polarity. 05325 * This parameter can be one of the following values: 05326 * @arg TIM_ICPolarity_Rising 05327 * @arg TIM_ICPolarity_Falling 05328 * @arg TIM_ICPolarity_BothEdge 05329 * @param TIM_ICFilter: Specifies the Input Capture Filter. 05330 * This parameter must be a value between 0x00 and 0x0F. 05331 * @retval None 05332 */ 05333 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) 05334 { 05335 uint32_t tmpccmr1 = 0; 05336 uint32_t tmpccer = 0; 05337 05338 /* Disable the Channel 1: Reset the CC1E Bit */ 05339 tmpccer = TIMx->CCER; 05340 TIMx->CCER &= ~TIM_CCER_CC1E; 05341 tmpccmr1 = TIMx->CCMR1; 05342 05343 /* Set the filter */ 05344 tmpccmr1 &= ~TIM_CCMR1_IC1F; 05345 tmpccmr1 |= (TIM_ICFilter << 4); 05346 05347 /* Select the Polarity and set the CC1E Bit */ 05348 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 05349 tmpccer |= TIM_ICPolarity; 05350 05351 /* Write to TIMx CCMR1 and CCER registers */ 05352 TIMx->CCMR1 = tmpccmr1; 05353 TIMx->CCER = tmpccer; 05354 } 05355 05356 /** 05357 * @brief Configure the TI2 as Input. 05358 * @param TIMx to select the TIM peripheral 05359 * @param TIM_ICPolarity : The Input Polarity. 05360 * This parameter can be one of the following values: 05361 * @arg TIM_ICPolarity_Rising 05362 * @arg TIM_ICPolarity_Falling 05363 * @arg TIM_ICPolarity_BothEdge 05364 * @param TIM_ICSelection: specifies the input to be used. 05365 * This parameter can be one of the following values: 05366 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. 05367 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. 05368 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. 05369 * @param TIM_ICFilter: Specifies the Input Capture Filter. 05370 * This parameter must be a value between 0x00 and 0x0F. 05371 * @retval None 05372 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 05373 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be 05374 * protected against un-initialized filter and polarity values. 05375 */ 05376 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05377 uint32_t TIM_ICFilter) 05378 { 05379 uint32_t tmpccmr1 = 0; 05380 uint32_t tmpccer = 0; 05381 05382 /* Disable the Channel 2: Reset the CC2E Bit */ 05383 TIMx->CCER &= ~TIM_CCER_CC2E; 05384 tmpccmr1 = TIMx->CCMR1; 05385 tmpccer = TIMx->CCER; 05386 05387 /* Select the Input */ 05388 tmpccmr1 &= ~TIM_CCMR1_CC2S; 05389 tmpccmr1 |= (TIM_ICSelection << 8); 05390 05391 /* Set the filter */ 05392 tmpccmr1 &= ~TIM_CCMR1_IC2F; 05393 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); 05394 05395 /* Select the Polarity and set the CC2E Bit */ 05396 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 05397 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); 05398 05399 /* Write to TIMx CCMR1 and CCER registers */ 05400 TIMx->CCMR1 = tmpccmr1 ; 05401 TIMx->CCER = tmpccer; 05402 } 05403 05404 /** 05405 * @brief Configure the Polarity and Filter for TI2. 05406 * @param TIMx to select the TIM peripheral. 05407 * @param TIM_ICPolarity : The Input Polarity. 05408 * This parameter can be one of the following values: 05409 * @arg TIM_ICPolarity_Rising 05410 * @arg TIM_ICPolarity_Falling 05411 * @arg TIM_ICPolarity_BothEdge 05412 * @param TIM_ICFilter: Specifies the Input Capture Filter. 05413 * This parameter must be a value between 0x00 and 0x0F. 05414 * @retval None 05415 */ 05416 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) 05417 { 05418 uint32_t tmpccmr1 = 0; 05419 uint32_t tmpccer = 0; 05420 05421 /* Disable the Channel 2: Reset the CC2E Bit */ 05422 TIMx->CCER &= ~TIM_CCER_CC2E; 05423 tmpccmr1 = TIMx->CCMR1; 05424 tmpccer = TIMx->CCER; 05425 05426 /* Set the filter */ 05427 tmpccmr1 &= ~TIM_CCMR1_IC2F; 05428 tmpccmr1 |= (TIM_ICFilter << 12); 05429 05430 /* Select the Polarity and set the CC2E Bit */ 05431 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 05432 tmpccer |= (TIM_ICPolarity << 4); 05433 05434 /* Write to TIMx CCMR1 and CCER registers */ 05435 TIMx->CCMR1 = tmpccmr1 ; 05436 TIMx->CCER = tmpccer; 05437 } 05438 05439 /** 05440 * @brief Configure the TI3 as Input. 05441 * @param TIMx to select the TIM peripheral 05442 * @param TIM_ICPolarity : The Input Polarity. 05443 * This parameter can be one of the following values: 05444 * @arg TIM_ICPolarity_Rising 05445 * @arg TIM_ICPolarity_Falling 05446 * @arg TIM_ICPolarity_BothEdge 05447 * @param TIM_ICSelection: specifies the input to be used. 05448 * This parameter can be one of the following values: 05449 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. 05450 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. 05451 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. 05452 * @param TIM_ICFilter: Specifies the Input Capture Filter. 05453 * This parameter must be a value between 0x00 and 0x0F. 05454 * @retval None 05455 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 05456 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be 05457 * protected against un-initialized filter and polarity values. 05458 */ 05459 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05460 uint32_t TIM_ICFilter) 05461 { 05462 uint32_t tmpccmr2 = 0; 05463 uint32_t tmpccer = 0; 05464 05465 /* Disable the Channel 3: Reset the CC3E Bit */ 05466 TIMx->CCER &= ~TIM_CCER_CC3E; 05467 tmpccmr2 = TIMx->CCMR2; 05468 tmpccer = TIMx->CCER; 05469 05470 /* Select the Input */ 05471 tmpccmr2 &= ~TIM_CCMR2_CC3S; 05472 tmpccmr2 |= TIM_ICSelection; 05473 05474 /* Set the filter */ 05475 tmpccmr2 &= ~TIM_CCMR2_IC3F; 05476 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); 05477 05478 /* Select the Polarity and set the CC3E Bit */ 05479 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); 05480 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); 05481 05482 /* Write to TIMx CCMR2 and CCER registers */ 05483 TIMx->CCMR2 = tmpccmr2; 05484 TIMx->CCER = tmpccer; 05485 } 05486 05487 /** 05488 * @brief Configure the TI4 as Input. 05489 * @param TIMx to select the TIM peripheral 05490 * @param TIM_ICPolarity : The Input Polarity. 05491 * This parameter can be one of the following values: 05492 * @arg TIM_ICPolarity_Rising 05493 * @arg TIM_ICPolarity_Falling 05494 * @arg TIM_ICPolarity_BothEdge 05495 * @param TIM_ICSelection: specifies the input to be used. 05496 * This parameter can be one of the following values: 05497 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. 05498 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. 05499 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. 05500 * @param TIM_ICFilter: Specifies the Input Capture Filter. 05501 * This parameter must be a value between 0x00 and 0x0F. 05502 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 05503 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be 05504 * protected against un-initialized filter and polarity values. 05505 * @retval None 05506 */ 05507 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, 05508 uint32_t TIM_ICFilter) 05509 { 05510 uint32_t tmpccmr2 = 0; 05511 uint32_t tmpccer = 0; 05512 05513 /* Disable the Channel 4: Reset the CC4E Bit */ 05514 TIMx->CCER &= ~TIM_CCER_CC4E; 05515 tmpccmr2 = TIMx->CCMR2; 05516 tmpccer = TIMx->CCER; 05517 05518 /* Select the Input */ 05519 tmpccmr2 &= ~TIM_CCMR2_CC4S; 05520 tmpccmr2 |= (TIM_ICSelection << 8); 05521 05522 /* Set the filter */ 05523 tmpccmr2 &= ~TIM_CCMR2_IC4F; 05524 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); 05525 05526 /* Select the Polarity and set the CC4E Bit */ 05527 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); 05528 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); 05529 05530 /* Write to TIMx CCMR2 and CCER registers */ 05531 TIMx->CCMR2 = tmpccmr2; 05532 TIMx->CCER = tmpccer ; 05533 } 05534 05535 /** 05536 * @brief Selects the Input Trigger source 05537 * @param TIMx to select the TIM peripheral 05538 * @param InputTriggerSource: The Input Trigger source. 05539 * This parameter can be one of the following values: 05540 * @arg TIM_TS_ITR0: Internal Trigger 0 05541 * @arg TIM_TS_ITR1: Internal Trigger 1 05542 * @arg TIM_TS_ITR2: Internal Trigger 2 05543 * @arg TIM_TS_ITR3: Internal Trigger 3 05544 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector 05545 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 05546 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 05547 * @arg TIM_TS_ETRF: External Trigger input 05548 * @retval None 05549 */ 05550 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) 05551 { 05552 uint32_t tmpsmcr = 0; 05553 05554 /* Get the TIMx SMCR register value */ 05555 tmpsmcr = TIMx->SMCR; 05556 /* Reset the TS Bits */ 05557 tmpsmcr &= ~TIM_SMCR_TS; 05558 /* Set the Input Trigger source and the slave mode*/ 05559 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; 05560 /* Write to TIMx SMCR */ 05561 TIMx->SMCR = tmpsmcr; 05562 } 05563 /** 05564 * @brief Configures the TIMx External Trigger (ETR). 05565 * @param TIMx to select the TIM peripheral 05566 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 05567 * This parameter can be one of the following values: 05568 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. 05569 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. 05570 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. 05571 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. 05572 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 05573 * This parameter can be one of the following values: 05574 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. 05575 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. 05576 * @param ExtTRGFilter: External Trigger Filter. 05577 * This parameter must be a value between 0x00 and 0x0F 05578 * @retval None 05579 */ 05580 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, 05581 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) 05582 { 05583 uint32_t tmpsmcr = 0; 05584 05585 tmpsmcr = TIMx->SMCR; 05586 05587 /* Reset the ETR Bits */ 05588 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 05589 05590 /* Set the Prescaler, the Filter value and the Polarity */ 05591 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); 05592 05593 /* Write to TIMx SMCR */ 05594 TIMx->SMCR = tmpsmcr; 05595 } 05596 05597 /** 05598 * @brief Enables or disables the TIM Capture Compare Channel x. 05599 * @param TIMx to select the TIM peripheral 05600 * @param Channel: specifies the TIM Channel 05601 * This parameter can be one of the following values: 05602 * @arg TIM_CHANNEL_1: TIM Channel 1 05603 * @arg TIM_CHANNEL_2: TIM Channel 2 05604 * @arg TIM_CHANNEL_3: TIM Channel 3 05605 * @arg TIM_CHANNEL_4: TIM Channel 4 05606 * @param ChannelState: specifies the TIM Channel CCxE bit new state. 05607 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. 05608 * @retval None 05609 */ 05610 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) 05611 { 05612 uint32_t tmp = 0; 05613 05614 /* Check the parameters */ 05615 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 05616 assert_param(IS_TIM_CHANNELS(Channel)); 05617 05618 tmp = TIM_CCER_CC1E << Channel; 05619 05620 /* Reset the CCxE Bit */ 05621 TIMx->CCER &= ~tmp; 05622 05623 /* Set or reset the CCxE Bit */ 05624 TIMx->CCER |= (uint32_t)(ChannelState << Channel); 05625 } 05626 05627 05628 /** 05629 * @} 05630 */ 05631 05632 #endif /* HAL_TIM_MODULE_ENABLED */ 05633 /** 05634 * @} 05635 */ 05636 05637 /** 05638 * @} 05639 */ 05640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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