stm32l4xx_hal_sram.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_sram.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   SRAM HAL module driver.
00008   *          This file provides a generic firmware to drive SRAM memories  
00009   *          mounted as external device.
00010   *         
00011   @verbatim
00012   ==============================================================================
00013                           ##### How to use this driver #####
00014   ==============================================================================  
00015   [..]
00016     This driver is a generic layered driver which contains a set of APIs used to 
00017     control SRAM memories. It uses the FMC layer functions to interface 
00018     with SRAM devices.  
00019     The following sequence should be followed to configure the FMC to interface
00020     with SRAM/PSRAM memories: 
00021       
00022    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
00023           SRAM_HandleTypeDef  hsram; and: 
00024           
00025        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 
00026             values of the structure member.
00027             
00028        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 
00029             base register instance for NOR or SRAM device 
00030                          
00031        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
00032             base register instance for NOR or SRAM extended mode 
00033              
00034    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended 
00035        mode timings; for example:
00036           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
00037       and fill its fields with the allowed values of the structure member.
00038       
00039    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
00040        performs the following sequence:
00041           
00042        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
00043        (##) Control register configuration using the FMC NORSRAM interface function 
00044             FMC_NORSRAM_Init()
00045        (##) Timing register configuration using the FMC NORSRAM interface function 
00046             FMC_NORSRAM_Timing_Init()
00047        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function 
00048             FMC_NORSRAM_Extended_Timing_Init()
00049        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()    
00050 
00051    (#) At this stage you can perform read/write accesses from/to the memory connected 
00052        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
00053        following APIs:
00054        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
00055        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
00056        
00057    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
00058        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation  
00059        
00060    (#) You can continuously monitor the SRAM device HAL state by calling the function
00061        HAL_SRAM_GetState()              
00062                              
00063   @endverbatim
00064   ******************************************************************************
00065   * @attention
00066   *
00067   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00068   *
00069   * Redistribution and use in source and binary forms, with or without modification,
00070   * are permitted provided that the following conditions are met:
00071   *   1. Redistributions of source code must retain the above copyright notice,
00072   *      this list of conditions and the following disclaimer.
00073   *   2. Redistributions in binary form must reproduce the above copyright notice,
00074   *      this list of conditions and the following disclaimer in the documentation
00075   *      and/or other materials provided with the distribution.
00076   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00077   *      may be used to endorse or promote products derived from this software
00078   *      without specific prior written permission.
00079   *
00080   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00081   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00082   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00083   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00084   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00085   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00086   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00087   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00088   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00089   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00090   *
00091   ******************************************************************************
00092   */ 
00093 
00094 /* Includes ------------------------------------------------------------------*/
00095 #include "stm32l4xx_hal.h"
00096 
00097 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
00098 
00099 /** @addtogroup STM32L4xx_HAL_Driver
00100   * @{
00101   */
00102 
00103 #ifdef HAL_SRAM_MODULE_ENABLED
00104 
00105 /** @defgroup SRAM SRAM
00106   * @brief SRAM HAL module driver.
00107   * @{
00108   */
00109 /* Private typedef -----------------------------------------------------------*/
00110 /* Private define ------------------------------------------------------------*/
00111 /* Private macro -------------------------------------------------------------*/    
00112 /* Private variables ---------------------------------------------------------*/
00113 /* Private function prototypes -----------------------------------------------*/
00114 /* Exported functions --------------------------------------------------------*/
00115 
00116 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
00117   * @{
00118   */
00119 
00120 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
00121   * @brief    Initialization and Configuration functions.
00122   *
00123   @verbatim    
00124   ==============================================================================
00125            ##### SRAM Initialization and de-initialization functions #####
00126   ==============================================================================
00127     [..]  This section provides functions allowing to initialize/de-initialize
00128           the SRAM memory.
00129   
00130 @endverbatim
00131   * @{
00132   */
00133 
00134 /**
00135   * @brief  Perform the SRAM device initialization sequence.
00136   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00137   *                the configuration information for SRAM module.
00138   * @param  Timing: Pointer to SRAM control timing structure 
00139   * @param  ExtTiming: Pointer to SRAM extended mode timing structure  
00140   * @retval HAL status
00141   */
00142 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
00143 { 
00144   /* Check the SRAM handle parameter */
00145   if(hsram == NULL)
00146   {
00147      return HAL_ERROR;
00148   }
00149   
00150   if(hsram->State == HAL_SRAM_STATE_RESET)
00151   {  
00152     /* Allocate lock resource and initialize it */
00153     hsram->Lock = HAL_UNLOCKED;
00154     
00155     /* Initialize the low level hardware (MSP) */
00156     HAL_SRAM_MspInit(hsram);
00157   }
00158   
00159   /* Initialize SRAM control Interface */
00160   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
00161 
00162   /* Initialize SRAM timing Interface */
00163   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 
00164 
00165   /* Initialize SRAM extended mode timing Interface */
00166   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);  
00167   
00168   /* Enable the NORSRAM device */
00169   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 
00170   
00171   return HAL_OK;
00172 }
00173 
00174 /**
00175   * @brief  Perform the SRAM device de-initialization sequence.
00176   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00177   *                the configuration information for SRAM module.
00178   * @retval HAL status
00179   */
00180 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
00181 { 
00182   /* De-Initialize the low level hardware (MSP) */
00183   HAL_SRAM_MspDeInit(hsram);
00184    
00185   /* Configure the SRAM registers with their reset values */
00186   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
00187 
00188   hsram->State = HAL_SRAM_STATE_RESET;
00189   
00190   /* Release Lock */
00191   __HAL_UNLOCK(hsram);
00192 
00193   return HAL_OK;
00194 }
00195 
00196 /**
00197   * @brief  Initialize the SRAM MSP.
00198   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00199   *                the configuration information for SRAM module.
00200   * @retval None
00201   */
00202 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
00203 {
00204   /* Prevent unused argument(s) compilation warning */
00205   UNUSED(hsram);
00206 
00207   /* NOTE : This function should not be modified, when the callback is needed,
00208             the HAL_SRAM_MspInit could be implemented in the user file
00209    */ 
00210 }
00211 
00212 /**
00213   * @brief  DeInitialize the SRAM MSP.
00214   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00215   *                the configuration information for SRAM module.
00216   * @retval None
00217   */
00218 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
00219 {
00220   /* Prevent unused argument(s) compilation warning */
00221   UNUSED(hsram);
00222 
00223   /* NOTE : This function should not be modified, when the callback is needed,
00224             the HAL_SRAM_MspDeInit could be implemented in the user file
00225    */ 
00226 }
00227 
00228 /**
00229   * @brief  DMA transfer complete callback.
00230   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00231   *                the configuration information for SRAM module.
00232   * @retval None
00233   */
00234 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
00235 {
00236   /* Prevent unused argument(s) compilation warning */
00237   UNUSED(hdma);
00238 
00239   /* NOTE : This function should not be modified, when the callback is needed,
00240             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
00241    */ 
00242 }
00243 
00244 /**
00245   * @brief  DMA transfer complete error callback.
00246   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
00247   *                the configuration information for SRAM module.
00248   * @retval None
00249   */
00250 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
00251 {
00252   /* Prevent unused argument(s) compilation warning */
00253   UNUSED(hdma);
00254 
00255   /* NOTE : This function should not be modified, when the callback is needed,
00256             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
00257    */ 
00258 }
00259 
00260 /**
00261   * @}
00262   */
00263 
00264 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 
00265   * @brief    Input Output and memory control functions 
00266   *
00267   @verbatim    
00268   ==============================================================================
00269                   ##### SRAM Input and Output functions #####
00270   ==============================================================================
00271   [..]  
00272     This section provides functions allowing to use and control the SRAM memory
00273   
00274 @endverbatim
00275   * @{
00276   */
00277 
00278 /**
00279   * @brief  Read 8-bit buffer from SRAM memory. 
00280   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00281   *                the configuration information for SRAM module.
00282   * @param  pAddress: Pointer to read start address
00283   * @param  pDstBuffer: Pointer to destination buffer  
00284   * @param  BufferSize: Size of the buffer to read from memory
00285   * @retval HAL status
00286   */
00287 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
00288 {
00289   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00290   
00291   /* Process Locked */
00292   __HAL_LOCK(hsram);
00293   
00294   /* Update the SRAM controller state */
00295   hsram->State = HAL_SRAM_STATE_BUSY;  
00296   
00297   /* Read data from memory */
00298   for(; BufferSize != 0; BufferSize--)
00299   {
00300     *pDstBuffer = *(__IO uint8_t *)psramaddress;
00301     pDstBuffer++;
00302     psramaddress++;
00303   }
00304   
00305   /* Update the SRAM controller state */
00306   hsram->State = HAL_SRAM_STATE_READY;    
00307 
00308   /* Process unlocked */
00309   __HAL_UNLOCK(hsram); 
00310     
00311   return HAL_OK;   
00312 }
00313 
00314 /**
00315   * @brief  Write 8-bit buffer to SRAM memory. 
00316   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00317   *                the configuration information for SRAM module.
00318   * @param  pAddress: Pointer to write start address
00319   * @param  pSrcBuffer: Pointer to source buffer to write  
00320   * @param  BufferSize: Size of the buffer to write to memory
00321   * @retval HAL status
00322   */
00323 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
00324 {
00325   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
00326   
00327   /* Check the SRAM controller state */
00328   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00329   {
00330     return  HAL_ERROR; 
00331   }
00332   
00333   /* Process Locked */
00334   __HAL_LOCK(hsram);
00335   
00336   /* Update the SRAM controller state */
00337   hsram->State = HAL_SRAM_STATE_BUSY; 
00338 
00339   /* Write data to memory */
00340   for(; BufferSize != 0; BufferSize--)
00341   {
00342     *(__IO uint8_t *)psramaddress = *pSrcBuffer; 
00343     pSrcBuffer++;
00344     psramaddress++;    
00345   }    
00346 
00347   /* Update the SRAM controller state */
00348   hsram->State = HAL_SRAM_STATE_READY; 
00349   
00350   /* Process unlocked */
00351   __HAL_UNLOCK(hsram);
00352     
00353   return HAL_OK;   
00354 }
00355 
00356 /**
00357   * @brief  Read 16-bit buffer from SRAM memory. 
00358   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00359   *                the configuration information for SRAM module.
00360   * @param  pAddress: Pointer to read start address
00361   * @param  pDstBuffer: Pointer to destination buffer  
00362   * @param  BufferSize: Size of the buffer to read from memory
00363   * @retval HAL status
00364   */
00365 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
00366 {
00367   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
00368   
00369   /* Process Locked */
00370   __HAL_LOCK(hsram);
00371   
00372   /* Update the SRAM controller state */
00373   hsram->State = HAL_SRAM_STATE_BUSY;  
00374   
00375   /* Read data from memory */
00376   for(; BufferSize != 0; BufferSize--)
00377   {
00378     *pDstBuffer = *(__IO uint16_t *)psramaddress;
00379     pDstBuffer++;
00380     psramaddress++;
00381   }
00382   
00383   /* Update the SRAM controller state */
00384   hsram->State = HAL_SRAM_STATE_READY;    
00385 
00386   /* Process unlocked */
00387   __HAL_UNLOCK(hsram); 
00388     
00389   return HAL_OK;  
00390 }
00391 
00392 /**
00393   * @brief  Write 16-bit buffer to SRAM memory. 
00394   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00395   *                the configuration information for SRAM module.
00396   * @param  pAddress: Pointer to write start address
00397   * @param  pSrcBuffer: Pointer to source buffer to write  
00398   * @param  BufferSize: Size of the buffer to write to memory
00399   * @retval HAL status
00400   */
00401 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
00402 {
00403   __IO uint16_t * psramaddress = (uint16_t *)pAddress; 
00404   
00405   /* Check the SRAM controller state */
00406   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00407   {
00408     return  HAL_ERROR; 
00409   }
00410   
00411   /* Process Locked */
00412   __HAL_LOCK(hsram);
00413   
00414   /* Update the SRAM controller state */
00415   hsram->State = HAL_SRAM_STATE_BUSY; 
00416 
00417   /* Write data to memory */
00418   for(; BufferSize != 0; BufferSize--)
00419   {
00420     *(__IO uint16_t *)psramaddress = *pSrcBuffer; 
00421     pSrcBuffer++;
00422     psramaddress++;    
00423   }    
00424 
00425   /* Update the SRAM controller state */
00426   hsram->State = HAL_SRAM_STATE_READY; 
00427   
00428   /* Process unlocked */
00429   __HAL_UNLOCK(hsram);
00430     
00431   return HAL_OK;  
00432 }
00433 
00434 /**
00435   * @brief  Read 32-bit buffer from SRAM memory. 
00436   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00437   *                the configuration information for SRAM module.
00438   * @param  pAddress: Pointer to read start address
00439   * @param  pDstBuffer: Pointer to destination buffer  
00440   * @param  BufferSize: Size of the buffer to read from memory
00441   * @retval HAL status
00442   */
00443 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00444 {
00445   /* Process Locked */
00446   __HAL_LOCK(hsram);
00447   
00448   /* Update the SRAM controller state */
00449   hsram->State = HAL_SRAM_STATE_BUSY;  
00450   
00451   /* Read data from memory */
00452   for(; BufferSize != 0; BufferSize--)
00453   {
00454     *pDstBuffer = *(__IO uint32_t *)pAddress;
00455     pDstBuffer++;
00456     pAddress++;
00457   }
00458   
00459   /* Update the SRAM controller state */
00460   hsram->State = HAL_SRAM_STATE_READY;    
00461 
00462   /* Process unlocked */
00463   __HAL_UNLOCK(hsram); 
00464     
00465   return HAL_OK;  
00466 }
00467 
00468 /**
00469   * @brief  Write 32-bit buffer to SRAM memory. 
00470   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00471   *                the configuration information for SRAM module.
00472   * @param  pAddress: Pointer to write start address
00473   * @param  pSrcBuffer: Pointer to source buffer to write  
00474   * @param  BufferSize: Size of the buffer to write to memory
00475   * @retval HAL status
00476   */
00477 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00478 {
00479   /* Check the SRAM controller state */
00480   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00481   {
00482     return  HAL_ERROR; 
00483   }
00484   
00485   /* Process Locked */
00486   __HAL_LOCK(hsram);
00487   
00488   /* Update the SRAM controller state */
00489   hsram->State = HAL_SRAM_STATE_BUSY; 
00490 
00491   /* Write data to memory */
00492   for(; BufferSize != 0; BufferSize--)
00493   {
00494     *(__IO uint32_t *)pAddress = *pSrcBuffer; 
00495     pSrcBuffer++;
00496     pAddress++;    
00497   }    
00498 
00499   /* Update the SRAM controller state */
00500   hsram->State = HAL_SRAM_STATE_READY; 
00501   
00502   /* Process unlocked */
00503   __HAL_UNLOCK(hsram);
00504     
00505   return HAL_OK;   
00506 }
00507 
00508 /**
00509   * @brief  Read a Word data buffer from the SRAM memory using DMA transfer.
00510   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00511   *                the configuration information for SRAM module.
00512   * @param  pAddress: Pointer to read start address
00513   * @param  pDstBuffer: Pointer to destination buffer  
00514   * @param  BufferSize: Size of the buffer to read from memory
00515   * @retval HAL status
00516   */
00517 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
00518 {
00519   /* Process Locked */
00520   __HAL_LOCK(hsram);  
00521   
00522   /* Update the SRAM controller state */
00523   hsram->State = HAL_SRAM_STATE_BUSY;   
00524   
00525   /* Configure DMA user callbacks */
00526   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00527   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00528 
00529   /* Enable the DMA Channel */
00530   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
00531   
00532   /* Update the SRAM controller state */
00533   hsram->State = HAL_SRAM_STATE_READY; 
00534   
00535   /* Process unlocked */
00536   __HAL_UNLOCK(hsram);  
00537   
00538   return HAL_OK; 
00539 }
00540 
00541 /**
00542   * @brief  Write a Word data buffer to SRAM memory using DMA transfer.
00543   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00544   *                the configuration information for SRAM module.
00545   * @param  pAddress: Pointer to write start address
00546   * @param  pSrcBuffer: Pointer to source buffer to write  
00547   * @param  BufferSize: Size of the buffer to write to memory
00548   * @retval HAL status
00549   */
00550 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
00551 {
00552   /* Check the SRAM controller state */
00553   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
00554   {
00555     return  HAL_ERROR; 
00556   }
00557   
00558   /* Process Locked */
00559   __HAL_LOCK(hsram);
00560   
00561   /* Update the SRAM controller state */
00562   hsram->State = HAL_SRAM_STATE_BUSY; 
00563   
00564   /* Configure DMA user callbacks */
00565   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
00566   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
00567 
00568   /* Enable the DMA Channel */
00569   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
00570   
00571   /* Update the SRAM controller state */
00572   hsram->State = HAL_SRAM_STATE_READY;  
00573   
00574   /* Process unlocked */
00575   __HAL_UNLOCK(hsram);  
00576   
00577   return HAL_OK;
00578 }
00579 
00580 /**
00581   * @}
00582   */
00583   
00584 /** @defgroup SRAM_Exported_Functions_Group3 Control functions 
00585  *  @brief   Control functions 
00586  *
00587 @verbatim   
00588   ==============================================================================
00589                         ##### SRAM Control functions #####
00590   ==============================================================================  
00591   [..]
00592     This subsection provides a set of functions allowing to control dynamically
00593     the SRAM interface.
00594 
00595 @endverbatim
00596   * @{
00597   */
00598     
00599 /**
00600   * @brief  Enable dynamically SRAM write operation.
00601   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00602   *                the configuration information for SRAM module.
00603   * @retval HAL status
00604   */
00605 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
00606 {
00607   /* Process Locked */
00608   __HAL_LOCK(hsram);
00609 
00610   /* Enable write operation */
00611   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 
00612   
00613   /* Update the SRAM controller state */
00614   hsram->State = HAL_SRAM_STATE_READY;
00615   
00616   /* Process unlocked */
00617   __HAL_UNLOCK(hsram); 
00618   
00619   return HAL_OK;  
00620 }
00621 
00622 /**
00623   * @brief  Disable dynamically SRAM write operation.
00624   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00625   *                the configuration information for SRAM module.
00626   * @retval HAL status
00627   */
00628 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
00629 {
00630   /* Process Locked */
00631   __HAL_LOCK(hsram);
00632 
00633   /* Update the SRAM controller state */
00634   hsram->State = HAL_SRAM_STATE_BUSY;
00635     
00636   /* Disable write operation */
00637   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 
00638   
00639   /* Update the SRAM controller state */
00640   hsram->State = HAL_SRAM_STATE_PROTECTED;
00641   
00642   /* Process unlocked */
00643   __HAL_UNLOCK(hsram); 
00644   
00645   return HAL_OK;  
00646 }
00647 
00648 /**
00649   * @}
00650   */
00651 
00652 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions 
00653  *  @brief   Peripheral State functions 
00654  *
00655 @verbatim   
00656   ==============================================================================
00657                       ##### SRAM State functions #####
00658   ==============================================================================  
00659   [..]
00660     This subsection permits to get in run-time the status of the SRAM controller 
00661     and the data flow.
00662 
00663 @endverbatim
00664   * @{
00665   */
00666   
00667 /**
00668   * @brief  Return the SRAM controller handle state.
00669   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
00670   *                the configuration information for SRAM module.
00671   * @retval HAL state
00672   */
00673 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
00674 {
00675   /* Return SRAM handle state */
00676   return hsram->State;
00677 }
00678 
00679 /**
00680   * @}
00681   */
00682 
00683 /**
00684   * @}
00685   */
00686 /**
00687   * @}
00688   */
00689 #endif /* HAL_SRAM_MODULE_ENABLED */
00690 
00691 /**
00692   * @}
00693   */
00694 
00695 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00696 
00697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/