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stm32l4xx_hal_rcc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_rcc.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of RCC HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_RCC_H 00040 #define __STM32L4xx_HAL_RCC_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_hal_def.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup RCC 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup RCC_Exported_Types RCC Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief RCC PLL configuration structure definition 00064 */ 00065 typedef struct 00066 { 00067 uint32_t PLLState; /*!< The new state of the PLL. 00068 This parameter can be a value of @ref RCC_PLL_Config */ 00069 00070 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. 00071 This parameter must be a value of @ref RCC_PLL_Clock_Source */ 00072 00073 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. 00074 This parameter must be a number between Min_Data = 1 and Max_Data = 8 */ 00075 00076 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. 00077 This parameter must be a number between Min_Data = 8 and Max_Data = 86 */ 00078 00079 uint32_t PLLP; /*!< PLLP: Division factor for SAI clock. 00080 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ 00081 00082 uint32_t PLLQ; /*!< PLLQ: Division factor for SDMMC1, RNG and USB clocks. 00083 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ 00084 00085 uint32_t PLLR; /*!< PLLR: Division for the main system clock. 00086 User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ. 00087 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ 00088 00089 }RCC_PLLInitTypeDef; 00090 00091 /** 00092 * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition 00093 */ 00094 typedef struct 00095 { 00096 uint32_t OscillatorType; /*!< The oscillators to be configured. 00097 This parameter can be a value of @ref RCC_Oscillator_Type */ 00098 00099 uint32_t HSEState; /*!< The new state of the HSE. 00100 This parameter can be a value of @ref RCC_HSE_Config */ 00101 00102 uint32_t LSEState; /*!< The new state of the LSE. 00103 This parameter can be a value of @ref RCC_LSE_Config */ 00104 00105 uint32_t HSIState; /*!< The new state of the HSI. 00106 This parameter can be a value of @ref RCC_HSI_Config */ 00107 00108 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). 00109 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F on STM32L47x/STM32L48x devices. 00110 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F on STM32L43x/STM32L44x/STM32L49x/STM32L4Ax/ devices */ 00111 00112 uint32_t LSIState; /*!< The new state of the LSI. 00113 This parameter can be a value of @ref RCC_LSI_Config */ 00114 00115 uint32_t MSIState; /*!< The new state of the MSI. 00116 This parameter can be a value of @ref RCC_MSI_Config */ 00117 00118 uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). 00119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00120 00121 uint32_t MSIClockRange; /*!< The MSI frequency range. 00122 This parameter can be a value of @ref RCC_MSI_Clock_Range */ 00123 00124 uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32L43x/STM32L44x/STM32L49x/STM32L4Ax devices). 00125 This parameter can be a value of @ref RCC_HSI48_Config */ 00126 00127 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ 00128 00129 }RCC_OscInitTypeDef; 00130 00131 /** 00132 * @brief RCC System, AHB and APB busses clock configuration structure definition 00133 */ 00134 typedef struct 00135 { 00136 uint32_t ClockType; /*!< The clock to be configured. 00137 This parameter can be a value of @ref RCC_System_Clock_Type */ 00138 00139 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). 00140 This parameter can be a value of @ref RCC_System_Clock_Source */ 00141 00142 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). 00143 This parameter can be a value of @ref RCC_AHB_Clock_Source */ 00144 00145 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). 00146 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00147 00148 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). 00149 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ 00150 00151 }RCC_ClkInitTypeDef; 00152 00153 /** 00154 * @} 00155 */ 00156 00157 /* Exported constants --------------------------------------------------------*/ 00158 /** @defgroup RCC_Exported_Constants RCC Exported Constants 00159 * @{ 00160 */ 00161 00162 /** @defgroup RCC_Timeout_Value Timeout Values 00163 * @{ 00164 */ 00165 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ 00166 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup RCC_Oscillator_Type Oscillator Type 00172 * @{ 00173 */ 00174 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) /*!< Oscillator configuration unchanged */ 00175 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) /*!< HSE to configure */ 00176 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) /*!< HSI to configure */ 00177 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) /*!< LSE to configure */ 00178 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) /*!< LSI to configure */ 00179 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010U) /*!< MSI to configure */ 00180 #if defined(RCC_HSI48_SUPPORT) 00181 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020U) /*!< HSI48 to configure */ 00182 #endif /* RCC_HSI48_SUPPORT */ 00183 /** 00184 * @} 00185 */ 00186 00187 /** @defgroup RCC_HSE_Config HSE Config 00188 * @{ 00189 */ 00190 #define RCC_HSE_OFF ((uint32_t)0x00000000U) /*!< HSE clock deactivation */ 00191 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ 00192 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup RCC_LSE_Config LSE Config 00198 * @{ 00199 */ 00200 #define RCC_LSE_OFF ((uint32_t)0x00000000U) /*!< LSE clock deactivation */ 00201 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ 00202 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ 00203 /** 00204 * @} 00205 */ 00206 00207 /** @defgroup RCC_HSI_Config HSI Config 00208 * @{ 00209 */ 00210 #define RCC_HSI_OFF ((uint32_t)0x00000000U) /*!< HSI clock deactivation */ 00211 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ 00212 00213 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)16) /*!< Default HSI calibration trimming value */ 00214 /** 00215 * @} 00216 */ 00217 00218 /** @defgroup RCC_LSI_Config LSI Config 00219 * @{ 00220 */ 00221 #define RCC_LSI_OFF ((uint32_t)0x00000000U) /*!< LSI clock deactivation */ 00222 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ 00223 /** 00224 * @} 00225 */ 00226 00227 /** @defgroup RCC_MSI_Config MSI Config 00228 * @{ 00229 */ 00230 #define RCC_MSI_OFF ((uint32_t)0x00000000U) /*!< MSI clock deactivation */ 00231 #define RCC_MSI_ON RCC_CR_MSION /*!< MSI clock activation */ 00232 00233 #define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /*!< Default MSI calibration trimming value */ 00234 /** 00235 * @} 00236 */ 00237 00238 #if defined(RCC_HSI48_SUPPORT) 00239 /** @defgroup RCC_HSI48_Config HSI48 Config 00240 * @{ 00241 */ 00242 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ 00243 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */ 00244 /** 00245 * @} 00246 */ 00247 #else 00248 /** @defgroup RCC_HSI48_Config HSI48 Config 00249 * @{ 00250 */ 00251 #define RCC_HSI48_OFF ((uint32_t)0x00000000U) /*!< HSI48 clock deactivation */ 00252 /** 00253 * @} 00254 */ 00255 #endif /* RCC_HSI48_SUPPORT */ 00256 00257 /** @defgroup RCC_PLL_Config PLL Config 00258 * @{ 00259 */ 00260 #define RCC_PLL_NONE ((uint32_t)0x00000000U) /*!< PLL configuration unchanged */ 00261 #define RCC_PLL_OFF ((uint32_t)0x00000001U) /*!< PLL deactivation */ 00262 #define RCC_PLL_ON ((uint32_t)0x00000002U) /*!< PLL activation */ 00263 /** 00264 * @} 00265 */ 00266 00267 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider 00268 * @{ 00269 */ 00270 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 00271 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) /*!< PLLP division factor = 2 */ 00272 #define RCC_PLLP_DIV3 ((uint32_t)0x00000003U) /*!< PLLP division factor = 3 */ 00273 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) /*!< PLLP division factor = 4 */ 00274 #define RCC_PLLP_DIV5 ((uint32_t)0x00000005U) /*!< PLLP division factor = 5 */ 00275 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) /*!< PLLP division factor = 6 */ 00276 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ 00277 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) /*!< PLLP division factor = 8 */ 00278 #define RCC_PLLP_DIV9 ((uint32_t)0x00000009U) /*!< PLLP division factor = 9 */ 00279 #define RCC_PLLP_DIV10 ((uint32_t)0x0000000AU) /*!< PLLP division factor = 10 */ 00280 #define RCC_PLLP_DIV11 ((uint32_t)0x0000000BU) /*!< PLLP division factor = 11 */ 00281 #define RCC_PLLP_DIV12 ((uint32_t)0x0000000CU) /*!< PLLP division factor = 12 */ 00282 #define RCC_PLLP_DIV13 ((uint32_t)0x0000000DU) /*!< PLLP division factor = 13 */ 00283 #define RCC_PLLP_DIV14 ((uint32_t)0x0000000EU) /*!< PLLP division factor = 14 */ 00284 #define RCC_PLLP_DIV15 ((uint32_t)0x0000000FU) /*!< PLLP division factor = 15 */ 00285 #define RCC_PLLP_DIV16 ((uint32_t)0x00000010U) /*!< PLLP division factor = 16 */ 00286 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ 00287 #define RCC_PLLP_DIV18 ((uint32_t)0x00000012U) /*!< PLLP division factor = 18 */ 00288 #define RCC_PLLP_DIV19 ((uint32_t)0x00000013U) /*!< PLLP division factor = 19 */ 00289 #define RCC_PLLP_DIV20 ((uint32_t)0x00000014U) /*!< PLLP division factor = 20 */ 00290 #define RCC_PLLP_DIV21 ((uint32_t)0x00000015U) /*!< PLLP division factor = 21 */ 00291 #define RCC_PLLP_DIV22 ((uint32_t)0x00000016U) /*!< PLLP division factor = 22 */ 00292 #define RCC_PLLP_DIV23 ((uint32_t)0x00000017U) /*!< PLLP division factor = 23 */ 00293 #define RCC_PLLP_DIV24 ((uint32_t)0x00000018U) /*!< PLLP division factor = 24 */ 00294 #define RCC_PLLP_DIV25 ((uint32_t)0x00000019U) /*!< PLLP division factor = 25 */ 00295 #define RCC_PLLP_DIV26 ((uint32_t)0x0000001AU) /*!< PLLP division factor = 26 */ 00296 #define RCC_PLLP_DIV27 ((uint32_t)0x0000001BU) /*!< PLLP division factor = 27 */ 00297 #define RCC_PLLP_DIV28 ((uint32_t)0x0000001CU) /*!< PLLP division factor = 28 */ 00298 #define RCC_PLLP_DIV29 ((uint32_t)0x0000001DU) /*!< PLLP division factor = 29 */ 00299 #define RCC_PLLP_DIV30 ((uint32_t)0x0000001EU) /*!< PLLP division factor = 30 */ 00300 #define RCC_PLLP_DIV31 ((uint32_t)0x0000001FU) /*!< PLLP division factor = 31 */ 00301 #else 00302 #define RCC_PLLP_DIV7 ((uint32_t)0x00000007U) /*!< PLLP division factor = 7 */ 00303 #define RCC_PLLP_DIV17 ((uint32_t)0x00000011U) /*!< PLLP division factor = 17 */ 00304 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 00305 /** 00306 * @} 00307 */ 00308 00309 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider 00310 * @{ 00311 */ 00312 #define RCC_PLLQ_DIV2 ((uint32_t)0x00000002U) /*!< PLLQ division factor = 2 */ 00313 #define RCC_PLLQ_DIV4 ((uint32_t)0x00000004U) /*!< PLLQ division factor = 4 */ 00314 #define RCC_PLLQ_DIV6 ((uint32_t)0x00000006U) /*!< PLLQ division factor = 6 */ 00315 #define RCC_PLLQ_DIV8 ((uint32_t)0x00000008U) /*!< PLLQ division factor = 8 */ 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider 00321 * @{ 00322 */ 00323 #define RCC_PLLR_DIV2 ((uint32_t)0x00000002U) /*!< PLLR division factor = 2 */ 00324 #define RCC_PLLR_DIV4 ((uint32_t)0x00000004U) /*!< PLLR division factor = 4 */ 00325 #define RCC_PLLR_DIV6 ((uint32_t)0x00000006U) /*!< PLLR division factor = 6 */ 00326 #define RCC_PLLR_DIV8 ((uint32_t)0x00000008U) /*!< PLLR division factor = 8 */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source 00332 * @{ 00333 */ 00334 #define RCC_PLLSOURCE_NONE ((uint32_t)0x00000000U) /*!< No clock selected as PLL entry clock source */ 00335 #define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as PLL entry clock source */ 00336 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ 00337 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00338 /** 00339 * @} 00340 */ 00341 00342 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output 00343 * @{ 00344 */ 00345 #if defined(RCC_PLLSAI2_SUPPORT) 00346 #define RCC_PLL_SAI3CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI3CLK selection from main PLL (for devices with PLLSAI2) */ 00347 #else 00348 #define RCC_PLL_SAI2CLK RCC_PLLCFGR_PLLPEN /*!< PLLSAI2CLK selection from main PLL (for devices without PLLSAI2) */ 00349 #endif /* RCC_PLLSAI2_SUPPORT */ 00350 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */ 00351 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */ 00352 /** 00353 * @} 00354 */ 00355 00356 /** @defgroup RCC_PLLSAI1_Clock_Output PLLSAI1 Clock Output 00357 * @{ 00358 */ 00359 #define RCC_PLLSAI1_SAI1CLK RCC_PLLSAI1CFGR_PLLSAI1PEN /*!< PLLSAI1CLK selection from PLLSAI1 */ 00360 #define RCC_PLLSAI1_48M2CLK RCC_PLLSAI1CFGR_PLLSAI1QEN /*!< PLL48M2CLK selection from PLLSAI1 */ 00361 #define RCC_PLLSAI1_ADC1CLK RCC_PLLSAI1CFGR_PLLSAI1REN /*!< PLLADC1CLK selection from PLLSAI1 */ 00362 /** 00363 * @} 00364 */ 00365 00366 #if defined(RCC_PLLSAI2_SUPPORT) 00367 00368 /** @defgroup RCC_PLLSAI2_Clock_Output PLLSAI2 Clock Output 00369 * @{ 00370 */ 00371 #define RCC_PLLSAI2_SAI2CLK RCC_PLLSAI2CFGR_PLLSAI2PEN /*!< PLLSAI2CLK selection from PLLSAI2 */ 00372 #define RCC_PLLSAI2_ADC2CLK RCC_PLLSAI2CFGR_PLLSAI2REN /*!< PLLADC2CLK selection from PLLSAI2 */ 00373 /** 00374 * @} 00375 */ 00376 00377 #endif /* RCC_PLLSAI2_SUPPORT */ 00378 00379 /** @defgroup RCC_MSI_Clock_Range MSI Clock Range 00380 * @{ 00381 */ 00382 #define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */ 00383 #define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */ 00384 #define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */ 00385 #define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */ 00386 #define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */ 00387 #define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */ 00388 #define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */ 00389 #define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */ 00390 #define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */ 00391 #define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */ 00392 #define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */ 00393 #define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */ 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup RCC_System_Clock_Type System Clock Type 00399 * @{ 00400 */ 00401 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) /*!< SYSCLK to configure */ 00402 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) /*!< HCLK to configure */ 00403 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) /*!< PCLK1 to configure */ 00404 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) /*!< PCLK2 to configure */ 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup RCC_System_Clock_Source System Clock Source 00410 * @{ 00411 */ 00412 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ 00413 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00414 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00415 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00416 /** 00417 * @} 00418 */ 00419 00420 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status 00421 * @{ 00422 */ 00423 #define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ 00424 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00425 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00426 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00427 /** 00428 * @} 00429 */ 00430 00431 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source 00432 * @{ 00433 */ 00434 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00435 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00436 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00437 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00438 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00439 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00440 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00441 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00442 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00443 /** 00444 * @} 00445 */ 00446 00447 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source 00448 * @{ 00449 */ 00450 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00451 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00452 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00453 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00454 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00455 /** 00456 * @} 00457 */ 00458 00459 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source 00460 * @{ 00461 */ 00462 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) /*!< No clock used as RTC clock */ 00463 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00464 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00465 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ 00466 /** 00467 * @} 00468 */ 00469 00470 /** @defgroup RCC_MCO_Index MCO Index 00471 * @{ 00472 */ 00473 #define RCC_MCO1 ((uint32_t)0x00000000U) 00474 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source 00480 * @{ 00481 */ 00482 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)0x00000000U) /*!< MCO1 output disabled, no clock on MCO1 */ 00483 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ 00484 #define RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */ 00485 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ 00486 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ 00487 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */ 00488 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ 00489 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ 00490 #if defined(RCC_HSI48_SUPPORT) 00491 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source (STM32L43x/STM32L44x devices) */ 00492 #endif /* RCC_HSI48_SUPPORT */ 00493 /** 00494 * @} 00495 */ 00496 00497 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler 00498 * @{ 00499 */ 00500 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */ 00501 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */ 00502 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */ 00503 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */ 00504 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */ 00505 /** 00506 * @} 00507 */ 00508 00509 /** @defgroup RCC_Interrupt Interrupts 00510 * @{ 00511 */ 00512 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00513 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ 00514 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ 00515 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ 00516 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ 00517 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00518 #define RCC_IT_PLLSAI1RDY RCC_CIFR_PLLSAI1RDYF /*!< PLLSAI1 Ready Interrupt flag */ 00519 #if defined(RCC_PLLSAI2_SUPPORT) 00520 #define RCC_IT_PLLSAI2RDY RCC_CIFR_PLLSAI2RDYF /*!< PLLSAI2 Ready Interrupt flag */ 00521 #endif /* RCC_PLLSAI2_SUPPORT */ 00522 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ 00523 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ 00524 #if defined(RCC_HSI48_SUPPORT) 00525 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ 00526 #endif /* RCC_HSI48_SUPPORT */ 00527 /** 00528 * @} 00529 */ 00530 00531 /** @defgroup RCC_Flag Flags 00532 * Elements values convention: XXXYYYYYb 00533 * - YYYYY : Flag position in the register 00534 * - XXX : Register index 00535 * - 001: CR register 00536 * - 010: BDCR register 00537 * - 011: CSR register 00538 * - 100: CRRCR register 00539 * @{ 00540 */ 00541 /* Flags in the CR register */ 00542 #define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI Ready flag */ 00543 #define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< HSI Ready flag */ 00544 #define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< HSE Ready flag */ 00545 #define RCC_FLAG_PLLRDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL Ready flag */ 00546 #define RCC_FLAG_PLLSAI1RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI1RDY))) /*!< PLLSAI1 Ready flag */ 00547 #if defined(RCC_PLLSAI2_SUPPORT) 00548 #define RCC_FLAG_PLLSAI2RDY ((uint32_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLSAI2RDY))) /*!< PLLSAI2 Ready flag */ 00549 #endif /* RCC_PLLSAI2_SUPPORT */ 00550 00551 /* Flags in the BDCR register */ 00552 #define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSERDY))) /*!< LSE Ready flag */ 00553 #define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | POSITION_VAL(RCC_BDCR_LSECSSD))) /*!< LSE Clock Security System Interrupt flag */ 00554 00555 /* Flags in the CSR register */ 00556 #define RCC_FLAG_LSIRDY ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY))) /*!< LSI Ready flag */ 00557 #define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_RMVF))) /*!< Remove reset flag */ 00558 #define RCC_FLAG_FWRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_FWRSTF))) /*!< Firewall reset flag */ 00559 #define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF))) /*!< Option Byte Loader reset flag */ 00560 #define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF))) /*!< PIN reset flag */ 00561 #define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_BORRSTF))) /*!< BOR reset flag */ 00562 #define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF))) /*!< Software Reset flag */ 00563 #define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */ 00564 #define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */ 00565 #define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */ 00566 00567 #if defined(RCC_HSI48_SUPPORT) 00568 /* Flags in the CRRCR register */ 00569 #define RCC_FLAG_HSI48RDY ((uint32_t)((CRRCR_REG_INDEX << 5U) | POSITION_VAL(RCC_CRRCR_HSI48RDY))) /*!< HSI48 Ready flag */ 00570 #endif /* RCC_HSI48_SUPPORT */ 00571 /** 00572 * @} 00573 */ 00574 00575 /** @defgroup RCC_LSEDrive_Config LSE Drive Config 00576 * @{ 00577 */ 00578 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< LSE low drive capability */ 00579 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ 00580 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ 00581 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock 00587 * @{ 00588 */ 00589 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00000000U) /*!< MSI selection after wake-up from STOP */ 00590 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ 00591 /** 00592 * @} 00593 */ 00594 00595 /** 00596 * @} 00597 */ 00598 00599 /* Exported macros -----------------------------------------------------------*/ 00600 00601 /** @defgroup RCC_Exported_Macros RCC Exported Macros 00602 * @{ 00603 */ 00604 00605 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable 00606 * @brief Enable or disable the AHB1 peripheral clock. 00607 * @note After reset, the peripheral clock (used for registers read/write access) 00608 * is disabled and the application software has to enable this clock before 00609 * using it. 00610 * @{ 00611 */ 00612 00613 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ 00614 __IO uint32_t tmpreg; \ 00615 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 00616 /* Delay after an RCC peripheral clock enabling */ \ 00617 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ 00618 UNUSED(tmpreg); \ 00619 } while(0) 00620 00621 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ 00622 __IO uint32_t tmpreg; \ 00623 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 00624 /* Delay after an RCC peripheral clock enabling */ \ 00625 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ 00626 UNUSED(tmpreg); \ 00627 } while(0) 00628 00629 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ 00630 __IO uint32_t tmpreg; \ 00631 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 00632 /* Delay after an RCC peripheral clock enabling */ \ 00633 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ 00634 UNUSED(tmpreg); \ 00635 } while(0) 00636 00637 #define __HAL_RCC_CRC_CLK_ENABLE() do { \ 00638 __IO uint32_t tmpreg; \ 00639 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 00640 /* Delay after an RCC peripheral clock enabling */ \ 00641 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ 00642 UNUSED(tmpreg); \ 00643 } while(0) 00644 00645 #define __HAL_RCC_TSC_CLK_ENABLE() do { \ 00646 __IO uint32_t tmpreg; \ 00647 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 00648 /* Delay after an RCC peripheral clock enabling */ \ 00649 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ 00650 UNUSED(tmpreg); \ 00651 } while(0) 00652 00653 00654 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) 00655 00656 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) 00657 00658 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) 00659 00660 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) 00661 00662 #define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) 00663 00664 /** 00665 * @} 00666 */ 00667 00668 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 00669 * @brief Enable or disable the AHB2 peripheral clock. 00670 * @note After reset, the peripheral clock (used for registers read/write access) 00671 * is disabled and the application software has to enable this clock before 00672 * using it. 00673 * @{ 00674 */ 00675 00676 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ 00677 __IO uint32_t tmpreg; \ 00678 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 00679 /* Delay after an RCC peripheral clock enabling */ \ 00680 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ 00681 UNUSED(tmpreg); \ 00682 } while(0) 00683 00684 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ 00685 __IO uint32_t tmpreg; \ 00686 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 00687 /* Delay after an RCC peripheral clock enabling */ \ 00688 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ 00689 UNUSED(tmpreg); \ 00690 } while(0) 00691 00692 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ 00693 __IO uint32_t tmpreg; \ 00694 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 00695 /* Delay after an RCC peripheral clock enabling */ \ 00696 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ 00697 UNUSED(tmpreg); \ 00698 } while(0) 00699 00700 #if defined(GPIOD) 00701 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ 00702 __IO uint32_t tmpreg; \ 00703 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 00704 /* Delay after an RCC peripheral clock enabling */ \ 00705 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ 00706 UNUSED(tmpreg); \ 00707 } while(0) 00708 #endif /* GPIOD */ 00709 00710 #if defined(GPIOE) 00711 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ 00712 __IO uint32_t tmpreg; \ 00713 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 00714 /* Delay after an RCC peripheral clock enabling */ \ 00715 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ 00716 UNUSED(tmpreg); \ 00717 } while(0) 00718 #endif /* GPIOE */ 00719 00720 #if defined(GPIOF) 00721 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ 00722 __IO uint32_t tmpreg; \ 00723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 00724 /* Delay after an RCC peripheral clock enabling */ \ 00725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ 00726 UNUSED(tmpreg); \ 00727 } while(0) 00728 #endif /* GPIOF */ 00729 00730 #if defined(GPIOG) 00731 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ 00732 __IO uint32_t tmpreg; \ 00733 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 00734 /* Delay after an RCC peripheral clock enabling */ \ 00735 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ 00736 UNUSED(tmpreg); \ 00737 } while(0) 00738 #endif /* GPIOG */ 00739 00740 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ 00741 __IO uint32_t tmpreg; \ 00742 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 00743 /* Delay after an RCC peripheral clock enabling */ \ 00744 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ 00745 UNUSED(tmpreg); \ 00746 } while(0) 00747 00748 #if defined(USB_OTG_FS) 00749 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ 00750 __IO uint32_t tmpreg; \ 00751 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 00752 /* Delay after an RCC peripheral clock enabling */ \ 00753 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ 00754 UNUSED(tmpreg); \ 00755 } while(0) 00756 #endif /* USB_OTG_FS */ 00757 00758 #define __HAL_RCC_ADC_CLK_ENABLE() do { \ 00759 __IO uint32_t tmpreg; \ 00760 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 00761 /* Delay after an RCC peripheral clock enabling */ \ 00762 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ 00763 UNUSED(tmpreg); \ 00764 } while(0) 00765 00766 #if defined(AES) 00767 #define __HAL_RCC_AES_CLK_ENABLE() do { \ 00768 __IO uint32_t tmpreg; \ 00769 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 00770 /* Delay after an RCC peripheral clock enabling */ \ 00771 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ 00772 UNUSED(tmpreg); \ 00773 } while(0) 00774 #endif /* AES */ 00775 00776 #define __HAL_RCC_RNG_CLK_ENABLE() do { \ 00777 __IO uint32_t tmpreg; \ 00778 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 00779 /* Delay after an RCC peripheral clock enabling */ \ 00780 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ 00781 UNUSED(tmpreg); \ 00782 } while(0) 00783 00784 00785 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) 00786 00787 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) 00788 00789 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) 00790 00791 #if defined(GPIOD) 00792 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) 00793 #endif /* GPIOD */ 00794 00795 #if defined(GPIOE) 00796 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) 00797 #endif /* GPIOE */ 00798 00799 #if defined(GPIOF) 00800 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) 00801 #endif /* GPIOF */ 00802 00803 #if defined(GPIOG) 00804 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) 00805 #endif /* GPIOG */ 00806 00807 #define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) 00808 00809 #if defined(USB_OTG_FS) 00810 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); 00811 #endif /* USB_OTG_FS */ 00812 00813 #define __HAL_RCC_ADC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) 00814 00815 #if defined(AES) 00816 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); 00817 #endif /* AES */ 00818 00819 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) 00820 00821 /** 00822 * @} 00823 */ 00824 00825 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable 00826 * @brief Enable or disable the AHB3 peripheral clock. 00827 * @note After reset, the peripheral clock (used for registers read/write access) 00828 * is disabled and the application software has to enable this clock before 00829 * using it. 00830 * @{ 00831 */ 00832 00833 #if defined(FMC_BANK1) 00834 #define __HAL_RCC_FMC_CLK_ENABLE() do { \ 00835 __IO uint32_t tmpreg; \ 00836 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 00837 /* Delay after an RCC peripheral clock enabling */ \ 00838 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ 00839 UNUSED(tmpreg); \ 00840 } while(0) 00841 #endif /* FMC_BANK1 */ 00842 00843 #if defined(QUADSPI) 00844 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \ 00845 __IO uint32_t tmpreg; \ 00846 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 00847 /* Delay after an RCC peripheral clock enabling */ \ 00848 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \ 00849 UNUSED(tmpreg); \ 00850 } while(0) 00851 #endif /* QUADSPI */ 00852 00853 00854 #if defined(FMC_BANK1) 00855 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) 00856 #endif /* FMC_BANK1 */ 00857 00858 #if defined(QUADSPI) 00859 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) 00860 #endif /* QUADSPI */ 00861 00862 /** 00863 * @} 00864 */ 00865 00866 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable 00867 * @brief Enable or disable the APB1 peripheral clock. 00868 * @note After reset, the peripheral clock (used for registers read/write access) 00869 * is disabled and the application software has to enable this clock before 00870 * using it. 00871 * @{ 00872 */ 00873 00874 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ 00875 __IO uint32_t tmpreg; \ 00876 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 00877 /* Delay after an RCC peripheral clock enabling */ \ 00878 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ 00879 UNUSED(tmpreg); \ 00880 } while(0) 00881 00882 #if defined(TIM3) 00883 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ 00884 __IO uint32_t tmpreg; \ 00885 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 00886 /* Delay after an RCC peripheral clock enabling */ \ 00887 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ 00888 UNUSED(tmpreg); \ 00889 } while(0) 00890 #endif /* TIM3 */ 00891 00892 #if defined(TIM4) 00893 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ 00894 __IO uint32_t tmpreg; \ 00895 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 00896 /* Delay after an RCC peripheral clock enabling */ \ 00897 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ 00898 UNUSED(tmpreg); \ 00899 } while(0) 00900 #endif /* TIM4 */ 00901 00902 #if defined(TIM5) 00903 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ 00904 __IO uint32_t tmpreg; \ 00905 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 00906 /* Delay after an RCC peripheral clock enabling */ \ 00907 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ 00908 UNUSED(tmpreg); \ 00909 } while(0) 00910 #endif /* TIM5 */ 00911 00912 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ 00913 __IO uint32_t tmpreg; \ 00914 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 00915 /* Delay after an RCC peripheral clock enabling */ \ 00916 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ 00917 UNUSED(tmpreg); \ 00918 } while(0) 00919 00920 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ 00921 __IO uint32_t tmpreg; \ 00922 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 00923 /* Delay after an RCC peripheral clock enabling */ \ 00924 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ 00925 UNUSED(tmpreg); \ 00926 } while(0) 00927 00928 #if defined(LCD) 00929 #define __HAL_RCC_LCD_CLK_ENABLE() do { \ 00930 __IO uint32_t tmpreg; \ 00931 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 00932 /* Delay after an RCC peripheral clock enabling */ \ 00933 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ 00934 UNUSED(tmpreg); \ 00935 } while(0) 00936 #endif /* LCD */ 00937 00938 #if defined(RCC_APB1ENR1_RTCAPBEN) 00939 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ 00940 __IO uint32_t tmpreg; \ 00941 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 00942 /* Delay after an RCC peripheral clock enabling */ \ 00943 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ 00944 UNUSED(tmpreg); \ 00945 } while(0) 00946 #endif /* RCC_APB1ENR1_RTCAPBEN */ 00947 00948 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ 00949 __IO uint32_t tmpreg; \ 00950 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 00951 /* Delay after an RCC peripheral clock enabling */ \ 00952 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ 00953 UNUSED(tmpreg); \ 00954 } while(0) 00955 00956 #if defined(SPI2) 00957 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ 00958 __IO uint32_t tmpreg; \ 00959 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 00960 /* Delay after an RCC peripheral clock enabling */ \ 00961 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ 00962 UNUSED(tmpreg); \ 00963 } while(0) 00964 #endif /* SPI2 */ 00965 00966 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ 00967 __IO uint32_t tmpreg; \ 00968 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 00969 /* Delay after an RCC peripheral clock enabling */ \ 00970 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ 00971 UNUSED(tmpreg); \ 00972 } while(0) 00973 00974 #define __HAL_RCC_USART2_CLK_ENABLE() do { \ 00975 __IO uint32_t tmpreg; \ 00976 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 00977 /* Delay after an RCC peripheral clock enabling */ \ 00978 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ 00979 UNUSED(tmpreg); \ 00980 } while(0) 00981 00982 #if defined(USART3) 00983 #define __HAL_RCC_USART3_CLK_ENABLE() do { \ 00984 __IO uint32_t tmpreg; \ 00985 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 00986 /* Delay after an RCC peripheral clock enabling */ \ 00987 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ 00988 UNUSED(tmpreg); \ 00989 } while(0) 00990 #endif /* USART3 */ 00991 00992 #if defined(UART4) 00993 #define __HAL_RCC_UART4_CLK_ENABLE() do { \ 00994 __IO uint32_t tmpreg; \ 00995 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 00996 /* Delay after an RCC peripheral clock enabling */ \ 00997 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ 00998 UNUSED(tmpreg); \ 00999 } while(0) 01000 #endif /* UART4 */ 01001 01002 #if defined(UART5) 01003 #define __HAL_RCC_UART5_CLK_ENABLE() do { \ 01004 __IO uint32_t tmpreg; \ 01005 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 01006 /* Delay after an RCC peripheral clock enabling */ \ 01007 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ 01008 UNUSED(tmpreg); \ 01009 } while(0) 01010 #endif /* UART5 */ 01011 01012 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ 01013 __IO uint32_t tmpreg; \ 01014 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 01015 /* Delay after an RCC peripheral clock enabling */ \ 01016 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ 01017 UNUSED(tmpreg); \ 01018 } while(0) 01019 01020 #if defined(I2C2) 01021 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ 01022 __IO uint32_t tmpreg; \ 01023 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 01024 /* Delay after an RCC peripheral clock enabling */ \ 01025 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ 01026 UNUSED(tmpreg); \ 01027 } while(0) 01028 #endif /* I2C2 */ 01029 01030 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ 01031 __IO uint32_t tmpreg; \ 01032 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 01033 /* Delay after an RCC peripheral clock enabling */ \ 01034 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ 01035 UNUSED(tmpreg); \ 01036 } while(0) 01037 01038 #if defined(CRS) 01039 #define __HAL_RCC_CRS_CLK_ENABLE() do { \ 01040 __IO uint32_t tmpreg; \ 01041 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 01042 /* Delay after an RCC peripheral clock enabling */ \ 01043 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ 01044 UNUSED(tmpreg); \ 01045 } while(0) 01046 #endif /* CRS */ 01047 01048 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \ 01049 __IO uint32_t tmpreg; \ 01050 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 01051 /* Delay after an RCC peripheral clock enabling */ \ 01052 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN); \ 01053 UNUSED(tmpreg); \ 01054 } while(0) 01055 01056 #if defined(USB) 01057 #define __HAL_RCC_USB_CLK_ENABLE() do { \ 01058 __IO uint32_t tmpreg; \ 01059 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 01060 /* Delay after an RCC peripheral clock enabling */ \ 01061 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); \ 01062 UNUSED(tmpreg); \ 01063 } while(0) 01064 #endif /* USB */ 01065 01066 #define __HAL_RCC_PWR_CLK_ENABLE() do { \ 01067 __IO uint32_t tmpreg; \ 01068 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 01069 /* Delay after an RCC peripheral clock enabling */ \ 01070 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ 01071 UNUSED(tmpreg); \ 01072 } while(0) 01073 01074 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ 01075 __IO uint32_t tmpreg; \ 01076 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 01077 /* Delay after an RCC peripheral clock enabling */ \ 01078 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ 01079 UNUSED(tmpreg); \ 01080 } while(0) 01081 01082 #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ 01083 __IO uint32_t tmpreg; \ 01084 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 01085 /* Delay after an RCC peripheral clock enabling */ \ 01086 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ 01087 UNUSED(tmpreg); \ 01088 } while(0) 01089 01090 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ 01091 __IO uint32_t tmpreg; \ 01092 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 01093 /* Delay after an RCC peripheral clock enabling */ \ 01094 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ 01095 UNUSED(tmpreg); \ 01096 } while(0) 01097 01098 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ 01099 __IO uint32_t tmpreg; \ 01100 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 01101 /* Delay after an RCC peripheral clock enabling */ \ 01102 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ 01103 UNUSED(tmpreg); \ 01104 } while(0) 01105 01106 #define __HAL_RCC_SWPMI1_CLK_ENABLE() do { \ 01107 __IO uint32_t tmpreg; \ 01108 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 01109 /* Delay after an RCC peripheral clock enabling */ \ 01110 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN); \ 01111 UNUSED(tmpreg); \ 01112 } while(0) 01113 01114 #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ 01115 __IO uint32_t tmpreg; \ 01116 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 01117 /* Delay after an RCC peripheral clock enabling */ \ 01118 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ 01119 UNUSED(tmpreg); \ 01120 } while(0) 01121 01122 01123 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) 01124 01125 #if defined(TIM3) 01126 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) 01127 #endif /* TIM3 */ 01128 01129 #if defined(TIM4) 01130 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) 01131 #endif /* TIM4 */ 01132 01133 #if defined(TIM5) 01134 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) 01135 #endif /* TIM5 */ 01136 01137 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) 01138 01139 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) 01140 01141 #if defined(LCD) 01142 #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); 01143 #endif /* LCD */ 01144 01145 #if defined(RCC_APB1ENR1_RTCAPBEN) 01146 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); 01147 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01148 01149 #if defined(SPI2) 01150 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) 01151 #endif /* SPI2 */ 01152 01153 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) 01154 01155 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) 01156 01157 #if defined(USART3) 01158 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) 01159 #endif /* USART3 */ 01160 01161 #if defined(UART4) 01162 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) 01163 #endif /* UART4 */ 01164 01165 #if defined(UART5) 01166 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) 01167 #endif /* UART5 */ 01168 01169 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) 01170 01171 #if defined(I2C2) 01172 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) 01173 #endif /* I2C2 */ 01174 01175 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) 01176 01177 #if defined(CRS) 01178 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); 01179 #endif /* CRS */ 01180 01181 #define __HAL_RCC_CAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) 01182 01183 #if defined(USB) 01184 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN); 01185 #endif /* USB */ 01186 01187 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) 01188 01189 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) 01190 01191 #define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) 01192 01193 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) 01194 01195 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) 01196 01197 #define __HAL_RCC_SWPMI1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) 01198 01199 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) 01200 01201 /** 01202 * @} 01203 */ 01204 01205 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable 01206 * @brief Enable or disable the APB2 peripheral clock. 01207 * @note After reset, the peripheral clock (used for registers read/write access) 01208 * is disabled and the application software has to enable this clock before 01209 * using it. 01210 * @{ 01211 */ 01212 01213 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ 01214 __IO uint32_t tmpreg; \ 01215 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 01216 /* Delay after an RCC peripheral clock enabling */ \ 01217 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ 01218 UNUSED(tmpreg); \ 01219 } while(0) 01220 01221 #define __HAL_RCC_FIREWALL_CLK_ENABLE() do { \ 01222 __IO uint32_t tmpreg; \ 01223 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 01224 /* Delay after an RCC peripheral clock enabling */ \ 01225 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN); \ 01226 UNUSED(tmpreg); \ 01227 } while(0) 01228 01229 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01230 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ 01231 __IO uint32_t tmpreg; \ 01232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 01233 /* Delay after an RCC peripheral clock enabling */ \ 01234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN); \ 01235 UNUSED(tmpreg); \ 01236 } while(0) 01237 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01238 01239 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ 01240 __IO uint32_t tmpreg; \ 01241 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 01242 /* Delay after an RCC peripheral clock enabling */ \ 01243 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ 01244 UNUSED(tmpreg); \ 01245 } while(0) 01246 01247 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ 01248 __IO uint32_t tmpreg; \ 01249 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 01250 /* Delay after an RCC peripheral clock enabling */ \ 01251 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ 01252 UNUSED(tmpreg); \ 01253 } while(0) 01254 01255 #if defined(TIM8) 01256 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ 01257 __IO uint32_t tmpreg; \ 01258 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 01259 /* Delay after an RCC peripheral clock enabling */ \ 01260 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ 01261 UNUSED(tmpreg); \ 01262 } while(0) 01263 #endif /* TIM8 */ 01264 01265 #define __HAL_RCC_USART1_CLK_ENABLE() do { \ 01266 __IO uint32_t tmpreg; \ 01267 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 01268 /* Delay after an RCC peripheral clock enabling */ \ 01269 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ 01270 UNUSED(tmpreg); \ 01271 } while(0) 01272 01273 01274 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ 01275 __IO uint32_t tmpreg; \ 01276 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 01277 /* Delay after an RCC peripheral clock enabling */ \ 01278 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ 01279 UNUSED(tmpreg); \ 01280 } while(0) 01281 01282 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ 01283 __IO uint32_t tmpreg; \ 01284 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 01285 /* Delay after an RCC peripheral clock enabling */ \ 01286 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ 01287 UNUSED(tmpreg); \ 01288 } while(0) 01289 01290 #if defined(TIM17) 01291 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ 01292 __IO uint32_t tmpreg; \ 01293 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 01294 /* Delay after an RCC peripheral clock enabling */ \ 01295 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ 01296 UNUSED(tmpreg); \ 01297 } while(0) 01298 #endif /* TIM17 */ 01299 01300 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ 01301 __IO uint32_t tmpreg; \ 01302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 01303 /* Delay after an RCC peripheral clock enabling */ \ 01304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ 01305 UNUSED(tmpreg); \ 01306 } while(0) 01307 01308 #if defined(SAI2) 01309 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ 01310 __IO uint32_t tmpreg; \ 01311 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 01312 /* Delay after an RCC peripheral clock enabling */ \ 01313 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ 01314 UNUSED(tmpreg); \ 01315 } while(0) 01316 #endif /* SAI2 */ 01317 01318 #if defined(DFSDM1_Filter0) 01319 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ 01320 __IO uint32_t tmpreg; \ 01321 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 01322 /* Delay after an RCC peripheral clock enabling */ \ 01323 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ 01324 UNUSED(tmpreg); \ 01325 } while(0) 01326 #endif /* DFSDM1_Filter0 */ 01327 01328 01329 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) 01330 01331 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01332 #define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) 01333 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01334 01335 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) 01336 01337 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) 01338 01339 #if defined(TIM8) 01340 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) 01341 #endif /* TIM8 */ 01342 01343 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) 01344 01345 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) 01346 01347 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) 01348 01349 #if defined(TIM17) 01350 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) 01351 #endif /* TIM17 */ 01352 01353 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) 01354 01355 #if defined(SAI2) 01356 #define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) 01357 #endif /* SAI2 */ 01358 01359 #if defined(DFSDM1_Filter0) 01360 #define __HAL_RCC_DFSDM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) 01361 #endif /* DFSDM1_Filter0 */ 01362 01363 /** 01364 * @} 01365 */ 01366 01367 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status 01368 * @brief Check whether the AHB1 peripheral clock is enabled or not. 01369 * @note After reset, the peripheral clock (used for registers read/write access) 01370 * is disabled and the application software has to enable this clock before 01371 * using it. 01372 * @{ 01373 */ 01374 01375 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != RESET) 01376 01377 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != RESET) 01378 01379 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != RESET) 01380 01381 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != RESET) 01382 01383 #define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != RESET) 01384 01385 01386 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == RESET) 01387 01388 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == RESET) 01389 01390 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == RESET) 01391 01392 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == RESET) 01393 01394 #define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == RESET) 01395 01396 /** 01397 * @} 01398 */ 01399 01400 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status 01401 * @brief Check whether the AHB2 peripheral clock is enabled or not. 01402 * @note After reset, the peripheral clock (used for registers read/write access) 01403 * is disabled and the application software has to enable this clock before 01404 * using it. 01405 * @{ 01406 */ 01407 01408 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != RESET) 01409 01410 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) 01411 01412 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != RESET) 01413 01414 #if defined(GPIOD) 01415 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != RESET) 01416 #endif /* GPIOD */ 01417 01418 #if defined(GPIOE) 01419 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != RESET) 01420 #endif /* GPIOE */ 01421 01422 #if defined(GPIOF) 01423 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != RESET) 01424 #endif /* GPIOF */ 01425 01426 #if defined(GPIOG) 01427 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != RESET) 01428 #endif /* GPIOG */ 01429 01430 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) != RESET) 01431 01432 #if defined(USB_OTG_FS) 01433 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) 01434 #endif /* USB_OTG_FS */ 01435 01436 #define __HAL_RCC_ADC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) != RESET) 01437 01438 #if defined(AES) 01439 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) 01440 #endif /* AES */ 01441 01442 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != RESET) 01443 01444 01445 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == RESET) 01446 01447 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == RESET) 01448 01449 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == RESET) 01450 01451 #if defined(GPIOD) 01452 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == RESET) 01453 #endif /* GPIOD */ 01454 01455 #if defined(GPIOE) 01456 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == RESET) 01457 #endif /* GPIOE */ 01458 01459 #if defined(GPIOF) 01460 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == RESET) 01461 #endif /* GPIOF */ 01462 01463 #if defined(GPIOG) 01464 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == RESET) 01465 #endif /* GPIOG */ 01466 01467 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN) == RESET) 01468 01469 #if defined(USB_OTG_FS) 01470 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) 01471 #endif /* USB_OTG_FS */ 01472 01473 #define __HAL_RCC_ADC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN) == RESET) 01474 01475 #if defined(AES) 01476 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) 01477 #endif /* AES */ 01478 01479 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == RESET) 01480 01481 /** 01482 * @} 01483 */ 01484 01485 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status 01486 * @brief Check whether the AHB3 peripheral clock is enabled or not. 01487 * @note After reset, the peripheral clock (used for registers read/write access) 01488 * is disabled and the application software has to enable this clock before 01489 * using it. 01490 * @{ 01491 */ 01492 01493 #if defined(FMC_BANK1) 01494 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != RESET) 01495 #endif /* FMC_BANK1 */ 01496 01497 #if defined(QUADSPI) 01498 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != RESET) 01499 #endif /* QUADSPI */ 01500 01501 #if defined(FMC_BANK1) 01502 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == RESET) 01503 #endif /* FMC_BANK1 */ 01504 01505 #if defined(QUADSPI) 01506 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == RESET) 01507 #endif /* QUADSPI */ 01508 01509 /** 01510 * @} 01511 */ 01512 01513 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status 01514 * @brief Check whether the APB1 peripheral clock is enabled or not. 01515 * @note After reset, the peripheral clock (used for registers read/write access) 01516 * is disabled and the application software has to enable this clock before 01517 * using it. 01518 * @{ 01519 */ 01520 01521 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != RESET) 01522 01523 #if defined(TIM3) 01524 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != RESET) 01525 #endif /* TIM3 */ 01526 01527 #if defined(TIM4) 01528 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != RESET) 01529 #endif /* TIM4 */ 01530 01531 #if defined(TIM5) 01532 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != RESET) 01533 #endif /* TIM5 */ 01534 01535 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != RESET) 01536 01537 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != RESET) 01538 01539 #if defined(LCD) 01540 #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) 01541 #endif /* LCD */ 01542 01543 #if defined(RCC_APB1ENR1_RTCAPBEN) 01544 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != RESET) 01545 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01546 01547 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != RESET) 01548 01549 #if defined(SPI2) 01550 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != RESET) 01551 #endif /* SPI2 */ 01552 01553 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != RESET) 01554 01555 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != RESET) 01556 01557 #if defined(USART3) 01558 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != RESET) 01559 #endif /* USART3 */ 01560 01561 #if defined(UART4) 01562 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != RESET) 01563 #endif /* UART4 */ 01564 01565 #if defined(UART5) 01566 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != RESET) 01567 #endif /* UART5 */ 01568 01569 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != RESET) 01570 01571 #if defined(I2C2) 01572 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != RESET) 01573 #endif /* I2C2 */ 01574 01575 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != RESET) 01576 01577 #if defined(CRS) 01578 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != RESET) 01579 #endif /* CRS */ 01580 01581 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != RESET) 01582 01583 #if defined(USB) 01584 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != RESET) 01585 #endif /* USB */ 01586 01587 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != RESET) 01588 01589 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) != RESET) 01590 01591 #define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) != RESET) 01592 01593 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != RESET) 01594 01595 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != RESET) 01596 01597 #define __HAL_RCC_SWPMI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) != RESET) 01598 01599 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != RESET) 01600 01601 01602 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == RESET) 01603 01604 #if defined(TIM3) 01605 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == RESET) 01606 #endif /* TIM3 */ 01607 01608 #if defined(TIM4) 01609 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == RESET) 01610 #endif /* TIM4 */ 01611 01612 #if defined(TIM5) 01613 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == RESET) 01614 #endif /* TIM5 */ 01615 01616 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == RESET) 01617 01618 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == RESET) 01619 01620 #if defined(LCD) 01621 #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) 01622 #endif /* LCD */ 01623 01624 #if defined(RCC_APB1ENR1_RTCAPBEN) 01625 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == RESET) 01626 #endif /* RCC_APB1ENR1_RTCAPBEN */ 01627 01628 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == RESET) 01629 01630 #if defined(SPI2) 01631 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == RESET) 01632 #endif /* SPI2 */ 01633 01634 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == RESET) 01635 01636 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == RESET) 01637 01638 #if defined(USART3) 01639 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == RESET) 01640 #endif /* USART3 */ 01641 01642 #if defined(UART4) 01643 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == RESET) 01644 #endif /* UART4 */ 01645 01646 #if defined(UART5) 01647 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == RESET) 01648 #endif /* UART5 */ 01649 01650 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == RESET) 01651 01652 #if defined(I2C2) 01653 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == RESET) 01654 #endif /* I2C2 */ 01655 01656 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == RESET) 01657 01658 #if defined(CRS) 01659 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == RESET) 01660 #endif /* CRS */ 01661 01662 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == RESET) 01663 01664 #if defined(USB) 01665 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == RESET) 01666 #endif /* USB */ 01667 01668 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == RESET) 01669 01670 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN) == RESET) 01671 01672 #define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN) == RESET) 01673 01674 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == RESET) 01675 01676 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == RESET) 01677 01678 #define __HAL_RCC_SWPMI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_SWPMI1EN) == RESET) 01679 01680 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == RESET) 01681 01682 /** 01683 * @} 01684 */ 01685 01686 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status 01687 * @brief Check whether the APB2 peripheral clock is enabled or not. 01688 * @note After reset, the peripheral clock (used for registers read/write access) 01689 * is disabled and the application software has to enable this clock before 01690 * using it. 01691 * @{ 01692 */ 01693 01694 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET) 01695 01696 #define __HAL_RCC_FIREWALL_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_FWEN) != RESET) 01697 01698 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01699 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) != RESET) 01700 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01701 01702 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != RESET) 01703 01704 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != RESET) 01705 01706 #if defined(TIM8) 01707 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != RESET) 01708 #endif /* TIM8 */ 01709 01710 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != RESET) 01711 01712 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != RESET) 01713 01714 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != RESET) 01715 01716 #if defined(TIM17) 01717 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != RESET) 01718 #endif /* TIM17 */ 01719 01720 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != RESET) 01721 01722 #if defined(SAI2) 01723 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != RESET) 01724 #endif /* SAI2 */ 01725 01726 #if defined(DFSDM1_Filter0) 01727 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) != RESET) 01728 #endif /* DFSDM1_Filter0 */ 01729 01730 01731 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == RESET) 01732 01733 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 01734 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN) == RESET) 01735 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 01736 01737 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == RESET) 01738 01739 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == RESET) 01740 01741 #if defined(TIM8) 01742 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == RESET) 01743 #endif /* TIM8 */ 01744 01745 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == RESET) 01746 01747 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == RESET) 01748 01749 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == RESET) 01750 01751 #if defined(TIM17) 01752 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == RESET) 01753 #endif /* TIM17 */ 01754 01755 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == RESET) 01756 01757 #if defined(SAI2) 01758 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == RESET) 01759 #endif /* SAI2 */ 01760 01761 #if defined(DFSDM1_Filter0) 01762 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN) == RESET) 01763 #endif /* DFSDM1_Filter0 */ 01764 01765 /** 01766 * @} 01767 */ 01768 01769 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset 01770 * @brief Force or release AHB1 peripheral reset. 01771 * @{ 01772 */ 01773 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU) 01774 01775 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 01776 01777 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 01778 01779 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 01780 01781 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 01782 01783 #define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 01784 01785 01786 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) 01787 01788 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST) 01789 01790 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST) 01791 01792 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST) 01793 01794 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) 01795 01796 #define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) 01797 01798 /** 01799 * @} 01800 */ 01801 01802 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset 01803 * @brief Force or release AHB2 peripheral reset. 01804 * @{ 01805 */ 01806 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU) 01807 01808 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 01809 01810 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 01811 01812 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 01813 01814 #if defined(GPIOD) 01815 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 01816 #endif /* GPIOD */ 01817 01818 #if defined(GPIOE) 01819 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 01820 #endif /* GPIOE */ 01821 01822 #if defined(GPIOF) 01823 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 01824 #endif /* GPIOF */ 01825 01826 #if defined(GPIOG) 01827 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 01828 #endif /* GPIOG */ 01829 01830 #define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 01831 01832 #if defined(USB_OTG_FS) 01833 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 01834 #endif /* USB_OTG_FS */ 01835 01836 #define __HAL_RCC_ADC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 01837 01838 #if defined(AES) 01839 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 01840 #endif /* AES */ 01841 01842 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 01843 01844 01845 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U) 01846 01847 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST) 01848 01849 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST) 01850 01851 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST) 01852 01853 #if defined(GPIOD) 01854 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST) 01855 #endif /* GPIOD */ 01856 01857 #if defined(GPIOE) 01858 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST) 01859 #endif /* GPIOE */ 01860 01861 #if defined(GPIOF) 01862 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST) 01863 #endif /* GPIOF */ 01864 01865 #if defined(GPIOG) 01866 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST) 01867 #endif /* GPIOG */ 01868 01869 #define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOHRST) 01870 01871 #if defined(USB_OTG_FS) 01872 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) 01873 #endif /* USB_OTG_FS */ 01874 01875 #define __HAL_RCC_ADC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADCRST) 01876 01877 #if defined(AES) 01878 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) 01879 #endif /* AES */ 01880 01881 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST) 01882 01883 /** 01884 * @} 01885 */ 01886 01887 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset 01888 * @brief Force or release AHB3 peripheral reset. 01889 * @{ 01890 */ 01891 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU) 01892 01893 #if defined(FMC_BANK1) 01894 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 01895 #endif /* FMC_BANK1 */ 01896 01897 #if defined(QUADSPI) 01898 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 01899 #endif /* QUADSPI */ 01900 01901 01902 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) 01903 01904 #if defined(FMC_BANK1) 01905 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST) 01906 #endif /* FMC_BANK1 */ 01907 01908 #if defined(QUADSPI) 01909 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST) 01910 #endif /* QUADSPI */ 01911 01912 /** 01913 * @} 01914 */ 01915 01916 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset 01917 * @brief Force or release APB1 peripheral reset. 01918 * @{ 01919 */ 01920 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU) 01921 01922 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 01923 01924 #if defined(TIM3) 01925 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 01926 #endif /* TIM3 */ 01927 01928 #if defined(TIM4) 01929 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 01930 #endif /* TIM4 */ 01931 01932 #if defined(TIM5) 01933 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 01934 #endif /* TIM5 */ 01935 01936 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 01937 01938 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 01939 01940 #if defined(LCD) 01941 #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 01942 #endif /* LCD */ 01943 01944 #if defined(SPI2) 01945 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 01946 #endif /* SPI2 */ 01947 01948 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 01949 01950 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 01951 01952 #if defined(USART3) 01953 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 01954 #endif /* USART3 */ 01955 01956 #if defined(UART4) 01957 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 01958 #endif /* UART4 */ 01959 01960 #if defined(UART5) 01961 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 01962 #endif /* UART5 */ 01963 01964 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 01965 01966 #if defined(I2C2) 01967 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 01968 #endif /* I2C2 */ 01969 01970 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 01971 01972 #if defined(CRS) 01973 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 01974 #endif /* CRS */ 01975 01976 #define __HAL_RCC_CAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 01977 01978 #if defined(USB) 01979 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 01980 #endif /* USB */ 01981 01982 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 01983 01984 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 01985 01986 #define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 01987 01988 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 01989 01990 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 01991 01992 #define __HAL_RCC_SWPMI1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 01993 01994 #define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 01995 01996 01997 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U) 01998 01999 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) 02000 02001 #if defined(TIM3) 02002 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) 02003 #endif /* TIM3 */ 02004 02005 #if defined(TIM4) 02006 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) 02007 #endif /* TIM4 */ 02008 02009 #if defined(TIM5) 02010 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) 02011 #endif /* TIM5 */ 02012 02013 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) 02014 02015 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) 02016 02017 #if defined(LCD) 02018 #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) 02019 #endif /* LCD */ 02020 02021 #if defined(SPI2) 02022 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) 02023 #endif /* SPI2 */ 02024 02025 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST) 02026 02027 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) 02028 02029 #if defined(USART3) 02030 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) 02031 #endif /* USART3 */ 02032 02033 #if defined(UART4) 02034 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) 02035 #endif /* UART4 */ 02036 02037 #if defined(UART5) 02038 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) 02039 #endif /* UART5 */ 02040 02041 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) 02042 02043 #if defined(I2C2) 02044 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) 02045 #endif /* I2C2 */ 02046 02047 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST) 02048 02049 #if defined(CRS) 02050 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) 02051 #endif /* CRS */ 02052 02053 #define __HAL_RCC_CAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CAN1RST) 02054 02055 #if defined(USB) 02056 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBFSRST) 02057 #endif /* USB */ 02058 02059 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST) 02060 02061 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_DAC1RST) 02062 02063 #define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_OPAMPRST) 02064 02065 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST) 02066 02067 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST) 02068 02069 #define __HAL_RCC_SWPMI1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_SWPMI1RST) 02070 02071 #define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) 02072 02073 /** 02074 * @} 02075 */ 02076 02077 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset 02078 * @brief Force or release APB2 peripheral reset. 02079 * @{ 02080 */ 02081 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU) 02082 02083 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 02084 02085 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 02086 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 02087 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 02088 02089 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 02090 02091 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 02092 02093 #if defined(TIM8) 02094 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 02095 #endif /* TIM8 */ 02096 02097 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 02098 02099 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 02100 02101 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 02102 02103 #if defined(TIM17) 02104 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 02105 #endif /* TIM17 */ 02106 02107 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 02108 02109 #if defined(SAI2) 02110 #define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 02111 #endif /* SAI2 */ 02112 02113 #if defined(DFSDM1_Filter0) 02114 #define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 02115 #endif /* DFSDM1_Filter0 */ 02116 02117 02118 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) 02119 02120 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST) 02121 02122 #if defined(SDMMC1) && defined(RCC_APB2RSTR_SDMMC1RST) 02123 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SDMMC1RST) 02124 #endif /* SDMMC1 && RCC_APB2RSTR_SDMMC1RST */ 02125 02126 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) 02127 02128 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) 02129 02130 #if defined(TIM8) 02131 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) 02132 #endif /* TIM8 */ 02133 02134 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) 02135 02136 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) 02137 02138 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) 02139 02140 #if defined(TIM17) 02141 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) 02142 #endif /* TIM17 */ 02143 02144 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) 02145 02146 #if defined(SAI2) 02147 #define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) 02148 #endif /* SAI2 */ 02149 02150 #if defined(DFSDM1_Filter0) 02151 #define __HAL_RCC_DFSDM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST) 02152 #endif /* DFSDM1_Filter0 */ 02153 02154 /** 02155 * @} 02156 */ 02157 02158 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable 02159 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. 02160 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02161 * power consumption. 02162 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02163 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02164 * @{ 02165 */ 02166 02167 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 02168 02169 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 02170 02171 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 02172 02173 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 02174 02175 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 02176 02177 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 02178 02179 02180 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) 02181 02182 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) 02183 02184 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) 02185 02186 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) 02187 02188 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) 02189 02190 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) 02191 02192 /** 02193 * @} 02194 */ 02195 02196 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable 02197 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. 02198 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02199 * power consumption. 02200 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02201 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02202 * @{ 02203 */ 02204 02205 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 02206 02207 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 02208 02209 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 02210 02211 #if defined(GPIOD) 02212 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 02213 #endif /* GPIOD */ 02214 02215 #if defined(GPIOE) 02216 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 02217 #endif /* GPIOE */ 02218 02219 #if defined(GPIOF) 02220 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 02221 #endif /* GPIOF */ 02222 02223 #if defined(GPIOG) 02224 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 02225 #endif /* GPIOG */ 02226 02227 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 02228 02229 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 02230 02231 #if defined(USB_OTG_FS) 02232 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 02233 #endif /* USB_OTG_FS */ 02234 02235 #define __HAL_RCC_ADC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 02236 02237 #if defined(AES) 02238 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 02239 #endif /* AES */ 02240 02241 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 02242 02243 02244 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) 02245 02246 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) 02247 02248 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) 02249 02250 #if defined(GPIOD) 02251 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) 02252 #endif /* GPIOD */ 02253 02254 #if defined(GPIOE) 02255 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) 02256 #endif /* GPIOE */ 02257 02258 #if defined(GPIOF) 02259 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) 02260 #endif /* GPIOF */ 02261 02262 #if defined(GPIOG) 02263 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) 02264 #endif /* GPIOG */ 02265 02266 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) 02267 02268 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) 02269 02270 #if defined(USB_OTG_FS) 02271 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) 02272 #endif /* USB_OTG_FS */ 02273 02274 #define __HAL_RCC_ADC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) 02275 02276 #if defined(AES) 02277 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) 02278 #endif /* AES */ 02279 02280 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) 02281 02282 /** 02283 * @} 02284 */ 02285 02286 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable 02287 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. 02288 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02289 * power consumption. 02290 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02291 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02292 * @{ 02293 */ 02294 02295 #if defined(QUADSPI) 02296 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 02297 #endif /* QUADSPI */ 02298 02299 #if defined(FMC_BANK1) 02300 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 02301 #endif /* FMC_BANK1 */ 02302 02303 02304 #if defined(QUADSPI) 02305 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) 02306 #endif /* QUADSPI */ 02307 02308 #if defined(FMC_BANK1) 02309 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) 02310 #endif /* FMC_BANK1 */ 02311 02312 /** 02313 * @} 02314 */ 02315 02316 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable 02317 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. 02318 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02319 * power consumption. 02320 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02321 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02322 * @{ 02323 */ 02324 02325 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 02326 02327 #if defined(TIM3) 02328 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 02329 #endif /* TIM3 */ 02330 02331 #if defined(TIM4) 02332 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 02333 #endif /* TIM4 */ 02334 02335 #if defined(TIM5) 02336 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 02337 #endif /* TIM5 */ 02338 02339 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 02340 02341 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 02342 02343 #if defined(LCD) 02344 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 02345 #endif /* LCD */ 02346 02347 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 02348 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 02349 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 02350 02351 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 02352 02353 #if defined(SPI2) 02354 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 02355 #endif /* SPI2 */ 02356 02357 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 02358 02359 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 02360 02361 #if defined(USART3) 02362 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 02363 #endif /* USART3 */ 02364 02365 #if defined(UART4) 02366 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 02367 #endif /* UART4 */ 02368 02369 #if defined(UART5) 02370 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 02371 #endif /* UART5 */ 02372 02373 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 02374 02375 #if defined(I2C2) 02376 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 02377 #endif /* I2C2 */ 02378 02379 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 02380 02381 #if defined(CRS) 02382 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 02383 #endif /* CRS */ 02384 02385 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 02386 02387 #if defined(USB) 02388 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 02389 #endif /* USB */ 02390 02391 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 02392 02393 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 02394 02395 #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 02396 02397 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 02398 02399 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 02400 02401 #define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 02402 02403 #define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 02404 02405 02406 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) 02407 02408 #if defined(TIM3) 02409 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) 02410 #endif /* TIM3 */ 02411 02412 #if defined(TIM4) 02413 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) 02414 #endif /* TIM4 */ 02415 02416 #if defined(TIM5) 02417 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) 02418 #endif /* TIM5 */ 02419 02420 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) 02421 02422 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) 02423 02424 #if defined(LCD) 02425 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) 02426 #endif /* LCD */ 02427 02428 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 02429 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) 02430 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 02431 02432 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) 02433 02434 #if defined(SPI2) 02435 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) 02436 #endif /* SPI2 */ 02437 02438 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) 02439 02440 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) 02441 02442 #if defined(USART3) 02443 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) 02444 #endif /* USART3 */ 02445 02446 #if defined(UART4) 02447 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) 02448 #endif /* UART4 */ 02449 02450 #if defined(UART5) 02451 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) 02452 #endif /* UART5 */ 02453 02454 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) 02455 02456 #if defined(I2C2) 02457 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) 02458 #endif /* I2C2 */ 02459 02460 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) 02461 02462 #if defined(CRS) 02463 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) 02464 #endif /* CRS */ 02465 02466 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) 02467 02468 #if defined(USB) 02469 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) 02470 #endif /* USB */ 02471 02472 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) 02473 02474 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) 02475 02476 #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) 02477 02478 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) 02479 02480 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) 02481 02482 #define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) 02483 02484 #define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) 02485 02486 /** 02487 * @} 02488 */ 02489 02490 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable 02491 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. 02492 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02493 * power consumption. 02494 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02495 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02496 * @{ 02497 */ 02498 02499 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 02500 02501 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 02502 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 02503 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 02504 02505 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 02506 02507 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 02508 02509 #if defined(TIM8) 02510 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 02511 #endif /* TIM8 */ 02512 02513 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 02514 02515 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 02516 02517 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 02518 02519 #if defined(TIM17) 02520 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 02521 #endif /* TIM17 */ 02522 02523 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 02524 02525 #if defined(SAI2) 02526 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 02527 #endif /* SAI2 */ 02528 02529 #if defined(DFSDM1_Filter0) 02530 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 02531 #endif /* DFSDM1_Filter0 */ 02532 02533 02534 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) 02535 02536 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 02537 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) 02538 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 02539 02540 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) 02541 02542 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) 02543 02544 #if defined(TIM8) 02545 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) 02546 #endif /* TIM8 */ 02547 02548 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) 02549 02550 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) 02551 02552 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) 02553 02554 #if defined(TIM17) 02555 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) 02556 #endif /* TIM17 */ 02557 02558 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) 02559 02560 #if defined(SAI2) 02561 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) 02562 #endif /* SAI2 */ 02563 02564 #if defined(DFSDM1_Filter0) 02565 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) 02566 #endif /* DFSDM1_Filter0 */ 02567 02568 /** 02569 * @} 02570 */ 02571 02572 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status 02573 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 02574 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02575 * power consumption. 02576 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02577 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02578 * @{ 02579 */ 02580 02581 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != RESET) 02582 02583 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != RESET) 02584 02585 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != RESET) 02586 02587 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != RESET) 02588 02589 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != RESET) 02590 02591 #define __HAL_RCC_TSC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) != RESET) 02592 02593 02594 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == RESET) 02595 02596 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == RESET) 02597 02598 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == RESET) 02599 02600 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == RESET) 02601 02602 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == RESET) 02603 02604 #define __HAL_RCC_TSC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) == RESET) 02605 02606 /** 02607 * @} 02608 */ 02609 02610 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status 02611 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 02612 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02613 * power consumption. 02614 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02615 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02616 * @{ 02617 */ 02618 02619 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != RESET) 02620 02621 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != RESET) 02622 02623 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != RESET) 02624 02625 #if defined(GPIOD) 02626 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != RESET) 02627 #endif /* GPIOD */ 02628 02629 #if defined(GPIOE) 02630 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != RESET) 02631 #endif /* GPIOE */ 02632 02633 #if defined(GPIOF) 02634 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != RESET) 02635 #endif /* GPIOF */ 02636 02637 #if defined(GPIOG) 02638 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != RESET) 02639 #endif /* GPIOG */ 02640 02641 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) != RESET) 02642 02643 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != RESET) 02644 02645 #if defined(USB_OTG_FS) 02646 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) 02647 #endif /* USB_OTG_FS */ 02648 02649 #define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) != RESET) 02650 02651 #if defined(AES) 02652 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) 02653 #endif /* AES */ 02654 02655 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != RESET) 02656 02657 02658 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == RESET) 02659 02660 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == RESET) 02661 02662 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == RESET) 02663 02664 #if defined(GPIOD) 02665 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == RESET) 02666 #endif /* GPIOD */ 02667 02668 #if defined(GPIOE) 02669 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == RESET) 02670 #endif /* GPIOE */ 02671 02672 #if defined(GPIOF) 02673 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == RESET) 02674 #endif /* GPIOF */ 02675 02676 #if defined(GPIOG) 02677 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == RESET) 02678 #endif /* GPIOG */ 02679 02680 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOHSMEN) == RESET) 02681 02682 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == RESET) 02683 02684 #if defined(USB_OTG_FS) 02685 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) 02686 #endif /* USB_OTG_FS */ 02687 02688 #define __HAL_RCC_ADC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADCSMEN) == RESET) 02689 02690 #if defined(AES) 02691 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) 02692 #endif /* AES */ 02693 02694 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == RESET) 02695 02696 /** 02697 * @} 02698 */ 02699 02700 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status 02701 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not. 02702 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02703 * power consumption. 02704 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02705 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02706 * @{ 02707 */ 02708 02709 #if defined(QUADSPI) 02710 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != RESET) 02711 #endif /* QUADSPI */ 02712 02713 #if defined(FMC_BANK1) 02714 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != RESET) 02715 #endif /* FMC_BANK1 */ 02716 02717 #if defined(QUADSPI) 02718 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == RESET) 02719 #endif /* QUADSPI */ 02720 02721 #if defined(FMC_BANK1) 02722 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == RESET) 02723 #endif /* FMC_BANK1 */ 02724 02725 /** 02726 * @} 02727 */ 02728 02729 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status 02730 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not. 02731 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02732 * power consumption. 02733 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02734 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02735 * @{ 02736 */ 02737 02738 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != RESET) 02739 02740 #if defined(TIM3) 02741 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != RESET) 02742 #endif /* TIM3 */ 02743 02744 #if defined(TIM4) 02745 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != RESET) 02746 #endif /* TIM4 */ 02747 02748 #if defined(TIM5) 02749 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != RESET) 02750 #endif /* TIM5 */ 02751 02752 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != RESET) 02753 02754 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != RESET) 02755 02756 #if defined(LCD) 02757 #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) 02758 #endif /* LCD */ 02759 02760 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 02761 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != RESET) 02762 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 02763 02764 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != RESET) 02765 02766 #if defined(SPI2) 02767 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != RESET) 02768 #endif /* SPI2 */ 02769 02770 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != RESET) 02771 02772 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != RESET) 02773 02774 #if defined(USART3) 02775 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != RESET) 02776 #endif /* USART3 */ 02777 02778 #if defined(UART4) 02779 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != RESET) 02780 #endif /* UART4 */ 02781 02782 #if defined(UART5) 02783 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != RESET) 02784 #endif /* UART5 */ 02785 02786 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != RESET) 02787 02788 #if defined(I2C2) 02789 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != RESET) 02790 #endif /* I2C2 */ 02791 02792 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != RESET) 02793 02794 #if defined(CRS) 02795 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != RESET) 02796 #endif /* CRS */ 02797 02798 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != RESET) 02799 02800 #if defined(USB) 02801 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != RESET) 02802 #endif /* USB */ 02803 02804 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != RESET) 02805 02806 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) != RESET) 02807 02808 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) != RESET) 02809 02810 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != RESET) 02811 02812 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != RESET) 02813 02814 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) != RESET) 02815 02816 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) != RESET) 02817 02818 02819 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == RESET) 02820 02821 #if defined(TIM3) 02822 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == RESET) 02823 #endif /* TIM3 */ 02824 02825 #if defined(TIM4) 02826 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == RESET) 02827 #endif /* TIM4 */ 02828 02829 #if defined(TIM5) 02830 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == RESET) 02831 #endif /* TIM5 */ 02832 02833 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == RESET) 02834 02835 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == RESET) 02836 02837 #if defined(LCD) 02838 #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) 02839 #endif /* LCD */ 02840 02841 #if defined(RCC_APB1SMENR1_RTCAPBSMEN) 02842 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == RESET) 02843 #endif /* RCC_APB1SMENR1_RTCAPBSMEN */ 02844 02845 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == RESET) 02846 02847 #if defined(SPI2) 02848 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == RESET) 02849 #endif /* SPI2 */ 02850 02851 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == RESET) 02852 02853 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == RESET) 02854 02855 #if defined(USART3) 02856 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == RESET) 02857 #endif /* USART3 */ 02858 02859 #if defined(UART4) 02860 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == RESET) 02861 #endif /* UART4 */ 02862 02863 #if defined(UART5) 02864 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == RESET) 02865 #endif /* UART5 */ 02866 02867 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == RESET) 02868 02869 #if defined(I2C2) 02870 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == RESET) 02871 #endif /* I2C2 */ 02872 02873 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == RESET) 02874 02875 #if defined(CRS) 02876 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == RESET) 02877 #endif /* CRS */ 02878 02879 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == RESET) 02880 02881 #if defined(USB) 02882 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == RESET) 02883 #endif /* USB */ 02884 02885 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == RESET) 02886 02887 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN) == RESET) 02888 02889 #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_OPAMPSMEN) == RESET) 02890 02891 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == RESET) 02892 02893 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == RESET) 02894 02895 #define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_SWPMI1SMEN) == RESET) 02896 02897 #define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) == RESET) 02898 02899 /** 02900 * @} 02901 */ 02902 02903 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status 02904 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not. 02905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce 02906 * power consumption. 02907 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. 02908 * @note By default, all peripheral clocks are enabled during SLEEP mode. 02909 * @{ 02910 */ 02911 02912 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET) 02913 02914 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 02915 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) != RESET) 02916 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 02917 02918 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != RESET) 02919 02920 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != RESET) 02921 02922 #if defined(TIM8) 02923 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != RESET) 02924 #endif /* TIM8 */ 02925 02926 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != RESET) 02927 02928 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != RESET) 02929 02930 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != RESET) 02931 02932 #if defined(TIM17) 02933 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != RESET) 02934 #endif /* TIM17 */ 02935 02936 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != RESET) 02937 02938 #if defined(SAI2) 02939 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) != RESET) 02940 #endif /* SAI2 */ 02941 02942 #if defined(DFSDM1_Filter0) 02943 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) != RESET) 02944 #endif /* DFSDM1_Filter0 */ 02945 02946 02947 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == RESET) 02948 02949 #if defined(SDMMC1) && defined(RCC_APB2SMENR_SDMMC1SMEN) 02950 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SDMMC1SMEN) == RESET) 02951 #endif /* SDMMC1 && RCC_APB2SMENR_SDMMC1SMEN */ 02952 02953 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == RESET) 02954 02955 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == RESET) 02956 02957 #if defined(TIM8) 02958 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == RESET) 02959 #endif /* TIM8 */ 02960 02961 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == RESET) 02962 02963 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == RESET) 02964 02965 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == RESET) 02966 02967 #if defined(TIM17) 02968 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == RESET) 02969 #endif /* TIM17 */ 02970 02971 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == RESET) 02972 02973 #if defined(SAI2) 02974 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) == RESET) 02975 #endif /* SAI2 */ 02976 02977 #if defined(DFSDM1_Filter0) 02978 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DFSDM1SMEN) == RESET) 02979 #endif /* DFSDM1_Filter0 */ 02980 02981 /** 02982 * @} 02983 */ 02984 02985 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset 02986 * @{ 02987 */ 02988 02989 /** @brief Macros to force or release the Backup domain reset. 02990 * @note This function resets the RTC peripheral (including the backup registers) 02991 * and the RTC clock source selection in RCC_CSR register. 02992 * @note The BKPSRAM is not affected by this reset. 02993 * @retval None 02994 */ 02995 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) 02996 02997 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) 02998 02999 /** 03000 * @} 03001 */ 03002 03003 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration 03004 * @{ 03005 */ 03006 03007 /** @brief Macros to enable or disable the RTC clock. 03008 * @note As the RTC is in the Backup domain and write access is denied to 03009 * this domain after reset, you have to enable write access using 03010 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC 03011 * (to be done once after reset). 03012 * @note These macros must be used after the RTC clock source was selected. 03013 * @retval None 03014 */ 03015 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 03016 03017 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) 03018 03019 /** 03020 * @} 03021 */ 03022 03023 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). 03024 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. 03025 * It is used (enabled by hardware) as system clock source after startup 03026 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure 03027 * of the HSE used directly or indirectly as system clock (if the Clock 03028 * Security System CSS is enabled). 03029 * @note HSI can not be stopped if it is used as system clock source. In this case, 03030 * you have to select another source of the system clock then stop the HSI. 03031 * @note After enabling the HSI, the application software should wait on HSIRDY 03032 * flag to be set indicating that HSI clock is stable and can be used as 03033 * system clock source. 03034 * This parameter can be: ENABLE or DISABLE. 03035 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 03036 * clock cycles. 03037 * @retval None 03038 */ 03039 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) 03040 03041 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) 03042 03043 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. 03044 * @note The calibration is used to compensate for the variations in voltage 03045 * and temperature that influence the frequency of the internal HSI RC. 03046 * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value 03047 * (default is RCC_HSICALIBRATION_DEFAULT). 03048 * This parameter must be a number between 0 and 31. 03049 * @retval None 03050 */ 03051 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ 03052 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_ICSCR_HSITRIM)) 03053 03054 /** 03055 * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) 03056 * in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup. 03057 * @note The enable of this function has not effect on the HSION bit. 03058 * This parameter can be: ENABLE or DISABLE. 03059 * @retval None 03060 */ 03061 #define __HAL_RCC_HSIAUTOMATIC_START_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIASFS) 03062 03063 #define __HAL_RCC_HSIAUTOMATIC_START_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS) 03064 03065 /** 03066 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) 03067 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs. 03068 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication 03069 * speed because of the HSI startup time. 03070 * @note The enable of this function has not effect on the HSION bit. 03071 * This parameter can be: ENABLE or DISABLE. 03072 * @retval None 03073 */ 03074 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) 03075 03076 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) 03077 03078 /** 03079 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). 03080 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. 03081 * It is used (enabled by hardware) as system clock source after 03082 * startup from Reset, wakeup from STOP and STANDBY mode, or in case 03083 * of failure of the HSE used directly or indirectly as system clock 03084 * (if the Clock Security System CSS is enabled). 03085 * @note MSI can not be stopped if it is used as system clock source. 03086 * In this case, you have to select another source of the system 03087 * clock then stop the MSI. 03088 * @note After enabling the MSI, the application software should wait on 03089 * MSIRDY flag to be set indicating that MSI clock is stable and can 03090 * be used as system clock source. 03091 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator 03092 * clock cycles. 03093 * @retval None 03094 */ 03095 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) 03096 03097 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) 03098 03099 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value. 03100 * @note The calibration is used to compensate for the variations in voltage 03101 * and temperature that influence the frequency of the internal MSI RC. 03102 * Refer to the Application Note AN3300 for more details on how to 03103 * calibrate the MSI. 03104 * @param __MSICALIBRATIONVALUE__: specifies the calibration trimming value 03105 * (default is RCC_MSICALIBRATION_DEFAULT). 03106 * This parameter must be a number between 0 and 255. 03107 * @retval None 03108 */ 03109 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ 03110 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) 03111 03112 /** 03113 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode 03114 * @note After restart from Reset , the MSI clock is around 4 MHz. 03115 * After stop the startup clock can be MSI (at any of its possible 03116 * frequencies, the one that was used before entering stop mode) or HSI. 03117 * After Standby its frequency can be selected between 4 possible values 03118 * (1, 2, 4 or 8 MHz). 03119 * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready 03120 * (MSIRDY=1). 03121 * @note The MSI clock range after reset can be modified on the fly. 03122 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 03123 * This parameter must be one of the following values: 03124 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 03125 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 03126 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 03127 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 03128 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 03129 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz 03130 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset) 03131 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 03132 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 03133 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 03134 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 03135 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 03136 * @retval None 03137 */ 03138 #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ 03139 do { \ 03140 SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ 03141 MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ 03142 } while(0) 03143 03144 /** 03145 * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode 03146 * After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz). 03147 * @param __MSIRANGEVALUE__: specifies the MSI clock range. 03148 * This parameter must be one of the following values: 03149 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 03150 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz 03151 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset) 03152 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 03153 * @retval None 03154 */ 03155 #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ 03156 MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) 03157 03158 /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode 03159 * @retval MSI clock range. 03160 * This parameter must be one of the following values: 03161 * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz 03162 * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz 03163 * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz 03164 * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz 03165 * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz 03166 * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2MHz 03167 * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4MHz (default after Reset) 03168 * @arg @ref RCC_MSIRANGE_7 MSI clock is around 8 MHz 03169 * @arg @ref RCC_MSIRANGE_8 MSI clock is around 16 MHz 03170 * @arg @ref RCC_MSIRANGE_9 MSI clock is around 24 MHz 03171 * @arg @ref RCC_MSIRANGE_10 MSI clock is around 32 MHz 03172 * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz 03173 */ 03174 #define __HAL_RCC_GET_MSI_RANGE() \ 03175 ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != RESET) ? \ 03176 (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ 03177 (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) 03178 03179 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). 03180 * @note After enabling the LSI, the application software should wait on 03181 * LSIRDY flag to be set indicating that LSI clock is stable and can 03182 * be used to clock the IWDG and/or the RTC. 03183 * @note LSI can not be disabled if the IWDG is running. 03184 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 03185 * clock cycles. 03186 * @retval None 03187 */ 03188 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION) 03189 03190 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION) 03191 03192 /** 03193 * @brief Macro to configure the External High Speed oscillator (HSE). 03194 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not 03195 * supported by this macro. User should request a transition to HSE Off 03196 * first and then HSE On or HSE Bypass. 03197 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application 03198 * software should wait on HSERDY flag to be set indicating that HSE clock 03199 * is stable and can be used to clock the PLL and/or system clock. 03200 * @note HSE state can not be changed if it is used directly or through the 03201 * PLL as system clock. In this case, you have to select another source 03202 * of the system clock then change the HSE state (ex. disable it). 03203 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. 03204 * @note This function reset the CSSON bit, so if the clock security system(CSS) 03205 * was previously enabled you have to enable it again after calling this 03206 * function. 03207 * @param __STATE__: specifies the new state of the HSE. 03208 * This parameter can be one of the following values: 03209 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after 03210 * 6 HSE oscillator clock cycles. 03211 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. 03212 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. 03213 * @retval None 03214 */ 03215 #define __HAL_RCC_HSE_CONFIG(__STATE__) \ 03216 do { \ 03217 if((__STATE__) == RCC_HSE_ON) \ 03218 { \ 03219 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 03220 } \ 03221 else if((__STATE__) == RCC_HSE_BYPASS) \ 03222 { \ 03223 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ 03224 SET_BIT(RCC->CR, RCC_CR_HSEON); \ 03225 } \ 03226 else \ 03227 { \ 03228 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ 03229 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ 03230 } \ 03231 } while(0) 03232 03233 /** 03234 * @brief Macro to configure the External Low Speed oscillator (LSE). 03235 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not 03236 * supported by this macro. User should request a transition to LSE Off 03237 * first and then LSE On or LSE Bypass. 03238 * @note As the LSE is in the Backup domain and write access is denied to 03239 * this domain after reset, you have to enable write access using 03240 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 03241 * (to be done once after reset). 03242 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application 03243 * software should wait on LSERDY flag to be set indicating that LSE clock 03244 * is stable and can be used to clock the RTC. 03245 * @param __STATE__: specifies the new state of the LSE. 03246 * This parameter can be one of the following values: 03247 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after 03248 * 6 LSE oscillator clock cycles. 03249 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. 03250 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. 03251 * @retval None 03252 */ 03253 #define __HAL_RCC_LSE_CONFIG(__STATE__) \ 03254 do { \ 03255 if((__STATE__) == RCC_LSE_ON) \ 03256 { \ 03257 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 03258 } \ 03259 else if((__STATE__) == RCC_LSE_BYPASS) \ 03260 { \ 03261 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 03262 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 03263 } \ 03264 else \ 03265 { \ 03266 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ 03267 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ 03268 } \ 03269 } while(0) 03270 03271 #if defined(RCC_HSI48_SUPPORT) 03272 03273 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). 03274 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. 03275 * @note After enabling the HSI48, the application software should wait on HSI48RDY 03276 * flag to be set indicating that HSI48 clock is stable. 03277 * This parameter can be: ENABLE or DISABLE. 03278 * @retval None 03279 */ 03280 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 03281 03282 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON) 03283 03284 #endif /* RCC_HSI48_SUPPORT */ 03285 03286 /** @brief Macros to configure the RTC clock (RTCCLK). 03287 * @note As the RTC clock configuration bits are in the Backup domain and write 03288 * access is denied to this domain after reset, you have to enable write 03289 * access using the Power Backup Access macro before to configure 03290 * the RTC clock source (to be done once after reset). 03291 * @note Once the RTC clock is configured it cannot be changed unless the 03292 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by 03293 * a Power On Reset (POR). 03294 * 03295 * @param __RTC_CLKSOURCE__: specifies the RTC clock source. 03296 * This parameter can be one of the following values: 03297 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 03298 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 03299 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 03300 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 03301 * 03302 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 03303 * work in STOP and STANDBY modes, and can be used as wakeup source. 03304 * However, when the HSE clock is used as RTC clock source, the RTC 03305 * cannot be used in STOP and STANDBY modes. 03306 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as 03307 * RTC clock source). 03308 * @retval None 03309 */ 03310 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ 03311 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) 03312 03313 03314 /** @brief Macro to get the RTC clock source. 03315 * @retval The returned value can be one of the following: 03316 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. 03317 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. 03318 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. 03319 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected 03320 */ 03321 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) 03322 03323 /** @brief Macros to enable or disable the main PLL. 03324 * @note After enabling the main PLL, the application software should wait on 03325 * PLLRDY flag to be set indicating that PLL clock is stable and can 03326 * be used as system clock source. 03327 * @note The main PLL can not be disabled if it is used as system clock source 03328 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. 03329 * @retval None 03330 */ 03331 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) 03332 03333 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) 03334 03335 /** @brief Macro to configure the PLL clock source. 03336 * @note This function must be used only when the main PLL is disabled. 03337 * @param __PLLSOURCE__: specifies the PLL entry clock source. 03338 * This parameter can be one of the following values: 03339 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 03340 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 03341 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 03342 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 03343 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 03344 * @retval None 03345 * 03346 */ 03347 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ 03348 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) 03349 03350 /** @brief Macro to configure the PLL source division factor M. 03351 * @note This function must be used only when the main PLL is disabled. 03352 * @param __PLLM__: specifies the division factor for PLL VCO input clock 03353 * This parameter must be a number between Min_Data = 1 and Max_Data = 8. 03354 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 03355 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 03356 * of 16 MHz to limit PLL jitter. 03357 * @retval None 03358 * 03359 */ 03360 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ 03361 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << 4U) 03362 03363 /** 03364 * @brief Macro to configure the main PLL clock source, multiplication and division factors. 03365 * @note This function must be used only when the main PLL is disabled. 03366 * 03367 * @param __PLLSOURCE__: specifies the PLL entry clock source. 03368 * This parameter can be one of the following values: 03369 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry 03370 * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL clock entry 03371 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry 03372 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry 03373 * @note This clock source is common for the main PLL and audio PLL (PLLSAI1 and PLLSAI2). 03374 * 03375 * @param __PLLM__: specifies the division factor for PLL VCO input clock. 03376 * This parameter must be a number between 1 and 8. 03377 * @note You have to set the PLLM parameter correctly to ensure that the VCO input 03378 * frequency ranges from 4 to 16 MHz. It is recommended to select a frequency 03379 * of 16 MHz to limit PLL jitter. 03380 * 03381 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock. 03382 * This parameter must be a number between 8 and 86. 03383 * @note You have to set the PLLN parameter correctly to ensure that the VCO 03384 * output frequency is between 64 and 344 MHz. 03385 * 03386 * @param __PLLP__: specifies the division factor for SAI clock. 03387 * This parameter must be a number in the range (7 or 17) for STM32L47x/STM32L48x 03388 * else (2 to 31). 03389 * 03390 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC1 and RNG clocks. 03391 * This parameter must be in the range (2, 4, 6 or 8). 03392 * @note If the USB OTG FS is used in your application, you have to set the 03393 * PLLQ parameter correctly to have 48 MHz clock for the USB. However, 03394 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work 03395 * correctly. 03396 * @param __PLLR__: specifies the division factor for the main system clock. 03397 * @note You have to set the PLLR parameter correctly to not exceed 80MHZ. 03398 * This parameter must be in the range (2, 4, 6 or 8). 03399 * @retval None 03400 */ 03401 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03402 03403 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 03404 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | \ 03405 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U) | \ 03406 (uint32_t)((__PLLP__) << 27U)) 03407 03408 #else 03409 03410 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ 03411 (RCC->PLLCFGR = (uint32_t)(((__PLLM__) - 1U) << 4U) | (uint32_t)((__PLLN__) << 8U) | (uint32_t)(((__PLLP__) >> 4U ) << 17U) | \ 03412 (uint32_t)(__PLLSOURCE__) | (uint32_t)((((__PLLQ__) >> 1U) - 1U) << 21U) | (uint32_t)((((__PLLR__) >> 1U) - 1U) << 25U)) 03413 03414 #endif /* RCC_PLLP_DIV_2_31_SUPPORT */ 03415 03416 /** @brief Macro to get the oscillator used as PLL clock source. 03417 * @retval The oscillator used as PLL clock source. The returned value can be one 03418 * of the following: 03419 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. 03420 * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. 03421 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. 03422 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. 03423 */ 03424 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) 03425 03426 /** 03427 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 03428 * @note Enabling/disabling clock outputs RCC_PLL_SAI3CLK and RCC_PLL_48M1CLK can be done at anytime 03429 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot 03430 * be stopped if used as System Clock. 03431 * @param __PLLCLOCKOUT__: specifies the PLL clock to be output. 03432 * This parameter can be one or a combination of the following values: 03433 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 03434 * high-quality audio performance on SAI interface in case. 03435 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 03436 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 03437 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 03438 * @retval None 03439 */ 03440 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 03441 03442 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 03443 03444 /** 03445 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK) 03446 * @param __PLLCLOCKOUT__: specifies the output PLL clock to be checked. 03447 * This parameter can be one of the following values: 03448 * @arg @ref RCC_PLL_SAI3CLK This clock is used to generate an accurate clock to achieve 03449 * high-quality audio performance on SAI interface in case. 03450 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB OTG FS (48 MHz), 03451 * the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). 03452 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 80MHz) 03453 * @retval SET / RESET 03454 */ 03455 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__)) 03456 03457 /** 03458 * @brief Macro to configure the system clock source. 03459 * @param __SYSCLKSOURCE__: specifies the system clock source. 03460 * This parameter can be one of the following values: 03461 * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. 03462 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. 03463 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. 03464 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. 03465 * @retval None 03466 */ 03467 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ 03468 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) 03469 03470 /** @brief Macro to get the clock source used as system clock. 03471 * @retval The clock source used as system clock. The returned value can be one 03472 * of the following: 03473 * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. 03474 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. 03475 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. 03476 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. 03477 */ 03478 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) 03479 03480 /** 03481 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. 03482 * @note As the LSE is in the Backup domain and write access is denied to 03483 * this domain after reset, you have to enable write access using 03484 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE 03485 * (to be done once after reset). 03486 * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. 03487 * This parameter can be one of the following values: 03488 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. 03489 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. 03490 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. 03491 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. 03492 * @retval None 03493 */ 03494 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ 03495 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) 03496 03497 /** 03498 * @brief Macro to configure the wake up from stop clock. 03499 * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. 03500 * This parameter can be one of the following values: 03501 * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source 03502 * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source 03503 * @retval None 03504 */ 03505 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ 03506 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) 03507 03508 03509 /** @brief Macro to configure the MCO clock. 03510 * @param __MCOCLKSOURCE__ specifies the MCO clock source. 03511 * This parameter can be one of the following values: 03512 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled 03513 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source 03514 * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source 03515 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source 03516 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee 03517 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source 03518 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source 03519 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source 03520 @if STM32L443xx 03521 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 03522 @endif 03523 * @param __MCODIV__ specifies the MCO clock prescaler. 03524 * This parameter can be one of the following values: 03525 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 03526 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 03527 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 03528 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 03529 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 03530 */ 03531 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ 03532 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) 03533 03534 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management 03535 * @brief macros to manage the specified RCC Flags and interrupts. 03536 * @{ 03537 */ 03538 03539 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable 03540 * the selected interrupts). 03541 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. 03542 * This parameter can be any combination of the following values: 03543 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 03544 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 03545 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 03546 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 03547 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 03548 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 03549 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 03550 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 03551 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 03552 @if STM32L443xx 03553 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 03554 @endif 03555 * @retval None 03556 */ 03557 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) 03558 03559 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 03560 * the selected interrupts). 03561 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. 03562 * This parameter can be any combination of the following values: 03563 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 03564 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 03565 * @arg @ref RCC_IT_MSIRDY HSI ready interrupt 03566 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 03567 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 03568 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 03569 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 03570 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 03571 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 03572 @if STM32L443xx 03573 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 03574 @endif 03575 * @retval None 03576 */ 03577 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) 03578 03579 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] 03580 * bits to clear the selected interrupt pending bits. 03581 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 03582 * This parameter can be any combination of the following values: 03583 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 03584 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 03585 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 03586 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 03587 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 03588 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 03589 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 03590 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 03591 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 03592 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 03593 @if STM32L443xx 03594 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 03595 @endif 03596 * @retval None 03597 */ 03598 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__)) 03599 03600 /** @brief Check whether the RCC interrupt has occurred or not. 03601 * @param __INTERRUPT__: specifies the RCC interrupt source to check. 03602 * This parameter can be one of the following values: 03603 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt 03604 * @arg @ref RCC_IT_LSERDY LSE ready interrupt 03605 * @arg @ref RCC_IT_MSIRDY MSI ready interrupt 03606 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt 03607 * @arg @ref RCC_IT_HSERDY HSE ready interrupt 03608 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt 03609 * @arg @ref RCC_IT_PLLSAI1RDY PLLSAI1 ready interrupt 03610 * @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt for devices with PLLSAI2 03611 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt 03612 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt 03613 @if STM32L443xx 03614 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48 03615 @endif 03616 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 03617 */ 03618 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) 03619 03620 /** @brief Set RMVF bit to clear the reset flags. 03621 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, 03622 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. 03623 * @retval None 03624 */ 03625 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) 03626 03627 /** @brief Check whether the selected RCC flag is set or not. 03628 * @param __FLAG__: specifies the flag to check. 03629 * This parameter can be one of the following values: 03630 * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready 03631 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready 03632 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready 03633 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready 03634 * @arg @ref RCC_FLAG_PLLSAI1RDY PLLSAI1 clock ready 03635 * @arg @ref RCC_FLAG_PLLSAI2RDY PLLSAI2 clock ready for devices with PLLSAI2 03636 @if STM32L443xx 03637 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48 03638 @endif 03639 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready 03640 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection 03641 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready 03642 * @arg @ref RCC_FLAG_BORRST BOR reset 03643 * @arg @ref RCC_FLAG_OBLRST OBLRST reset 03644 * @arg @ref RCC_FLAG_PINRST Pin reset 03645 * @arg @ref RCC_FLAG_FWRST FIREWALL reset 03646 * @arg @ref RCC_FLAG_RMVF Remove reset Flag 03647 * @arg @ref RCC_FLAG_SFTRST Software reset 03648 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset 03649 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset 03650 * @arg @ref RCC_FLAG_LPWRRST Low Power reset 03651 * @retval The new state of __FLAG__ (TRUE or FALSE). 03652 */ 03653 #if defined(RCC_HSI48_SUPPORT) 03654 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 03655 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \ 03656 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 03657 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ 03658 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 03659 ? 1U : 0U) 03660 #else 03661 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ 03662 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ 03663 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR))) & \ 03664 ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) \ 03665 ? 1U : 0U) 03666 #endif /* RCC_HSI48_SUPPORT */ 03667 03668 /** 03669 * @} 03670 */ 03671 03672 /** 03673 * @} 03674 */ 03675 03676 /* Private constants ---------------------------------------------------------*/ 03677 /** @defgroup RCC_Private_Constants RCC Private Constants 03678 * @{ 03679 */ 03680 /* Defines used for Flags */ 03681 #define CR_REG_INDEX ((uint32_t)1U) 03682 #define BDCR_REG_INDEX ((uint32_t)2U) 03683 #define CSR_REG_INDEX ((uint32_t)3U) 03684 #if defined(RCC_HSI48_SUPPORT) 03685 #define CRRCR_REG_INDEX ((uint32_t)4U) 03686 #endif /* RCC_HSI48_SUPPORT */ 03687 03688 #define RCC_FLAG_MASK ((uint32_t)0x1FU) 03689 /** 03690 * @} 03691 */ 03692 03693 /* Private macros ------------------------------------------------------------*/ 03694 /** @addtogroup RCC_Private_Macros 03695 * @{ 03696 */ 03697 03698 #if defined(RCC_HSI48_SUPPORT) 03699 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 03700 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 03701 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 03702 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \ 03703 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 03704 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 03705 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 03706 #else 03707 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ 03708 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ 03709 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ 03710 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) || \ 03711 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ 03712 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) 03713 #endif /* RCC_HSI48_SUPPORT */ 03714 03715 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ 03716 ((__HSE__) == RCC_HSE_BYPASS)) 03717 03718 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ 03719 ((__LSE__) == RCC_LSE_BYPASS)) 03720 03721 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) 03722 03723 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)31U) 03724 03725 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) 03726 03727 #define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) 03728 03729 #define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U) 03730 03731 #if defined(RCC_HSI48_SUPPORT) 03732 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) 03733 #endif /* RCC_HSI48_SUPPORT */ 03734 03735 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \ 03736 ((__PLL__) == RCC_PLL_ON)) 03737 03738 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \ 03739 ((__SOURCE__) == RCC_PLLSOURCE_MSI) || \ 03740 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ 03741 ((__SOURCE__) == RCC_PLLSOURCE_HSE)) 03742 03743 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 8U)) 03744 03745 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) 03746 03747 #if defined(RCC_PLLP_DIV_2_31_SUPPORT) 03748 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U)) 03749 #else 03750 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) == 7U) || ((__VALUE__) == 17U)) 03751 #endif /*RCC_PLLP_DIV_2_31_SUPPORT */ 03752 03753 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 03754 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 03755 03756 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \ 03757 ((__VALUE__) == 6U) || ((__VALUE__) == 8U)) 03758 03759 #define IS_RCC_PLLSAI1CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI1_SAI1CLK) == RCC_PLLSAI1_SAI1CLK) || \ 03760 (((__VALUE__) & RCC_PLLSAI1_48M2CLK) == RCC_PLLSAI1_48M2CLK) || \ 03761 (((__VALUE__) & RCC_PLLSAI1_ADC1CLK) == RCC_PLLSAI1_ADC1CLK)) && \ 03762 (((__VALUE__) & ~(RCC_PLLSAI1_SAI1CLK|RCC_PLLSAI1_48M2CLK|RCC_PLLSAI1_ADC1CLK)) == 0U)) 03763 03764 #if defined(RCC_PLLSAI2_SUPPORT) 03765 #define IS_RCC_PLLSAI2CLOCKOUT_VALUE(__VALUE__) (((((__VALUE__) & RCC_PLLSAI2_SAI2CLK) == RCC_PLLSAI2_SAI2CLK) || \ 03766 (((__VALUE__) & RCC_PLLSAI2_ADC2CLK) == RCC_PLLSAI2_ADC2CLK)) && \ 03767 (((__VALUE__) & ~(RCC_PLLSAI2_SAI2CLK|RCC_PLLSAI2_ADC2CLK)) == 0U)) 03768 #endif /* RCC_PLLSAI2_SUPPORT */ 03769 03770 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ 03771 ((__RANGE__) == RCC_MSIRANGE_1) || \ 03772 ((__RANGE__) == RCC_MSIRANGE_2) || \ 03773 ((__RANGE__) == RCC_MSIRANGE_3) || \ 03774 ((__RANGE__) == RCC_MSIRANGE_4) || \ 03775 ((__RANGE__) == RCC_MSIRANGE_5) || \ 03776 ((__RANGE__) == RCC_MSIRANGE_6) || \ 03777 ((__RANGE__) == RCC_MSIRANGE_7) || \ 03778 ((__RANGE__) == RCC_MSIRANGE_8) || \ 03779 ((__RANGE__) == RCC_MSIRANGE_9) || \ 03780 ((__RANGE__) == RCC_MSIRANGE_10) || \ 03781 ((__RANGE__) == RCC_MSIRANGE_11)) 03782 03783 #define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ 03784 ((__RANGE__) == RCC_MSIRANGE_5) || \ 03785 ((__RANGE__) == RCC_MSIRANGE_6) || \ 03786 ((__RANGE__) == RCC_MSIRANGE_7)) 03787 03788 #define IS_RCC_CLOCKTYPE(__CLK__) ((1U <= (__CLK__)) && ((__CLK__) <= 15U)) 03789 03790 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ 03791 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ 03792 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ 03793 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) 03794 03795 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ 03796 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ 03797 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ 03798 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ 03799 ((__HCLK__) == RCC_SYSCLK_DIV512)) 03800 03801 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ 03802 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ 03803 ((__PCLK__) == RCC_HCLK_DIV16)) 03804 03805 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ 03806 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ 03807 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ 03808 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) 03809 03810 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) 03811 03812 #if defined(RCC_HSI48_SUPPORT) 03813 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 03814 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 03815 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 03816 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 03817 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 03818 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 03819 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 03820 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ 03821 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) 03822 #else 03823 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ 03824 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ 03825 ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ 03826 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ 03827 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ 03828 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ 03829 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ 03830 ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) 03831 #endif /* RCC_HSI48_SUPPORT */ 03832 03833 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ 03834 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ 03835 ((__DIV__) == RCC_MCODIV_16)) 03836 03837 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ 03838 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ 03839 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ 03840 ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) 03841 03842 #define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \ 03843 ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) 03844 /** 03845 * @} 03846 */ 03847 03848 /* Include RCC HAL Extended module */ 03849 #include "stm32l4xx_hal_rcc_ex.h" 03850 03851 /* Exported functions --------------------------------------------------------*/ 03852 /** @addtogroup RCC_Exported_Functions 03853 * @{ 03854 */ 03855 03856 03857 /** @addtogroup RCC_Exported_Functions_Group1 03858 * @{ 03859 */ 03860 03861 /* Initialization and de-initialization functions ******************************/ 03862 void HAL_RCC_DeInit(void); 03863 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 03864 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); 03865 03866 /** 03867 * @} 03868 */ 03869 03870 /** @addtogroup RCC_Exported_Functions_Group2 03871 * @{ 03872 */ 03873 03874 /* Peripheral Control functions ************************************************/ 03875 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); 03876 void HAL_RCC_EnableCSS(void); 03877 uint32_t HAL_RCC_GetSysClockFreq(void); 03878 uint32_t HAL_RCC_GetHCLKFreq(void); 03879 uint32_t HAL_RCC_GetPCLK1Freq(void); 03880 uint32_t HAL_RCC_GetPCLK2Freq(void); 03881 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); 03882 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); 03883 /* CSS NMI IRQ handler */ 03884 void HAL_RCC_NMI_IRQHandler(void); 03885 /* User Callbacks in non blocking mode (IT mode) */ 03886 void HAL_RCC_CSSCallback(void); 03887 03888 /** 03889 * @} 03890 */ 03891 03892 /** 03893 * @} 03894 */ 03895 03896 /** 03897 * @} 03898 */ 03899 03900 /** 03901 * @} 03902 */ 03903 03904 #ifdef __cplusplus 03905 } 03906 #endif 03907 03908 #endif /* __STM32L4xx_HAL_RCC_H */ 03909 03910 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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