stm32l4xx_hal_qspi.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_qspi.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of QSPI HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************  
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_QSPI_H
00040 #define __STM32L4xx_HAL_QSPI_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048 
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup QSPI
00054   * @{
00055   */ 
00056 
00057 /* Exported types ------------------------------------------------------------*/ 
00058 /** @defgroup QSPI_Exported_Types QSPI Exported Types
00059   * @{
00060   */
00061 
00062 /** 
00063   * @brief  QSPI Init structure definition  
00064   */
00065 typedef struct
00066 {
00067   uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
00068                                   This parameter can be a number between 0 and 255 */ 
00069   uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
00070                                   This parameter can be a value between 1 and 16 */
00071   uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 
00072                                   take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
00073                                   This parameter can be a value of @ref QSPI_SampleShifting */
00074   uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 
00075                                   required to address the flash memory. The flash capacity can be up to 4GB 
00076                                   (addressed using 32 bits) in indirect mode, but the addressable space in 
00077                                   memory-mapped mode is limited to 256MB
00078                                   This parameter can be a number between 0 and 31 */
00079   uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 
00080                                   of clock cycles which the chip select must remain high between commands.
00081                                   This parameter can be a value of @ref QSPI_ChipSelectHighTime */   
00082   uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
00083                                   This parameter can be a value of @ref QSPI_ClockMode */
00084 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00085   uint32_t FlashID;            /* Specifies the Flash which will be used,
00086                                   This parameter can be a value of @ref QSPI_Flash_Select */
00087   uint32_t DualFlash;          /* Specifies the Dual Flash Mode State
00088                                   This parameter can be a value of @ref QSPI_DualFlash_Mode */                                               
00089 #endif
00090 }QSPI_InitTypeDef;
00091 
00092 /** 
00093   * @brief HAL QSPI State structures definition  
00094   */ 
00095 typedef enum
00096 {
00097   HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
00098   HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
00099   HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */ 
00100   HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */ 
00101   HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
00102   HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
00103   HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
00104   HAL_QSPI_STATE_ABORT             = 0x08,    /*!< Peripheral with abort request ongoing                 */
00105   HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
00106 }HAL_QSPI_StateTypeDef;
00107 
00108 /** 
00109   * @brief  QSPI Handle Structure definition  
00110   */  
00111 typedef struct
00112 {
00113   QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
00114   QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
00115   uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
00116   __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
00117   __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
00118   uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
00119   __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
00120   __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
00121   DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
00122   __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
00123   __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
00124   __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
00125   uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ 
00126 }QSPI_HandleTypeDef;
00127 
00128 /** 
00129   * @brief  QSPI Command structure definition  
00130   */
00131 typedef struct
00132 {
00133   uint32_t Instruction;        /* Specifies the Instruction to be sent
00134                                   This parameter can be a value (8-bit) between 0x00 and 0xFF */
00135   uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
00136                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00137   uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
00138                                   This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
00139   uint32_t AddressSize;        /* Specifies the Address Size
00140                                   This parameter can be a value of @ref QSPI_AddressSize */
00141   uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
00142                                   This parameter can be a value of @ref QSPI_AlternateBytesSize */
00143   uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
00144                                   This parameter can be a number between 0 and 31 */
00145   uint32_t InstructionMode;    /* Specifies the Instruction Mode
00146                                   This parameter can be a value of @ref QSPI_InstructionMode */
00147   uint32_t AddressMode;        /* Specifies the Address Mode
00148                                   This parameter can be a value of @ref QSPI_AddressMode */
00149   uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
00150                                   This parameter can be a value of @ref QSPI_AlternateBytesMode */
00151   uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
00152                                   This parameter can be a value of @ref QSPI_DataMode */
00153   uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)
00154                                   This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 
00155                                   until end of memory)*/
00156   uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
00157                                   This parameter can be a value of @ref QSPI_DdrMode */
00158   uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of 
00159                                   system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
00160                                   This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
00161   uint32_t SIOOMode;           /* Specifies the send instruction only once mode
00162                                   This parameter can be a value of @ref QSPI_SIOOMode */
00163 }QSPI_CommandTypeDef;
00164 
00165 /** 
00166   * @brief  QSPI Auto Polling mode configuration structure definition  
00167   */
00168 typedef struct
00169 {
00170   uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
00171                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00172   uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. 
00173                                   This parameter can be any value between 0 and 0xFFFFFFFF */
00174   uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
00175                                   This parameter can be any value between 0 and 0xFFFF */
00176   uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
00177                                   This parameter can be any value between 1 and 4 */
00178   uint32_t MatchMode;          /* Specifies the method used for determining a match.
00179                                   This parameter can be a value of @ref QSPI_MatchMode */
00180   uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
00181                                   This parameter can be a value of @ref QSPI_AutomaticStop */
00182 }QSPI_AutoPollingTypeDef;
00183                            
00184 /** 
00185   * @brief  QSPI Memory Mapped mode configuration structure definition  
00186   */
00187 typedef struct
00188 {
00189   uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
00190                                   This parameter can be any value between 0 and 0xFFFF */
00191   uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select. 
00192                                   This parameter can be a value of @ref QSPI_TimeOutActivation */
00193 }QSPI_MemoryMappedTypeDef;
00194 
00195 /**
00196   * @}
00197   */
00198 
00199 /* Exported constants --------------------------------------------------------*/
00200 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
00201   * @{
00202   */
00203 
00204 /** @defgroup QSPI_ErrorCode QSPI Error Code
00205   * @{
00206   */ 
00207 #define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error                 */
00208 #define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error            */
00209 #define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error           */
00210 #define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error       */
00211 #define HAL_QSPI_ERROR_INVALID_PARAM   ((uint32_t)0x00000008) /*!< Invalid parameters error */
00212 /**
00213   * @}
00214   */ 
00215 
00216 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
00217   * @{
00218   */
00219 #define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000)        /*!<No clock cycle shift to sample data*/
00220 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
00221 /**
00222   * @}
00223   */ 
00224 
00225 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
00226   * @{
00227   */
00228 #define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
00229 #define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
00230 #define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
00231 #define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
00232 #define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
00233 #define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
00234 #define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
00235 #define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
00236 /**
00237   * @}
00238   */
00239 
00240 /** @defgroup QSPI_ClockMode QSPI Clock Mode
00241   * @{
00242   */
00243 #define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
00244 #define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
00245 /**
00246   * @}
00247   */
00248 
00249 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00250 /** @defgroup QSPI_Flash_Select QSPI Flash Select
00251   * @{
00252   */
00253 #define QSPI_FLASH_ID_1                ((uint32_t)0x00000000)      /*!<FLASH 1 selected*/
00254 #define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
00255 /**
00256   * @}
00257   */  
00258 
00259   /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
00260   * @{
00261   */
00262 #define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
00263 #define QSPI_DUALFLASH_DISABLE         ((uint32_t)0x00000000)     /*!<Dual-flash mode disabled*/
00264 /**
00265   * @}
00266   */ 
00267 #endif
00268 
00269 /** @defgroup QSPI_AddressSize QSPI Address Size
00270   * @{
00271   */
00272 #define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
00273 #define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
00274 #define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
00275 #define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
00276 /**
00277   * @}
00278   */  
00279 
00280 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
00281   * @{
00282   */
00283 #define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
00284 #define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
00285 #define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
00286 #define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
00287 /**
00288   * @}
00289   */
00290 
00291 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
00292 * @{
00293 */
00294 #define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
00295 #define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
00296 #define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
00297 #define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
00298 /**
00299   * @}
00300   */
00301 
00302 /** @defgroup QSPI_AddressMode QSPI Address Mode
00303 * @{
00304 */
00305 #define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
00306 #define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
00307 #define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
00308 #define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
00309 /**
00310   * @}
00311   */  
00312 
00313 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
00314 * @{
00315 */
00316 #define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
00317 #define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
00318 #define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
00319 #define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
00320 /**
00321   * @}
00322   */  
00323 
00324 /** @defgroup QSPI_DataMode QSPI Data Mode
00325   * @{
00326   */
00327 #define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
00328 #define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
00329 #define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
00330 #define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
00331 /**
00332   * @}
00333   */  
00334 
00335 /** @defgroup QSPI_DdrMode QSPI DDR Mode
00336   * @{
00337   */
00338 #define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
00339 #define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
00340 /**
00341   * @}
00342   */
00343 
00344 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
00345   * @{
00346   */
00347 #define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
00348 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00349 #define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
00350 #endif
00351 /**
00352   * @}
00353   */
00354 
00355 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
00356   * @{
00357   */
00358 #define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
00359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
00360 /**
00361   * @}
00362   */
00363 
00364 /** @defgroup QSPI_MatchMode QSPI Match Mode
00365   * @{
00366   */
00367 #define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
00368 #define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
00369 /**
00370   * @}
00371   */  
00372 
00373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
00374   * @{
00375   */
00376 #define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
00377 #define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
00378 /**
00379   * @}
00380   */  
00381 
00382 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
00383   * @{
00384   */
00385 #define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
00386 #define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
00387 /**
00388   * @}
00389   */  
00390 
00391 /** @defgroup QSPI_Flags QSPI Flags
00392   * @{
00393   */
00394 #define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
00395 #define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
00396 #define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
00397 #define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
00398 #define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
00399 #define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
00400 /**
00401   * @}
00402   */
00403 
00404 /** @defgroup QSPI_Interrupts QSPI Interrupts
00405   * @{
00406   */  
00407 #define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
00408 #define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
00409 #define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
00410 #define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
00411 #define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
00412 /**
00413   * @}
00414   */
00415 
00416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
00417   * @brief QSPI Timeout definition
00418   * @{
00419   */ 
00420 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
00421 /**
00422   * @}
00423   */  
00424 
00425 /**
00426   * @}
00427   */
00428 
00429 /* Exported macros -----------------------------------------------------------*/
00430 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
00431   * @{
00432   */
00433 /** @brief Reset QSPI handle state.
00434   * @param  __HANDLE__: QSPI handle.
00435   * @retval None
00436   */
00437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
00438 
00439 /** @brief  Enable the QSPI peripheral.
00440   * @param  __HANDLE__: specifies the QSPI Handle.
00441   * @retval None
00442   */ 
00443 #define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00444 
00445 /** @brief  Disable the QSPI peripheral.
00446   * @param  __HANDLE__: specifies the QSPI Handle.
00447   * @retval None
00448   */
00449 #define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
00450 
00451 /** @brief  Enable the specified QSPI interrupt.
00452   * @param  __HANDLE__: specifies the QSPI Handle.
00453   * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
00454   *          This parameter can be one of the following values:
00455   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00456   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00457   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00458   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00459   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00460   * @retval None
00461   */
00462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00463 
00464 
00465 /** @brief  Disable the specified QSPI interrupt.
00466   * @param  __HANDLE__: specifies the QSPI Handle.
00467   * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
00468   *          This parameter can be one of the following values:
00469   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00470   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00471   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00472   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00473   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00474   * @retval None
00475   */
00476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
00477 
00478 /** @brief  Check whether the specified QSPI interrupt source is enabled or not.
00479   * @param  __HANDLE__: specifies the QSPI Handle.
00480   * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
00481   *          This parameter can be one of the following values:
00482   *            @arg QSPI_IT_TO: QSPI Timeout interrupt
00483   *            @arg QSPI_IT_SM: QSPI Status match interrupt
00484   *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
00485   *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
00486   *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
00487   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
00488   */
00489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 
00490 
00491 /**
00492   * @brief  Check whether the selected QSPI flag is set or not.
00493   * @param  __HANDLE__: specifies the QSPI Handle.
00494   * @param  __FLAG__: specifies the QSPI flag to check.
00495   *          This parameter can be one of the following values:
00496   *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
00497   *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
00498   *            @arg QSPI_FLAG_SM:   QSPI Status match flag
00499   *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
00500   *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
00501   *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
00502   * @retval None
00503   */
00504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
00505 
00506 /** @brief  Clears the specified QSPI's flag status.
00507   * @param  __HANDLE__: specifies the QSPI Handle.
00508   * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
00509   *          This parameter can be one of the following values:
00510   *            @arg QSPI_FLAG_TO: QSPI Timeout flag
00511   *            @arg QSPI_FLAG_SM: QSPI Status match flag
00512   *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
00513   *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
00514   * @retval None
00515   */
00516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
00517 /**
00518   * @}
00519   */
00520 
00521 /* Exported functions --------------------------------------------------------*/  
00522 /** @addtogroup QSPI_Exported_Functions
00523   * @{
00524   */
00525 /* Initialization/de-initialization functions  ********************************/
00526 HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
00527 HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
00528 void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
00529 void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
00530 
00531 /* IO operation functions *****************************************************/
00532 /* QSPI IRQ handler method */
00533 void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
00534 
00535 /* QSPI indirect mode */
00536 HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
00537 HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00538 HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
00539 HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
00540 HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00541 HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00542 HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00543 HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
00544 
00545 /* QSPI status flag polling mode */
00546 HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
00547 HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
00548 
00549 /* QSPI memory-mapped mode */
00550 HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
00551 
00552 /* Callback functions in non-blocking modes ***********************************/
00553 void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
00554 void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);
00555 void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
00556 
00557 /* QSPI indirect mode */
00558 void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
00559 void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00560 void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
00561 void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00562 void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
00563 
00564 /* QSPI status flag polling mode */
00565 void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
00566 
00567 /* QSPI memory-mapped mode */
00568 void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
00569 
00570 /* Peripheral Control and State functions  ************************************/
00571 HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);
00572 uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);
00573 HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);
00574 HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);
00575 void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
00576 HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
00577 uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
00578 /**
00579   * @}
00580   */
00581 /* End of exported functions -------------------------------------------------*/  
00582 
00583 /* Private macros ------------------------------------------------------------*/
00584 /** @defgroup QSPI_Private_Macros QSPI Private Macros
00585 * @{
00586 */
00587 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
00588 
00589 #define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0) && ((THR) <= 16))
00590 
00591 #define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
00592                                             ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
00593 
00594 #define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31))
00595 
00596 #define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
00597                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
00598                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
00599                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
00600                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
00601                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
00602                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
00603                                             ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
00604 
00605 #define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
00606                                             ((CLKMODE) == QSPI_CLOCK_MODE_3))
00607 
00608 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00609 #define IS_QSPI_FLASH_ID(FLASH)            (((FLASH) == QSPI_FLASH_ID_1) || \
00610                                             ((FLASH) == QSPI_FLASH_ID_2)) 
00611                                   
00612 #define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \
00613                                             ((MODE) == QSPI_DUALFLASH_DISABLE))
00614 #endif
00615 
00616 #define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF) 
00617 
00618 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
00619                                             ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
00620                                             ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
00621                                             ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
00622 
00623 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
00624                                             ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
00625                                             ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
00626                                             ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
00627 
00628 #define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31) 
00629 
00630 #define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
00631                                             ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
00632                                             ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
00633                                             ((MODE) == QSPI_INSTRUCTION_4_LINES))
00634 
00635 #define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
00636                                             ((MODE) == QSPI_ADDRESS_1_LINE)  || \
00637                                             ((MODE) == QSPI_ADDRESS_2_LINES) || \
00638                                             ((MODE) == QSPI_ADDRESS_4_LINES))
00639 
00640 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
00641                                             ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
00642                                             ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
00643                                             ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
00644 
00645 #define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
00646                                             ((MODE) == QSPI_DATA_1_LINE)  || \
00647                                             ((MODE) == QSPI_DATA_2_LINES) || \
00648                                             ((MODE) == QSPI_DATA_4_LINES))
00649 
00650 #define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
00651                                             ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
00652 
00653 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || defined(STM32L443xx)
00654 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
00655                                             ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
00656 #else
00657 #define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
00658 #endif
00659 
00660 #define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
00661                                             ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
00662 
00663 #define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 
00664 
00665 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4)) 
00666 
00667 #define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
00668                                             ((MODE) == QSPI_MATCH_MODE_OR)) 
00669 
00670 #define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
00671                                             ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 
00672 
00673 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
00674                                             ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 
00675 
00676 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF) 
00677 /**
00678 * @}
00679 */ 
00680 /* End of private macros -----------------------------------------------------*/
00681 
00682 /**
00683   * @}
00684   */ 
00685 
00686 /**
00687   * @}
00688   */ 
00689   
00690 #ifdef __cplusplus
00691 }
00692 #endif
00693 
00694 #endif /* __STM32L4xx_HAL_QSPI_H */
00695 
00696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/