stm32l4xx_hal_pwr_ex.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_pwr_ex.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of PWR HAL Extended module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_PWR_EX_H
00040 #define __STM32L4xx_HAL_PWR_EX_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048 
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup PWREx
00054   * @{
00055   */
00056 
00057 
00058 /* Exported types ------------------------------------------------------------*/
00059 
00060 /** @defgroup PWREx_Exported_Types PWR Extended Exported Types
00061   * @{
00062   */
00063 
00064 
00065 /**
00066   * @brief  PWR PVM configuration structure definition
00067   */
00068 typedef struct
00069 {
00070   uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold. 
00071                            This parameter can be a value of @ref PWREx_PVM_Type. 
00072                            @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 
00073 @if STM32L486xx
00074                            @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 
00075 @endif
00076                            @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 
00077                            @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
00078 
00079   uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
00080                            This parameter can be a value of @ref PWREx_PVM_Mode. */
00081 }PWR_PVMTypeDef;
00082 
00083 /**
00084   * @}
00085   */ 
00086 
00087 /* Exported constants --------------------------------------------------------*/
00088 
00089 /** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
00090   * @{
00091   */
00092 
00093 /** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
00094   * @{
00095   */
00096 #define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */
00097 /**
00098   * @}
00099   */  
00100 
00101 
00102 /** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
00103   * @{
00104   */                                                      
00105 #define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00106 #define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00107 #define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00108 #define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00109 #define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00110 #define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
00111 #define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
00112 #define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
00113 #define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
00114 #define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
00115 #define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
00116 #define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
00117 #define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
00118 #define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
00119 #define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
00120 /**
00121   * @}
00122   */
00123 
00124 /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
00125   * @{
00126   */
00127 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \
00128     defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00129 #define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
00130 #endif /* STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00131 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00132 #define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
00133 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
00134 #define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
00135 #define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
00136 /**
00137   * @}
00138   */  
00139   
00140 /** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
00141   * @{
00142   */
00143 #define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
00144 #define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
00145 #define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
00146 #define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
00147 #define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
00148 #define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
00149 #define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
00150 /**
00151   * @}
00152   */
00153   
00154   
00155 
00156 /** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
00157   * @{
00158   */
00159 #define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR1_VOS_0     /*!< Voltage scaling range 1 */
00160 #define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR1_VOS_1     /*!< Voltage scaling range 2 */
00161 /**
00162   * @}
00163   */
00164 
00165   
00166 /** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
00167   * @{
00168   */
00169 #define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */
00170 #define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
00171 /**
00172   * @}
00173   */
00174   
00175 /** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
00176   * @{
00177   */
00178 #define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)
00179 #define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
00180 /**
00181   * @}
00182   */ 
00183   
00184 /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
00185   * @{
00186   */
00187 #define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
00188 #define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
00189 #define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
00190 #define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
00191 #define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
00192 #define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
00193 #define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
00194 #define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
00195 #define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
00196 #define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
00197 #define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
00198 #define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
00199 #define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
00200 #define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
00201 #define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
00202 #define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
00203 /**
00204   * @}
00205   */ 
00206   
00207 /** @defgroup PWREx_GPIO GPIO port
00208   * @{
00209   */
00210 #define PWR_GPIO_A   0x00000000      /*!< GPIO port A */
00211 #define PWR_GPIO_B   0x00000001      /*!< GPIO port B */
00212 #define PWR_GPIO_C   0x00000002      /*!< GPIO port C */
00213 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) ||                                                   \
00214     defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00215 #define PWR_GPIO_D   0x00000003      /*!< GPIO port D */
00216 #define PWR_GPIO_E   0x00000004      /*!< GPIO port E */
00217 #endif
00218 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00219 #define PWR_GPIO_F   0x00000005      /*!< GPIO port F */
00220 #define PWR_GPIO_G   0x00000006      /*!< GPIO port G */
00221 #endif
00222 #define PWR_GPIO_H   0x00000007      /*!< GPIO port H */
00223 /**
00224   * @}
00225   */ 
00226   
00227 /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
00228   * @{
00229   */    
00230 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00231 #define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
00232 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00233 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00234 #define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
00235 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00236 #define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
00237 #define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */ 
00238 /**
00239   * @}
00240   */ 
00241   
00242 /** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
00243   * @{
00244   */    
00245 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00246 #define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */
00247 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00248 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00249 #define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */
00250 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00251 #define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */
00252 #define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */ 
00253 /**
00254   * @}
00255   */ 
00256   
00257 /** @defgroup PWREx_Flag  PWR Status Flags
00258   *        Elements values convention: 0000 0000 0XXY YYYYb
00259   *           - Y YYYY  : Flag position in the XX register (5 bits)
00260   *           - XX  : Status register (2 bits)
00261   *                 - 01: SR1 register
00262   *                 - 10: SR2 register
00263   *        The only exception is PWR_FLAG_WU, encompassing all
00264   *        wake-up flags and set to PWR_SR1_WUF.    
00265   * @{   
00266   */  
00267 #define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */
00268 #define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */
00269 #define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */
00270 #define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */
00271 #define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */
00272 #define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
00273 #define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */
00274 #define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */
00275 
00276 #define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */
00277 #define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */
00278 #define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */
00279 #define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */
00280 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00281 #define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */
00282 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00283 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00284 #define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */
00285 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00286 #define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */
00287 #define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */
00288 /**
00289   * @}
00290   */        
00291 
00292 /**
00293   * @}
00294   */  
00295 
00296 /* Exported macros -----------------------------------------------------------*/
00297 /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
00298  * @{
00299  */
00300 
00301 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00302 /**
00303   * @brief Enable the PVM1 Extended Interrupt Line.
00304   * @retval None
00305   */
00306 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
00307 
00308 /**
00309   * @brief Disable the PVM1 Extended Interrupt Line.
00310   * @retval None
00311   */
00312 #define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
00313 
00314 /**
00315   * @brief Enable the PVM1 Event Line.
00316   * @retval None
00317   */
00318 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
00319 
00320 /**
00321   * @brief Disable the PVM1 Event Line.
00322   * @retval None
00323   */
00324 #define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
00325 
00326 /**
00327   * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
00328   * @retval None
00329   */
00330 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
00331 
00332 /**
00333   * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
00334   * @retval None
00335   */
00336 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
00337 
00338 /**
00339   * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
00340   * @retval None
00341   */
00342 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
00343 
00344 
00345 /**
00346   * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
00347   * @retval None
00348   */
00349 #define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
00350 
00351 
00352 /**
00353   * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
00354   * @retval None
00355   */
00356 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00357   do {                                                    \
00358     __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
00359     __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
00360   } while(0)
00361 
00362 /**
00363   * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
00364   * @retval None
00365   */
00366 #define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00367   do {                                                     \
00368     __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
00369     __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
00370   } while(0)
00371 
00372 /**
00373   * @brief  Generate a Software interrupt on selected EXTI line.
00374   * @retval None
00375   */
00376 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
00377 
00378 /**
00379   * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
00380   * @retval EXTI PVM1 Line Status.
00381   */
00382 #define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
00383 
00384 /**
00385   * @brief Clear the PVM1 EXTI flag.
00386   * @retval None
00387   */
00388 #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
00389 
00390 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00391 
00392 
00393 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00394 /**
00395   * @brief Enable the PVM2 Extended Interrupt Line.
00396   * @retval None
00397   */
00398 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
00399 
00400 /**
00401   * @brief Disable the PVM2 Extended Interrupt Line.
00402   * @retval None
00403   */
00404 #define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
00405 
00406 /**
00407   * @brief Enable the PVM2 Event Line.
00408   * @retval None
00409   */
00410 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
00411 
00412 /**
00413   * @brief Disable the PVM2 Event Line.
00414   * @retval None
00415   */
00416 #define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
00417 
00418 /**
00419   * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
00420   * @retval None
00421   */
00422 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
00423 
00424 /**
00425   * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
00426   * @retval None
00427   */
00428 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
00429 
00430 /**
00431   * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
00432   * @retval None
00433   */
00434 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
00435 
00436 
00437 /**
00438   * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
00439   * @retval None
00440   */
00441 #define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
00442 
00443 
00444 /**
00445   * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
00446   * @retval None
00447   */
00448 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00449   do {                                                    \
00450     __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
00451     __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
00452   } while(0)
00453   
00454 /**
00455   * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
00456   * @retval None
00457   */
00458 #define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00459   do {                                                     \
00460     __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
00461     __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
00462   } while(0)
00463 
00464 /**
00465   * @brief  Generate a Software interrupt on selected EXTI line.
00466   * @retval None
00467   */
00468 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
00469 
00470 /**
00471   * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
00472   * @retval EXTI PVM2 Line Status.
00473   */
00474 #define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
00475 
00476 /**
00477   * @brief Clear the PVM2 EXTI flag.
00478   * @retval None
00479   */
00480 #define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
00481 
00482 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00483 
00484 
00485 /**
00486   * @brief Enable the PVM3 Extended Interrupt Line.
00487   * @retval None
00488   */
00489 #define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
00490 
00491 /**
00492   * @brief Disable the PVM3 Extended Interrupt Line.
00493   * @retval None
00494   */
00495 #define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
00496 
00497 /**
00498   * @brief Enable the PVM3 Event Line.
00499   * @retval None
00500   */
00501 #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
00502 
00503 /**
00504   * @brief Disable the PVM3 Event Line.
00505   * @retval None
00506   */
00507 #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
00508 
00509 /**
00510   * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
00511   * @retval None
00512   */
00513 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
00514 
00515 /**
00516   * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
00517   * @retval None
00518   */
00519 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
00520 
00521 /**
00522   * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
00523   * @retval None
00524   */
00525 #define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
00526 
00527 
00528 /**
00529   * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
00530   * @retval None
00531   */
00532 #define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
00533 
00534 
00535 /**
00536   * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
00537   * @retval None
00538   */
00539 #define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00540   do {                                                    \
00541     __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
00542     __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
00543   } while(0)
00544   
00545 /**
00546   * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
00547   * @retval None
00548   */
00549 #define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00550   do {                                                     \
00551     __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
00552     __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
00553   } while(0)
00554 
00555 /**
00556   * @brief  Generate a Software interrupt on selected EXTI line.
00557   * @retval None
00558   */
00559 #define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
00560 
00561 /**
00562   * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
00563   * @retval EXTI PVM3 Line Status.
00564   */
00565 #define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
00566 
00567 /**
00568   * @brief Clear the PVM3 EXTI flag.
00569   * @retval None
00570   */
00571 #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
00572 
00573 
00574 
00575 
00576 /**
00577   * @brief Enable the PVM4 Extended Interrupt Line.
00578   * @retval None
00579   */
00580 #define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
00581 
00582 /**
00583   * @brief Disable the PVM4 Extended Interrupt Line.
00584   * @retval None
00585   */
00586 #define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
00587 
00588 /**
00589   * @brief Enable the PVM4 Event Line.
00590   * @retval None
00591   */
00592 #define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
00593 
00594 /**
00595   * @brief Disable the PVM4 Event Line.
00596   * @retval None
00597   */
00598 #define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
00599 
00600 /**
00601   * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
00602   * @retval None
00603   */
00604 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
00605 
00606 /**
00607   * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
00608   * @retval None
00609   */
00610 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
00611 
00612 /**
00613   * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
00614   * @retval None
00615   */
00616 #define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
00617 
00618 
00619 /**
00620   * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
00621   * @retval None
00622   */
00623 #define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
00624 
00625 
00626 /**
00627   * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
00628   * @retval None
00629   */
00630 #define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
00631   do {                                                    \
00632     __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
00633     __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
00634   } while(0)
00635   
00636 /**
00637   * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
00638   * @retval None
00639   */
00640 #define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
00641   do {                                                     \
00642     __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
00643     __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
00644   } while(0)
00645 
00646 /**
00647   * @brief  Generate a Software interrupt on selected EXTI line.
00648   * @retval None
00649   */
00650 #define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
00651 
00652 /**
00653   * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
00654   * @retval EXTI PVM4 Line Status.
00655   */
00656 #define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
00657 
00658 /**
00659   * @brief Clear the PVM4 EXTI flag.
00660   * @retval None
00661   */
00662 #define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
00663 
00664 
00665 /**
00666   * @brief Configure the main internal regulator output voltage.
00667   * @param  __REGULATOR__: specifies the regulator output voltage to achieve
00668   *         a tradeoff between performance and power consumption.
00669   *          This parameter can be one of the following values:
00670   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
00671   *                                                typical output voltage at 1.2 V,  
00672   *                                                system frequency up to 80 MHz.
00673   *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
00674   *                                                typical output voltage at 1.0 V,                
00675   *                                                system frequency up to 26 MHz.  
00676   * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
00677   *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
00678   *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.   
00679   * @retval None
00680   */
00681 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
00682                                                             __IO uint32_t tmpreg;                               \
00683                                                             MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
00684                                                             /* Delay after an RCC peripheral clock enabling */  \
00685                                                             tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
00686                                                             UNUSED(tmpreg);                                     \
00687                                                           } while(0)
00688 
00689 /**
00690   * @}
00691   */
00692   
00693 /* Private macros --------------------------------------------------------*/
00694 /** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
00695   * @{
00696   */
00697 
00698 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
00699                                 ((PIN) == PWR_WAKEUP_PIN2) || \
00700                                 ((PIN) == PWR_WAKEUP_PIN3) || \
00701                                 ((PIN) == PWR_WAKEUP_PIN4) || \
00702                                 ((PIN) == PWR_WAKEUP_PIN5) || \
00703                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
00704                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
00705                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
00706                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
00707                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
00708                                 ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
00709                                 ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
00710                                 ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
00711                                 ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
00712                                 ((PIN) == PWR_WAKEUP_PIN5_LOW))
00713                                 
00714 #if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00715 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
00716                                ((TYPE) == PWR_PVM_2) ||\
00717                                ((TYPE) == PWR_PVM_3) ||\
00718                                ((TYPE) == PWR_PVM_4))
00719 #elif defined (STM32L471xx)
00720 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
00721                                ((TYPE) == PWR_PVM_3) ||\
00722                                ((TYPE) == PWR_PVM_4))
00723 #endif
00724 
00725 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
00726 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
00727                                ((TYPE) == PWR_PVM_3) ||\
00728                                ((TYPE) == PWR_PVM_4))
00729 #elif defined (STM32L431xx)
00730 #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_3) ||\
00731                                ((TYPE) == PWR_PVM_4))
00732 #endif                                  
00733 
00734 #define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
00735                                 ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
00736                                 ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
00737                                 ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
00738                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
00739                                 ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
00740                                 ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))  
00741                                 
00742 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
00743                                              ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
00744                                              
00745 #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
00746                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))  
00747                                                   
00748 #define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
00749                                            ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 
00750                                            
00751 #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
00752                                            
00753                              
00754 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00755 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00756                            ((GPIO) == PWR_GPIO_B) ||\
00757                            ((GPIO) == PWR_GPIO_C) ||\
00758                            ((GPIO) == PWR_GPIO_D) ||\
00759                            ((GPIO) == PWR_GPIO_E) ||\
00760                            ((GPIO) == PWR_GPIO_F) ||\
00761                            ((GPIO) == PWR_GPIO_G) ||\
00762                            ((GPIO) == PWR_GPIO_H))
00763 #endif
00764 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx)
00765 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00766                            ((GPIO) == PWR_GPIO_B) ||\
00767                            ((GPIO) == PWR_GPIO_C) ||\
00768                            ((GPIO) == PWR_GPIO_D) ||\
00769                            ((GPIO) == PWR_GPIO_E) ||\
00770                            ((GPIO) == PWR_GPIO_H))
00771 #elif defined (STM32L432xx) || defined (STM32L442xx)
00772 #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
00773                            ((GPIO) == PWR_GPIO_B) ||\
00774                            ((GPIO) == PWR_GPIO_C) ||\
00775                            ((GPIO) == PWR_GPIO_H))
00776 #endif
00777 
00778 
00779 /**
00780   * @}
00781   */  
00782   
00783 
00784 /** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
00785   * @{
00786   */
00787   
00788 /** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 
00789   * @{
00790   */
00791 
00792 
00793 /* Peripheral Control functions  **********************************************/
00794 uint32_t HAL_PWREx_GetVoltageRange(void);
00795 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
00796 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
00797 void HAL_PWREx_DisableBatteryCharging(void);
00798 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00799 void HAL_PWREx_EnableVddUSB(void);
00800 void HAL_PWREx_DisableVddUSB(void);
00801 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00802 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00803 void HAL_PWREx_EnableVddIO2(void);
00804 void HAL_PWREx_DisableVddIO2(void);
00805 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00806 void HAL_PWREx_EnableInternalWakeUpLine(void);
00807 void HAL_PWREx_DisableInternalWakeUpLine(void);
00808 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00809 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
00810 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00811 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
00812 void HAL_PWREx_EnablePullUpPullDownConfig(void);
00813 void HAL_PWREx_DisablePullUpPullDownConfig(void);
00814 void HAL_PWREx_EnableSRAM2ContentRetention(void);
00815 void HAL_PWREx_DisableSRAM2ContentRetention(void);
00816 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00817 void HAL_PWREx_EnablePVM1(void);
00818 void HAL_PWREx_DisablePVM1(void);
00819 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00820 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00821 void HAL_PWREx_EnablePVM2(void);
00822 void HAL_PWREx_DisablePVM2(void);
00823 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00824 void HAL_PWREx_EnablePVM3(void);
00825 void HAL_PWREx_DisablePVM3(void);
00826 void HAL_PWREx_EnablePVM4(void);
00827 void HAL_PWREx_DisablePVM4(void);
00828 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
00829 
00830 
00831 /* Low Power modes configuration functions ************************************/
00832 void HAL_PWREx_EnableLowPowerRunMode(void);
00833 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
00834 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
00835 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
00836 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
00837 void HAL_PWREx_EnterSHUTDOWNMode(void);
00838 
00839 void HAL_PWREx_PVD_PVM_IRQHandler(void);
00840 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00841 void HAL_PWREx_PVM1Callback(void);
00842 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00843 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
00844 void HAL_PWREx_PVM2Callback(void);
00845 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
00846 void HAL_PWREx_PVM3Callback(void);
00847 void HAL_PWREx_PVM4Callback(void);
00848 
00849 
00850 /**
00851   * @}
00852   */
00853 
00854 /**
00855   * @}
00856   */
00857 
00858 /**
00859   * @}
00860   */
00861 
00862 /**
00863   * @}
00864   */
00865 
00866 #ifdef __cplusplus
00867 }
00868 #endif
00869 
00870 
00871 #endif /* __STM32L4xx_HAL_PWR_EX_H */
00872 
00873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/