stm32l4xx_hal_i2c.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_i2c.c
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   I2C HAL module driver.
00008   *          This file provides firmware functions to manage the following
00009   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
00010   *           + Initialization and de-initialization functions
00011   *           + IO operation functions
00012   *           + Peripheral State and Errors functions
00013   *
00014   @verbatim
00015   ==============================================================================
00016                         ##### How to use this driver #####
00017   ==============================================================================
00018     [..]
00019     The I2C HAL driver can be used as follows:
00020 
00021     (#) Declare a I2C_HandleTypeDef handle structure, for example:
00022         I2C_HandleTypeDef  hi2c;
00023 
00024     (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
00025         (##) Enable the I2Cx interface clock
00026         (##) I2C pins configuration
00027             (+++) Enable the clock for the I2C GPIOs
00028             (+++) Configure I2C pins as alternate function open-drain
00029         (##) NVIC configuration if you need to use interrupt process
00030             (+++) Configure the I2Cx interrupt priority
00031             (+++) Enable the NVIC I2C IRQ Channel
00032         (##) DMA Configuration if you need to use DMA process
00033             (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
00034             (+++) Enable the DMAx interface clock using
00035             (+++) Configure the DMA handle parameters
00036             (+++) Configure the DMA Tx or Rx channel
00037             (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
00038             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
00039                   the DMA Tx or Rx channel
00040 
00041     (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
00042         Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
00043 
00044     (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
00045         (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
00046 
00047     (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
00048 
00049     (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
00050 
00051     *** Polling mode IO operation ***
00052     =================================
00053     [..]
00054       (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
00055       (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
00056       (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
00057       (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
00058 
00059     *** Polling mode IO MEM operation ***
00060     =====================================
00061     [..]
00062       (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
00063       (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
00064 
00065 
00066     *** Interrupt mode IO operation ***
00067     ===================================
00068     [..]
00069       (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
00070       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00071            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00072       (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
00073       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00074            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00075       (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
00076       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00077            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00078       (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
00079       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00080            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00081       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00082            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00083       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00084       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00085            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00086       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00087            This action will inform Master to generate a Stop condition to discard the communication.
00088 
00089 
00090     *** Interrupt mode IO sequential operation ***
00091     ===================================
00092     [..]
00093       (@) These interfaces allow to manage a sequential transfer with a repeated start condition
00094           when a direction change during transfer
00095     [..]
00096       (+) A specific option field manage the different steps of a sequential transfer
00097       (+) Option field values are defined through I2C_XFEROPTIONS and are listed below:
00098       (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
00099       (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
00100                             and data to transfer without a final stop condition
00101       (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
00102                             and with new data to transfer if the direction change or manage only the new data to transfer
00103                             if no direction change and without a final stop condition in both cases
00104       (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
00105                             and with new data to transfer if the direction change or manage only the new data to transfer
00106                             if no direction change and with a final stop condition in both cases
00107 
00108       (+) Differents sequential I2C interfaces are listed below:
00109       (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
00110       (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00111            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00112       (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
00113       (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00114            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00115       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00116       (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00117            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00118       (+++) mean HAL_I2C_MasterTxCpltCallback() in case of previous state was master transmit
00119       (+++) mean HAL_I2c_MasterRxCpltCallback() in case of previous state was master receive
00120       (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
00121       (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
00122            add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
00123       (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
00124            add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
00125       (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
00126       (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00127            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00128       (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
00129       (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00130            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00131       (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00132            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00133       (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00134       (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00135            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00136       (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00137            This action will inform Master to generate a Stop condition to discard the communication.
00138 
00139     *** Interrupt mode IO MEM operation ***
00140     =======================================
00141     [..]
00142       (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
00143           HAL_I2C_Mem_Write_IT()
00144       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00145            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00146       (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
00147           HAL_I2C_Mem_Read_IT()
00148       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00149            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00150       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00151            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00152 
00153     *** DMA mode IO operation ***
00154     ==============================
00155     [..]
00156       (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
00157           HAL_I2C_Master_Transmit_DMA()
00158       (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
00159            add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
00160       (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
00161           HAL_I2C_Master_Receive_DMA()
00162       (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
00163            add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
00164       (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
00165           HAL_I2C_Slave_Transmit_DMA()
00166       (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
00167            add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
00168       (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
00169           HAL_I2C_Slave_Receive_DMA()
00170       (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
00171            add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
00172       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00173            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00174       (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
00175       (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
00176            add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
00177       (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
00178            This action will inform Master to generate a Stop condition to discard the communication.
00179 
00180     *** DMA mode IO MEM operation ***
00181     =================================
00182     [..]
00183       (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
00184           HAL_I2C_Mem_Write_DMA()
00185       (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
00186            add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
00187       (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
00188           HAL_I2C_Mem_Read_DMA()
00189       (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
00190            add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
00191       (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
00192            add his own code by customization of function pointer HAL_I2C_ErrorCallback()
00193 
00194 
00195      *** I2C HAL driver macros list ***
00196      ==================================
00197      [..]
00198        Below the list of most used macros in I2C HAL driver.
00199 
00200       (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
00201       (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
00202       (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
00203       (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
00204       (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
00205       (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
00206       (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
00207 
00208      [..]
00209        (@) You can refer to the I2C HAL driver header file for more useful macros
00210 
00211   @endverbatim
00212   ******************************************************************************
00213   * @attention
00214   *
00215   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00216   *
00217   * Redistribution and use in source and binary forms, with or without modification,
00218   * are permitted provided that the following conditions are met:
00219   *   1. Redistributions of source code must retain the above copyright notice,
00220   *      this list of conditions and the following disclaimer.
00221   *   2. Redistributions in binary form must reproduce the above copyright notice,
00222   *      this list of conditions and the following disclaimer in the documentation
00223   *      and/or other materials provided with the distribution.
00224   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00225   *      may be used to endorse or promote products derived from this software
00226   *      without specific prior written permission.
00227   *
00228   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00229   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00230   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00231   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00232   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00233   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00234   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00235   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00236   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00237   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00238   *
00239   ******************************************************************************
00240   */ 
00241 
00242 /* Includes ------------------------------------------------------------------*/
00243 #include "stm32l4xx_hal.h"
00244 
00245 /** @addtogroup STM32L4xx_HAL_Driver
00246   * @{
00247   */
00248 
00249 /** @defgroup I2C I2C
00250   * @brief I2C HAL module driver
00251   * @{
00252   */
00253 
00254 #ifdef HAL_I2C_MODULE_ENABLED
00255 
00256 /* Private typedef -----------------------------------------------------------*/
00257 /* Private define ------------------------------------------------------------*/
00258 
00259 /** @defgroup I2C_Private_Define I2C Private Define
00260   * @{
00261   */
00262 #define TIMING_CLEAR_MASK   (0xF0FFFFFFU)  /*!< I2C TIMING clear register Mask */
00263 #define I2C_TIMEOUT_ADDR    (10000U)       /*!< 10 s  */
00264 #define I2C_TIMEOUT_BUSY    (25U)          /*!< 25 ms */
00265 #define I2C_TIMEOUT_DIR     (25U)          /*!< 25 ms */
00266 #define I2C_TIMEOUT_RXNE    (25U)          /*!< 25 ms */
00267 #define I2C_TIMEOUT_STOPF   (25U)          /*!< 25 ms */
00268 #define I2C_TIMEOUT_TC      (25U)          /*!< 25 ms */
00269 #define I2C_TIMEOUT_TCR     (25U)          /*!< 25 ms */
00270 #define I2C_TIMEOUT_TXIS    (25U)          /*!< 25 ms */
00271 #define I2C_TIMEOUT_FLAG    (25U)          /*!< 25 ms */
00272 
00273 #define MAX_NBYTE_SIZE      255U
00274 #define SlaveAddr_SHIFT     7U
00275 #define SlaveAddr_MSK       0x06U
00276 
00277 /* Private define for @ref PreviousState usage */
00278 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */
00279 #define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */
00280 #define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */
00281 #define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */
00282 #define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */
00283 #define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */
00284 #define I2C_STATE_MEM_BUSY_TX     ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
00285 #define I2C_STATE_MEM_BUSY_RX     ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM))               /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
00286 
00287 
00288 /* Private define to centralize the enable/disable of Interrupts */
00289 #define I2C_XFER_TX_IT          (0x00000001U)
00290 #define I2C_XFER_RX_IT          (0x00000002U)
00291 #define I2C_XFER_LISTEN_IT      (0x00000004U)
00292 
00293 #define I2C_XFER_ERROR_IT       (0x00000011U)
00294 #define I2C_XFER_CPLT_IT        (0x00000012U)
00295 #define I2C_XFER_RELOAD_IT      (0x00000012U)
00296 /**
00297   * @}
00298   */
00299 
00300 /* Private macro -------------------------------------------------------------*/
00301 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX)   ? \
00302                                             ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \
00303                                             ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR)))
00304 
00305 /* Private variables ---------------------------------------------------------*/
00306 /* Private function prototypes -----------------------------------------------*/
00307 
00308 /** @defgroup I2C_Private_Functions I2C Private Functions
00309   * @{
00310   */
00311 /* Private functions to handle DMA transfer */
00312 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
00313 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
00314 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
00315 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
00316 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
00317 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
00318 
00319 /* Private functions to handle IT transfer */
00320 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00321 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
00322 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
00323 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00324 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00325 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
00326 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
00327 
00328 /* Private functions to handle IT transfer */
00329 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00330 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
00331 
00332 /* Private functions for I2C transfer IRQ handler */
00333 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00334 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00335 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00336 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
00337 
00338 /* Private functions to handle flags during polling transfer */
00339 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
00340 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00341 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00342 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00343 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
00344 
00345 /* Private functions to centralize the enable/disable of Interrupts */
00346 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00347 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
00348 
00349 /* Private functions to flush TXDR register */
00350 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
00351 
00352 /* Private functions to handle  start, restart or stop a transfer */
00353 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
00354 /**
00355   * @}
00356   */
00357 
00358 /* Exported functions --------------------------------------------------------*/
00359 
00360 /** @defgroup I2C_Exported_Functions I2C Exported Functions
00361   * @{
00362   */
00363 
00364 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
00365  *  @brief    Initialization and Configuration functions 
00366  *
00367 @verbatim
00368  ===============================================================================
00369               ##### Initialization and de-initialization functions #####
00370  ===============================================================================
00371     [..]  This subsection provides a set of functions allowing to initialize and
00372           deinitialize the I2Cx peripheral:
00373 
00374       (+) User must Implement HAL_I2C_MspInit() function in which he configures
00375           all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
00376 
00377       (+) Call the function HAL_I2C_Init() to configure the selected device with
00378           the selected configuration:
00379         (++) Clock Timing
00380         (++) Own Address 1
00381         (++) Addressing mode (Master, Slave)
00382         (++) Dual Addressing mode
00383         (++) Own Address 2
00384         (++) Own Address 2 Mask
00385         (++) General call mode
00386         (++) Nostretch mode
00387 
00388       (+) Call the function HAL_I2C_DeInit() to restore the default configuration
00389           of the selected I2Cx peripheral.
00390 
00391 @endverbatim
00392   * @{
00393   */
00394 
00395 /**
00396   * @brief  Initializes the I2C according to the specified parameters
00397   *         in the I2C_InitTypeDef and initialize the associated handle.
00398   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00399   *                the configuration information for the specified I2C.
00400   * @retval HAL status
00401   */
00402 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
00403 {
00404   /* Check the I2C handle allocation */
00405   if(hi2c == NULL)
00406   {
00407     return HAL_ERROR;
00408   }
00409 
00410   /* Check the parameters */
00411   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00412   assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
00413   assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
00414   assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
00415   assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
00416   assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
00417   assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
00418   assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
00419 
00420   if(hi2c->State == HAL_I2C_STATE_RESET)
00421   {
00422     /* Allocate lock resource and initialize it */
00423     hi2c->Lock = HAL_UNLOCKED;
00424 
00425     /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
00426     HAL_I2C_MspInit(hi2c);
00427   }
00428 
00429   hi2c->State = HAL_I2C_STATE_BUSY;
00430 
00431   /* Disable the selected I2C peripheral */
00432   __HAL_I2C_DISABLE(hi2c);
00433 
00434   /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
00435   /* Configure I2Cx: Frequency range */
00436   hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
00437 
00438   /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
00439   /* Configure I2Cx: Own Address1 and ack own address1 mode */
00440   hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
00441   if(hi2c->Init.OwnAddress1 != 0U)
00442   {
00443     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
00444     {
00445       hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
00446     }
00447     else /* I2C_ADDRESSINGMODE_10BIT */
00448     {
00449       hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
00450     }
00451   }
00452 
00453   /*---------------------------- I2Cx CR2 Configuration ----------------------*/
00454   /* Configure I2Cx: Addressing Master mode */
00455   if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00456   {
00457     hi2c->Instance->CR2 = (I2C_CR2_ADD10);
00458   }
00459   /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
00460   hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
00461 
00462   /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
00463   /* Configure I2Cx: Dual mode and Own Address2 */
00464   hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
00465 
00466   /*---------------------------- I2Cx CR1 Configuration ----------------------*/
00467   /* Configure I2Cx: Generalcall and NoStretch mode */
00468   hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
00469 
00470   /* Enable the selected I2C peripheral */
00471   __HAL_I2C_ENABLE(hi2c);
00472 
00473   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00474   hi2c->State = HAL_I2C_STATE_READY;
00475   hi2c->PreviousState = I2C_STATE_NONE;
00476   hi2c->Mode = HAL_I2C_MODE_NONE;
00477 
00478   return HAL_OK;
00479 }
00480 
00481 /**
00482   * @brief  DeInitialize the I2C peripheral.
00483   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00484   *                the configuration information for the specified I2C.
00485   * @retval HAL status
00486   */
00487 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
00488 {
00489   /* Check the I2C handle allocation */
00490   if(hi2c == NULL)
00491   {
00492     return HAL_ERROR;
00493   }
00494 
00495   /* Check the parameters */
00496   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
00497 
00498   hi2c->State = HAL_I2C_STATE_BUSY;
00499 
00500   /* Disable the I2C Peripheral Clock */
00501   __HAL_I2C_DISABLE(hi2c);
00502 
00503   /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
00504   HAL_I2C_MspDeInit(hi2c);
00505 
00506   hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00507   hi2c->State = HAL_I2C_STATE_RESET;
00508   hi2c->PreviousState = I2C_STATE_NONE;
00509   hi2c->Mode = HAL_I2C_MODE_NONE;
00510 
00511   /* Release Lock */
00512   __HAL_UNLOCK(hi2c);
00513 
00514   return HAL_OK;
00515 }
00516 
00517 /**
00518   * @brief Initialize the I2C MSP.
00519   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00520   *                the configuration information for the specified I2C.
00521   * @retval None
00522   */
00523 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
00524 {
00525   /* Prevent unused argument(s) compilation warning */
00526   UNUSED(hi2c);
00527 
00528   /* NOTE : This function should not be modified, when the callback is needed,
00529             the HAL_I2C_MspInit could be implemented in the user file
00530    */
00531 }
00532 
00533 /**
00534   * @brief DeInitialize the I2C MSP.
00535   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00536   *                the configuration information for the specified I2C.
00537   * @retval None
00538   */
00539 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
00540 {
00541   /* Prevent unused argument(s) compilation warning */
00542   UNUSED(hi2c);
00543 
00544   /* NOTE : This function should not be modified, when the callback is needed,
00545             the HAL_I2C_MspDeInit could be implemented in the user file
00546    */
00547 }
00548 
00549 /**
00550   * @}
00551   */
00552 
00553 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
00554  *  @brief   Data transfers functions 
00555  *
00556 @verbatim
00557  ===============================================================================
00558                       ##### IO operation functions #####
00559  ===============================================================================
00560     [..]
00561     This subsection provides a set of functions allowing to manage the I2C data
00562     transfers.
00563 
00564     (#) There are two modes of transfer:
00565        (++) Blocking mode : The communication is performed in the polling mode.
00566             The status of all data processing is returned by the same function 
00567             after finishing transfer.
00568        (++) No-Blocking mode : The communication is performed using Interrupts
00569             or DMA. These functions return the status of the transfer startup.
00570             The end of the data processing will be indicated through the
00571             dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
00572             using DMA mode.
00573 
00574     (#) Blocking mode functions are :
00575         (++) HAL_I2C_Master_Transmit()
00576         (++) HAL_I2C_Master_Receive()
00577         (++) HAL_I2C_Slave_Transmit()
00578         (++) HAL_I2C_Slave_Receive()
00579         (++) HAL_I2C_Mem_Write()
00580         (++) HAL_I2C_Mem_Read()
00581         (++) HAL_I2C_IsDeviceReady()
00582 
00583     (#) No-Blocking mode functions with Interrupt are :
00584         (++) HAL_I2C_Master_Transmit_IT()
00585         (++) HAL_I2C_Master_Receive_IT()
00586         (++) HAL_I2C_Slave_Transmit_IT()
00587         (++) HAL_I2C_Slave_Receive_IT()
00588         (++) HAL_I2C_Mem_Write_IT()
00589         (++) HAL_I2C_Mem_Read_IT()
00590 
00591     (#) No-Blocking mode functions with DMA are :
00592         (++) HAL_I2C_Master_Transmit_DMA()
00593         (++) HAL_I2C_Master_Receive_DMA()
00594         (++) HAL_I2C_Slave_Transmit_DMA()
00595         (++) HAL_I2C_Slave_Receive_DMA()
00596         (++) HAL_I2C_Mem_Write_DMA()
00597         (++) HAL_I2C_Mem_Read_DMA()
00598 
00599     (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
00600         (++) HAL_I2C_MemTxCpltCallback()
00601         (++) HAL_I2C_MemRxCpltCallback()
00602         (++) HAL_I2C_MasterTxCpltCallback()
00603         (++) HAL_I2C_MasterRxCpltCallback()
00604         (++) HAL_I2C_SlaveTxCpltCallback()
00605         (++) HAL_I2C_SlaveRxCpltCallback()
00606         (++) HAL_I2C_ErrorCallback()
00607 
00608 @endverbatim
00609   * @{
00610   */
00611 
00612 /**
00613   * @brief  Transmits in master mode an amount of data in blocking mode.
00614   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00615   *                the configuration information for the specified I2C.
00616   * @param  DevAddress Target device address
00617   * @param  pData Pointer to data buffer
00618   * @param  Size Amount of data to be sent
00619   * @param  Timeout Timeout duration
00620   * @retval HAL status
00621   */
00622 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00623 {
00624   uint32_t tickstart = 0U;
00625 
00626   if(hi2c->State == HAL_I2C_STATE_READY)
00627   {
00628     /* Process Locked */
00629     __HAL_LOCK(hi2c);
00630 
00631     /* Init tickstart for timeout management*/
00632     tickstart = HAL_GetTick();
00633 
00634     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00635     {
00636       return HAL_TIMEOUT;
00637     }
00638 
00639     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00640     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00641     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00642     
00643     /* Prepare transfer parameters */
00644     hi2c->pBuffPtr  = pData;
00645     hi2c->XferCount = Size;
00646     hi2c->XferISR   = NULL;
00647 
00648     /* Send Slave Address */
00649     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00650     if(hi2c->XferCount > MAX_NBYTE_SIZE)
00651     {
00652       hi2c->XferSize = MAX_NBYTE_SIZE;
00653       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
00654     }
00655     else
00656     {
00657       hi2c->XferSize = hi2c->XferCount;
00658       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
00659     }
00660 
00661     while(hi2c->XferCount > 0U)
00662     {
00663       /* Wait until TXIS flag is set */
00664       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00665       {
00666         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00667         {
00668           return HAL_ERROR;
00669         }
00670         else
00671         {
00672           return HAL_TIMEOUT;
00673         }
00674       }
00675       /* Write data to TXDR */
00676       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00677       hi2c->XferCount--;
00678       hi2c->XferSize--;
00679 
00680       if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
00681       {
00682         /* Wait until TCR flag is set */
00683         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00684         {
00685           return HAL_TIMEOUT;
00686         }
00687 
00688         if(hi2c->XferCount > MAX_NBYTE_SIZE)
00689         {
00690           hi2c->XferSize = MAX_NBYTE_SIZE;
00691           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00692         }
00693         else
00694         {
00695           hi2c->XferSize = hi2c->XferCount;
00696           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00697         }
00698       }
00699     }
00700 
00701     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00702     /* Wait until STOPF flag is set */
00703     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00704     {
00705       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00706       {
00707         return HAL_ERROR;
00708       }
00709       else
00710       {
00711         return HAL_TIMEOUT;
00712       }
00713     }
00714 
00715     /* Clear STOP Flag */
00716     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00717 
00718     /* Clear Configuration Register 2 */
00719     I2C_RESET_CR2(hi2c);
00720 
00721     hi2c->State = HAL_I2C_STATE_READY;
00722     hi2c->Mode  = HAL_I2C_MODE_NONE;
00723 
00724     /* Process Unlocked */
00725     __HAL_UNLOCK(hi2c);
00726 
00727     return HAL_OK;
00728   }
00729   else
00730   {
00731     return HAL_BUSY;
00732   }
00733 }
00734 
00735 /**
00736   * @brief  Receives in master mode an amount of data in blocking mode.
00737   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00738   *                the configuration information for the specified I2C.
00739   * @param  DevAddress Target device address
00740   * @param  pData Pointer to data buffer
00741   * @param  Size Amount of data to be sent
00742   * @param  Timeout Timeout duration
00743   * @retval HAL status
00744   */
00745 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00746 {
00747   uint32_t tickstart = 0U;
00748 
00749   if(hi2c->State == HAL_I2C_STATE_READY)
00750   {    
00751     /* Process Locked */
00752     __HAL_LOCK(hi2c);
00753 
00754     /* Init tickstart for timeout management*/
00755     tickstart = HAL_GetTick();
00756 
00757     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
00758     {
00759       return HAL_TIMEOUT;
00760     }
00761 
00762     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
00763     hi2c->Mode      = HAL_I2C_MODE_MASTER;
00764     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00765 
00766     /* Prepare transfer parameters */
00767     hi2c->pBuffPtr  = pData;
00768     hi2c->XferCount = Size;
00769     hi2c->XferISR   = NULL;
00770 
00771     /* Send Slave Address */
00772     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
00773     if(hi2c->XferCount > MAX_NBYTE_SIZE)
00774     {
00775       hi2c->XferSize = MAX_NBYTE_SIZE;
00776       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
00777     }
00778     else
00779     {
00780       hi2c->XferSize = hi2c->XferCount;
00781       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
00782     }
00783 
00784     while(hi2c->XferCount > 0U)
00785     {
00786       /* Wait until RXNE flag is set */
00787       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00788       {
00789         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00790         {
00791           return HAL_ERROR;
00792         }
00793         else
00794         {
00795           return HAL_TIMEOUT;
00796         }
00797       }
00798 
00799       /* Read data from RXDR */
00800       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
00801       hi2c->XferSize--;
00802       hi2c->XferCount--;
00803 
00804       if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
00805       {
00806         /* Wait until TCR flag is set */
00807         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
00808         {
00809           return HAL_TIMEOUT;
00810         }
00811 
00812         if(hi2c->XferCount > MAX_NBYTE_SIZE)
00813         {
00814           hi2c->XferSize = MAX_NBYTE_SIZE;
00815           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
00816         }
00817         else
00818         {
00819           hi2c->XferSize = hi2c->XferCount;
00820           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
00821         }
00822       }
00823     }
00824 
00825     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
00826     /* Wait until STOPF flag is set */
00827     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00828     {
00829       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00830       {
00831         return HAL_ERROR;
00832       }
00833       else
00834       {
00835         return HAL_TIMEOUT;
00836       }
00837     }
00838     
00839     /* Clear STOP Flag */
00840     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
00841 
00842     /* Clear Configuration Register 2 */
00843     I2C_RESET_CR2(hi2c);
00844 
00845     hi2c->State = HAL_I2C_STATE_READY;
00846     hi2c->Mode  = HAL_I2C_MODE_NONE;
00847 
00848     /* Process Unlocked */
00849     __HAL_UNLOCK(hi2c);
00850 
00851     return HAL_OK;
00852   }
00853   else
00854   {
00855     return HAL_BUSY;
00856   }
00857 }
00858 
00859 /**
00860   * @brief  Transmits in slave mode an amount of data in blocking mode. 
00861   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
00862   *                the configuration information for the specified I2C.
00863   * @param  pData Pointer to data buffer
00864   * @param  Size Amount of data to be sent
00865   * @param  Timeout Timeout duration
00866   * @retval HAL status
00867   */
00868 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
00869 {
00870   uint32_t tickstart = 0U;
00871 
00872   if(hi2c->State == HAL_I2C_STATE_READY)
00873   {
00874     if((pData == NULL) || (Size == 0U))
00875     {
00876       return  HAL_ERROR;
00877     }
00878     /* Process Locked */
00879     __HAL_LOCK(hi2c);
00880     
00881     /* Init tickstart for timeout management*/
00882     tickstart = HAL_GetTick();
00883 
00884     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
00885     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
00886     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00887 
00888     /* Prepare transfer parameters */
00889     hi2c->pBuffPtr  = pData;
00890     hi2c->XferCount = Size;
00891     hi2c->XferISR   = NULL;
00892 
00893     /* Enable Address Acknowledge */
00894     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
00895 
00896     /* Wait until ADDR flag is set */
00897     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00898     {
00899       /* Disable Address Acknowledge */
00900       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00901       return HAL_TIMEOUT;
00902     }
00903 
00904     /* Clear ADDR flag */
00905     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00906 
00907     /* If 10bit addressing mode is selected */
00908     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
00909     {
00910       /* Wait until ADDR flag is set */
00911       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
00912       {
00913         /* Disable Address Acknowledge */
00914         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00915         return HAL_TIMEOUT;
00916       }
00917 
00918       /* Clear ADDR flag */
00919       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
00920     }
00921 
00922     /* Wait until DIR flag is set Transmitter mode */
00923     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
00924     {
00925       /* Disable Address Acknowledge */
00926       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00927       return HAL_TIMEOUT;
00928     }
00929 
00930     while(hi2c->XferCount > 0U)
00931     {
00932       /* Wait until TXIS flag is set */
00933       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00934       {
00935         /* Disable Address Acknowledge */
00936         hi2c->Instance->CR2 |= I2C_CR2_NACK;
00937 
00938         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00939         {
00940           return HAL_ERROR;
00941         }
00942         else
00943         {
00944           return HAL_TIMEOUT;
00945         }
00946       }
00947 
00948       /* Write data to TXDR */
00949       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
00950       hi2c->XferCount--;
00951     }
00952 
00953     /* Wait until STOP flag is set */
00954     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
00955     {
00956       /* Disable Address Acknowledge */
00957       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00958 
00959       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
00960       {
00961     /* Normal use case for Transmitter mode */
00962     /* A NACK is generated to confirm the end of transfer */
00963     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
00964       }
00965       else
00966       {
00967         return HAL_TIMEOUT;
00968       }
00969     }
00970 
00971     /* Clear STOP flag */
00972     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
00973 
00974     /* Wait until BUSY flag is reset */ 
00975     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
00976     {
00977       /* Disable Address Acknowledge */
00978       hi2c->Instance->CR2 |= I2C_CR2_NACK;
00979       return HAL_TIMEOUT;
00980     }
00981 
00982     /* Disable Address Acknowledge */
00983     hi2c->Instance->CR2 |= I2C_CR2_NACK;
00984 
00985     hi2c->State = HAL_I2C_STATE_READY;
00986     hi2c->Mode  = HAL_I2C_MODE_NONE;
00987 
00988     /* Process Unlocked */
00989     __HAL_UNLOCK(hi2c);
00990 
00991     return HAL_OK;
00992   }
00993   else
00994   {
00995     return HAL_BUSY;
00996   }
00997 }
00998 
00999 /**
01000   * @brief  Receive in slave mode an amount of data in blocking mode
01001   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01002   *                the configuration information for the specified I2C.
01003   * @param  pData Pointer to data buffer
01004   * @param  Size Amount of data to be sent
01005   * @param  Timeout Timeout duration
01006   * @retval HAL status
01007   */
01008 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01009 {
01010   uint32_t tickstart = 0U;
01011 
01012   if(hi2c->State == HAL_I2C_STATE_READY)
01013   {  
01014     if((pData == NULL) || (Size == 0U))
01015     {
01016       return  HAL_ERROR;
01017     }
01018     /* Process Locked */
01019     __HAL_LOCK(hi2c);
01020 
01021     /* Init tickstart for timeout management*/
01022     tickstart = HAL_GetTick();
01023 
01024     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01025     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
01026     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01027 
01028     /* Prepare transfer parameters */
01029     hi2c->pBuffPtr  = pData;
01030     hi2c->XferCount = Size;
01031     hi2c->XferISR   = NULL;
01032 
01033     /* Enable Address Acknowledge */
01034     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01035 
01036     /* Wait until ADDR flag is set */
01037     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
01038     {
01039       /* Disable Address Acknowledge */
01040       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01041       return HAL_TIMEOUT;
01042     }
01043 
01044     /* Clear ADDR flag */
01045     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
01046 
01047     /* Wait until DIR flag is reset Receiver mode */
01048     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
01049     {
01050       /* Disable Address Acknowledge */
01051       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01052       return HAL_TIMEOUT;
01053     }
01054 
01055     while(hi2c->XferCount > 0U)
01056     {
01057       /* Wait until RXNE flag is set */
01058       if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01059       {
01060         /* Disable Address Acknowledge */
01061         hi2c->Instance->CR2 |= I2C_CR2_NACK;
01062 
01063         /* Store Last receive data if any */
01064         if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
01065         {
01066           /* Read data from RXDR */
01067           (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01068           hi2c->XferCount--;
01069         }
01070 
01071         if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
01072         {
01073           return HAL_TIMEOUT;
01074         }
01075         else
01076         {
01077           return HAL_ERROR;
01078         }
01079       }
01080 
01081       /* Read data from RXDR */
01082       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01083       hi2c->XferCount--;
01084     }
01085 
01086     /* Wait until STOP flag is set */
01087     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01088     {
01089       /* Disable Address Acknowledge */
01090       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01091 
01092       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01093       {
01094         return HAL_ERROR;
01095       }
01096       else
01097       {
01098         return HAL_TIMEOUT;
01099       }
01100     }
01101 
01102     /* Clear STOP flag */
01103     __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
01104 
01105     /* Wait until BUSY flag is reset */
01106     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
01107     {
01108       /* Disable Address Acknowledge */
01109       hi2c->Instance->CR2 |= I2C_CR2_NACK;
01110       return HAL_TIMEOUT;
01111     }
01112 
01113     /* Disable Address Acknowledge */
01114     hi2c->Instance->CR2 |= I2C_CR2_NACK;
01115 
01116     hi2c->State = HAL_I2C_STATE_READY;
01117     hi2c->Mode  = HAL_I2C_MODE_NONE;
01118 
01119     /* Process Unlocked */
01120     __HAL_UNLOCK(hi2c);
01121 
01122     return HAL_OK;
01123   }
01124   else
01125   {
01126     return HAL_BUSY;
01127   }
01128 }
01129 
01130 /**
01131   * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt
01132   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01133   *                the configuration information for the specified I2C.
01134   * @param  DevAddress Target device address
01135   * @param  pData Pointer to data buffer
01136   * @param  Size Amount of data to be sent
01137   * @retval HAL status
01138   */
01139 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01140 {
01141   uint32_t xfermode = 0U;
01142 
01143   if(hi2c->State == HAL_I2C_STATE_READY)
01144   {
01145     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01146     {
01147       return HAL_BUSY;
01148     }
01149 
01150     /* Process Locked */
01151     __HAL_LOCK(hi2c);
01152 
01153     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01154     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01155     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01156 
01157     /* Prepare transfer parameters */
01158     hi2c->pBuffPtr    = pData;
01159     hi2c->XferCount   = Size;
01160     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01161     hi2c->XferISR     = I2C_Master_ISR_IT;
01162     
01163     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01164     {
01165       hi2c->XferSize = MAX_NBYTE_SIZE;
01166       xfermode = I2C_RELOAD_MODE;
01167     }
01168     else
01169     {
01170       hi2c->XferSize = hi2c->XferCount;
01171       xfermode = I2C_AUTOEND_MODE;
01172     }
01173 
01174     /* Send Slave Address */
01175     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01176     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01177 
01178     /* Process Unlocked */
01179     __HAL_UNLOCK(hi2c); 
01180 
01181     /* Note : The I2C interrupts must be enabled after unlocking current process
01182               to avoid the risk of I2C interrupt handle execution before current
01183               process unlock */
01184 
01185     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01186     /* possible to enable all of these */
01187     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01188     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01189 
01190     return HAL_OK;
01191   }
01192   else
01193   {
01194     return HAL_BUSY;
01195   }
01196 }
01197 
01198 /**
01199   * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt
01200   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01201   *                the configuration information for the specified I2C.
01202   * @param  DevAddress Target device address
01203   * @param  pData Pointer to data buffer
01204   * @param  Size Amount of data to be sent
01205   * @retval HAL status
01206   */
01207 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01208 {
01209   uint32_t xfermode = 0U;
01210 
01211   if(hi2c->State == HAL_I2C_STATE_READY)
01212   {
01213     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01214     {
01215       return HAL_BUSY;
01216     }
01217 
01218     /* Process Locked */
01219     __HAL_LOCK(hi2c);
01220 
01221     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01222     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01223     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01224 
01225     /* Prepare transfer parameters */
01226     hi2c->pBuffPtr    = pData;
01227     hi2c->XferCount   = Size;
01228     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01229     hi2c->XferISR     = I2C_Master_ISR_IT;
01230     
01231     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01232     {
01233       hi2c->XferSize = MAX_NBYTE_SIZE;
01234       xfermode = I2C_RELOAD_MODE;
01235     }
01236     else
01237     {
01238       hi2c->XferSize = hi2c->XferCount;
01239       xfermode = I2C_AUTOEND_MODE;
01240     }
01241 
01242     /* Send Slave Address */
01243     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01244     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01245     
01246     /* Process Unlocked */
01247     __HAL_UNLOCK(hi2c);
01248 
01249     /* Note : The I2C interrupts must be enabled after unlocking current process
01250               to avoid the risk of I2C interrupt handle execution before current
01251               process unlock */
01252 
01253     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01254     /* possible to enable all of these */
01255     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01256     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
01257 
01258     return HAL_OK;
01259   }
01260   else
01261   {
01262     return HAL_BUSY;
01263   }
01264 }
01265 
01266 /**
01267   * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt
01268   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01269   *                the configuration information for the specified I2C.
01270   * @param  pData Pointer to data buffer
01271   * @param  Size Amount of data to be sent
01272   * @retval HAL status
01273   */
01274 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01275 {
01276   if(hi2c->State == HAL_I2C_STATE_READY)
01277   {
01278     /* Process Locked */
01279     __HAL_LOCK(hi2c);
01280 
01281     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01282     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01283     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01284 
01285     /* Enable Address Acknowledge */
01286     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01287 
01288     /* Prepare transfer parameters */
01289     hi2c->pBuffPtr    = pData;
01290     hi2c->XferCount   = Size;
01291     hi2c->XferSize    = hi2c->XferCount;
01292     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01293     hi2c->XferISR     = I2C_Slave_ISR_IT;
01294 
01295     /* Process Unlocked */
01296     __HAL_UNLOCK(hi2c);
01297 
01298     /* Note : The I2C interrupts must be enabled after unlocking current process
01299               to avoid the risk of I2C interrupt handle execution before current
01300               process unlock */
01301 
01302     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01303     /* possible to enable all of these */
01304     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01305     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
01306 
01307     return HAL_OK;
01308   }
01309   else
01310   {
01311     return HAL_BUSY;
01312   }
01313 }
01314 
01315 /**
01316   * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt 
01317   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01318   *                the configuration information for the specified I2C.
01319   * @param  pData Pointer to data buffer
01320   * @param  Size Amount of data to be sent
01321   * @retval HAL status
01322   */
01323 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01324 {
01325   if(hi2c->State == HAL_I2C_STATE_READY)
01326   {
01327     /* Process Locked */
01328     __HAL_LOCK(hi2c);
01329 
01330     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01331     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01332     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01333 
01334     /* Enable Address Acknowledge */
01335     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01336 
01337     /* Prepare transfer parameters */
01338     hi2c->pBuffPtr    = pData;
01339     hi2c->XferCount   = Size;
01340     hi2c->XferSize    = hi2c->XferCount;
01341     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01342     hi2c->XferISR     = I2C_Slave_ISR_IT;
01343 
01344     /* Process Unlocked */
01345     __HAL_UNLOCK(hi2c);
01346 
01347     /* Note : The I2C interrupts must be enabled after unlocking current process
01348               to avoid the risk of I2C interrupt handle execution before current
01349               process unlock */
01350 
01351     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
01352     /* possible to enable all of these */
01353     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01354     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
01355 
01356     return HAL_OK;
01357   }
01358   else
01359   {
01360     return HAL_BUSY;
01361   }
01362 }
01363 
01364 /**
01365   * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA
01366   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01367   *                the configuration information for the specified I2C.
01368   * @param  DevAddress Target device address
01369   * @param  pData Pointer to data buffer
01370   * @param  Size Amount of data to be sent
01371   * @retval HAL status
01372   */
01373 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01374 {
01375   uint32_t xfermode = 0U;
01376 
01377   if(hi2c->State == HAL_I2C_STATE_READY)
01378   {
01379     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01380     {
01381       return HAL_BUSY;
01382     }
01383 
01384     /* Process Locked */
01385     __HAL_LOCK(hi2c);
01386 
01387     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01388     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01389     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01390 
01391     /* Prepare transfer parameters */
01392     hi2c->pBuffPtr    = pData;
01393     hi2c->XferCount   = Size;
01394     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01395     hi2c->XferISR     = I2C_Master_ISR_DMA;
01396     
01397     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01398     {
01399       hi2c->XferSize = MAX_NBYTE_SIZE;
01400       xfermode = I2C_RELOAD_MODE;
01401     }
01402     else
01403     {
01404       hi2c->XferSize = hi2c->XferCount;
01405       xfermode = I2C_AUTOEND_MODE;
01406     }
01407 
01408     if(hi2c->XferSize > 0U)
01409     {
01410       /* Set the I2C DMA transfer complete callback */
01411       hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
01412 
01413       /* Set the DMA error callback */
01414       hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01415 
01416       /* Set the unused DMA callbacks to NULL */
01417       hi2c->hdmatx->XferHalfCpltCallback = NULL;
01418       hi2c->hdmatx->XferAbortCallback = NULL;
01419 
01420       /* Enable the DMA channel */
01421       HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01422 
01423       /* Send Slave Address */
01424       /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01425       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
01426 
01427       /* Update XferCount value */
01428       hi2c->XferCount -= hi2c->XferSize;
01429 
01430       /* Process Unlocked */
01431       __HAL_UNLOCK(hi2c);
01432 
01433       /* Note : The I2C interrupts must be enabled after unlocking current process
01434                 to avoid the risk of I2C interrupt handle execution before current
01435                 process unlock */
01436       /* Enable ERR and NACK interrupts */
01437       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01438 
01439       /* Enable DMA Request */
01440       hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
01441     }
01442     else
01443     {
01444       /* Update Transfer ISR function pointer */
01445       hi2c->XferISR = I2C_Master_ISR_IT;
01446       
01447       /* Send Slave Address */
01448       /* Set NBYTES to write and generate START condition */
01449       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
01450 
01451       /* Process Unlocked */
01452       __HAL_UNLOCK(hi2c);
01453 
01454       /* Note : The I2C interrupts must be enabled after unlocking current process
01455                 to avoid the risk of I2C interrupt handle execution before current
01456                 process unlock */
01457       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01458       /* possible to enable all of these */
01459       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01460       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01461     }
01462 
01463     return HAL_OK;
01464   }
01465   else
01466   {
01467     return HAL_BUSY;
01468   }
01469 }
01470 
01471 /**
01472   * @brief  Receive in master mode an amount of data in non-blocking mode with DMA
01473   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01474   *                the configuration information for the specified I2C.
01475   * @param  DevAddress Target device address
01476   * @param  pData Pointer to data buffer
01477   * @param  Size Amount of data to be sent
01478   * @retval HAL status
01479   */
01480 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
01481 {
01482   uint32_t xfermode = 0U;
01483 
01484   if(hi2c->State == HAL_I2C_STATE_READY)
01485   {
01486     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
01487     {
01488       return HAL_BUSY;
01489     }
01490 
01491     /* Process Locked */
01492     __HAL_LOCK(hi2c);
01493 
01494     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01495     hi2c->Mode        = HAL_I2C_MODE_MASTER;
01496     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01497 
01498     /* Prepare transfer parameters */
01499     hi2c->pBuffPtr    = pData;
01500     hi2c->XferCount   = Size;
01501     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01502     hi2c->XferISR     = I2C_Master_ISR_DMA;
01503     
01504     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01505     {
01506       hi2c->XferSize = MAX_NBYTE_SIZE;
01507       xfermode = I2C_RELOAD_MODE;
01508     }
01509     else
01510     {
01511       hi2c->XferSize = hi2c->XferCount;
01512       xfermode = I2C_AUTOEND_MODE;
01513     }
01514 
01515     if(hi2c->XferSize > 0U)
01516     {
01517       /* Set the I2C DMA transfer complete callback */
01518       hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
01519 
01520       /* Set the DMA error callback */
01521       hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01522 
01523       /* Set the unused DMA callbacks to NULL */
01524       hi2c->hdmarx->XferHalfCpltCallback = NULL;
01525       hi2c->hdmarx->XferAbortCallback = NULL;
01526 
01527       /* Enable the DMA channel */
01528       HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01529 
01530       /* Send Slave Address */
01531       /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01532       I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
01533 
01534       /* Update XferCount value */
01535       hi2c->XferCount -= hi2c->XferSize;
01536 
01537       /* Process Unlocked */
01538       __HAL_UNLOCK(hi2c);
01539 
01540       /* Note : The I2C interrupts must be enabled after unlocking current process
01541                 to avoid the risk of I2C interrupt handle execution before current
01542                 process unlock */
01543       /* Enable ERR and NACK interrupts */
01544       I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
01545 
01546       /* Enable DMA Request */
01547       hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01548     }
01549     else
01550     {
01551       /* Update Transfer ISR function pointer */
01552       hi2c->XferISR = I2C_Master_ISR_IT;
01553       
01554       /* Send Slave Address */
01555       /* Set NBYTES to read and generate START condition */
01556       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01557 
01558       /* Process Unlocked */
01559       __HAL_UNLOCK(hi2c);
01560 
01561       /* Note : The I2C interrupts must be enabled after unlocking current process
01562                 to avoid the risk of I2C interrupt handle execution before current
01563                 process unlock */
01564       /* Enable ERR, TC, STOP, NACK, TXI interrupt */
01565       /* possible to enable all of these */
01566       /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
01567       I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
01568     }
01569     return HAL_OK;
01570   }
01571   else
01572   {
01573     return HAL_BUSY;
01574   }
01575 }
01576 
01577 /**
01578   * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA
01579   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01580   *                the configuration information for the specified I2C.
01581   * @param  pData Pointer to data buffer
01582   * @param  Size Amount of data to be sent
01583   * @retval HAL status
01584   */
01585 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01586 {
01587   if(hi2c->State == HAL_I2C_STATE_READY)
01588   {
01589     if((pData == NULL) || (Size == 0U))
01590     {
01591       return  HAL_ERROR;
01592     }   
01593     /* Process Locked */
01594     __HAL_LOCK(hi2c);
01595 
01596     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
01597     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01598     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01599 
01600     /* Prepare transfer parameters */
01601     hi2c->pBuffPtr    = pData;
01602     hi2c->XferCount   = Size;
01603     hi2c->XferSize    = hi2c->XferCount;
01604     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01605     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01606 
01607     /* Set the I2C DMA transfer complete callback */
01608     hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
01609 
01610     /* Set the DMA error callback */
01611     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
01612 
01613     /* Set the unused DMA callbacks to NULL */
01614     hi2c->hdmatx->XferHalfCpltCallback = NULL;
01615     hi2c->hdmatx->XferAbortCallback = NULL;
01616 
01617     /* Enable the DMA channel */
01618     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
01619 
01620     /* Enable Address Acknowledge */
01621     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01622 
01623     /* Process Unlocked */
01624     __HAL_UNLOCK(hi2c);
01625 
01626     /* Note : The I2C interrupts must be enabled after unlocking current process
01627               to avoid the risk of I2C interrupt handle execution before current
01628               process unlock */
01629     /* Enable ERR, STOP, NACK, ADDR interrupts */
01630     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01631 
01632     /* Enable DMA Request */
01633     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; 
01634 
01635     return HAL_OK;
01636   }
01637   else
01638   {
01639     return HAL_BUSY;
01640   }
01641 }
01642 
01643 /**
01644   * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA
01645   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01646   *                the configuration information for the specified I2C.
01647   * @param  pData Pointer to data buffer
01648   * @param  Size Amount of data to be sent
01649   * @retval HAL status
01650   */
01651 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
01652 {
01653   if(hi2c->State == HAL_I2C_STATE_READY)
01654   {
01655     if((pData == NULL) || (Size == 0U)) 
01656     {
01657       return  HAL_ERROR;
01658     }   
01659     /* Process Locked */
01660     __HAL_LOCK(hi2c);
01661 
01662     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
01663     hi2c->Mode        = HAL_I2C_MODE_SLAVE;
01664     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
01665 
01666     /* Prepare transfer parameters */
01667     hi2c->pBuffPtr    = pData;
01668     hi2c->XferCount   = Size;
01669     hi2c->XferSize    = hi2c->XferCount;
01670     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
01671     hi2c->XferISR     = I2C_Slave_ISR_DMA;
01672 
01673     /* Set the I2C DMA transfer complete callback */
01674     hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
01675 
01676     /* Set the DMA error callback */
01677     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
01678 
01679     /* Set the unused DMA callbacks to NULL */
01680     hi2c->hdmarx->XferHalfCpltCallback = NULL;
01681     hi2c->hdmarx->XferAbortCallback = NULL;
01682 
01683     /* Enable the DMA channel */
01684     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
01685 
01686     /* Enable Address Acknowledge */
01687     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
01688 
01689     /* Process Unlocked */
01690     __HAL_UNLOCK(hi2c);
01691 
01692     /* Note : The I2C interrupts must be enabled after unlocking current process
01693               to avoid the risk of I2C interrupt handle execution before current
01694               process unlock */
01695     /* Enable ERR, STOP, NACK, ADDR interrupts */
01696     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
01697 
01698     /* Enable DMA Request */
01699     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
01700 
01701     return HAL_OK;
01702   }
01703   else
01704   {
01705     return HAL_BUSY;
01706   }
01707 }
01708 /**
01709   * @brief  Write an amount of data in blocking mode to a specific memory address
01710   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01711   *                the configuration information for the specified I2C.
01712   * @param  DevAddress Target device address
01713   * @param  MemAddress Internal memory address
01714   * @param  MemAddSize Size of internal memory address
01715   * @param  pData Pointer to data buffer
01716   * @param  Size Amount of data to be sent
01717   * @param  Timeout Timeout duration
01718   * @retval HAL status
01719   */
01720 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01721 {
01722   uint32_t tickstart = 0U;
01723 
01724   /* Check the parameters */
01725   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01726 
01727   if(hi2c->State == HAL_I2C_STATE_READY)
01728   {
01729     if((pData == NULL) || (Size == 0U))
01730     {
01731       return  HAL_ERROR;
01732     }
01733 
01734     /* Process Locked */
01735     __HAL_LOCK(hi2c);
01736 
01737     /* Init tickstart for timeout management*/
01738     tickstart = HAL_GetTick();
01739 
01740     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01741     {
01742       return HAL_TIMEOUT;
01743     }
01744 
01745     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
01746     hi2c->Mode      = HAL_I2C_MODE_MEM;
01747     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01748 
01749     /* Prepare transfer parameters */
01750     hi2c->pBuffPtr  = pData;
01751     hi2c->XferCount = Size;
01752     hi2c->XferISR   = NULL;
01753 
01754     /* Send Slave Address and Memory Address */
01755     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01756     {
01757       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01758       {
01759         /* Process Unlocked */
01760         __HAL_UNLOCK(hi2c);
01761         return HAL_ERROR;
01762       }
01763       else
01764       {
01765         /* Process Unlocked */
01766         __HAL_UNLOCK(hi2c);
01767         return HAL_TIMEOUT;
01768       }
01769     }
01770 
01771     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
01772     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01773     {
01774       hi2c->XferSize = MAX_NBYTE_SIZE;
01775       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01776     }
01777     else
01778     {
01779       hi2c->XferSize = hi2c->XferCount;
01780       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01781     }
01782 
01783     do
01784     {
01785       /* Wait until TXIS flag is set */
01786       if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01787       {
01788         if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01789         {
01790           return HAL_ERROR;
01791         }
01792         else
01793         {
01794           return HAL_TIMEOUT;
01795         }
01796       }
01797 
01798       /* Write data to TXDR */
01799       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
01800       hi2c->XferCount--;
01801       hi2c->XferSize--;
01802 
01803       if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
01804       {
01805         /* Wait until TCR flag is set */
01806         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01807         {
01808           return HAL_TIMEOUT;
01809         }
01810 
01811         if(hi2c->XferCount > MAX_NBYTE_SIZE)
01812         {
01813           hi2c->XferSize = MAX_NBYTE_SIZE;
01814           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01815         }
01816         else
01817         {
01818           hi2c->XferSize = hi2c->XferCount;
01819           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01820         }
01821       }
01822 
01823     }while(hi2c->XferCount > 0U);
01824 
01825     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01826     /* Wait until STOPF flag is reset */ 
01827     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01828     {
01829       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01830       {
01831         return HAL_ERROR;
01832       }
01833       else
01834       {
01835         return HAL_TIMEOUT;
01836       }
01837     }
01838 
01839     /* Clear STOP Flag */
01840     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01841 
01842     /* Clear Configuration Register 2 */
01843     I2C_RESET_CR2(hi2c);
01844 
01845     hi2c->State = HAL_I2C_STATE_READY;
01846     hi2c->Mode  = HAL_I2C_MODE_NONE;
01847 
01848     /* Process Unlocked */
01849     __HAL_UNLOCK(hi2c);
01850 
01851     return HAL_OK;
01852   }
01853   else
01854   {
01855     return HAL_BUSY;
01856   }
01857 }
01858 
01859 /**
01860   * @brief  Read an amount of data in blocking mode from a specific memory address
01861   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
01862   *                the configuration information for the specified I2C.
01863   * @param  DevAddress Target device address
01864   * @param  MemAddress Internal memory address
01865   * @param  MemAddSize Size of internal memory address
01866   * @param  pData Pointer to data buffer
01867   * @param  Size Amount of data to be sent
01868   * @param  Timeout Timeout duration
01869   * @retval HAL status
01870   */
01871 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
01872 {
01873   uint32_t tickstart = 0U;
01874 
01875   /* Check the parameters */
01876   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
01877 
01878   if(hi2c->State == HAL_I2C_STATE_READY)
01879   {
01880     if((pData == NULL) || (Size == 0U))
01881     {
01882       return  HAL_ERROR;
01883     }
01884 
01885     /* Process Locked */
01886     __HAL_LOCK(hi2c);
01887 
01888     /* Init tickstart for timeout management*/
01889     tickstart = HAL_GetTick();
01890 
01891     if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
01892     {
01893       return HAL_TIMEOUT;
01894     }
01895 
01896     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
01897     hi2c->Mode      = HAL_I2C_MODE_MEM;
01898     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
01899 
01900     /* Prepare transfer parameters */
01901     hi2c->pBuffPtr  = pData;
01902     hi2c->XferCount = Size;
01903     hi2c->XferISR   = NULL;
01904 
01905     /* Send Slave Address and Memory Address */
01906     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
01907     {
01908       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01909       {
01910         /* Process Unlocked */
01911         __HAL_UNLOCK(hi2c);
01912         return HAL_ERROR;
01913       }
01914       else
01915       {
01916         /* Process Unlocked */
01917         __HAL_UNLOCK(hi2c);
01918         return HAL_TIMEOUT;
01919       }
01920     }
01921 
01922     /* Send Slave Address */
01923     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
01924     if(hi2c->XferCount > MAX_NBYTE_SIZE)
01925     {
01926       hi2c->XferSize = MAX_NBYTE_SIZE;
01927       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
01928     }
01929     else
01930     {
01931       hi2c->XferSize = hi2c->XferCount;
01932       I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
01933     }
01934 
01935     do
01936     {
01937       /* Wait until RXNE flag is set */
01938       if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
01939       {
01940         return HAL_TIMEOUT;
01941       }
01942 
01943       /* Read data from RXDR */
01944       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
01945       hi2c->XferSize--;
01946       hi2c->XferCount--;
01947 
01948       if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
01949       {
01950         /* Wait until TCR flag is set */
01951         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
01952         {
01953           return HAL_TIMEOUT;
01954         }
01955 
01956         if(hi2c->XferCount > MAX_NBYTE_SIZE)
01957         {
01958           hi2c->XferSize = MAX_NBYTE_SIZE;
01959           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
01960         }
01961         else
01962         {
01963           hi2c->XferSize = hi2c->XferCount;
01964           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
01965         }
01966       }
01967     }while(hi2c->XferCount > 0U);
01968 
01969     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
01970     /* Wait until STOPF flag is reset */ 
01971     if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
01972     {
01973       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
01974       {
01975         return HAL_ERROR;
01976       }
01977       else
01978       {
01979         return HAL_TIMEOUT;
01980       }
01981     }
01982 
01983     /* Clear STOP Flag */
01984     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
01985 
01986     /* Clear Configuration Register 2 */
01987     I2C_RESET_CR2(hi2c);
01988 
01989     hi2c->State = HAL_I2C_STATE_READY;
01990     hi2c->Mode  = HAL_I2C_MODE_NONE;
01991 
01992     /* Process Unlocked */
01993     __HAL_UNLOCK(hi2c);
01994 
01995     return HAL_OK;
01996   }
01997   else
01998   {
01999     return HAL_BUSY;
02000   }
02001 }
02002 /**
02003   * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address
02004   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02005   *                the configuration information for the specified I2C.
02006   * @param  DevAddress Target device address
02007   * @param  MemAddress Internal memory address
02008   * @param  MemAddSize Size of internal memory address
02009   * @param  pData Pointer to data buffer
02010   * @param  Size Amount of data to be sent
02011   * @retval HAL status
02012   */
02013 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02014 {
02015   uint32_t tickstart = 0U;
02016   uint32_t xfermode = 0U;
02017 
02018   /* Check the parameters */
02019   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02020 
02021   if(hi2c->State == HAL_I2C_STATE_READY)
02022   {
02023     if((pData == NULL) || (Size == 0U))
02024     {
02025       return  HAL_ERROR;
02026     }
02027     
02028     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02029     {
02030       return HAL_BUSY;
02031     }
02032 
02033     /* Process Locked */
02034     __HAL_LOCK(hi2c);
02035 
02036     /* Init tickstart for timeout management*/
02037     tickstart = HAL_GetTick();
02038 
02039     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02040     hi2c->Mode        = HAL_I2C_MODE_MEM;
02041     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02042 
02043     /* Prepare transfer parameters */
02044     hi2c->pBuffPtr    = pData;
02045     hi2c->XferCount   = Size;
02046     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02047     hi2c->XferISR     = I2C_Master_ISR_IT;
02048     
02049     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02050     {
02051       hi2c->XferSize = MAX_NBYTE_SIZE;
02052       xfermode = I2C_RELOAD_MODE;
02053     }
02054     else
02055     {
02056       hi2c->XferSize = hi2c->XferCount;
02057       xfermode = I2C_AUTOEND_MODE;
02058     }
02059 
02060     /* Send Slave Address and Memory Address */
02061     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02062     {
02063       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02064       {
02065         /* Process Unlocked */
02066         __HAL_UNLOCK(hi2c);
02067         return HAL_ERROR;
02068       }
02069       else
02070       {
02071         /* Process Unlocked */
02072         __HAL_UNLOCK(hi2c);
02073         return HAL_TIMEOUT;
02074       }
02075     }
02076 
02077     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02078     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02079 
02080     /* Process Unlocked */
02081     __HAL_UNLOCK(hi2c); 
02082 
02083     /* Note : The I2C interrupts must be enabled after unlocking current process 
02084               to avoid the risk of I2C interrupt handle execution before current
02085               process unlock */
02086 
02087     /* Enable ERR, TC, STOP, NACK, TXI interrupt */
02088     /* possible to enable all of these */
02089     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02090     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02091 
02092     return HAL_OK;
02093   }
02094   else
02095   {
02096     return HAL_BUSY;
02097   }
02098 }
02099 
02100 /**
02101   * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address
02102   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02103   *                the configuration information for the specified I2C.
02104   * @param  DevAddress Target device address
02105   * @param  MemAddress Internal memory address
02106   * @param  MemAddSize Size of internal memory address
02107   * @param  pData Pointer to data buffer
02108   * @param  Size Amount of data to be sent
02109   * @retval HAL status
02110   */
02111 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02112 {
02113   uint32_t tickstart = 0U;
02114   uint32_t xfermode = 0U;
02115 
02116   /* Check the parameters */
02117   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02118 
02119   if(hi2c->State == HAL_I2C_STATE_READY)
02120   {
02121     if((pData == NULL) || (Size == 0U))
02122     {
02123       return  HAL_ERROR;
02124     }
02125     
02126     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02127     {
02128       return HAL_BUSY;
02129     }
02130 
02131     /* Process Locked */
02132     __HAL_LOCK(hi2c);
02133 
02134     /* Init tickstart for timeout management*/
02135     tickstart = HAL_GetTick();
02136 
02137     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02138     hi2c->Mode        = HAL_I2C_MODE_MEM;
02139     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02140 
02141     /* Prepare transfer parameters */
02142     hi2c->pBuffPtr    = pData;
02143     hi2c->XferCount   = Size;
02144     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02145     hi2c->XferISR     = I2C_Master_ISR_IT;
02146     
02147     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02148     {
02149       hi2c->XferSize = MAX_NBYTE_SIZE;
02150       xfermode = I2C_RELOAD_MODE;
02151     }
02152     else
02153     {
02154       hi2c->XferSize = hi2c->XferCount;
02155       xfermode = I2C_AUTOEND_MODE;
02156     }
02157 
02158     /* Send Slave Address and Memory Address */
02159     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02160     {
02161       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02162       {
02163         /* Process Unlocked */
02164         __HAL_UNLOCK(hi2c);
02165         return HAL_ERROR;
02166       }
02167       else
02168       {
02169         /* Process Unlocked */
02170         __HAL_UNLOCK(hi2c);
02171         return HAL_TIMEOUT;
02172       }
02173     }
02174 
02175     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02176     I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02177 
02178     /* Process Unlocked */
02179     __HAL_UNLOCK(hi2c);
02180 
02181     /* Note : The I2C interrupts must be enabled after unlocking current process
02182               to avoid the risk of I2C interrupt handle execution before current
02183               process unlock */
02184 
02185     /* Enable ERR, TC, STOP, NACK, RXI interrupt */
02186     /* possible to enable all of these */
02187     /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
02188     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02189 
02190     return HAL_OK;
02191   }
02192   else
02193   {
02194     return HAL_BUSY;
02195   }
02196 }
02197 /**
02198   * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address
02199   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02200   *                the configuration information for the specified I2C.
02201   * @param  DevAddress Target device address
02202   * @param  MemAddress Internal memory address
02203   * @param  MemAddSize Size of internal memory address
02204   * @param  pData Pointer to data buffer
02205   * @param  Size Amount of data to be sent
02206   * @retval HAL status
02207   */
02208 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02209 {
02210   uint32_t tickstart = 0U;
02211   uint32_t xfermode = 0U;
02212 
02213   /* Check the parameters */
02214   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02215 
02216   if(hi2c->State == HAL_I2C_STATE_READY)
02217   {
02218     if((pData == NULL) || (Size == 0U))
02219     {
02220       return  HAL_ERROR;
02221     }
02222 
02223     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02224     {
02225       return HAL_BUSY;
02226     }
02227 
02228     /* Process Locked */
02229     __HAL_LOCK(hi2c);
02230 
02231     /* Init tickstart for timeout management*/
02232     tickstart = HAL_GetTick();
02233 
02234     hi2c->State       = HAL_I2C_STATE_BUSY_TX;
02235     hi2c->Mode        = HAL_I2C_MODE_MEM;
02236     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02237 
02238     /* Prepare transfer parameters */
02239     hi2c->pBuffPtr    = pData;
02240     hi2c->XferCount   = Size;
02241     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02242     hi2c->XferISR     = I2C_Master_ISR_DMA;
02243     
02244     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02245     {
02246       hi2c->XferSize = MAX_NBYTE_SIZE;
02247       xfermode = I2C_RELOAD_MODE;
02248     }
02249     else
02250     {
02251       hi2c->XferSize = hi2c->XferCount;
02252       xfermode = I2C_AUTOEND_MODE;
02253     }
02254 
02255     /* Send Slave Address and Memory Address */
02256     if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02257     {
02258       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02259       {
02260         /* Process Unlocked */
02261         __HAL_UNLOCK(hi2c);
02262         return HAL_ERROR;
02263       }
02264       else
02265       {
02266         /* Process Unlocked */
02267         __HAL_UNLOCK(hi2c);
02268         return HAL_TIMEOUT;
02269       }
02270     }
02271 
02272     /* Set the I2C DMA transfer complete callback */
02273     hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
02274 
02275     /* Set the DMA error callback */
02276     hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
02277 
02278     /* Set the unused DMA callbacks to NULL */
02279     hi2c->hdmatx->XferHalfCpltCallback = NULL;
02280     hi2c->hdmatx->XferAbortCallback = NULL;
02281 
02282     /* Enable the DMA channel */
02283     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
02284 
02285     /* Send Slave Address */
02286     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02287     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
02288 
02289     /* Update XferCount value */
02290     hi2c->XferCount -= hi2c->XferSize;
02291 
02292     /* Process Unlocked */
02293     __HAL_UNLOCK(hi2c);
02294 
02295     /* Note : The I2C interrupts must be enabled after unlocking current process
02296               to avoid the risk of I2C interrupt handle execution before current
02297               process unlock */
02298     /* Enable ERR and NACK interrupts */
02299     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02300 
02301     /* Enable DMA Request */
02302     hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
02303 
02304     return HAL_OK;
02305   }
02306   else
02307   {
02308     return HAL_BUSY;
02309   }
02310 }
02311 
02312 /**
02313   * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.
02314   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02315   *                the configuration information for the specified I2C.
02316   * @param  DevAddress Target device address
02317   * @param  MemAddress Internal memory address
02318   * @param  MemAddSize Size of internal memory address
02319   * @param  pData Pointer to data buffer
02320   * @param  Size Amount of data to be read
02321   * @retval HAL status
02322   */
02323 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
02324 {
02325   uint32_t tickstart = 0U;
02326   uint32_t xfermode = 0U;
02327 
02328   /* Check the parameters */
02329   assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
02330 
02331   if(hi2c->State == HAL_I2C_STATE_READY)
02332   {
02333     if((pData == NULL) || (Size == 0U))
02334     {
02335       return  HAL_ERROR;
02336     }
02337 
02338     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02339     {
02340       return HAL_BUSY;
02341     }
02342 
02343     /* Process Locked */
02344     __HAL_LOCK(hi2c);
02345 
02346     /* Init tickstart for timeout management*/
02347     tickstart = HAL_GetTick();
02348 
02349     hi2c->State       = HAL_I2C_STATE_BUSY_RX;
02350     hi2c->Mode        = HAL_I2C_MODE_MEM;
02351     hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
02352 
02353     /* Prepare transfer parameters */
02354     hi2c->pBuffPtr    = pData;
02355     hi2c->XferCount   = Size;
02356     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
02357     hi2c->XferISR     = I2C_Master_ISR_DMA;
02358 
02359     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02360     {
02361       hi2c->XferSize = MAX_NBYTE_SIZE;
02362       xfermode = I2C_RELOAD_MODE;
02363     }
02364     else
02365     {
02366       hi2c->XferSize = hi2c->XferCount;
02367       xfermode = I2C_AUTOEND_MODE;
02368     }
02369 
02370     /* Send Slave Address and Memory Address */
02371     if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
02372     {
02373       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
02374       {
02375         /* Process Unlocked */
02376         __HAL_UNLOCK(hi2c);
02377         return HAL_ERROR;
02378       }
02379       else
02380       {
02381         /* Process Unlocked */
02382         __HAL_UNLOCK(hi2c);
02383         return HAL_TIMEOUT;
02384       }
02385     }
02386 
02387     /* Set the I2C DMA transfer complete callback */
02388     hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
02389 
02390     /* Set the DMA error callback */
02391     hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
02392 
02393     /* Set the unused DMA callbacks to NULL */
02394     hi2c->hdmarx->XferHalfCpltCallback = NULL;
02395     hi2c->hdmarx->XferAbortCallback = NULL;
02396 
02397     /* Enable the DMA channel */
02398     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
02399 
02400     /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
02401     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
02402 
02403     /* Update XferCount value */
02404     hi2c->XferCount -= hi2c->XferSize;
02405 
02406     /* Process Unlocked */
02407     __HAL_UNLOCK(hi2c);
02408 
02409     /* Enable DMA Request */
02410     hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
02411 
02412     /* Note : The I2C interrupts must be enabled after unlocking current process
02413               to avoid the risk of I2C interrupt handle execution before current
02414               process unlock */
02415     /* Enable ERR and NACK interrupts */
02416     I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
02417 
02418     return HAL_OK;
02419   }
02420   else
02421   {
02422     return HAL_BUSY;
02423   }
02424 }
02425 
02426 /**
02427   * @brief  Checks if target device is ready for communication.
02428   * @note   This function is used with Memory devices
02429   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02430   *                the configuration information for the specified I2C.
02431   * @param  DevAddress Target device address
02432   * @param  Trials Number of trials
02433   * @param  Timeout Timeout duration
02434   * @retval HAL status
02435   */
02436 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
02437 {
02438   uint32_t tickstart = 0U;
02439 
02440   __IO uint32_t I2C_Trials = 0U;
02441 
02442   if(hi2c->State == HAL_I2C_STATE_READY)
02443   {
02444     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
02445     {
02446       return HAL_BUSY;
02447     }
02448 
02449     /* Process Locked */
02450     __HAL_LOCK(hi2c);
02451 
02452     hi2c->State = HAL_I2C_STATE_BUSY;
02453     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02454 
02455     do
02456     {
02457       /* Generate Start */
02458       hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
02459 
02460       /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
02461       /* Wait until STOPF flag is set or a NACK flag is set*/
02462       tickstart = HAL_GetTick();
02463       while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
02464       {
02465         if(Timeout != HAL_MAX_DELAY)
02466         {
02467           if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
02468           {
02469             /* Device is ready */
02470             hi2c->State = HAL_I2C_STATE_READY;
02471             /* Process Unlocked */
02472             __HAL_UNLOCK(hi2c);
02473             return HAL_TIMEOUT;
02474           }
02475         } 
02476       }
02477 
02478       /* Check if the NACKF flag has not been set */
02479       if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
02480       {
02481         /* Wait until STOPF flag is reset */ 
02482         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02483         {
02484           return HAL_TIMEOUT;
02485         }
02486 
02487         /* Clear STOP Flag */
02488         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02489 
02490         /* Device is ready */
02491         hi2c->State = HAL_I2C_STATE_READY;
02492 
02493         /* Process Unlocked */
02494         __HAL_UNLOCK(hi2c);
02495 
02496         return HAL_OK;
02497       }
02498       else
02499       {
02500         /* Wait until STOPF flag is reset */
02501         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02502         {
02503           return HAL_TIMEOUT;
02504         }
02505 
02506         /* Clear NACK Flag */
02507         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
02508 
02509         /* Clear STOP Flag, auto generated with autoend*/
02510         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02511       }
02512 
02513       /* Check if the maximum allowed number of trials has been reached */
02514       if (I2C_Trials++ == Trials)
02515       {
02516         /* Generate Stop */
02517         hi2c->Instance->CR2 |= I2C_CR2_STOP;
02518 
02519         /* Wait until STOPF flag is reset */ 
02520         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
02521         {
02522           return HAL_TIMEOUT;
02523         }
02524 
02525         /* Clear STOP Flag */
02526         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
02527       }
02528     }while(I2C_Trials < Trials);
02529 
02530     hi2c->State = HAL_I2C_STATE_READY;
02531 
02532     /* Process Unlocked */
02533     __HAL_UNLOCK(hi2c);
02534 
02535     return HAL_TIMEOUT;
02536   }
02537   else
02538   {
02539     return HAL_BUSY;
02540   }
02541 }
02542 
02543 /**
02544   * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
02545   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02546   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02547   *                the configuration information for the specified I2C.
02548   * @param  DevAddress Target device address
02549   * @param  pData Pointer to data buffer
02550   * @param  Size Amount of data to be sent
02551   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02552   * @retval HAL status
02553   */
02554 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02555 {
02556   uint32_t xfermode = 0U;
02557   uint32_t xferrequest = I2C_GENERATE_START_WRITE;
02558 
02559   /* Check the parameters */
02560   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02561 
02562   if(hi2c->State == HAL_I2C_STATE_READY)
02563   {
02564     /* Process Locked */
02565     __HAL_LOCK(hi2c);
02566 
02567     hi2c->State     = HAL_I2C_STATE_BUSY_TX;
02568     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02569     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02570 
02571     /* Prepare transfer parameters */
02572     hi2c->pBuffPtr    = pData;
02573     hi2c->XferCount   = Size;
02574     hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
02575     hi2c->XferISR     = I2C_Master_ISR_IT;
02576 
02577     /* If size > MAX_NBYTE_SIZE, use reload mode */
02578     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02579     {
02580       hi2c->XferSize = MAX_NBYTE_SIZE;
02581       xfermode = I2C_RELOAD_MODE;
02582     }
02583     else
02584     {
02585       hi2c->XferSize = hi2c->XferCount;
02586       xfermode = hi2c->XferOptions;
02587     }
02588 
02589     /* Send Slave Address and set NBYTES to write */
02590     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
02591 
02592     /* Process Unlocked */
02593     __HAL_UNLOCK(hi2c);
02594 
02595     /* Note : The I2C interrupts must be enabled after unlocking current process
02596               to avoid the risk of I2C interrupt handle execution before current
02597               process unlock */
02598     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
02599 
02600     return HAL_OK;
02601   }
02602   else
02603   {
02604     return HAL_BUSY;
02605   }
02606 }
02607 
02608 /**
02609   * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
02610   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02611   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02612   *                the configuration information for the specified I2C.
02613   * @param  DevAddress Target device address
02614   * @param  pData Pointer to data buffer
02615   * @param  Size Amount of data to be sent
02616   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02617   * @retval HAL status
02618   */
02619 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02620 {
02621   uint32_t xfermode = 0U;
02622   uint32_t xferrequest = I2C_GENERATE_START_READ;
02623 
02624   /* Check the parameters */
02625   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02626 
02627   if(hi2c->State == HAL_I2C_STATE_READY)
02628   {
02629     /* Process Locked */
02630     __HAL_LOCK(hi2c);
02631 
02632     hi2c->State     = HAL_I2C_STATE_BUSY_RX;
02633     hi2c->Mode      = HAL_I2C_MODE_MASTER;
02634     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02635 
02636     /* Prepare transfer parameters */
02637     hi2c->pBuffPtr    = pData;
02638     hi2c->XferCount   = Size;
02639     hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
02640     hi2c->XferISR     = I2C_Master_ISR_IT;
02641 
02642     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
02643     if(hi2c->XferCount > MAX_NBYTE_SIZE)
02644     {
02645       hi2c->XferSize = MAX_NBYTE_SIZE;
02646       xfermode = I2C_RELOAD_MODE;
02647     }
02648     else
02649     {
02650       hi2c->XferSize = hi2c->XferCount;
02651       xfermode = hi2c->XferOptions;
02652     }
02653 
02654     /* Send Slave Address and set NBYTES to read */
02655     I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
02656 
02657     /* Process Unlocked */
02658     __HAL_UNLOCK(hi2c);
02659 
02660     /* Note : The I2C interrupts must be enabled after unlocking current process
02661               to avoid the risk of I2C interrupt handle execution before current
02662               process unlock */
02663     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
02664 
02665     return HAL_OK;
02666   }
02667   else
02668   {
02669     return HAL_BUSY;
02670   }
02671 }
02672 
02673 /**
02674   * @brief  Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02675   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02676   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02677   *                the configuration information for the specified I2C.
02678   * @param  pData Pointer to data buffer
02679   * @param  Size Amount of data to be sent
02680   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02681   * @retval HAL status
02682   */
02683 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02684 {
02685   /* Check the parameters */
02686   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02687 
02688   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02689   {
02690     if((pData == NULL) || (Size == 0U))
02691     {
02692       return  HAL_ERROR;
02693     }
02694 
02695     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02696     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
02697 
02698     /* Process Locked */
02699     __HAL_LOCK(hi2c);
02700 
02701     hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;
02702     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02703     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02704 
02705     /* Enable Address Acknowledge */
02706     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02707 
02708     /* Prepare transfer parameters */
02709     hi2c->pBuffPtr    = pData;
02710     hi2c->XferCount   = Size;
02711     hi2c->XferSize    = hi2c->XferCount;
02712     hi2c->XferOptions = XferOptions;
02713     hi2c->XferISR     = I2C_Slave_ISR_IT;
02714 
02715     if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
02716     {
02717       /* Clear ADDR flag after prepare the transfer parameters */
02718       /* This action will generate an acknowledge to the Master */
02719       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
02720     }
02721 
02722     /* Process Unlocked */
02723     __HAL_UNLOCK(hi2c);
02724 
02725     /* Note : The I2C interrupts must be enabled after unlocking current process
02726     to avoid the risk of I2C interrupt handle execution before current
02727     process unlock */
02728     /* REnable ADDR interrupt */
02729     I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
02730 
02731     return HAL_OK;
02732   }
02733   else
02734   {
02735     return HAL_ERROR;
02736   }
02737 }
02738 
02739 /**
02740   * @brief  Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
02741   * @note   This interface allow to manage repeated start condition when a direction change during transfer
02742   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02743   *                the configuration information for the specified I2C.
02744   * @param  pData Pointer to data buffer
02745   * @param  Size Amount of data to be sent
02746   * @param  XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
02747   * @retval HAL status
02748   */
02749 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
02750 {
02751   /* Check the parameters */
02752   assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
02753 
02754   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02755   {
02756     if((pData == NULL) || (Size == 0U))
02757     {
02758       return  HAL_ERROR;
02759     }
02760 
02761     /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
02762     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
02763 
02764     /* Process Locked */
02765     __HAL_LOCK(hi2c);
02766 
02767     hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;
02768     hi2c->Mode      = HAL_I2C_MODE_SLAVE;
02769     hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
02770 
02771     /* Enable Address Acknowledge */
02772     hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
02773 
02774     /* Prepare transfer parameters */
02775     hi2c->pBuffPtr    = pData;
02776     hi2c->XferCount   = Size;
02777     hi2c->XferSize    = hi2c->XferCount;
02778     hi2c->XferOptions = XferOptions;
02779     hi2c->XferISR     = I2C_Slave_ISR_IT;
02780 
02781     if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
02782     {
02783       /* Clear ADDR flag after prepare the transfer parameters */
02784       /* This action will generate an acknowledge to the Master */
02785       __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
02786     }
02787 
02788     /* Process Unlocked */
02789     __HAL_UNLOCK(hi2c);
02790 
02791     /* Note : The I2C interrupts must be enabled after unlocking current process
02792     to avoid the risk of I2C interrupt handle execution before current
02793     process unlock */
02794     /* REnable ADDR interrupt */
02795     I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
02796 
02797     return HAL_OK;
02798   }
02799   else
02800   {
02801     return HAL_ERROR;
02802   }
02803 }
02804 
02805 /**
02806   * @brief  Enable the Address listen mode with Interrupt.
02807   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02808   *                the configuration information for the specified I2C.
02809   * @retval HAL status
02810   */
02811 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
02812 {
02813   if(hi2c->State == HAL_I2C_STATE_READY)
02814   {
02815     hi2c->State = HAL_I2C_STATE_LISTEN;
02816     hi2c->XferISR = I2C_Slave_ISR_IT;
02817 
02818     /* Enable the Address Match interrupt */
02819     I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02820 
02821     return HAL_OK;
02822   }
02823   else
02824   {
02825     return HAL_BUSY;
02826   }
02827 }
02828 
02829 /**
02830   * @brief  Disable the Address listen mode with Interrupt.
02831   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02832   *                the configuration information for the specified I2C
02833   * @retval HAL status
02834   */
02835 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
02836 {
02837   /* Declaration of tmp to prevent undefined behavior of volatile usage */
02838   uint32_t tmp;
02839 
02840   /* Disable Address listen mode only if a transfer is not ongoing */
02841   if(hi2c->State == HAL_I2C_STATE_LISTEN)
02842   {
02843     tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
02844     hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
02845     hi2c->State = HAL_I2C_STATE_READY;
02846     hi2c->Mode = HAL_I2C_MODE_NONE;
02847     hi2c->XferISR = NULL;
02848 
02849     /* Disable the Address Match interrupt */
02850     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
02851 
02852     return HAL_OK;
02853   }
02854   else
02855   {
02856     return HAL_BUSY;
02857   }
02858 }
02859 
02860 /**
02861   * @brief  Abort a master I2C IT or DMA process communication with Interrupt.
02862   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02863   *                the configuration information for the specified I2C.
02864   * @param  DevAddress Target device address
02865   * @retval HAL status
02866   */
02867 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
02868 {
02869   if(hi2c->Mode == HAL_I2C_MODE_MASTER)
02870   {
02871     /* Process Locked */
02872     __HAL_LOCK(hi2c);
02873 
02874     /* Disable Interrupts */
02875     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
02876     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
02877 
02878     /* Set State at HAL_I2C_STATE_ABORT */
02879     hi2c->State = HAL_I2C_STATE_ABORT;
02880 
02881     /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
02882     /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
02883     I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
02884 
02885     /* Process Unlocked */
02886     __HAL_UNLOCK(hi2c);
02887 
02888     /* Note : The I2C interrupts must be enabled after unlocking current process 
02889               to avoid the risk of I2C interrupt handle execution before current
02890               process unlock */
02891     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
02892 
02893     return HAL_OK;
02894   }
02895   else
02896   {
02897     /* Wrong usage of abort function */
02898     /* This function should be used only in case of abort monitored by master device */
02899     return HAL_ERROR;
02900   }
02901 }
02902 
02903 /**
02904   * @}
02905   */
02906 
02907 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
02908  * @{
02909  */   
02910 
02911 /**
02912   * @brief  This function handles I2C event interrupt request.
02913   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02914   *                the configuration information for the specified I2C.
02915   * @retval None
02916   */
02917 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
02918 {
02919   /* Get current IT Flags and IT sources value */
02920   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02921   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02922 
02923   /* I2C events treatment -------------------------------------*/
02924   if(hi2c->XferISR != NULL)
02925   {
02926     hi2c->XferISR(hi2c, itflags, itsources);
02927   }
02928 }
02929 
02930 /**
02931   * @brief  This function handles I2C error interrupt request.
02932   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02933   *                the configuration information for the specified I2C.
02934   * @retval None
02935   */
02936 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
02937 {
02938   uint32_t itflags   = READ_REG(hi2c->Instance->ISR);
02939   uint32_t itsources = READ_REG(hi2c->Instance->CR1);
02940 
02941   /* I2C Bus error interrupt occurred ------------------------------------*/
02942   if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02943   {
02944     hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
02945 
02946     /* Clear BERR flag */
02947     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
02948   }
02949 
02950   /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
02951   if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02952   {
02953     hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
02954 
02955     /* Clear OVR flag */
02956     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
02957   }
02958 
02959   /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
02960   if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
02961   {
02962     hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
02963 
02964     /* Clear ARLO flag */
02965     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
02966   }
02967 
02968   /* Call the Error Callback in case of Error detected */
02969   if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) !=  HAL_I2C_ERROR_NONE)
02970   {
02971     I2C_ITError(hi2c, hi2c->ErrorCode);
02972   }
02973 }
02974 
02975 /**
02976   * @brief  Master Tx Transfer completed callback.
02977   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02978   *                the configuration information for the specified I2C.
02979   * @retval None
02980   */
02981 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
02982 {
02983   /* Prevent unused argument(s) compilation warning */
02984   UNUSED(hi2c);
02985 
02986   /* NOTE : This function should not be modified, when the callback is needed,
02987             the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
02988    */
02989 }
02990 
02991 /**
02992   * @brief  Master Rx Transfer completed callback.
02993   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
02994   *                the configuration information for the specified I2C.
02995   * @retval None
02996   */
02997 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
02998 {
02999   /* Prevent unused argument(s) compilation warning */
03000   UNUSED(hi2c);
03001 
03002   /* NOTE : This function should not be modified, when the callback is needed,
03003             the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
03004    */
03005 }
03006 
03007 /** @brief  Slave Tx Transfer completed callback.
03008   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03009   *                the configuration information for the specified I2C.
03010   * @retval None
03011   */
03012 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
03013 {
03014   /* Prevent unused argument(s) compilation warning */
03015   UNUSED(hi2c);
03016 
03017   /* NOTE : This function should not be modified, when the callback is needed,
03018             the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
03019    */
03020 }
03021 
03022 /**
03023   * @brief  Slave Rx Transfer completed callback.
03024   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03025   *                the configuration information for the specified I2C.
03026   * @retval None
03027   */
03028 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
03029 {
03030   /* Prevent unused argument(s) compilation warning */
03031   UNUSED(hi2c);
03032 
03033   /* NOTE : This function should not be modified, when the callback is needed,
03034             the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
03035    */
03036 }
03037 
03038 /**
03039   * @brief  Slave Address Match callback.
03040   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03041   *                the configuration information for the specified I2C.
03042   * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFEROPTIONS
03043   * @param  AddrMatchCode: Address Match Code
03044   * @retval None
03045   */
03046 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
03047 {
03048   /* Prevent unused argument(s) compilation warning */
03049   UNUSED(hi2c);
03050   UNUSED(TransferDirection);
03051   UNUSED(AddrMatchCode);
03052 
03053   /* NOTE : This function should not be modified, when the callback is needed,
03054             the HAL_I2C_AddrCallback() could be implemented in the user file
03055    */
03056 }
03057 
03058 /**
03059   * @brief  Listen Complete callback.
03060   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03061   *                the configuration information for the specified I2C.
03062   * @retval None
03063   */
03064 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
03065 {
03066   /* Prevent unused argument(s) compilation warning */
03067   UNUSED(hi2c);
03068 
03069   /* NOTE : This function should not be modified, when the callback is needed,
03070             the HAL_I2C_ListenCpltCallback() could be implemented in the user file
03071    */
03072 }
03073 
03074 /**
03075   * @brief  Memory Tx Transfer completed callback.
03076   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03077   *                the configuration information for the specified I2C.
03078   * @retval None
03079   */
03080 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
03081 {
03082   /* Prevent unused argument(s) compilation warning */
03083   UNUSED(hi2c);
03084 
03085   /* NOTE : This function should not be modified, when the callback is needed,
03086             the HAL_I2C_MemTxCpltCallback could be implemented in the user file
03087    */
03088 }
03089 
03090 /**
03091   * @brief  Memory Rx Transfer completed callback.
03092   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03093   *                the configuration information for the specified I2C.
03094   * @retval None
03095   */
03096 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
03097 {
03098   /* Prevent unused argument(s) compilation warning */
03099   UNUSED(hi2c);
03100 
03101   /* NOTE : This function should not be modified, when the callback is needed,
03102             the HAL_I2C_MemRxCpltCallback could be implemented in the user file
03103    */
03104 }
03105 
03106 /**
03107   * @brief  I2C error callback.
03108   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03109   *                the configuration information for the specified I2C.
03110   * @retval None
03111   */
03112 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
03113 {
03114   /* Prevent unused argument(s) compilation warning */
03115   UNUSED(hi2c);
03116 
03117   /* NOTE : This function should not be modified, when the callback is needed,
03118             the HAL_I2C_ErrorCallback could be implemented in the user file
03119    */
03120 }
03121 
03122 /**
03123   * @brief  I2C abort callback.
03124   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03125   *                the configuration information for the specified I2C.
03126   * @retval None
03127   */
03128 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
03129 {
03130   /* Prevent unused argument(s) compilation warning */
03131   UNUSED(hi2c);
03132 
03133   /* NOTE : This function should not be modified, when the callback is needed,
03134             the HAL_I2C_AbortCpltCallback could be implemented in the user file
03135    */
03136 }
03137 
03138 /**
03139   * @}
03140   */
03141 
03142 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
03143  *  @brief   Peripheral State, Mode and Error functions
03144  *
03145 @verbatim
03146  ===============================================================================
03147             ##### Peripheral State, Mode and Error functions #####
03148  ===============================================================================
03149     [..]
03150     This subsection permit to get in run-time the status of the peripheral
03151     and the data flow.
03152 
03153 @endverbatim
03154   * @{
03155   */
03156 
03157 /**
03158   * @brief  Return the I2C handle state.
03159   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03160   *                the configuration information for the specified I2C.
03161   * @retval HAL state
03162   */
03163 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
03164 {
03165   /* Return I2C handle state */
03166   return hi2c->State;
03167 }
03168 
03169 /**
03170   * @brief  Returns the I2C Master, Slave, Memory or no mode.
03171   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03172   *         the configuration information for I2C module
03173   * @retval HAL mode
03174   */
03175 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
03176 {
03177   return hi2c->Mode;
03178 }
03179 
03180 /**
03181 * @brief  Return the I2C error code.
03182   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03183   *              the configuration information for the specified I2C.
03184 * @retval I2C Error Code
03185 */
03186 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
03187 {
03188   return hi2c->ErrorCode;
03189 }
03190 
03191 /**
03192   * @}
03193   */  
03194 
03195 /**
03196   * @}
03197   */
03198 
03199 /** @addtogroup I2C_Private_Functions
03200   * @{
03201   */
03202 
03203 /**
03204   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
03205   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03206   *                the configuration information for the specified I2C.
03207   * @param  ITFlags Interrupt flags to handle.
03208   * @param  ITSources Interrupt sources enabled.
03209   * @retval HAL status
03210   */
03211 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
03212 {
03213   uint16_t devaddress = 0U;
03214 
03215   /* Process Locked */
03216   __HAL_LOCK(hi2c);
03217 
03218   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03219   {
03220     /* Clear NACK Flag */
03221     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03222 
03223     /* Set corresponding Error Code */
03224     /* No need to generate STOP, it is automatically done */
03225     /* Error callback will be send during stop flag treatment */
03226     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03227 
03228     /* Flush TX register */
03229     I2C_Flush_TXDR(hi2c);
03230   }
03231   else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03232   {
03233     /* Read data from RXDR */
03234     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03235     hi2c->XferSize--;
03236     hi2c->XferCount--;
03237   }
03238   else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03239   {
03240     /* Write data to TXDR */
03241     hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03242     hi2c->XferSize--;
03243     hi2c->XferCount--;  
03244   }
03245   else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03246   {
03247     if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
03248     {
03249       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03250       
03251       if(hi2c->XferCount > MAX_NBYTE_SIZE)
03252       {
03253         hi2c->XferSize = MAX_NBYTE_SIZE;
03254         I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
03255       }
03256       else
03257       {
03258         hi2c->XferSize = hi2c->XferCount;
03259         if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
03260         {
03261           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
03262         }
03263         else
03264         {
03265           I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
03266         }
03267       }
03268     }
03269     else
03270     {
03271       /* Call TxCpltCallback() if no stop mode is set */
03272       if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03273       {
03274         /* Call I2C Master Sequential complete process */
03275         I2C_ITMasterSequentialCplt(hi2c);
03276       }
03277       else
03278       {
03279         /* Wrong size Status regarding TCR flag event */
03280         /* Call the corresponding callback to inform upper layer of End of Transfer */
03281         I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03282       }
03283     }
03284   }
03285   else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03286   {
03287     if(hi2c->XferCount == 0U)
03288     {
03289       if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
03290       {
03291         /* Generate a stop condition in case of no transfer option */
03292         if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
03293         {
03294           /* Generate Stop */
03295           hi2c->Instance->CR2 |= I2C_CR2_STOP;
03296         }
03297         else
03298         {
03299           /* Call I2C Master Sequential complete process */
03300           I2C_ITMasterSequentialCplt(hi2c);
03301         }
03302       }
03303     }
03304     else
03305     {
03306       /* Wrong size Status regarding TC flag event */
03307       /* Call the corresponding callback to inform upper layer of End of Transfer */
03308       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03309     }
03310   }
03311 
03312   if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03313   {
03314     /* Call I2C Master complete process */
03315     I2C_ITMasterCplt(hi2c, ITFlags);
03316   }
03317 
03318   /* Process Unlocked */
03319   __HAL_UNLOCK(hi2c);
03320 
03321   return HAL_OK;
03322 }
03323 
03324 /**
03325   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
03326   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03327   *                the configuration information for the specified I2C.
03328   * @param  ITFlags Interrupt flags to handle.
03329   * @param  ITSources Interrupt sources enabled.
03330   * @retval HAL status
03331   */
03332 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
03333 {
03334   /* Process locked */
03335   __HAL_LOCK(hi2c);
03336   
03337   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03338   {
03339     /* Check that I2C transfer finished */
03340     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03341     /* Mean XferCount == 0*/
03342     /* So clear Flag NACKF only */
03343     if(hi2c->XferCount == 0U)
03344     {
03345       if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
03346         (hi2c->State == HAL_I2C_STATE_LISTEN))
03347       {
03348         /* Call I2C Listen complete process */
03349         I2C_ITListenCplt(hi2c, ITFlags);
03350       }
03351       else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
03352       {
03353         /* Clear NACK Flag */
03354         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03355 
03356         /* Flush TX register */
03357         I2C_Flush_TXDR(hi2c);
03358 
03359         /* Last Byte is Transmitted */
03360         /* Call I2C Slave Sequential complete process */
03361         I2C_ITSlaveSequentialCplt(hi2c);
03362       }
03363       else
03364       {
03365         /* Clear NACK Flag */
03366         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03367       }
03368     }
03369     else
03370     {
03371       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03372       /* Clear NACK Flag */
03373       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03374 
03375       /* Set ErrorCode corresponding to a Non-Acknowledge */
03376       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03377     }
03378   }
03379   else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
03380   {
03381     if(hi2c->XferCount > 0U)
03382     {
03383       /* Read data from RXDR */
03384       (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
03385       hi2c->XferSize--;
03386       hi2c->XferCount--;
03387     }
03388 
03389     if((hi2c->XferCount == 0U) && \
03390        (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
03391     {
03392       /* Call I2C Slave Sequential complete process */
03393       I2C_ITSlaveSequentialCplt(hi2c);
03394    }
03395   }
03396   else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03397   {
03398     I2C_ITAddrCplt(hi2c, ITFlags);
03399   }
03400   else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
03401   {
03402     /* Write data to TXDR only if XferCount not reach "0" */
03403     /* A TXIS flag can be set, during STOP treatment      */
03404     /* Check if all Datas have already been sent */
03405     /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
03406     if(hi2c->XferCount > 0U)
03407     {
03408       /* Write data to TXDR */
03409       hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
03410       hi2c->XferCount--;
03411       hi2c->XferSize--;
03412     }
03413     else
03414     {
03415       if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
03416       {
03417         /* Last Byte is Transmitted */
03418         /* Call I2C Slave Sequential complete process */
03419         I2C_ITSlaveSequentialCplt(hi2c);
03420       }
03421     }
03422   }
03423 
03424   /* Check if STOPF is set */
03425   if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03426   {
03427     /* Call I2C Slave complete process */
03428     I2C_ITSlaveCplt(hi2c, ITFlags);
03429   }
03430 
03431   /* Process Unlocked */
03432   __HAL_UNLOCK(hi2c);
03433 
03434   return HAL_OK;
03435 }
03436 
03437 /**
03438   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
03439   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03440   *                the configuration information for the specified I2C.
03441   * @param  ITFlags Interrupt flags to handle.
03442   * @param  ITSources Interrupt sources enabled.
03443   * @retval HAL status
03444   */
03445 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
03446 {
03447   uint16_t devaddress = 0U;
03448   uint32_t xfermode = 0U;
03449 
03450   /* Process Locked */
03451   __HAL_LOCK(hi2c);
03452 
03453   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03454   {
03455     /* Clear NACK Flag */
03456     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03457 
03458     /* Set corresponding Error Code */
03459     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03460     
03461     /* No need to generate STOP, it is automatically done */
03462     /* But enable STOP interrupt, to treat it */
03463     /* Error callback will be send during stop flag treatment */
03464     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
03465 
03466     /* Flush TX register */
03467     I2C_Flush_TXDR(hi2c);
03468   }
03469   else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
03470   {
03471     /* Disable TC interrupt */
03472     __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
03473     
03474     if(hi2c->XferCount != 0U)
03475     {
03476       /* Recover Slave address */
03477       devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
03478       
03479       /* Prepare the new XferSize to transfer */
03480       if(hi2c->XferCount > MAX_NBYTE_SIZE)
03481       {
03482         hi2c->XferSize = MAX_NBYTE_SIZE;
03483         xfermode = I2C_RELOAD_MODE;
03484       }
03485       else
03486       {
03487         hi2c->XferSize = hi2c->XferCount;
03488         xfermode = I2C_AUTOEND_MODE;
03489       }
03490 
03491       /* Set the new XferSize in Nbytes register */
03492       I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
03493 
03494       /* Update XferCount value */
03495       hi2c->XferCount -= hi2c->XferSize;
03496 
03497       /* Enable DMA Request */
03498       if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03499       {
03500         hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
03501       }
03502       else
03503       {
03504         hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
03505       }
03506     }
03507     else
03508     {
03509       /* Wrong size Status regarding TCR flag event */
03510       /* Call the corresponding callback to inform upper layer of End of Transfer */
03511       I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
03512     }
03513   }
03514   else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03515   {
03516     /* Call I2C Master complete process */
03517     I2C_ITMasterCplt(hi2c, ITFlags);
03518   }
03519 
03520   /* Process Unlocked */
03521   __HAL_UNLOCK(hi2c);
03522 
03523   return HAL_OK;
03524 }
03525 
03526 /**
03527   * @brief  Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
03528   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03529   *                the configuration information for the specified I2C.
03530   * @param  ITFlags Interrupt flags to handle.
03531   * @param  ITSources Interrupt sources enabled.
03532   * @retval HAL status
03533   */
03534 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) 
03535 {
03536   /* Process locked */
03537   __HAL_LOCK(hi2c);
03538   
03539   if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
03540   {
03541     /* Check that I2C transfer finished */
03542     /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
03543     /* Mean XferCount == 0 */
03544     /* So clear Flag NACKF only */
03545     if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
03546     {
03547       /* Clear NACK Flag */
03548       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03549     }
03550     else
03551     {
03552       /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
03553       /* Clear NACK Flag */
03554       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03555       
03556       /* Set ErrorCode corresponding to a Non-Acknowledge */
03557       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03558     }
03559   }
03560   else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
03561   {
03562     /* Clear ADDR flag */
03563     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03564   }
03565   else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
03566   {
03567     /* Call I2C Slave complete process */
03568     I2C_ITSlaveCplt(hi2c, ITFlags);
03569   }
03570 
03571   /* Process Unlocked */
03572   __HAL_UNLOCK(hi2c);
03573 
03574   return HAL_OK;
03575 }
03576 
03577 /**
03578   * @brief  Master sends target device address followed by internal memory address for write request.
03579   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03580   *                the configuration information for the specified I2C.
03581   * @param  DevAddress Target device address
03582   * @param  MemAddress Internal memory address
03583   * @param  MemAddSize Size of internal memory address
03584   * @param  Timeout Timeout duration
03585   * @param  Tickstart Tick start value
03586   * @retval HAL status
03587   */
03588 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03589 {
03590   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
03591 
03592   /* Wait until TXIS flag is set */
03593   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03594   {
03595     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03596     {
03597       return HAL_ERROR;
03598     }
03599     else
03600     {
03601       return HAL_TIMEOUT;
03602     }
03603   }
03604 
03605   /* If Memory address size is 8Bit */
03606   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03607   {
03608     /* Send Memory Address */
03609     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03610   }
03611   /* If Memory address size is 16Bit */
03612   else
03613   {
03614     /* Send MSB of Memory Address */
03615     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03616 
03617     /* Wait until TXIS flag is set */
03618     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03619     {
03620       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03621       {
03622         return HAL_ERROR;
03623       }
03624       else
03625       {
03626         return HAL_TIMEOUT;
03627       }
03628     }
03629     
03630     /* Send LSB of Memory Address */
03631     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03632   }
03633 
03634   /* Wait until TCR flag is set */
03635   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
03636   {
03637     return HAL_TIMEOUT;
03638   }
03639 
03640 return HAL_OK;
03641 }
03642 
03643 /**
03644   * @brief  Master sends target device address followed by internal memory address for read request.
03645   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
03646   *                the configuration information for the specified I2C.
03647   * @param  DevAddress Target device address
03648   * @param  MemAddress Internal memory address
03649   * @param  MemAddSize Size of internal memory address
03650   * @param  Timeout Timeout duration
03651   * @param  Tickstart Tick start value
03652   * @retval HAL status
03653   */
03654 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
03655 {
03656   I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
03657 
03658   /* Wait until TXIS flag is set */
03659   if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03660   {
03661     if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03662     {
03663       return HAL_ERROR;
03664     }
03665     else
03666     {
03667       return HAL_TIMEOUT;
03668     }
03669   }
03670 
03671   /* If Memory address size is 8Bit */
03672   if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
03673   {
03674     /* Send Memory Address */
03675     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03676   }
03677   /* If Memory address size is 16Bit */
03678   else
03679   {
03680     /* Send MSB of Memory Address */
03681     hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
03682 
03683     /* Wait until TXIS flag is set */
03684     if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
03685     {
03686       if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
03687       {
03688         return HAL_ERROR;
03689       }
03690       else
03691       {
03692         return HAL_TIMEOUT;
03693       }
03694     }
03695     
03696     /* Send LSB of Memory Address */
03697     hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
03698   }
03699 
03700   /* Wait until TC flag is set */
03701   if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
03702   {
03703     return HAL_TIMEOUT;
03704   }
03705   
03706   return HAL_OK;
03707 }
03708 
03709 /**
03710   * @brief  I2C Address complete process callback.
03711   * @param  hi2c I2C handle.
03712   * @param  ITFlags Interrupt flags to handle.
03713   * @retval None
03714   */
03715 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03716 {
03717   uint8_t transferdirection = 0U;
03718   uint16_t slaveaddrcode = 0U;
03719   uint16_t ownadd1code = 0U;
03720   uint16_t ownadd2code = 0U;
03721 
03722   /* In case of Listen state, need to inform upper layer of address match code event */
03723   if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
03724   {
03725     transferdirection = I2C_GET_DIR(hi2c);
03726     slaveaddrcode     = I2C_GET_ADDR_MATCH(hi2c);
03727     ownadd1code       = I2C_GET_OWN_ADDRESS1(hi2c);
03728     ownadd2code       = I2C_GET_OWN_ADDRESS2(hi2c);
03729 
03730     /* If 10bits addressing mode is selected */
03731     if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
03732     {
03733       if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
03734       {
03735         slaveaddrcode = ownadd1code;
03736         hi2c->AddrEventCount++;
03737         if(hi2c->AddrEventCount == 2U)
03738         {
03739           /* Reset Address Event counter */
03740           hi2c->AddrEventCount = 0U;
03741 
03742           /* Clear ADDR flag */
03743           __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
03744 
03745           /* Process Unlocked */
03746           __HAL_UNLOCK(hi2c);
03747 
03748           /* Call Slave Addr callback */
03749           HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03750         }
03751       }
03752       else
03753       {
03754         slaveaddrcode = ownadd2code;
03755 
03756         /* Disable ADDR Interrupts */
03757         I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03758 
03759         /* Process Unlocked */
03760         __HAL_UNLOCK(hi2c);
03761 
03762         /* Call Slave Addr callback */
03763         HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03764       }
03765     }
03766     /* else 7 bits addressing mode is selected */
03767     else
03768     {
03769       /* Disable ADDR Interrupts */
03770       I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
03771 
03772       /* Process Unlocked */
03773       __HAL_UNLOCK(hi2c);
03774 
03775       /* Call Slave Addr callback */
03776       HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
03777     }
03778   }
03779   /* Else clear address flag only */
03780   else
03781   {
03782     /* Clear ADDR flag */
03783     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
03784 
03785     /* Process Unlocked */
03786     __HAL_UNLOCK(hi2c);
03787   }
03788 }
03789 
03790 /**
03791   * @brief  I2C Master sequential complete process.
03792   * @param  hi2c I2C handle.
03793   * @retval None
03794   */
03795 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
03796 {
03797   /* Reset I2C handle mode */
03798   hi2c->Mode = HAL_I2C_MODE_NONE;
03799 
03800   /* No Generate Stop, to permit restart mode */
03801   /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
03802   if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
03803   {
03804     hi2c->State         = HAL_I2C_STATE_READY;
03805     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
03806     hi2c->XferISR       = NULL;
03807 
03808     /* Disable Interrupts */
03809     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03810 
03811     /* Process Unlocked */
03812     __HAL_UNLOCK(hi2c);
03813 
03814     /* Call the corresponding callback to inform upper layer of End of Transfer */
03815     HAL_I2C_MasterTxCpltCallback(hi2c);
03816   }
03817   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03818   else
03819   {
03820     hi2c->State         = HAL_I2C_STATE_READY;
03821     hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
03822     hi2c->XferISR       = NULL;
03823 
03824     /* Disable Interrupts */
03825     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03826 
03827     /* Process Unlocked */
03828     __HAL_UNLOCK(hi2c);
03829 
03830     /* Call the corresponding callback to inform upper layer of End of Transfer */
03831     HAL_I2C_MasterRxCpltCallback(hi2c);
03832   }
03833 }
03834 
03835 /**
03836   * @brief  I2C Slave sequential complete process.
03837   * @param  hi2c I2C handle.
03838   * @retval None
03839   */
03840 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
03841 {
03842   /* Reset I2C handle mode */
03843   hi2c->Mode = HAL_I2C_MODE_NONE;
03844 
03845   if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
03846   {
03847     /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
03848     hi2c->State         = HAL_I2C_STATE_LISTEN;
03849     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
03850 
03851     /* Disable Interrupts */
03852     I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
03853 
03854     /* Process Unlocked */
03855     __HAL_UNLOCK(hi2c);
03856 
03857     /* Call the Tx complete callback to inform upper layer of the end of transmit process */
03858     HAL_I2C_SlaveTxCpltCallback(hi2c);
03859   }
03860 
03861   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
03862   {
03863     /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
03864     hi2c->State         = HAL_I2C_STATE_LISTEN;
03865     hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
03866 
03867     /* Disable Interrupts */
03868     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
03869 
03870     /* Process Unlocked */
03871     __HAL_UNLOCK(hi2c);
03872 
03873     /* Call the Rx complete callback to inform upper layer of the end of receive process */
03874     HAL_I2C_SlaveRxCpltCallback(hi2c);
03875   }
03876 }
03877 
03878 /**
03879   * @brief  I2C Master complete process.
03880   * @param  hi2c I2C handle.
03881   * @param  ITFlags Interrupt flags to handle.
03882   * @retval None
03883   */
03884 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03885 {
03886   /* Clear STOP Flag */
03887   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03888 
03889   /* Clear Configuration Register 2 */
03890   I2C_RESET_CR2(hi2c);
03891 
03892   /* Reset handle parameters */
03893   hi2c->PreviousState = I2C_STATE_NONE;
03894   hi2c->XferISR       = NULL;
03895   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
03896 
03897   if((ITFlags & I2C_FLAG_AF) != RESET)
03898   {
03899     /* Clear NACK Flag */
03900     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
03901 
03902     /* Set acknowledge error code */
03903     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
03904   }
03905 
03906   /* Flush TX register */
03907   I2C_Flush_TXDR(hi2c);
03908 
03909   /* Disable Interrupts */
03910   I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
03911 
03912   /* Call the corresponding callback to inform upper layer of End of Transfer */
03913   if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
03914   {
03915     /* Call the corresponding callback to inform upper layer of End of Transfer */
03916     I2C_ITError(hi2c, hi2c->ErrorCode);
03917   }
03918   /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
03919   else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
03920   {
03921     hi2c->State = HAL_I2C_STATE_READY;
03922 
03923     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03924     {
03925       hi2c->Mode = HAL_I2C_MODE_NONE;
03926 
03927       /* Process Unlocked */
03928       __HAL_UNLOCK(hi2c);
03929 
03930       /* Call the corresponding callback to inform upper layer of End of Transfer */
03931       HAL_I2C_MemTxCpltCallback(hi2c);
03932     }
03933     else
03934     {
03935       hi2c->Mode = HAL_I2C_MODE_NONE;
03936 
03937       /* Process Unlocked */
03938       __HAL_UNLOCK(hi2c);
03939 
03940       /* Call the corresponding callback to inform upper layer of End of Transfer */
03941       HAL_I2C_MasterTxCpltCallback(hi2c);
03942     }
03943   }
03944   /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
03945   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
03946   {
03947     hi2c->State = HAL_I2C_STATE_READY;
03948 
03949     if (hi2c->Mode == HAL_I2C_MODE_MEM)
03950     {
03951       hi2c->Mode = HAL_I2C_MODE_NONE;
03952 
03953       /* Process Unlocked */
03954       __HAL_UNLOCK(hi2c);
03955 
03956       HAL_I2C_MemRxCpltCallback(hi2c);
03957     }
03958     else
03959     {
03960       hi2c->Mode = HAL_I2C_MODE_NONE;
03961 
03962       /* Process Unlocked */
03963       __HAL_UNLOCK(hi2c);
03964 
03965       HAL_I2C_MasterRxCpltCallback(hi2c);
03966     }
03967   }
03968 }
03969 
03970 /**
03971   * @brief  I2C Slave complete process.
03972   * @param  hi2c I2C handle.
03973   * @param  ITFlags Interrupt flags to handle.
03974   * @retval None
03975   */
03976 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
03977 {
03978   /* Clear STOP Flag */
03979   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
03980 
03981   /* Clear ADDR flag */
03982   __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
03983 
03984   /* Disable all interrupts */
03985   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
03986 
03987   /* Disable Address Acknowledge */
03988   hi2c->Instance->CR2 |= I2C_CR2_NACK;
03989 
03990   /* Clear Configuration Register 2 */
03991   I2C_RESET_CR2(hi2c);
03992 
03993   /* Flush TX register */
03994   I2C_Flush_TXDR(hi2c);
03995 
03996   /* If a DMA is ongoing, Update handle size context */
03997   if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
03998      ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
03999   {
04000     hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
04001   }
04002 
04003   /* All data are not transferred, so set error code accordingly */
04004   if(hi2c->XferCount != 0U)
04005   {
04006     /* Set ErrorCode corresponding to a Non-Acknowledge */
04007     hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04008   }
04009 
04010   /* Store Last receive data if any */
04011   if(((ITFlags & I2C_FLAG_RXNE) != RESET))
04012   {
04013     /* Read data from RXDR */
04014     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04015 
04016     if((hi2c->XferSize > 0U))
04017     {
04018       hi2c->XferSize--;
04019       hi2c->XferCount--;
04020 
04021       /* Set ErrorCode corresponding to a Non-Acknowledge */
04022       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04023     }
04024   }
04025 
04026   hi2c->PreviousState = I2C_STATE_NONE;
04027   hi2c->Mode = HAL_I2C_MODE_NONE;
04028   hi2c->XferISR = NULL;
04029 
04030   if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
04031   {
04032     /* Call the corresponding callback to inform upper layer of End of Transfer */
04033     I2C_ITError(hi2c, hi2c->ErrorCode);
04034 
04035     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04036     if(hi2c->State == HAL_I2C_STATE_LISTEN)
04037     {
04038       /* Call I2C Listen complete process */
04039       I2C_ITListenCplt(hi2c, ITFlags);
04040     }
04041   }
04042   else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
04043   {
04044     hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04045     hi2c->State = HAL_I2C_STATE_READY;
04046 
04047     /* Process Unlocked */
04048     __HAL_UNLOCK(hi2c);
04049 
04050     /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04051     HAL_I2C_ListenCpltCallback(hi2c);
04052   }
04053   /* Call the corresponding callback to inform upper layer of End of Transfer */
04054   else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
04055   {
04056     hi2c->State = HAL_I2C_STATE_READY;
04057 
04058     /* Process Unlocked */
04059     __HAL_UNLOCK(hi2c);
04060 
04061     /* Call the Slave Rx Complete callback */
04062     HAL_I2C_SlaveRxCpltCallback(hi2c);
04063   }
04064   else
04065   {
04066     hi2c->State = HAL_I2C_STATE_READY;
04067 
04068     /* Process Unlocked */
04069     __HAL_UNLOCK(hi2c);
04070 
04071     /* Call the Slave Tx Complete callback */
04072     HAL_I2C_SlaveTxCpltCallback(hi2c);
04073   }
04074 }
04075 
04076 /**
04077   * @brief  I2C Listen complete process.
04078   * @param  hi2c I2C handle.
04079   * @param  ITFlags Interrupt flags to handle.
04080   * @retval None
04081   */
04082 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
04083 {
04084   /* Reset handle parameters */
04085   hi2c->XferOptions = I2C_NO_OPTION_FRAME;
04086   hi2c->PreviousState = I2C_STATE_NONE;
04087   hi2c->State = HAL_I2C_STATE_READY;
04088   hi2c->Mode = HAL_I2C_MODE_NONE;
04089   hi2c->XferISR = NULL;
04090 
04091   /* Store Last receive data if any */
04092   if(((ITFlags & I2C_FLAG_RXNE) != RESET))
04093   {
04094     /* Read data from RXDR */
04095     (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
04096 
04097     if((hi2c->XferSize > 0U))
04098     {
04099       hi2c->XferSize--;
04100       hi2c->XferCount--;
04101 
04102       /* Set ErrorCode corresponding to a Non-Acknowledge */
04103       hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
04104     }
04105   }
04106 
04107   /* Disable all Interrupts*/
04108   I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04109 
04110   /* Clear NACK Flag */
04111   __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04112 
04113   /* Process Unlocked */
04114   __HAL_UNLOCK(hi2c);
04115 
04116   /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
04117   HAL_I2C_ListenCpltCallback(hi2c);
04118 }
04119 
04120 /**
04121   * @brief  I2C interrupts error process.
04122   * @param  hi2c I2C handle.
04123   * @param  ErrorCode Error code to handle.
04124   * @retval None
04125   */
04126 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
04127 {
04128   /* Reset handle parameters */
04129   hi2c->Mode          = HAL_I2C_MODE_NONE;
04130   hi2c->XferOptions   = I2C_NO_OPTION_FRAME;
04131   hi2c->XferCount     = 0U;
04132 
04133   /* Set new error code */
04134   hi2c->ErrorCode |= ErrorCode;
04135 
04136   /* Disable Interrupts */
04137   if((hi2c->State == HAL_I2C_STATE_LISTEN)         ||
04138      (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
04139      (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
04140   {
04141     /* Disable all interrupts, except interrupts related to LISTEN state */
04142     I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04143 
04144     /* keep HAL_I2C_STATE_LISTEN if set */
04145     hi2c->State         = HAL_I2C_STATE_LISTEN;
04146     hi2c->PreviousState = I2C_STATE_NONE;
04147     hi2c->XferISR       = I2C_Slave_ISR_IT;
04148   }
04149   else
04150   {
04151     /* Disable all interrupts */
04152     I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
04153     
04154     /* If state is an abort treatment on goind, don't change state */
04155     /* This change will be do later */
04156     if(hi2c->State != HAL_I2C_STATE_ABORT)
04157     {
04158       /* Set HAL_I2C_STATE_READY */
04159       hi2c->State         = HAL_I2C_STATE_READY;
04160     }
04161     hi2c->PreviousState = I2C_STATE_NONE;
04162     hi2c->XferISR       = NULL;
04163   }
04164 
04165   /* Abort DMA TX transfer if any */
04166   if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
04167   {
04168     hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04169 
04170     /* Set the I2C DMA Abort callback :
04171        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04172     hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
04173 
04174     /* Process Unlocked */
04175     __HAL_UNLOCK(hi2c);
04176 
04177     /* Abort DMA TX */
04178     if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
04179     {
04180       /* Call Directly XferAbortCallback function in case of error */
04181       hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
04182     }
04183   }
04184   /* Abort DMA RX transfer if any */
04185   else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
04186   {
04187     hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04188 
04189     /* Set the I2C DMA Abort callback :
04190        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
04191     hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
04192 
04193     /* Process Unlocked */
04194     __HAL_UNLOCK(hi2c);
04195 
04196     /* Abort DMA RX */
04197     if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
04198     {
04199       /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
04200       hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
04201     }
04202   }
04203   else if(hi2c->State == HAL_I2C_STATE_ABORT)
04204   {
04205     hi2c->State = HAL_I2C_STATE_READY;
04206     
04207     /* Process Unlocked */
04208     __HAL_UNLOCK(hi2c);
04209 
04210     /* Call the corresponding callback to inform upper layer of End of Transfer */
04211     HAL_I2C_AbortCpltCallback(hi2c);
04212   }
04213   else
04214   {
04215     /* Process Unlocked */
04216     __HAL_UNLOCK(hi2c);
04217 
04218     /* Call the corresponding callback to inform upper layer of End of Transfer */
04219     HAL_I2C_ErrorCallback(hi2c);
04220   }
04221 }
04222 
04223 /**
04224   * @brief  I2C Tx data register flush process.
04225   * @param  hi2c I2C handle.
04226   * @retval None
04227   */
04228 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
04229 {
04230   /* If a pending TXIS flag is set */
04231   /* Write a dummy data in TXDR to clear it */
04232   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
04233   {
04234      hi2c->Instance->TXDR = 0x00U;
04235   }
04236 
04237   /* Flush TX register if not empty */
04238   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
04239   {
04240     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
04241   }
04242 }
04243 
04244 /**
04245   * @brief  DMA I2C master transmit process complete callback.
04246   * @param  hdma DMA handle
04247   * @retval None
04248   */
04249 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
04250 {
04251   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04252 
04253   /* Disable DMA Request */
04254   hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
04255 
04256   /* If last transfer, enable STOP interrupt */
04257   if(hi2c->XferCount == 0U)
04258   {
04259     /* Enable STOP interrupt */
04260     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04261   }
04262   /* else prepare a new DMA transfer and enable TCReload interrupt */
04263   else
04264   {
04265     /* Update Buffer pointer */
04266     hi2c->pBuffPtr += hi2c->XferSize;
04267 
04268     /* Set the XferSize to transfer */
04269     if(hi2c->XferCount > MAX_NBYTE_SIZE)
04270     {
04271       hi2c->XferSize = MAX_NBYTE_SIZE;
04272     }
04273     else
04274     {
04275       hi2c->XferSize = hi2c->XferCount;
04276     }
04277 
04278     /* Enable the DMA channel */
04279     HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
04280 
04281     /* Enable TC interrupts */
04282     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04283   }
04284 }
04285 
04286 /**
04287   * @brief  DMA I2C slave transmit process complete callback.
04288   * @param  hdma DMA handle
04289   * @retval None
04290   */
04291 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
04292 {
04293   /* No specific action, Master fully manage the generation of STOP condition */
04294   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04295   /* So STOP condition should be manage through Interrupt treatment */
04296 }
04297 
04298 /**
04299   * @brief DMA I2C master receive process complete callback.
04300   * @param  hdma DMA handle
04301   * @retval None
04302   */
04303 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
04304 {
04305   I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
04306 
04307   /* Disable DMA Request */
04308   hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
04309 
04310   /* If last transfer, enable STOP interrupt */
04311   if(hi2c->XferCount == 0U)
04312   {
04313     /* Enable STOP interrupt */
04314     I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
04315   }
04316   /* else prepare a new DMA transfer and enable TCReload interrupt */
04317   else
04318   {
04319     /* Update Buffer pointer */
04320     hi2c->pBuffPtr += hi2c->XferSize;
04321 
04322     /* Set the XferSize to transfer */
04323     if(hi2c->XferCount > MAX_NBYTE_SIZE)
04324     {
04325       hi2c->XferSize = MAX_NBYTE_SIZE;
04326     }
04327     else
04328     {
04329       hi2c->XferSize = hi2c->XferCount;
04330     }
04331 
04332     /* Enable the DMA channel */
04333     HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
04334 
04335     /* Enable TC interrupts */
04336     I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
04337   }
04338 }
04339 
04340 /**
04341   * @brief  DMA I2C slave receive process complete callback.
04342   * @param  hdma DMA handle
04343   * @retval None
04344   */
04345 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
04346 {
04347   /* No specific action, Master fully manage the generation of STOP condition */
04348   /* Mean that this generation can arrive at any time, at the end or during DMA process */
04349   /* So STOP condition should be manage through Interrupt treatment */
04350 }
04351 
04352 /**
04353   * @brief  DMA I2C communication error callback.
04354   * @param hdma DMA handle
04355   * @retval None
04356   */
04357 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
04358 {
04359   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04360 
04361   /* Disable Acknowledge */
04362   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04363 
04364   /* Call the corresponding callback to inform upper layer of End of Transfer */
04365   I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
04366 }
04367 
04368 /**
04369   * @brief DMA I2C communication abort callback
04370   *        (To be called at end of DMA Abort procedure).
04371   * @param hdma: DMA handle.
04372   * @retval None
04373   */
04374 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
04375 {
04376   I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
04377 
04378   /* Disable Acknowledge */
04379   hi2c->Instance->CR2 |= I2C_CR2_NACK;
04380 
04381   /* Reset AbortCpltCallback */
04382   hi2c->hdmatx->XferAbortCallback = NULL;
04383   hi2c->hdmarx->XferAbortCallback = NULL;
04384 
04385   /* Check if come from abort from user */
04386   if(hi2c->State == HAL_I2C_STATE_ABORT)
04387   {
04388     hi2c->State = HAL_I2C_STATE_READY;
04389     
04390     /* Call the corresponding callback to inform upper layer of End of Transfer */
04391     HAL_I2C_AbortCpltCallback(hi2c);
04392   }
04393   else
04394   {
04395     /* Call the corresponding callback to inform upper layer of End of Transfer */
04396     HAL_I2C_ErrorCallback(hi2c);
04397   }
04398 }
04399 
04400 /**
04401   * @brief  This function handles I2C Communication Timeout.
04402   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04403   *                the configuration information for the specified I2C.
04404   * @param  Flag Specifies the I2C flag to check.
04405   * @param  Status The new Flag status (SET or RESET).
04406   * @param  Timeout Timeout duration
04407   * @param  Tickstart Tick start value
04408   * @retval HAL status
04409   */
04410 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
04411 {
04412   while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
04413   {
04414     /* Check for the Timeout */
04415     if(Timeout != HAL_MAX_DELAY)
04416     {
04417       if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
04418       {
04419         hi2c->State= HAL_I2C_STATE_READY;
04420         hi2c->Mode = HAL_I2C_MODE_NONE;
04421 
04422         /* Process Unlocked */
04423         __HAL_UNLOCK(hi2c);
04424         return HAL_TIMEOUT;
04425       }
04426     }
04427   }
04428   return HAL_OK;
04429 }
04430 
04431 /**
04432   * @brief  This function handles I2C Communication Timeout for specific usage of TXIS flag.
04433   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04434   *                the configuration information for the specified I2C.
04435   * @param  Timeout Timeout duration
04436   * @param  Tickstart Tick start value
04437   * @retval HAL status
04438   */
04439 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04440 {
04441   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
04442   {
04443     /* Check if a NACK is detected */
04444     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04445     {
04446       return HAL_ERROR;
04447     }
04448 
04449     /* Check for the Timeout */
04450     if(Timeout != HAL_MAX_DELAY)
04451     {
04452       if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04453       {
04454         hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04455         hi2c->State= HAL_I2C_STATE_READY;
04456         hi2c->Mode = HAL_I2C_MODE_NONE;
04457 
04458         /* Process Unlocked */
04459         __HAL_UNLOCK(hi2c);
04460 
04461         return HAL_TIMEOUT;
04462       }
04463     }
04464   }
04465   return HAL_OK;
04466 }
04467 
04468 /**
04469   * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.
04470   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04471   *                the configuration information for the specified I2C.
04472   * @param  Timeout Timeout duration
04473   * @param  Tickstart Tick start value
04474   * @retval HAL status
04475   */
04476 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04477 {
04478   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04479   {
04480     /* Check if a NACK is detected */
04481     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04482     {
04483       return HAL_ERROR;
04484     }
04485 
04486     /* Check for the Timeout */
04487     if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04488     {
04489       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04490       hi2c->State= HAL_I2C_STATE_READY;
04491       hi2c->Mode = HAL_I2C_MODE_NONE;
04492 
04493       /* Process Unlocked */
04494       __HAL_UNLOCK(hi2c);
04495 
04496       return HAL_TIMEOUT;
04497     }
04498   }
04499   return HAL_OK;
04500 }
04501 
04502 /**
04503   * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.
04504   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04505   *                the configuration information for the specified I2C.
04506   * @param  Timeout Timeout duration
04507   * @param  Tickstart Tick start value
04508   * @retval HAL status
04509   */
04510 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04511 {
04512   while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
04513   {
04514     /* Check if a NACK is detected */
04515     if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
04516     {
04517       return HAL_ERROR;
04518     }
04519 
04520     /* Check if a STOPF is detected */
04521     if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
04522     {
04523       /* Clear STOP Flag */
04524       __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04525 
04526       /* Clear Configuration Register 2 */
04527       I2C_RESET_CR2(hi2c);
04528 
04529       hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
04530       hi2c->State= HAL_I2C_STATE_READY;
04531       hi2c->Mode = HAL_I2C_MODE_NONE;
04532 
04533       /* Process Unlocked */
04534       __HAL_UNLOCK(hi2c);
04535 
04536       return HAL_ERROR;
04537     }
04538 
04539     /* Check for the Timeout */
04540     if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04541     {
04542       hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
04543       hi2c->State= HAL_I2C_STATE_READY;
04544 
04545       /* Process Unlocked */
04546       __HAL_UNLOCK(hi2c);
04547 
04548       return HAL_TIMEOUT;
04549     }
04550   }
04551   return HAL_OK;
04552 }
04553 
04554 /**
04555   * @brief  This function handles Acknowledge failed detection during an I2C Communication.
04556   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04557   *                the configuration information for the specified I2C.
04558   * @param  Timeout Timeout duration
04559   * @param  Tickstart Tick start value
04560   * @retval HAL status
04561   */
04562 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
04563 {
04564   if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
04565   {
04566     /* Wait until STOP Flag is reset */
04567     /* AutoEnd should be initiate after AF */
04568     while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
04569     {
04570       /* Check for the Timeout */
04571       if(Timeout != HAL_MAX_DELAY)
04572       {
04573       if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
04574         {
04575           hi2c->State= HAL_I2C_STATE_READY;
04576           hi2c->Mode = HAL_I2C_MODE_NONE;
04577 
04578           /* Process Unlocked */
04579           __HAL_UNLOCK(hi2c);
04580           return HAL_TIMEOUT;
04581         }
04582       }
04583     }
04584 
04585     /* Clear NACKF Flag */
04586     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
04587 
04588     /* Clear STOP Flag */
04589     __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
04590 
04591     /* Flush TX register */
04592     I2C_Flush_TXDR(hi2c);
04593 
04594     /* Clear Configuration Register 2 */
04595     I2C_RESET_CR2(hi2c);
04596 
04597     hi2c->ErrorCode = HAL_I2C_ERROR_AF;
04598     hi2c->State= HAL_I2C_STATE_READY;
04599     hi2c->Mode = HAL_I2C_MODE_NONE;
04600 
04601     /* Process Unlocked */
04602     __HAL_UNLOCK(hi2c);
04603 
04604     return HAL_ERROR;
04605   }
04606   return HAL_OK;
04607 }
04608 
04609 /**
04610   * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
04611   * @param  hi2c I2C handle.
04612   * @param  DevAddress Specifies the slave address to be programmed.
04613   * @param  Size Specifies the number of bytes to be programmed.
04614   *   This parameter must be a value between 0 and 255.
04615   * @param  Mode New state of the I2C START condition generation.
04616   *   This parameter can be one of the following values:
04617   *     @arg @ref I2C_RELOAD_MODE Enable Reload mode .
04618   *     @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
04619   *     @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
04620   * @param  Request New state of the I2C START condition generation.
04621   *   This parameter can be one of the following values:
04622   *     @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
04623   *     @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
04624   *     @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
04625   *     @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
04626   * @retval None
04627   */
04628 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c,  uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
04629 {
04630   uint32_t tmpreg = 0U;
04631 
04632   /* Check the parameters */
04633   assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
04634   assert_param(IS_TRANSFER_MODE(Mode));
04635   assert_param(IS_TRANSFER_REQUEST(Request));
04636 
04637   /* Get the CR2 register value */
04638   tmpreg = hi2c->Instance->CR2;
04639 
04640   /* clear tmpreg specific bits */
04641   tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
04642 
04643   /* update tmpreg */
04644   tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
04645             (uint32_t)Mode | (uint32_t)Request);
04646 
04647   /* update CR2 register */
04648   hi2c->Instance->CR2 = tmpreg;
04649 }
04650 
04651 /**
04652   * @brief  Manage the enabling of Interrupts.
04653   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04654   *                the configuration information for the specified I2C.
04655   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
04656   * @retval HAL status
04657   */
04658 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04659 {
04660   uint32_t tmpisr = 0U;
04661 
04662   if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
04663      (hi2c->XferISR == I2C_Slave_ISR_DMA))
04664   {
04665     if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04666     {
04667       /* Enable ERR, STOP, NACK and ADDR interrupts */
04668       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04669     }
04670 
04671     if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04672     {
04673       /* Enable ERR and NACK interrupts */
04674       tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04675     }
04676 
04677     if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04678     {
04679       /* Enable STOP interrupts */
04680       tmpisr |= I2C_IT_STOPI;
04681     }
04682     
04683     if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04684     {
04685       /* Enable TC interrupts */
04686       tmpisr |= I2C_IT_TCI;
04687     }
04688   }
04689   else
04690   {
04691     if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04692     {
04693       /* Enable ERR, STOP, NACK, and ADDR interrupts */
04694       tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04695     }
04696 
04697     if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04698     {
04699       /* Enable ERR, TC, STOP, NACK and RXI interrupts */
04700       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
04701     }
04702 
04703     if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04704     {
04705       /* Enable ERR, TC, STOP, NACK and TXI interrupts */
04706       tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
04707     }
04708 
04709     if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04710     {
04711       /* Enable STOP interrupts */
04712       tmpisr |= I2C_IT_STOPI;
04713     }
04714   }
04715   
04716   /* Enable interrupts only at the end */
04717   /* to avoid the risk of I2C interrupt handle execution before */
04718   /* all interrupts requested done */
04719   __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
04720 
04721   return HAL_OK;
04722 }
04723 
04724 /**
04725   * @brief  Manage the disabling of Interrupts.
04726   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
04727   *                the configuration information for the specified I2C.
04728   * @param  InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
04729   * @retval HAL status
04730   */
04731 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
04732 {
04733   uint32_t tmpisr = 0U;
04734 
04735   if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
04736   {
04737     /* Disable TC and TXI interrupts */
04738     tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
04739 
04740     if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04741     {
04742       /* Disable NACK and STOP interrupts */
04743       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04744     }
04745   }
04746 
04747   if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
04748   {
04749     /* Disable TC and RXI interrupts */
04750     tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
04751 
04752     if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
04753     {
04754       /* Disable NACK and STOP interrupts */
04755       tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04756     }
04757   }
04758 
04759   if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
04760   {
04761     /* Disable ADDR, NACK and STOP interrupts */
04762     tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
04763   }
04764 
04765   if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
04766   {
04767     /* Enable ERR and NACK interrupts */
04768     tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
04769   }
04770 
04771   if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
04772   {
04773     /* Enable STOP interrupts */
04774     tmpisr |= I2C_IT_STOPI;
04775   }
04776   
04777   if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
04778   {
04779     /* Enable TC interrupts */
04780     tmpisr |= I2C_IT_TCI;
04781   }
04782 
04783   /* Disable interrupts only at the end */
04784   /* to avoid a breaking situation like at "t" time */
04785   /* all disable interrupts request are not done */
04786   __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
04787 
04788   return HAL_OK;
04789 }
04790 
04791 /**
04792   * @}
04793   */
04794 
04795 #endif /* HAL_I2C_MODULE_ENABLED */
04796 /**
04797   * @}
04798   */
04799 
04800 /**
04801   * @}
04802   */
04803 
04804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/