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stm32l4xx_hal_flash_ex.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_flash_ex.c 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Extended FLASH HAL module driver. 00008 * This file provides firmware functions to manage the following 00009 * functionalities of the FLASH extended peripheral: 00010 * + Extended programming operations functions 00011 * 00012 @verbatim 00013 ============================================================================== 00014 ##### Flash Extended features ##### 00015 ============================================================================== 00016 00017 [..] Comparing to other previous devices, the FLASH interface for STM32L4xx 00018 devices contains the following additional features 00019 00020 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write 00021 capability (RWW) 00022 (+) Dual bank memory organization 00023 (+) PCROP protection for all banks 00024 00025 ##### How to use this driver ##### 00026 ============================================================================== 00027 [..] This driver provides functions to configure and program the FLASH memory 00028 of all STM32L4xx devices. It includes 00029 (#) Flash Memory Erase functions: 00030 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 00031 HAL_FLASH_Lock() functions 00032 (++) Erase function: Erase page, erase all sectors 00033 (++) There are two modes of erase : 00034 (+++) Polling Mode using HAL_FLASHEx_Erase() 00035 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() 00036 00037 (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to : 00038 (++) Set/Reset the write protection 00039 (++) Set the Read protection Level 00040 (++) Program the user Option Bytes 00041 (++) Configure the PCROP protection 00042 00043 (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to : 00044 (++) Get the value of a write protection area 00045 (++) Know if the read protection is activated 00046 (++) Get the value of the user Option Bytes 00047 (++) Get the value of a PCROP area 00048 00049 @endverbatim 00050 ****************************************************************************** 00051 * @attention 00052 * 00053 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00054 * 00055 * Redistribution and use in source and binary forms, with or without modification, 00056 * are permitted provided that the following conditions are met: 00057 * 1. Redistributions of source code must retain the above copyright notice, 00058 * this list of conditions and the following disclaimer. 00059 * 2. Redistributions in binary form must reproduce the above copyright notice, 00060 * this list of conditions and the following disclaimer in the documentation 00061 * and/or other materials provided with the distribution. 00062 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00063 * may be used to endorse or promote products derived from this software 00064 * without specific prior written permission. 00065 * 00066 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00067 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00068 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00069 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00070 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00071 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00072 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00073 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00074 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00075 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00076 * 00077 ****************************************************************************** 00078 */ 00079 00080 /* Includes ------------------------------------------------------------------*/ 00081 #include "stm32l4xx_hal.h" 00082 00083 /** @addtogroup STM32L4xx_HAL_Driver 00084 * @{ 00085 */ 00086 00087 /** @defgroup FLASHEx FLASHEx 00088 * @brief FALSH Extended HAL module driver 00089 * @{ 00090 */ 00091 00092 #ifdef HAL_FLASH_MODULE_ENABLED 00093 00094 /* Private typedef -----------------------------------------------------------*/ 00095 /* Private define ------------------------------------------------------------*/ 00096 /* Private macro -------------------------------------------------------------*/ 00097 /* Private variables ---------------------------------------------------------*/ 00098 /** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables 00099 * @{ 00100 */ 00101 extern FLASH_ProcessTypeDef pFlash; 00102 /** 00103 * @} 00104 */ 00105 00106 /* Private function prototypes -----------------------------------------------*/ 00107 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 00108 * @{ 00109 */ 00110 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 00111 void FLASH_PageErase(uint32_t Page, uint32_t Banks); 00112 static void FLASH_MassErase(uint32_t Banks); 00113 void FLASH_FlushCaches(void); 00114 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); 00115 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel); 00116 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); 00117 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr); 00118 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset); 00119 static uint32_t FLASH_OB_GetRDP(void); 00120 static uint32_t FLASH_OB_GetUser(void); 00121 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr); 00122 /** 00123 * @} 00124 */ 00125 00126 /* Exported functions -------------------------------------------------------*/ 00127 /** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions 00128 * @{ 00129 */ 00130 00131 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions 00132 * @brief Extended IO operation functions 00133 * 00134 @verbatim 00135 =============================================================================== 00136 ##### Extended programming operation functions ##### 00137 =============================================================================== 00138 [..] 00139 This subsection provides a set of functions allowing to manage the Extended FLASH 00140 programming operations Operations. 00141 00142 @endverbatim 00143 * @{ 00144 */ 00145 /** 00146 * @brief Perform a mass erase or erase the specified FLASH memory pages. 00147 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that 00148 * contains the configuration information for the erasing. 00149 * 00150 * @param[out] PageError : pointer to variable that contains the configuration 00151 * information on faulty page in case of error (0xFFFFFFFF means that all 00152 * the pages have been correctly erased) 00153 * 00154 * @retval HAL Status 00155 */ 00156 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) 00157 { 00158 HAL_StatusTypeDef status = HAL_ERROR; 00159 uint32_t page_index = 0; 00160 00161 /* Process Locked */ 00162 __HAL_LOCK(&pFlash); 00163 00164 /* Check the parameters */ 00165 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); 00166 00167 /* Wait for last operation to be completed */ 00168 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00169 00170 if (status == HAL_OK) 00171 { 00172 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 00173 00174 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 00175 { 00176 /* Mass erase to be done */ 00177 FLASH_MassErase(pEraseInit->Banks); 00178 00179 /* Wait for last operation to be completed */ 00180 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00181 00182 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00183 /* If the erase operation is completed, disable the MER1 and MER2 Bits */ 00184 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2)); 00185 #else 00186 /* If the erase operation is completed, disable the MER1 Bit */ 00187 CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1)); 00188 #endif 00189 } 00190 else 00191 { 00192 /*Initialization of PageError variable*/ 00193 *PageError = 0xFFFFFFFF; 00194 00195 for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) 00196 { 00197 FLASH_PageErase(page_index, pEraseInit->Banks); 00198 00199 /* Wait for last operation to be completed */ 00200 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00201 00202 /* If the erase operation is completed, disable the PER Bit */ 00203 CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB)); 00204 00205 if (status != HAL_OK) 00206 { 00207 /* In case of error, stop erase procedure and return the faulty address */ 00208 *PageError = page_index; 00209 break; 00210 } 00211 } 00212 } 00213 00214 /* Flush the caches to be sure of the data consistency */ 00215 FLASH_FlushCaches(); 00216 } 00217 00218 /* Process Unlocked */ 00219 __HAL_UNLOCK(&pFlash); 00220 00221 return status; 00222 } 00223 00224 /** 00225 * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. 00226 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that 00227 * contains the configuration information for the erasing. 00228 * 00229 * @retval HAL Status 00230 */ 00231 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) 00232 { 00233 HAL_StatusTypeDef status = HAL_OK; 00234 00235 /* Process Locked */ 00236 __HAL_LOCK(&pFlash); 00237 00238 /* Check the parameters */ 00239 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); 00240 00241 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 00242 00243 /* Enable End of Operation and Error interrupts */ 00244 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR); 00245 00246 pFlash.Bank = pEraseInit->Banks; 00247 00248 if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) 00249 { 00250 /* Mass erase to be done */ 00251 pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE; 00252 FLASH_MassErase(pEraseInit->Banks); 00253 } 00254 else 00255 { 00256 /* Erase by page to be done */ 00257 pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE; 00258 pFlash.NbPagesToErase = pEraseInit->NbPages; 00259 pFlash.Page = pEraseInit->Page; 00260 00261 /*Erase 1st page and wait for IT */ 00262 FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); 00263 } 00264 00265 return status; 00266 } 00267 00268 /** 00269 * @brief Program Option bytes. 00270 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that 00271 * contains the configuration information for the programming. 00272 * 00273 * @retval HAL Status 00274 */ 00275 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) 00276 { 00277 HAL_StatusTypeDef status = HAL_ERROR; 00278 00279 /* Process Locked */ 00280 __HAL_LOCK(&pFlash); 00281 00282 /* Check the parameters */ 00283 assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); 00284 00285 pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; 00286 00287 /* Write protection configuration */ 00288 if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET) 00289 { 00290 /* Configure of Write protection on the selected area */ 00291 status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); 00292 } 00293 00294 /* Read protection configuration */ 00295 if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET) 00296 { 00297 /* Configure the Read protection level */ 00298 status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); 00299 } 00300 00301 /* User Configuration */ 00302 if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET) 00303 { 00304 /* Configure the user option bytes */ 00305 status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); 00306 } 00307 00308 /* PCROP Configuration */ 00309 if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET) 00310 { 00311 /* Configure the Proprietary code readout protection */ 00312 status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr); 00313 } 00314 00315 /* Process Unlocked */ 00316 __HAL_UNLOCK(&pFlash); 00317 00318 return status; 00319 } 00320 00321 /** 00322 * @brief Get the Option bytes configuration. 00323 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that contains the 00324 * configuration information. The fields pOBInit->WRPArea and 00325 * pOBInit->PCROPConfig should indicate which area is requested 00326 * for the WRP and PCROP 00327 * 00328 * @retval None 00329 */ 00330 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) 00331 { 00332 pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP); 00333 00334 /* Get write protection on the selected area */ 00335 FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); 00336 00337 /* Get Read protection level */ 00338 pOBInit->RDPLevel = FLASH_OB_GetRDP(); 00339 00340 /* Get the user option bytes */ 00341 pOBInit->USERConfig = FLASH_OB_GetUser(); 00342 00343 /* Get the Proprietary code readout protection */ 00344 FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr)); 00345 00346 } 00347 00348 /** 00349 * @} 00350 */ 00351 00352 /** 00353 * @} 00354 */ 00355 00356 /* Private functions ---------------------------------------------------------*/ 00357 00358 /** @addtogroup FLASHEx_Private_Functions 00359 * @{ 00360 */ 00361 /** 00362 * @brief Mass erase of FLASH memory. 00363 * @param Banks: Banks to be erased 00364 * This parameter can be one of the following values: 00365 * @arg FLASH_BANK_1: Bank1 to be erased 00366 * @arg FLASH_BANK_2: Bank2 to be erased 00367 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased 00368 * @retval None 00369 */ 00370 static void FLASH_MassErase(uint32_t Banks) 00371 { 00372 /* Check the parameters */ 00373 assert_param(IS_FLASH_BANK(Banks)); 00374 00375 /* Set the Mass Erase Bit for the bank 1 if requested */ 00376 if((Banks & FLASH_BANK_1) != RESET) 00377 { 00378 SET_BIT(FLASH->CR, FLASH_CR_MER1); 00379 } 00380 00381 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00382 /* Set the Mass Erase Bit for the bank 2 if requested */ 00383 if((Banks & FLASH_BANK_2) != RESET) 00384 { 00385 SET_BIT(FLASH->CR, FLASH_CR_MER2); 00386 } 00387 #endif 00388 00389 /* Proceed to erase all sectors */ 00390 SET_BIT(FLASH->CR, FLASH_CR_STRT); 00391 } 00392 00393 /** 00394 * @brief Erase the specified FLASH memory page. 00395 * @param Page: FLASH page to erase 00396 * This parameter must be a value between 0 and (max number of pages in the bank - 1) 00397 * @param Banks: Bank(s) where the page will be erased 00398 * This parameter can be one or a combination of the following values: 00399 * @arg FLASH_BANK_1: Page in bank 1 to be erased 00400 * @arg FLASH_BANK_2: Page in bank 2 to be erased 00401 * @retval None 00402 */ 00403 void FLASH_PageErase(uint32_t Page, uint32_t Banks) 00404 { 00405 /* Check the parameters */ 00406 assert_param(IS_FLASH_PAGE(Page)); 00407 assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); 00408 00409 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00410 if((Banks & FLASH_BANK_1) != RESET) 00411 { 00412 CLEAR_BIT(FLASH->CR, FLASH_CR_BKER); 00413 } 00414 else 00415 { 00416 SET_BIT(FLASH->CR, FLASH_CR_BKER); 00417 } 00418 #endif 00419 00420 /* Proceed to erase the page */ 00421 MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << 3)); 00422 SET_BIT(FLASH->CR, FLASH_CR_PER); 00423 SET_BIT(FLASH->CR, FLASH_CR_STRT); 00424 } 00425 00426 /** 00427 * @brief Flush the instruction and data caches. 00428 * @retval None 00429 */ 00430 void FLASH_FlushCaches(void) 00431 { 00432 /* Flush instruction cache */ 00433 if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) 00434 { 00435 /* Disable instruction cache */ 00436 __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); 00437 /* Reset instruction cache */ 00438 __HAL_FLASH_INSTRUCTION_CACHE_RESET(); 00439 /* Enable instruction cache */ 00440 __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); 00441 } 00442 00443 /* Flush data cache */ 00444 if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) 00445 { 00446 /* Disable data cache */ 00447 __HAL_FLASH_DATA_CACHE_DISABLE(); 00448 /* Reset data cache */ 00449 __HAL_FLASH_DATA_CACHE_RESET(); 00450 /* Enable data cache */ 00451 __HAL_FLASH_DATA_CACHE_ENABLE(); 00452 } 00453 } 00454 00455 /** 00456 * @brief Configure the write protection of the desired pages. 00457 * 00458 * @note When the memory read protection level is selected (RDP level = 1), 00459 * it is not possible to program or erase Flash memory if the CPU debug 00460 * features are connected (JTAG or single wire) or boot code is being 00461 * executed from RAM or System flash, even if WRP is not activated. 00462 * @note To configure the WRP options, the option lock bit OPTLOCK must be 00463 * cleared with the call of the HAL_FLASH_OB_Unlock() function. 00464 * @note To validate the WRP options, the option bytes must be reloaded 00465 * through the call of the HAL_FLASH_OB_Launch() function. 00466 * 00467 * @param WRPArea: specifies the area to be configured. 00468 * This parameter can be one of the following values: 00469 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A 00470 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B 00471 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply for STM32L43x/STM32L44x devices) 00472 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply for STM32L43x/STM32L44x devices) 00473 * 00474 * @param WRPStartOffset: specifies the start page of the write protected area 00475 * This parameter can be page number between 0 and (max number of pages in the bank - 1) 00476 * 00477 * @param WRDPEndOffset: specifies the end page of the write protected area 00478 * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) 00479 * 00480 * @retval HAL Status 00481 */ 00482 static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset) 00483 { 00484 HAL_StatusTypeDef status = HAL_OK; 00485 00486 /* Check the parameters */ 00487 assert_param(IS_OB_WRPAREA(WRPArea)); 00488 assert_param(IS_FLASH_PAGE(WRPStartOffset)); 00489 assert_param(IS_FLASH_PAGE(WRDPEndOffset)); 00490 00491 /* Wait for last operation to be completed */ 00492 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00493 00494 if(status == HAL_OK) 00495 { 00496 /* Configure the write protected area */ 00497 if(WRPArea == OB_WRPAREA_BANK1_AREAA) 00498 { 00499 MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), 00500 (WRPStartOffset | (WRDPEndOffset << 16))); 00501 } 00502 else if(WRPArea == OB_WRPAREA_BANK1_AREAB) 00503 { 00504 MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), 00505 (WRPStartOffset | (WRDPEndOffset << 16))); 00506 } 00507 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00508 else if(WRPArea == OB_WRPAREA_BANK2_AREAA) 00509 { 00510 MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), 00511 (WRPStartOffset | (WRDPEndOffset << 16))); 00512 } 00513 else if(WRPArea == OB_WRPAREA_BANK2_AREAB) 00514 { 00515 MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), 00516 (WRPStartOffset | (WRDPEndOffset << 16))); 00517 } 00518 #endif 00519 00520 /* Set OPTSTRT Bit */ 00521 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00522 00523 /* Wait for last operation to be completed */ 00524 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00525 00526 /* If the option byte program operation is completed, disable the OPTSTRT Bit */ 00527 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00528 } 00529 00530 return status; 00531 } 00532 00533 /** 00534 * @brief Set the read protection level. 00535 * 00536 * @note To configure the RDP level, the option lock bit OPTLOCK must be 00537 * cleared with the call of the HAL_FLASH_OB_Unlock() function. 00538 * @note To validate the RDP level, the option bytes must be reloaded 00539 * through the call of the HAL_FLASH_OB_Launch() function. 00540 * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible 00541 * to go back to level 1 or 0 !!! 00542 * 00543 * @param RDPLevel: specifies the read protection level. 00544 * This parameter can be one of the following values: 00545 * @arg OB_RDP_LEVEL_0: No protection 00546 * @arg OB_RDP_LEVEL_1: Read protection of the memory 00547 * @arg OB_RDP_LEVEL_2: Full chip protection 00548 * 00549 * @retval HAL status 00550 */ 00551 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel) 00552 { 00553 HAL_StatusTypeDef status = HAL_OK; 00554 00555 /* Check the parameters */ 00556 assert_param(IS_OB_RDP_LEVEL(RDPLevel)); 00557 00558 /* Wait for last operation to be completed */ 00559 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00560 00561 if(status == HAL_OK) 00562 { 00563 /* Configure the RDP level in the option bytes register */ 00564 MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); 00565 00566 /* Set OPTSTRT Bit */ 00567 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00568 00569 /* Wait for last operation to be completed */ 00570 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00571 00572 /* If the option byte program operation is completed, disable the OPTSTRT Bit */ 00573 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00574 } 00575 00576 return status; 00577 } 00578 00579 /** 00580 * @brief Program the FLASH User Option Byte. 00581 * 00582 * @note To configure the user option bytes, the option lock bit OPTLOCK must 00583 * be cleared with the call of the HAL_FLASH_OB_Unlock() function. 00584 * @note To validate the user option bytes, the option bytes must be reloaded 00585 * through the call of the HAL_FLASH_OB_Launch() function. 00586 * 00587 * @param UserType: The FLASH User Option Bytes to be modified 00588 * @param UserConfig: The FLASH User Option Bytes values: 00589 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16), 00590 * IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), 00591 * DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 00592 * 00593 * @retval HAL status 00594 */ 00595 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) 00596 { 00597 uint32_t optr_reg_val = 0; 00598 uint32_t optr_reg_mask = 0; 00599 HAL_StatusTypeDef status = HAL_OK; 00600 00601 /* Check the parameters */ 00602 assert_param(IS_OB_USER_TYPE(UserType)); 00603 00604 /* Wait for last operation to be completed */ 00605 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00606 00607 if(status == HAL_OK) 00608 { 00609 if((UserType & OB_USER_BOR_LEV) != RESET) 00610 { 00611 /* BOR level option byte should be modified */ 00612 assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); 00613 00614 /* Set value and mask for BOR level option byte */ 00615 optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); 00616 optr_reg_mask |= FLASH_OPTR_BOR_LEV; 00617 } 00618 00619 if((UserType & OB_USER_nRST_STOP) != RESET) 00620 { 00621 /* nRST_STOP option byte should be modified */ 00622 assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); 00623 00624 /* Set value and mask for nRST_STOP option byte */ 00625 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); 00626 optr_reg_mask |= FLASH_OPTR_nRST_STOP; 00627 } 00628 00629 if((UserType & OB_USER_nRST_STDBY) != RESET) 00630 { 00631 /* nRST_STDBY option byte should be modified */ 00632 assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); 00633 00634 /* Set value and mask for nRST_STDBY option byte */ 00635 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); 00636 optr_reg_mask |= FLASH_OPTR_nRST_STDBY; 00637 } 00638 00639 if((UserType & OB_USER_nRST_SHDW) != RESET) 00640 { 00641 /* nRST_SHDW option byte should be modified */ 00642 assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); 00643 00644 /* Set value and mask for nRST_SHDW option byte */ 00645 optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); 00646 optr_reg_mask |= FLASH_OPTR_nRST_SHDW; 00647 } 00648 00649 if((UserType & OB_USER_IWDG_SW) != RESET) 00650 { 00651 /* IWDG_SW option byte should be modified */ 00652 assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); 00653 00654 /* Set value and mask for IWDG_SW option byte */ 00655 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); 00656 optr_reg_mask |= FLASH_OPTR_IWDG_SW; 00657 } 00658 00659 if((UserType & OB_USER_IWDG_STOP) != RESET) 00660 { 00661 /* IWDG_STOP option byte should be modified */ 00662 assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); 00663 00664 /* Set value and mask for IWDG_STOP option byte */ 00665 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); 00666 optr_reg_mask |= FLASH_OPTR_IWDG_STOP; 00667 } 00668 00669 if((UserType & OB_USER_IWDG_STDBY) != RESET) 00670 { 00671 /* IWDG_STDBY option byte should be modified */ 00672 assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); 00673 00674 /* Set value and mask for IWDG_STDBY option byte */ 00675 optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); 00676 optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; 00677 } 00678 00679 if((UserType & OB_USER_WWDG_SW) != RESET) 00680 { 00681 /* WWDG_SW option byte should be modified */ 00682 assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); 00683 00684 /* Set value and mask for WWDG_SW option byte */ 00685 optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); 00686 optr_reg_mask |= FLASH_OPTR_WWDG_SW; 00687 } 00688 00689 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00690 if((UserType & OB_USER_BFB2) != RESET) 00691 { 00692 /* BFB2 option byte should be modified */ 00693 assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2)); 00694 00695 /* Set value and mask for BFB2 option byte */ 00696 optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2); 00697 optr_reg_mask |= FLASH_OPTR_BFB2; 00698 } 00699 00700 if((UserType & OB_USER_DUALBANK) != RESET) 00701 { 00702 /* DUALBANK option byte should be modified */ 00703 assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); 00704 00705 /* Set value and mask for DUALBANK option byte */ 00706 optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); 00707 optr_reg_mask |= FLASH_OPTR_DUALBANK; 00708 } 00709 #endif 00710 00711 if((UserType & OB_USER_nBOOT1) != RESET) 00712 { 00713 /* nBOOT1 option byte should be modified */ 00714 assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1)); 00715 00716 /* Set value and mask for nBOOT1 option byte */ 00717 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1); 00718 optr_reg_mask |= FLASH_OPTR_nBOOT1; 00719 } 00720 00721 if((UserType & OB_USER_SRAM2_PE) != RESET) 00722 { 00723 /* SRAM2_PE option byte should be modified */ 00724 assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE)); 00725 00726 /* Set value and mask for SRAM2_PE option byte */ 00727 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE); 00728 optr_reg_mask |= FLASH_OPTR_SRAM2_PE; 00729 } 00730 00731 if((UserType & OB_USER_SRAM2_RST) != RESET) 00732 { 00733 /* SRAM2_RST option byte should be modified */ 00734 assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); 00735 00736 /* Set value and mask for SRAM2_RST option byte */ 00737 optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); 00738 optr_reg_mask |= FLASH_OPTR_SRAM2_RST; 00739 } 00740 00741 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 00742 if((UserType & OB_USER_nSWBOOT0) != RESET) 00743 { 00744 /* nSWBOOT0 option byte should be modified */ 00745 assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); 00746 00747 /* Set value and mask for nSWBOOT0 option byte */ 00748 optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); 00749 optr_reg_mask |= FLASH_OPTR_nSWBOOT0; 00750 } 00751 00752 if((UserType & OB_USER_nBOOT0) != RESET) 00753 { 00754 /* nBOOT0 option byte should be modified */ 00755 assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); 00756 00757 /* Set value and mask for nBOOT0 option byte */ 00758 optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); 00759 optr_reg_mask |= FLASH_OPTR_nBOOT0; 00760 } 00761 #endif 00762 00763 /* Configure the option bytes register */ 00764 MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); 00765 00766 /* Set OPTSTRT Bit */ 00767 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00768 00769 /* Wait for last operation to be completed */ 00770 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00771 00772 /* If the option byte program operation is completed, disable the OPTSTRT Bit */ 00773 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00774 } 00775 00776 return status; 00777 } 00778 00779 /** 00780 * @brief Configure the Proprietary code readout protection of the desired addresses. 00781 * 00782 * @note To configure the PCROP options, the option lock bit OPTLOCK must be 00783 * cleared with the call of the HAL_FLASH_OB_Unlock() function. 00784 * @note To validate the PCROP options, the option bytes must be reloaded 00785 * through the call of the HAL_FLASH_OB_Launch() function. 00786 * 00787 * @param PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option). 00788 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 00789 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE 00790 * 00791 * @param PCROPStartAddr: specifies the start address of the Proprietary code readout protection 00792 * This parameter can be an address between begin and end of the bank 00793 * 00794 * @param PCROPEndAddr: specifies the end address of the Proprietary code readout protection 00795 * This parameter can be an address between PCROPStartAddr and end of the bank 00796 * 00797 * @retval HAL Status 00798 */ 00799 static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr) 00800 { 00801 HAL_StatusTypeDef status = HAL_OK; 00802 uint32_t reg_value = 0; 00803 uint32_t bank1_addr; 00804 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00805 uint32_t bank2_addr; 00806 #endif 00807 00808 /* Check the parameters */ 00809 assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH)); 00810 assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); 00811 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr)); 00812 assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr)); 00813 00814 /* Wait for last operation to be completed */ 00815 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00816 00817 if(status == HAL_OK) 00818 { 00819 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00820 /* Get the information about the bank swapping */ 00821 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) 00822 { 00823 bank1_addr = FLASH_BASE; 00824 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; 00825 } 00826 else 00827 { 00828 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; 00829 bank2_addr = FLASH_BASE; 00830 } 00831 #else 00832 bank1_addr = FLASH_BASE; 00833 #endif 00834 00835 /* Configure the Proprietary code readout protection */ 00836 if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1) 00837 { 00838 reg_value = ((PCROPStartAddr - bank1_addr) >> 3); 00839 MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value); 00840 00841 reg_value = ((PCROPEndAddr - bank1_addr) >> 3); 00842 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value); 00843 } 00844 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00845 else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2) 00846 { 00847 reg_value = ((PCROPStartAddr - bank2_addr) >> 3); 00848 MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value); 00849 00850 reg_value = ((PCROPEndAddr - bank2_addr) >> 3); 00851 MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value); 00852 } 00853 #endif 00854 00855 MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP)); 00856 00857 /* Set OPTSTRT Bit */ 00858 SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00859 00860 /* Wait for last operation to be completed */ 00861 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); 00862 00863 /* If the option byte program operation is completed, disable the OPTSTRT Bit */ 00864 CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 00865 } 00866 00867 return status; 00868 } 00869 00870 /** 00871 * @brief Return the FLASH Write Protection Option Bytes value. 00872 * 00873 * @param[in] WRPArea: specifies the area to be returned. 00874 * This parameter can be one of the following values: 00875 * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A 00876 * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B 00877 * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A (don't apply to STM32L43x/STM32L44x devices) 00878 * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B (don't apply to STM32L43x/STM32L44x devices) 00879 * 00880 * @param[out] WRPStartOffset: specifies the address where to copied the start page 00881 * of the write protected area 00882 * 00883 * @param[out] WRDPEndOffset: specifies the address where to copied the end page of 00884 * the write protected area 00885 * 00886 * @retval None 00887 */ 00888 static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset) 00889 { 00890 /* Check the parameters */ 00891 assert_param(IS_OB_WRPAREA(WRPArea)); 00892 00893 /* Get the configuration of the write protected area */ 00894 if(WRPArea == OB_WRPAREA_BANK1_AREAA) 00895 { 00896 *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT); 00897 *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16); 00898 } 00899 else if(WRPArea == OB_WRPAREA_BANK1_AREAB) 00900 { 00901 *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT); 00902 *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16); 00903 } 00904 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00905 else if(WRPArea == OB_WRPAREA_BANK2_AREAA) 00906 { 00907 *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT); 00908 *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16); 00909 } 00910 else if(WRPArea == OB_WRPAREA_BANK2_AREAB) 00911 { 00912 *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT); 00913 *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16); 00914 } 00915 #endif 00916 } 00917 00918 /** 00919 * @brief Return the FLASH Read Protection level. 00920 * @retval FLASH ReadOut Protection Status: 00921 * This return value can be one of the following values: 00922 * @arg OB_RDP_LEVEL_0: No protection 00923 * @arg OB_RDP_LEVEL_1: Read protection of the memory 00924 * @arg OB_RDP_LEVEL_2: Full chip protection 00925 */ 00926 static uint32_t FLASH_OB_GetRDP(void) 00927 { 00928 if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && 00929 (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2)) 00930 { 00931 return (OB_RDP_LEVEL_1); 00932 } 00933 else 00934 { 00935 return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP)); 00936 } 00937 } 00938 00939 /** 00940 * @brief Return the FLASH User Option Byte value. 00941 * @retval The FLASH User Option Bytes values: 00942 * For STM32L47x/STM32L48x devices : 00943 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), 00944 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), 00945 * BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 00946 * For STM32L43x/STM32L44x devices : 00947 * BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), 00948 * IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), 00949 * nBOOT1(Bit23), SRAM2_PE(Bit24), SRAM2_RST(Bit25), nSWBOOT0(Bit26) and nBOOT0(Bit27). 00950 */ 00951 static uint32_t FLASH_OB_GetUser(void) 00952 { 00953 uint32_t user_config = READ_REG(FLASH->OPTR); 00954 CLEAR_BIT(user_config, FLASH_OPTR_RDP); 00955 00956 return user_config; 00957 } 00958 00959 /** 00960 * @brief Return the FLASH Write Protection Option Bytes value. 00961 * 00962 * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option). 00963 * This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 00964 * with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE 00965 * 00966 * @param PCROPStartAddr [out]: specifies the address where to copied the start address 00967 * of the Proprietary code readout protection 00968 * 00969 * @param PCROPEndAddr [out]: specifies the address where to copied the end address of 00970 * the Proprietary code readout protection 00971 * 00972 * @retval None 00973 */ 00974 static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr) 00975 { 00976 uint32_t reg_value = 0; 00977 uint32_t bank1_addr; 00978 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00979 uint32_t bank2_addr; 00980 #endif 00981 00982 /* Check the parameters */ 00983 assert_param(IS_FLASH_BANK_EXCLUSIVE((*PCROPConfig) & FLASH_BANK_BOTH)); 00984 00985 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00986 /* Get the information about the bank swapping */ 00987 if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) 00988 { 00989 bank1_addr = FLASH_BASE; 00990 bank2_addr = FLASH_BASE + FLASH_BANK_SIZE; 00991 } 00992 else 00993 { 00994 bank1_addr = FLASH_BASE + FLASH_BANK_SIZE; 00995 bank2_addr = FLASH_BASE; 00996 } 00997 #else 00998 bank1_addr = FLASH_BASE; 00999 #endif 01000 01001 if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1) 01002 { 01003 reg_value = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT); 01004 *PCROPStartAddr = (reg_value << 3) + bank1_addr; 01005 01006 reg_value = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END); 01007 *PCROPEndAddr = (reg_value << 3) + bank1_addr; 01008 } 01009 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 01010 else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2) 01011 { 01012 reg_value = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT); 01013 *PCROPStartAddr = (reg_value << 3) + bank2_addr; 01014 01015 reg_value = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END); 01016 *PCROPEndAddr = (reg_value << 3) + bank2_addr; 01017 } 01018 #endif 01019 01020 *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP); 01021 } 01022 /** 01023 * @} 01024 */ 01025 01026 /** 01027 * @} 01028 */ 01029 01030 #endif /* HAL_FLASH_MODULE_ENABLED */ 01031 01032 /** 01033 * @} 01034 */ 01035 01036 /** 01037 * @} 01038 */ 01039 01040 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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