stm32l4xx_hal_dma.h

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dma.h
00004   * @author  MCD Application Team
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   Header file of DMA HAL module.
00008   ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00012   *
00013   * Redistribution and use in source and binary forms, with or without modification,
00014   * are permitted provided that the following conditions are met:
00015   *   1. Redistributions of source code must retain the above copyright notice,
00016   *      this list of conditions and the following disclaimer.
00017   *   2. Redistributions in binary form must reproduce the above copyright notice,
00018   *      this list of conditions and the following disclaimer in the documentation
00019   *      and/or other materials provided with the distribution.
00020   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00021   *      may be used to endorse or promote products derived from this software
00022   *      without specific prior written permission.
00023   *
00024   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00027   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00028   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00029   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00030   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00031   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00032   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00033   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00034   *
00035   ******************************************************************************
00036   */
00037 
00038 /* Define to prevent recursive inclusion -------------------------------------*/
00039 #ifndef __STM32L4xx_HAL_DMA_H
00040 #define __STM32L4xx_HAL_DMA_H
00041 
00042 #ifdef __cplusplus
00043  extern "C" {
00044 #endif
00045 
00046 /* Includes ------------------------------------------------------------------*/
00047 #include "stm32l4xx_hal_def.h"
00048 
00049 /** @addtogroup STM32L4xx_HAL_Driver
00050   * @{
00051   */
00052 
00053 /** @addtogroup DMA
00054   * @{
00055   */
00056 
00057 /* Exported types ------------------------------------------------------------*/
00058 
00059 /** @defgroup DMA_Exported_Types DMA Exported Types
00060   * @{
00061   */
00062 
00063 /**
00064   * @brief  DMA Configuration Structure definition
00065   */
00066 typedef struct
00067 {
00068   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
00069                                            This parameter can be a value of @ref DMA_request */
00070 
00071   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
00072                                            from memory to memory or from peripheral to memory.
00073                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
00074 
00075   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
00076                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
00077 
00078   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
00079                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
00080 
00081   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
00082                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
00083 
00084   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
00085                                            This parameter can be a value of @ref DMA_Memory_data_size */
00086 
00087   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
00088                                            This parameter can be a value of @ref DMA_mode
00089                                            @note The circular buffer mode cannot be used if the memory-to-memory
00090                                                  data transfer is configured on the selected Channel */
00091 
00092   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
00093                                            This parameter can be a value of @ref DMA_Priority_level */
00094 } DMA_InitTypeDef;
00095 
00096 /**
00097   * @brief  HAL DMA State structures definition
00098   */
00099 typedef enum
00100 {
00101   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */
00102   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use      */
00103   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */
00104   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                     */
00105 }HAL_DMA_StateTypeDef;
00106 
00107 /**
00108   * @brief  HAL DMA Error Code structure definition
00109   */
00110 typedef enum
00111 {
00112   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
00113   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
00114 }HAL_DMA_LevelCompleteTypeDef;
00115 
00116 
00117 /** 
00118   * @brief  HAL DMA Callback ID structure definition
00119   */
00120 typedef enum
00121 {
00122   HAL_DMA_XFER_CPLT_CB_ID          = 0x00,    /*!< Full transfer     */
00123   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01,    /*!< Half transfer     */
00124   HAL_DMA_XFER_ERROR_CB_ID         = 0x02,    /*!< Error             */
00125   HAL_DMA_XFER_ABORT_CB_ID         = 0x03,    /*!< Abort             */
00126   HAL_DMA_XFER_ALL_CB_ID           = 0x04     /*!< All               */
00127     
00128 }HAL_DMA_CallbackIDTypeDef;
00129 
00130 /**
00131   * @brief  DMA handle Structure definition
00132   */
00133 typedef struct __DMA_HandleTypeDef
00134 {
00135   DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
00136                                                                                 
00137   DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
00138                                                                                 
00139   HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
00140                                                                                 
00141   __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
00142                                                                                 
00143   void                  *Parent;                                                     /*!< Parent object state                  */
00144 
00145   void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
00146 
00147   void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
00148 
00149   void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
00150 
00151   void                  (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer abort callback          */  
00152   
00153   __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
00154 
00155   DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
00156   
00157   uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */  
00158 }DMA_HandleTypeDef;
00159 /**
00160   * @}
00161   */
00162 
00163 /* Exported constants --------------------------------------------------------*/
00164 
00165 /** @defgroup DMA_Exported_Constants DMA Exported Constants
00166   * @{
00167   */
00168 
00169 /** @defgroup DMA_Error_Code DMA Error Code
00170   * @{
00171   */
00172 #define HAL_DMA_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error             */
00173 #define HAL_DMA_ERROR_TE            ((uint32_t)0x00000001)    /*!< Transfer error       */
00174 #define HAL_DMA_ERROR_NO_XFER       ((uint32_t)0x00000004)    /*!< no ongoing transfer  */
00175 #define HAL_DMA_ERROR_TIMEOUT       ((uint32_t)0x00000020)    /*!< Timeout error        */
00176 #define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)    /*!< Not supported mode   */
00177 /**
00178   * @}
00179   */
00180 
00181 /** @defgroup DMA_request DMA request
00182   * @{
00183   */
00184 #define DMA_REQUEST_0                     ((uint32_t)0x00000000)
00185 #define DMA_REQUEST_1                     ((uint32_t)0x00000001)
00186 #define DMA_REQUEST_2                     ((uint32_t)0x00000002)
00187 #define DMA_REQUEST_3                     ((uint32_t)0x00000003)
00188 #define DMA_REQUEST_4                     ((uint32_t)0x00000004)
00189 #define DMA_REQUEST_5                     ((uint32_t)0x00000005)
00190 #define DMA_REQUEST_6                     ((uint32_t)0x00000006)
00191 #define DMA_REQUEST_7                     ((uint32_t)0x00000007)
00192 
00193 /**
00194   * @}
00195   */
00196 
00197 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
00198   * @{
00199   */
00200 #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
00201 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
00202 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
00203 
00204 /**
00205   * @}
00206   */
00207 
00208 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
00209   * @{
00210   */
00211 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
00212 #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
00213 /**
00214   * @}
00215   */
00216 
00217 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
00218   * @{
00219   */
00220 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
00221 #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
00222 /**
00223   * @}
00224   */
00225 
00226 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
00227   * @{
00228   */
00229 #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
00230 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
00231 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
00232 /**
00233   * @}
00234   */
00235 
00236 /** @defgroup DMA_Memory_data_size DMA Memory data size
00237   * @{
00238   */
00239 #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
00240 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
00241 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
00242 /**
00243   * @}
00244   */
00245 
00246 /** @defgroup DMA_mode DMA mode
00247   * @{
00248   */
00249 #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
00250 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
00251 /**
00252   * @}
00253   */
00254 
00255 /** @defgroup DMA_Priority_level DMA Priority level
00256   * @{
00257   */
00258 #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
00259 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
00260 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
00261 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
00262 /**
00263   * @}
00264   */
00265 
00266 
00267 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
00268   * @{
00269   */
00270 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
00271 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
00272 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
00273 /**
00274   * @}
00275   */
00276 
00277 /** @defgroup DMA_flag_definitions DMA flag definitions
00278   * @{
00279   */
00280 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
00281 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
00282 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
00283 #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
00284 #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
00285 #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
00286 #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
00287 #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
00288 #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
00289 #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
00290 #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
00291 #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
00292 #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
00293 #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
00294 #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
00295 #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
00296 #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
00297 #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
00298 #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
00299 #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
00300 #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
00301 #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
00302 #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
00303 #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
00304 #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
00305 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
00306 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
00307 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
00308 /**
00309   * @}
00310   */
00311 
00312 /**
00313   * @}
00314   */
00315 
00316 /* Exported macros -----------------------------------------------------------*/
00317 /** @defgroup DMA_Exported_Macros DMA Exported Macros
00318   * @{
00319   */
00320 
00321 /** @brief  Reset DMA handle state.
00322   * @param  __HANDLE__: DMA handle
00323   * @retval None
00324   */
00325 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
00326 
00327 /**
00328   * @brief  Enable the specified DMA Channel.
00329   * @param  __HANDLE__: DMA handle
00330   * @retval None
00331   */
00332 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
00333 
00334 /**
00335   * @brief  Disable the specified DMA Channel.
00336   * @param  __HANDLE__: DMA handle
00337   * @retval None
00338   */
00339 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
00340 
00341 
00342 /* Interrupt & Flag management */
00343 
00344 /**
00345   * @brief  Return the current DMA Channel transfer complete flag.
00346   * @param  __HANDLE__: DMA handle
00347   * @retval The specified transfer complete flag index.
00348   */
00349 
00350 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
00351 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
00352  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
00353  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
00354  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
00355  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
00356  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
00357  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
00358  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
00359  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
00360  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
00361  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
00362  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
00363    DMA_FLAG_TC7)
00364 
00365 /**
00366   * @brief  Return the current DMA Channel half transfer complete flag.
00367   * @param  __HANDLE__: DMA handle
00368   * @retval The specified half transfer complete flag index.
00369   */
00370 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
00371 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
00372  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
00373  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
00374  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
00375  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
00376  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
00377  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
00378  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
00379  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
00380  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
00381  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
00382  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
00383    DMA_FLAG_HT7)
00384 
00385 /**
00386   * @brief  Return the current DMA Channel transfer error flag.
00387   * @param  __HANDLE__: DMA handle
00388   * @retval The specified transfer error flag index.
00389   */
00390 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
00391 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
00392  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
00393  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
00394  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
00395  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
00396  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
00397  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
00398  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
00399  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
00400  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
00401  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
00402  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
00403    DMA_FLAG_TE7)
00404 
00405 /**
00406   * @brief  Return the current DMA Channel Global interrupt flag.
00407   * @param  __HANDLE__: DMA handle
00408   * @retval The specified transfer error flag index.
00409   */
00410 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
00411 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
00412  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
00413  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
00414  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
00415  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
00416  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
00417  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
00418  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
00419  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
00420  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
00421  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
00422  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
00423    DMA_ISR_GIF7)
00424 
00425 /**
00426   * @brief  Get the DMA Channel pending flags.
00427   * @param  __HANDLE__: DMA handle
00428   * @param  __FLAG__: Get the specified flag.
00429   *          This parameter can be any combination of the following values:
00430   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00431   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00432   *            @arg DMA_FLAG_TEx:  Transfer error flag
00433   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00434   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
00435   * @retval The state of FLAG (SET or RESET).
00436   */
00437 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00438  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
00439 
00440 /**
00441   * @brief  Clear the DMA Channel pending flags.
00442   * @param  __HANDLE__: DMA handle
00443   * @param  __FLAG__: specifies the flag to clear.
00444   *          This parameter can be any combination of the following values:
00445   *            @arg DMA_FLAG_TCx:  Transfer complete flag
00446   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
00447   *            @arg DMA_FLAG_TEx:  Transfer error flag
00448   *            @arg DMA_FLAG_GLx:  Global interrupt flag
00449   *         Where x can be from 1 to 7 to select the DMA Channel x flag.
00450   * @retval None
00451   */
00452 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
00453  (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
00454 
00455 /**
00456   * @brief  Enable the specified DMA Channel interrupts.
00457   * @param  __HANDLE__: DMA handle
00458   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00459   *          This parameter can be any combination of the following values:
00460   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00461   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00462   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00463   * @retval None
00464   */
00465 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
00466 
00467 /**
00468   * @brief  Disable the specified DMA Channel interrupts.
00469   * @param  __HANDLE__: DMA handle
00470   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
00471   *          This parameter can be any combination of the following values:
00472   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00473   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00474   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00475   * @retval None
00476   */
00477 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
00478 
00479 /**
00480   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
00481   * @param  __HANDLE__: DMA handle
00482   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
00483   *          This parameter can be one of the following values:
00484   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
00485   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
00486   *            @arg DMA_IT_TE:  Transfer error interrupt mask
00487   * @retval The state of DMA_IT (SET or RESET).
00488   */
00489 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
00490 
00491 /**
00492   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
00493   * @param  __HANDLE__: DMA handle
00494   * @retval The number of remaining data units in the current DMA Channel transfer.
00495   */
00496 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
00497 
00498 /**
00499   * @}
00500   */
00501 
00502 /* Exported functions --------------------------------------------------------*/
00503 
00504 /** @addtogroup DMA_Exported_Functions
00505   * @{
00506   */
00507 
00508 /** @addtogroup DMA_Exported_Functions_Group1
00509   * @{
00510   */
00511 /* Initialization and de-initialization functions *****************************/
00512 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
00513 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
00514 /**
00515   * @}
00516   */
00517 
00518 /** @addtogroup DMA_Exported_Functions_Group2
00519   * @{
00520   */
00521 /* IO operation functions *****************************************************/
00522 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00523 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
00524 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
00525 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
00526 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
00527 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
00528 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
00529 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
00530 
00531 /**
00532   * @}
00533   */
00534 
00535 /** @addtogroup DMA_Exported_Functions_Group3
00536   * @{
00537   */
00538 /* Peripheral State and Error functions ***************************************/
00539 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
00540 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
00541 /**
00542   * @}
00543   */
00544 
00545 /**
00546   * @}
00547   */
00548 
00549 /* Private macros ------------------------------------------------------------*/
00550 /** @defgroup DMA_Private_Macros DMA Private Macros
00551   * @{
00552   */
00553 
00554 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
00555                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
00556                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
00557 
00558 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
00559 
00560 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
00561                                             ((STATE) == DMA_PINC_DISABLE))
00562 
00563 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
00564                                         ((STATE) == DMA_MINC_DISABLE))
00565 
00566 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
00567                                      ((REQUEST) == DMA_REQUEST_1) || \
00568                                      ((REQUEST) == DMA_REQUEST_2) || \
00569                                      ((REQUEST) == DMA_REQUEST_3) || \
00570                                      ((REQUEST) == DMA_REQUEST_4) || \
00571                                      ((REQUEST) == DMA_REQUEST_5) || \
00572                                      ((REQUEST) == DMA_REQUEST_6) || \
00573                                      ((REQUEST) == DMA_REQUEST_7))
00574 
00575 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
00576                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
00577                                            ((SIZE) == DMA_PDATAALIGN_WORD))
00578 
00579 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
00580                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
00581                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
00582 
00583 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
00584                            ((MODE) == DMA_CIRCULAR))
00585 
00586 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
00587                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
00588                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
00589                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
00590 
00591 /**
00592   * @}
00593   */ 
00594 
00595 /* Private functions ---------------------------------------------------------*/
00596 
00597 /**
00598   * @}
00599   */
00600 
00601 /**
00602   * @}
00603   */
00604 
00605 #ifdef __cplusplus
00606 }
00607 #endif
00608 
00609 #endif /* __STM32L4xx_HAL_DMA_H */
00610 
00611 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/