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stm32l4xx_hal_dfsdm.h
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dfsdm.h 00004 * @author MCD Application Team 00005 * @version V1.5.1 00006 * @date 31-May-2016 00007 * @brief Header file of DFSDM HAL module. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00012 * 00013 * Redistribution and use in source and binary forms, with or without modification, 00014 * are permitted provided that the following conditions are met: 00015 * 1. Redistributions of source code must retain the above copyright notice, 00016 * this list of conditions and the following disclaimer. 00017 * 2. Redistributions in binary form must reproduce the above copyright notice, 00018 * this list of conditions and the following disclaimer in the documentation 00019 * and/or other materials provided with the distribution. 00020 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00021 * may be used to endorse or promote products derived from this software 00022 * without specific prior written permission. 00023 * 00024 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00027 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00028 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00029 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00030 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00031 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00032 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00033 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00034 * 00035 ****************************************************************************** 00036 */ 00037 00038 /* Define to prevent recursive inclusion -------------------------------------*/ 00039 #ifndef __STM32L4xx_HAL_DFSDM_H 00040 #define __STM32L4xx_HAL_DFSDM_H 00041 00042 #ifdef __cplusplus 00043 extern "C" { 00044 #endif 00045 00046 #if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) 00047 /* Includes ------------------------------------------------------------------*/ 00048 #include "stm32l4xx_hal_def.h" 00049 00050 /** @addtogroup STM32L4xx_HAL_Driver 00051 * @{ 00052 */ 00053 00054 /** @addtogroup DFSDM 00055 * @{ 00056 */ 00057 00058 /* Exported types ------------------------------------------------------------*/ 00059 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 00060 * @{ 00061 */ 00062 00063 /** 00064 * @brief HAL DFSDM Channel states definition 00065 */ 00066 typedef enum 00067 { 00068 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 00069 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 00070 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 00071 }HAL_DFSDM_Channel_StateTypeDef; 00072 00073 /** 00074 * @brief DFSDM channel output clock structure definition 00075 */ 00076 typedef struct 00077 { 00078 FunctionalState Activation; /*!< Output clock enable/disable */ 00079 uint32_t Selection; /*!< Output clock is system clock or audio clock. 00080 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 00081 uint32_t Divider; /*!< Output clock divider. 00082 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 00083 }DFSDM_Channel_OutputClockTypeDef; 00084 00085 /** 00086 * @brief DFSDM channel input structure definition 00087 */ 00088 typedef struct 00089 { 00090 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. 00091 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 00092 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 00093 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 00094 uint32_t Pins; /*!< Input pins are taken from same or following channel. 00095 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 00096 }DFSDM_Channel_InputTypeDef; 00097 00098 /** 00099 * @brief DFSDM channel serial interface structure definition 00100 */ 00101 typedef struct 00102 { 00103 uint32_t Type; /*!< SPI or Manchester modes. 00104 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 00105 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 00106 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 00107 }DFSDM_Channel_SerialInterfaceTypeDef; 00108 00109 /** 00110 * @brief DFSDM channel analog watchdog structure definition 00111 */ 00112 typedef struct 00113 { 00114 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 00115 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 00116 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 00117 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 00118 }DFSDM_Channel_AwdTypeDef; 00119 00120 /** 00121 * @brief DFSDM channel init structure definition 00122 */ 00123 typedef struct 00124 { 00125 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 00126 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 00127 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 00128 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 00129 int32_t Offset; /*!< DFSDM channel offset. 00130 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00131 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 00132 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00133 }DFSDM_Channel_InitTypeDef; 00134 00135 /** 00136 * @brief DFSDM channel handle structure definition 00137 */ 00138 typedef struct 00139 { 00140 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 00141 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 00142 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 00143 }DFSDM_Channel_HandleTypeDef; 00144 00145 /** 00146 * @brief HAL DFSDM Filter states definition 00147 */ 00148 typedef enum 00149 { 00150 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 00151 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 00152 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 00153 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 00154 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 00155 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 00156 }HAL_DFSDM_Filter_StateTypeDef; 00157 00158 /** 00159 * @brief DFSDM filter regular conversion parameters structure definition 00160 */ 00161 typedef struct 00162 { 00163 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 00164 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00165 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 00166 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 00167 }DFSDM_Filter_RegularParamTypeDef; 00168 00169 /** 00170 * @brief DFSDM filter injected conversion parameters structure definition 00171 */ 00172 typedef struct 00173 { 00174 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 00175 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00176 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 00177 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 00178 uint32_t ExtTrigger; /*!< External trigger. 00179 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 00180 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 00181 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 00182 }DFSDM_Filter_InjectedParamTypeDef; 00183 00184 /** 00185 * @brief DFSDM filter parameters structure definition 00186 */ 00187 typedef struct 00188 { 00189 uint32_t SincOrder; /*!< Sinc filter order. 00190 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 00191 uint32_t Oversampling; /*!< Filter oversampling ratio. 00192 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 00193 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 00194 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 00195 }DFSDM_Filter_FilterParamTypeDef; 00196 00197 /** 00198 * @brief DFSDM filter init structure definition 00199 */ 00200 typedef struct 00201 { 00202 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 00203 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 00204 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 00205 }DFSDM_Filter_InitTypeDef; 00206 00207 /** 00208 * @brief DFSDM filter handle structure definition 00209 */ 00210 typedef struct 00211 { 00212 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 00213 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 00214 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 00215 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 00216 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 00217 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 00218 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 00219 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 00220 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 00221 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 00222 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 00223 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 00224 uint32_t ErrorCode; /*!< DFSDM filter error code */ 00225 }DFSDM_Filter_HandleTypeDef; 00226 00227 /** 00228 * @brief DFSDM filter analog watchdog parameters structure definition 00229 */ 00230 typedef struct 00231 { 00232 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 00233 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 00234 uint32_t Channel; /*!< Analog watchdog channel selection. 00235 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 00236 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 00237 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00238 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 00239 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00240 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 00241 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00242 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 00243 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00244 }DFSDM_Filter_AwdParamTypeDef; 00245 00246 /** 00247 * @} 00248 */ 00249 /* End of exported types -----------------------------------------------------*/ 00250 00251 /* Exported constants --------------------------------------------------------*/ 00252 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 00253 * @{ 00254 */ 00255 00256 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 00257 * @{ 00258 */ 00259 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ 00260 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 00266 * @{ 00267 */ 00268 #define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ 00269 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 00275 * @{ 00276 */ 00277 #define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ 00278 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 00279 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 00280 /** 00281 * @} 00282 */ 00283 00284 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 00285 * @{ 00286 */ 00287 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ 00288 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 00294 * @{ 00295 */ 00296 #define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ 00297 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 00298 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 00299 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 00300 /** 00301 * @} 00302 */ 00303 00304 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 00305 * @{ 00306 */ 00307 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ 00308 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 00309 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 00310 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 00311 /** 00312 * @} 00313 */ 00314 00315 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 00316 * @{ 00317 */ 00318 #define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ 00319 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 00320 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 00321 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 00327 * @{ 00328 */ 00329 #define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ 00330 #define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ 00331 #define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 00337 * @{ 00338 */ 00339 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ 00340 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 00341 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 00342 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 00343 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */ 00344 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */ 00345 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */ 00346 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 00347 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ 00348 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 00349 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 00355 * @{ 00356 */ 00357 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 00358 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 00359 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 00365 * @{ 00366 */ 00367 #define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ 00368 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 00369 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 00370 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 00371 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 00372 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 00373 /** 00374 * @} 00375 */ 00376 00377 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 00378 * @{ 00379 */ 00380 #define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ 00381 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 00382 /** 00383 * @} 00384 */ 00385 00386 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 00387 * @{ 00388 */ 00389 #define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 00390 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ 00391 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ 00392 #define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ 00393 /** 00394 * @} 00395 */ 00396 00397 /** @defgroup DFSDM_BreakSignals DFSDM break signals 00398 * @{ 00399 */ 00400 #define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ 00401 #define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ 00402 #define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ 00403 #define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ 00404 #define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 00410 * @{ 00411 */ 00412 /* DFSDM Channels ------------------------------------------------------------*/ 00413 /* The DFSDM channels are defined as follows: 00414 - in 16-bit LSB the channel mask is set 00415 - in 16-bit MSB the channel number is set 00416 e.g. for channel 5 definition: 00417 - the channel mask is 0x00000020 (bit 5 is set) 00418 - the channel number 5 is 0x00050000 00419 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 00420 #define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) 00421 #define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) 00422 #define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) 00423 #define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) 00424 #define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) 00425 #define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) 00426 #define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) 00427 #define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) 00428 /** 00429 * @} 00430 */ 00431 00432 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 00433 * @{ 00434 */ 00435 #define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ 00436 #define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ 00437 /** 00438 * @} 00439 */ 00440 00441 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 00442 * @{ 00443 */ 00444 #define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ 00445 #define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ 00446 /** 00447 * @} 00448 */ 00449 00450 /** 00451 * @} 00452 */ 00453 /* End of exported constants -------------------------------------------------*/ 00454 00455 /* Exported macros -----------------------------------------------------------*/ 00456 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 00457 * @{ 00458 */ 00459 00460 /** @brief Reset DFSDM channel handle state. 00461 * @param __HANDLE__: DFSDM channel handle. 00462 * @retval None 00463 */ 00464 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 00465 00466 /** @brief Reset DFSDM filter handle state. 00467 * @param __HANDLE__: DFSDM filter handle. 00468 * @retval None 00469 */ 00470 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 00471 00472 /** 00473 * @} 00474 */ 00475 /* End of exported macros ----------------------------------------------------*/ 00476 00477 /* Exported functions --------------------------------------------------------*/ 00478 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 00479 * @{ 00480 */ 00481 00482 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 00483 * @{ 00484 */ 00485 /* Channel initialization and de-initialization functions *********************/ 00486 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00487 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00488 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00489 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00490 /** 00491 * @} 00492 */ 00493 00494 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 00495 * @{ 00496 */ 00497 /* Channel operation functions ************************************************/ 00498 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00499 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00500 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00501 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00502 00503 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00504 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00505 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00506 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00507 00508 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00509 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 00510 00511 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00512 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00513 00514 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00515 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00516 /** 00517 * @} 00518 */ 00519 00520 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 00521 * @{ 00522 */ 00523 /* Channel state function *****************************************************/ 00524 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00525 /** 00526 * @} 00527 */ 00528 00529 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 00530 * @{ 00531 */ 00532 /* Filter initialization and de-initialization functions *********************/ 00533 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00534 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00535 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00536 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00537 /** 00538 * @} 00539 */ 00540 00541 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 00542 * @{ 00543 */ 00544 /* Filter control functions *********************/ 00545 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00546 uint32_t Channel, 00547 uint32_t ContinuousMode); 00548 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00549 uint32_t Channel); 00550 /** 00551 * @} 00552 */ 00553 00554 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 00555 * @{ 00556 */ 00557 /* Filter operation functions *********************/ 00558 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00559 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00560 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00561 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00562 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00563 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00564 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00565 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00566 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00567 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00568 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00569 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00570 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00571 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00572 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00573 DFSDM_Filter_AwdParamTypeDef* awdParam); 00574 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00575 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 00576 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00577 00578 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00579 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00580 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00581 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00582 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00583 00584 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00585 00586 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00587 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00588 00589 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00590 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00591 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00592 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00593 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 00594 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00595 /** 00596 * @} 00597 */ 00598 00599 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 00600 * @{ 00601 */ 00602 /* Filter state functions *****************************************************/ 00603 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00604 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00605 /** 00606 * @} 00607 */ 00608 00609 /** 00610 * @} 00611 */ 00612 /* End of exported functions -------------------------------------------------*/ 00613 00614 /* Private macros ------------------------------------------------------------*/ 00615 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 00616 * @{ 00617 */ 00618 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 00619 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 00620 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) 00621 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 00622 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 00623 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 00624 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 00625 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 00626 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 00627 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 00628 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 00629 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 00630 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 00631 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 00632 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 00633 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 00634 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 00635 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 00636 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 00637 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 00638 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 00639 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 00640 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) 00641 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00642 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) 00643 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) 00644 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00645 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 00646 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00647 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 00648 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 00649 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 00650 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 00651 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 00652 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 00653 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 00654 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 00655 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 00656 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 00657 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 00658 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 00659 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 00660 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 00661 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 00662 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 00663 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 00664 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 00665 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 00666 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 00667 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 00668 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 00669 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) 00670 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) 00671 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 00672 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 00673 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00674 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 00675 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 00676 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 00677 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 00678 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 00679 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 00680 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 00681 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 00682 ((CHANNEL) == DFSDM_CHANNEL_7)) 00683 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) 00684 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 00685 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 00686 /** 00687 * @} 00688 */ 00689 /* End of private macros -----------------------------------------------------*/ 00690 00691 /** 00692 * @} 00693 */ 00694 00695 /** 00696 * @} 00697 */ 00698 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ 00699 #ifdef __cplusplus 00700 } 00701 #endif 00702 00703 #endif /* __STM32L4xx_HAL_DFSDM_H */ 00704 00705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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