stm32l4xx_hal_adc.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_adc.c
00004   * @author  MCD Application conversion
00005   * @version V1.5.1
00006   * @date    31-May-2016
00007   * @brief   This file provides firmware functions to manage the following 
00008   *          functionalities of the Analog to Digital Convertor (ADC)
00009   *          peripheral:
00010   *           + Initialization and de-initialization functions
00011   *             ++ Configuration of ADC
00012   *           + Operation functions
00013   *             ++ Start, stop, get result of regular conversions of regular 
00014   *                using 3 possible modes: polling, interruption or DMA.
00015   *           + Control functions
00016   *             ++ Analog Watchdog configuration
00017   *             ++ Channels configuration on regular group
00018   *           + State functions
00019   *             ++ ADC state machine management
00020   *             ++ Interrupts and flags management
00021   *     
00022    @verbatim      
00023   ==============================================================================
00024                     ##### ADC specific features #####
00025   ==============================================================================
00026   [..] 
00027   (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
00028 
00029   (#) Interrupt generation at the end of regular conversion and in case of 
00030       analog watchdog and overrun events.
00031   
00032   (#) Single and continuous conversion modes.
00033   
00034   (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
00035   
00036   (#) Data alignment with in-built data coherency.
00037   
00038   (#) Channel-wise programmable sampling time.
00039 
00040   (#) External trigger (timer or EXTI) with configurable polarity for  
00041       regular groups.
00042 
00043   (#) DMA request generation for transfer of regular group converted data.
00044   
00045   (#) Configurable delay between conversions in Dual interleaved mode.
00046 
00047   (#) ADC channels selectable single/differential input.
00048 
00049   (#) ADC offset on regular groups.
00050 
00051   (#) ADC supply requirements: 1.62 V to 3.6 V.
00052   
00053   (#) ADC input range: from Vref_ (connected to Vssa) to Vref+ (connected to 
00054       Vdda or to an external voltage reference).
00055       
00056 
00057 
00058                      ##### How to use this driver #####
00059   ==============================================================================
00060     [..]
00061 
00062     (#) Enable the ADC interface 
00063         As prerequisite, in HAL_ADC_MspInit(), ADC clock source must be  
00064         configured at RCC top level.
00065 
00066         Two different clock sources are available:
00067         (++) - the ADC clock can be a specific clock source, coming from the system 
00068         clock, the PLLSAI1 or the PLLSAI2 running up to 80MHz.
00069         (++) - or the ADC clock can be derived from the AHB clock of the ADC bus 
00070        interface, divided by a programmable factor
00071 
00072 
00073         (++) For example, in case of PLLSAI2:
00074             (+++) __HAL_RCC_ADC_CLK_ENABLE();
00075             (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
00076             (+++) where
00077               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC
00078               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLLSAI2
00079 
00080                       
00081     (#) ADC pins configuration
00082          (++) Enable the clock for the ADC GPIOs using the following function:
00083              __HAL_RCC_GPIOx_CLK_ENABLE();   
00084          (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();  
00085   
00086     (#) Configure the ADC parameters (conversion resolution, data alignment,  
00087          continuous mode, ...) using the HAL_ADC_Init() function.
00088          
00089     (#) Optionally, perform an automatic ADC calibration to improve the
00090         conversion accuracy using function HAL_ADCEx_Calibration_Start().
00091 
00092     (#) Activate the ADC peripheral using one of the start functions: 
00093         HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(),
00094         HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT() or 
00095         HAL_ADCEx_MultiModeStart_DMA() when multimode feature is available.
00096   
00097    *** Channels to regular group configuration ***
00098      ============================================
00099      [..]    
00100        (+) To configure the ADC regular group features, use 
00101            HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
00102        (+) To activate the continuous mode, use the HAL_ADC_Init() function.   
00103        (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
00104   
00105      *** DMA for regular configuration ***
00106      ============================================================= 
00107      [..]
00108        (+) To enable the DMA mode for regular group, use the  
00109            HAL_ADC_Start_DMA() function.
00110        (+) To enable the generation of DMA requests continuously at the end of 
00111            the last DMA transfer, resort to DMAContinuousRequests parameter of 
00112            ADC handle initialization structure.
00113   
00114 
00115   
00116     @endverbatim
00117   ******************************************************************************
00118   * @attention
00119   *
00120   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
00121   *
00122   * Redistribution and use in source and binary forms, with or without modification,
00123   * are permitted provided that the following conditions are met:
00124   *   1. Redistributions of source code must retain the above copyright notice,
00125   *      this list of conditions and the following disclaimer.
00126   *   2. Redistributions in binary form must reproduce the above copyright notice,
00127   *      this list of conditions and the following disclaimer in the documentation
00128   *      and/or other materials provided with the distribution.
00129   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00130   *      may be used to endorse or promote products derived from this software
00131   *      without specific prior written permission.
00132   *
00133   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00134   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00135   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00136   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00137   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00138   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00139   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00140   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00141   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00142   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00143   *
00144   ******************************************************************************  
00145   */
00146 
00147 /* Includes ------------------------------------------------------------------*/
00148 #include "stm32l4xx_hal.h"
00149 
00150 /** @addtogroup STM32L4xx_HAL_Driver
00151   * @{
00152   */
00153 
00154 /** @defgroup ADC ADC
00155   * @brief ADC HAL module driver
00156   * @{
00157   */ 
00158 
00159 #ifdef HAL_ADC_MODULE_ENABLED
00160     
00161 /* Private typedef -----------------------------------------------------------*/
00162 /* Private define ------------------------------------------------------------*/
00163 
00164 /** @defgroup ADC_Private_Constants ADC Private Constants
00165   * @{                                                         
00166   */
00167   
00168 #define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
00169                                        ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
00170                                        ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
00171                                        ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL))   /*!< ADC_CFGR fields of parameters that can be updated 
00172                                                                                   when no regular conversion is on-going */
00173                                       
00174 #define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR  |\
00175                                        ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
00176                                        ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
00177                                                                                  (neither regular nor injected) is on-going  */
00178 
00179 #define ADC_CFGR_WD_FIELDS  ((uint32_t)(ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN | \
00180                                         ADC_CFGR_AWD1EN | ADC_CFGR_AWD1CH))  /*!< ADC_CFGR fields of Analog Watchdog parameters that can be updated when no
00181                                                                                   conversion (neither regular nor injected) is on-going  */
00182   
00183 #define ADC_OFR_FIELDS  ((uint32_t)(ADC_OFR1_OFFSET1 | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1_EN)) /*!< ADC_OFR fields of parameters that can be updated when no conversion
00184                                                                                                         (neither regular nor injected) is on-going */
00185 
00186 
00187   
00188 /* Delay to wait before setting ADEN once ADCAL has been reset
00189    must be at least 4 ADC clock cycles.
00190    Assuming lowest ADC clock (140 KHz according to DS), this
00191    4 ADC clock cycles duration is equal to
00192    4 / 140,000 = 0.028 ms.
00193    ADC_ENABLE_TIMEOUT set to 2 is a margin large enough to ensure
00194    the 4 ADC clock cycles have elapsed while waiting for ADRDY
00195    to become 1 */        
00196   #define ADC_ENABLE_TIMEOUT              ((uint32_t)  2)    /*!< ADC enable time-out value  */
00197   #define ADC_DISABLE_TIMEOUT             ((uint32_t)  2)    /*!< ADC disable time-out value */
00198    
00199     
00200                                                                             
00201 /* Delay for ADC voltage regulator startup time                               */
00202 /*  Maximum delay is 10 microseconds                                          */
00203 /* (refer device RM, parameter Tadcvreg_stup).                                */
00204 #define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */
00205   
00206   
00207 /* Timeout to wait for current conversion on going to be completed.           */
00208 /* Timeout fixed to worst case, for 1 channel.                                */
00209 /*   - maximum sampling time (640.5 adc_clk)                                  */
00210 /*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
00211 /*   - ADC clock with prescaler 256                                           */
00212 /*     653 * 256 = 167168 clock cycles max                                    */
00213 /* Unit: cycles of CPU clock.                                                 */
00214 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 167168)  /*!< ADC conversion completion time-out value */
00215   
00216   
00217 
00218   
00219 /**
00220   * @}
00221   */  
00222   
00223 /* Private macro -------------------------------------------------------------*/
00224 /* Private variables ---------------------------------------------------------*/
00225 /* Private function prototypes -----------------------------------------------*/
00226 /* Exported functions --------------------------------------------------------*/
00227 
00228 /** @defgroup ADC_Exported_Functions ADC Exported Functions
00229   * @{
00230   */ 
00231 
00232 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
00233  *  @brief    Initialization and Configuration functions 
00234  *
00235 @verbatim    
00236  ===============================================================================
00237               ##### Initialization and de-initialization functions #####
00238  ===============================================================================
00239     [..]  This section provides functions allowing to:
00240       (+) Initialize and configure the ADC. 
00241       (+) De-initialize the ADC. 
00242          
00243 @endverbatim
00244   * @{
00245   */
00246 
00247 /**
00248   * @brief  Initialize the ADC peripheral and regular group according to  
00249   *         parameters specified in structure "ADC_InitTypeDef".
00250   * @note   As prerequisite, ADC clock must be configured at RCC top level
00251   *         depending on possible clock sources: System/PLLSAI1/PLLSAI2 clocks 
00252   *         or AHB clock.
00253   * @note   Possibility to update parameters on the fly:
00254   *         this function initializes the ADC MSP (HAL_ADC_MspInit()) only when
00255   *         coming from ADC state reset. Following calls to this function can
00256   *         be used to reconfigure some parameters of ADC_InitTypeDef  
00257   *         structure on the fly, without modifying MSP configuration. If ADC  
00258   *         MSP has to be modified again, HAL_ADC_DeInit() must be called
00259   *         before HAL_ADC_Init().
00260   *         The setting of these parameters is conditioned by ADC state.
00261   *         For parameters constraints, see comments of structure 
00262   *         "ADC_InitTypeDef".
00263   * @note   This function configures the ADC within 2 scopes: scope of entire 
00264   *         ADC and scope of regular group. For parameters details, see comments 
00265   *         of structure "ADC_InitTypeDef".
00266   * @note   Parameters related to common ADC registers (ADC clock mode) are set 
00267   *         only if all ADCs are disabled.
00268   *         If this is not the case, these common parameters setting are  
00269   *         bypassed without error reporting: it can be the intended behaviour in
00270   *         case of update of a parameter of ADC_InitTypeDef on the fly,
00271   *         without  disabling the other ADCs.
00272   * @param  hadc: ADC handle
00273   * @retval HAL status
00274   */
00275 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
00276 {
00277   HAL_StatusTypeDef tmp_status = HAL_OK;
00278 
00279   ADC_Common_TypeDef *tmpADC_Common;
00280   uint32_t tmpCFGR = 0;
00281   __IO uint32_t wait_loop_index = 0;
00282   
00283   /* Check ADC handle */
00284   if(hadc == NULL)
00285   {
00286     return HAL_ERROR;
00287   }
00288   
00289   /* Check the parameters */
00290   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00291   assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); 
00292   assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
00293   assert_param(IS_ADC_DFSDMCFG_MODE(hadc));  
00294   assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 
00295   assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
00296   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
00297   assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
00298   assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
00299   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
00300   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
00301   assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
00302   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
00303   assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
00304   
00305   if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
00306   {
00307     assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
00308     assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
00309     
00310     if (hadc->Init.DiscontinuousConvMode == ENABLE)
00311     { 
00312       assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
00313     }
00314   }
00315 
00316   
00317   /* DISCEN and CONT bits can't be set at the same time */
00318   assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
00319  
00320   
00321   /* Actions performed only if ADC is coming from state reset:                */
00322   /* - Initialization of ADC MSP                                              */
00323   if (hadc->State == HAL_ADC_STATE_RESET)
00324   {
00325     /* Init the low level hardware */
00326     HAL_ADC_MspInit(hadc);
00327     
00328     /* Set ADC error code to none */
00329     ADC_CLEAR_ERRORCODE(hadc);
00330     
00331     /* Initialize Lock */
00332     hadc->Lock = HAL_UNLOCKED;
00333   }
00334     
00335     
00336   /* - Exit from deep-power-down mode and ADC voltage regulator enable        */    
00337   /*  Exit deep power down mode if still in that state */
00338   if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_DEEPPWD))
00339   {
00340     /* Exit deep power down mode */ 
00341     CLEAR_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
00342     
00343     /* System was in deep power down mode, calibration must
00344      be relaunched or a previously saved calibration factor 
00345      re-applied once the ADC voltage regulator is enabled */    
00346   }
00347   
00348 
00349   if  (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))
00350   {  
00351     /* Enable ADC internal voltage regulator */
00352     SET_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN);
00353     
00354     /* Delay for ADC stabilization time */
00355     /* Wait loop initialization and execution */
00356     /* Note: Variable divided by 2 to compensate partially                    */
00357     /*       CPU processing cycles.                                           */
00358     wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000 * 2)));
00359     while(wait_loop_index != 0)
00360     {
00361       wait_loop_index--;
00362     }
00363   }
00364 
00365 
00366  
00367   
00368   /* Verification that ADC voltage regulator is correctly enabled, whether    */
00369   /* or not ADC is coming from state reset (if any potential problem of       */
00370   /* clocking, voltage regulator would not be enabled).                       */
00371   if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN))  
00372   {
00373     /* Update ADC state machine to error */
00374     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00375     
00376     /* Set ADC error code to ADC IP internal error */
00377     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
00378     
00379     tmp_status = HAL_ERROR;
00380   }
00381  
00382 
00383   /* Configuration of ADC parameters if previous preliminary actions are      */ 
00384   /* correctly completed and if there is no conversion on going on regular    */
00385   /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
00386   /* called to update a parameter on the fly).                                */
00387   if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL) &&
00388       (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  )
00389   {
00390     
00391     /* Initialize the ADC state */
00392     SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00393     
00394     /* Configuration of common ADC parameters                                 */
00395     
00396     /* Pointer to the common control register                                 */
00397     tmpADC_Common = ADC_COMMON_REGISTER(hadc);
00398     
00399   
00400     /* Parameters update conditioned to ADC state:                            */
00401     /* Parameters that can be updated only when ADC is disabled:              */
00402     /*  - clock configuration                                                 */
00403     if ((ADC_IS_ENABLE(hadc) == RESET)   &&
00404          (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )         
00405     {
00406       /* Reset configuration of ADC common register CCR:                      */
00407       /*                                                                      */
00408       /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
00409       /*     according to adc->Init.ClockPrescaler. It selects the clock      */
00410       /*    source and sets the clock division factor.                        */
00411       /*                                                                      */
00412       /* Some parameters of this register are not reset, since they are set   */
00413       /* by other functions and must be kept in case of usage of this         */
00414       /* function on the fly (update of a parameter of ADC_InitTypeDef        */
00415       /* without needing to reconfigure all other ADC groups/channels         */
00416       /* parameters):                                                         */
00417       /*   - when multimode feature is available, multimode-related           */
00418       /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
00419       /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
00420       /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
00421       /*     (set into HAL_ADC_ConfigChannel() or                             */
00422       /*     HAL_ADCEx_InjectedConfigChannel() )                              */
00423            
00424       MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_PRESC|ADC_CCR_CKMODE, hadc->Init.ClockPrescaler);
00425     }
00426       
00427       
00428     /* Configuration of ADC:                                                  */
00429     /*  - resolution                               Init.Resolution            */
00430     /*  - data alignment                           Init.DataAlign             */
00431     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00432     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
00433     /*  - continuous conversion mode               Init.ContinuousConvMode    */
00434     /*  - overrun                                  Init.Overrun               */
00435     /*  - discontinuous mode                       Init.DiscontinuousConvMode */
00436     /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */    
00437     tmpCFGR  = ( ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode)          |
00438                  hadc->Init.Overrun                                          |
00439                  hadc->Init.DataAlign                                        |
00440                  hadc->Init.Resolution                                       |
00441                 ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) |
00442                 ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion) );
00443       
00444     /* Enable external trigger if trigger selection is different of software  */
00445     /* start.                                                                 */
00446     /*  - external trigger to start conversion     Init.ExternalTrigConv      */
00447     /*  - external trigger polarity                Init.ExternalTrigConvEdge  */    
00448     /* Note:  parameter ExternalTrigConvEdge set to "trigger edge none" is    */
00449     /*        equivalent to software start.                                   */
00450     if ((hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
00451     &&  (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE))
00452     {
00453       tmpCFGR |= ( hadc->Init.ExternalTrigConv |  hadc->Init.ExternalTrigConvEdge);
00454     }
00455     
00456      /* Update Configuration Register CFGR */
00457      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 
00458      
00459 
00460     /* Parameters update conditioned to ADC state:                            */
00461     /* Parameters that can be updated when ADC is disabled or enabled without */
00462     /* conversion on going on regular and injected groups:                    */
00463     /*  - DMA continuous request          Init.DMAContinuousRequests          */
00464     /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
00465     /*  - Oversampling parameters         Init.Oversampling                     */    
00466     if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
00467     {
00468       tmpCFGR = ( ADC_CFGR_DFSDM(hadc)                                 |
00469                   ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait)       |
00470                   ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) );
00471                
00472       MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);                    
00473     
00474  
00475       if (hadc->Init.OversamplingMode == ENABLE)
00476       {
00477         assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
00478         assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
00479         assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
00480         assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
00481         
00482         if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
00483         ||  (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
00484         {
00485             /* Multi trigger is not applicable to software-triggered conversions */
00486             assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
00487         }    
00488     
00489     
00490        /* Configuration of Oversampler:                                       */
00491        /*  - Oversampling Ratio                                               */
00492        /*  - Right bit shift                                                  */
00493        /*  - Triggered mode                                                   */
00494        /*  - Oversampling mode (continued/resumed)                            */    
00495        MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS, 
00496                                ADC_CFGR2_ROVSE                     | 
00497                                hadc->Init.Oversampling.Ratio         |
00498                                hadc->Init.Oversampling.RightBitShift |
00499                                hadc->Init.Oversampling.TriggeredMode |
00500                                hadc->Init.Oversampling.OversamplingStopReset);
00501       }  
00502       else
00503       {
00504         /* Disable Regular OverSampling */
00505         CLEAR_BIT( hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
00506       }    
00507  
00508     
00509     }   /*  if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
00510     
00511 
00512     
00513     
00514     /* Configuration of regular group sequencer:                              */
00515     /* - if scan mode is disabled, regular channels sequence length is set to */
00516     /*   0x00: 1 channel converted (channel on regular rank 1)                */
00517     /*   Parameter "NbrOfConversion" is discarded.                            */
00518     /*   Note: Scan mode is not present by hardware on this device, but       */
00519     /*   emulated by software for alignment over all STM32 devices.           */
00520     /* - if scan mode is enabled, regular channels sequence length is set to  */
00521     /*   parameter "NbrOfConversion"                                          */
00522 
00523     if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
00524     {
00525       /* Set number of ranks in regular group sequencer */     
00526       MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));  
00527     } 
00528     else
00529     {
00530       CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
00531     }
00532     
00533     
00534     /* Initialize the ADC state */
00535     /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
00536     ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
00537   }
00538   else
00539   {
00540     /* Update ADC state machine to error */
00541     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
00542         
00543     tmp_status = HAL_ERROR;
00544   }  /*  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)  && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)  ) */
00545   
00546   
00547   /* Return function status */
00548   return tmp_status;
00549 
00550 }
00551 
00552 /**
00553   * @brief  Deinitialize the ADC peripheral registers to their default reset
00554   *         values, with deinitialization of the ADC MSP.           
00555   * @note   Keep in mind that all ADCs use the same clock: disabling
00556   *         the clock will reset all ADCs.
00557   * @note   By default, HAL_ADC_DeInit() sets DEEPPWD: this saves more power by
00558   *         reducing the leakage currents and is particularly interesting before
00559   *         entering STOP 1 or STOP 2 modes.         
00560   * @param  hadc: ADC handle
00561   * @retval HAL status
00562   */
00563 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
00564 {  
00565   /* Check ADC handle */
00566   if(hadc == NULL)
00567   {
00568      return HAL_ERROR;
00569   }
00570   
00571   /* Check the parameters */
00572   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00573   
00574   /* Change ADC state */
00575   SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
00576   
00577   /* Stop potential conversion on going, on regular and injected groups */
00578   /* No check on ADC_ConversionStop() return status, if the conversion
00579     stop failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */
00580   ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00581 
00582   
00583   /* Disable ADC peripheral if conversions are effectively stopped            */
00584   /* Flush register JSQR: reset the queue sequencer when injected             */
00585   /* queue sequencer is enabled and ADC disabled.                             */
00586   /* The software and hardware triggers of the injected sequence are both     */
00587   /* internally disabled just after the completion of the last valid          */
00588   /* injected sequence.                                                       */
00589   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
00590     
00591   /* Disable the ADC peripheral */
00592   /* No check on ADC_Disable() return status, if the ADC disabling process
00593     failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */  
00594   ADC_Disable(hadc);
00595 
00596 
00597   /* ========== Reset ADC registers ========== */
00598   /* Reset register IER */
00599   __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
00600                               ADC_IT_JQOVF | ADC_IT_OVR  |
00601                               ADC_IT_JEOS  | ADC_IT_JEOC |
00602                               ADC_IT_EOS   | ADC_IT_EOC  |
00603                               ADC_IT_EOSMP | ADC_IT_RDY                 ) );
00604       
00605   /* Reset register ISR */
00606   __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
00607                               ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
00608                               ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
00609                               ADC_FLAG_EOS   | ADC_FLAG_EOC  |
00610                               ADC_FLAG_EOSMP | ADC_FLAG_RDY                   ) );
00611   
00612   /* Reset register CR */
00613  /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, 
00614     ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": 
00615     no direct reset applicable. 
00616     Update CR register to reset value where doable by software */
00617   CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
00618   SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);    
00619       
00620   /* Reset register CFGR */
00621   CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
00622   SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);  
00623   
00624   /* Reset register CFGR2 */
00625   CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |   
00626                                   ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE    );                                 
00627   
00628   /* Reset register SMPR1 */
00629   CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);                                 
00630   
00631   /* Reset register SMPR2 */
00632   CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | 
00633                              ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | 
00634                              ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10    );                                 
00635   
00636   /* Reset register TR1 */
00637   CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
00638   
00639   /* Reset register TR2 */
00640   CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);    
00641   
00642   /* Reset register TR3 */
00643   CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);      
00644   
00645   /* Reset register SQR1 */
00646   CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | 
00647                             ADC_SQR1_SQ1 | ADC_SQR1_L);                              
00648   
00649   /* Reset register SQR2 */
00650   CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | 
00651                             ADC_SQR2_SQ6 | ADC_SQR2_SQ5);                                
00652   
00653   /* Reset register SQR3 */
00654   CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | 
00655                             ADC_SQR3_SQ11 | ADC_SQR3_SQ10);                                 
00656   
00657   /* Reset register SQR4 */
00658   CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); 
00659   
00660   /* Register JSQR was reset when the ADC was disabled */
00661   
00662   /* Reset register DR */
00663   /* bits in access mode read only, no direct reset applicable*/
00664     
00665   /* Reset register OFR1 */
00666   CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); 
00667   /* Reset register OFR2 */
00668   CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); 
00669   /* Reset register OFR3 */
00670   CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); 
00671   /* Reset register OFR4 */
00672   CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
00673   
00674   /* Reset registers JDR1, JDR2, JDR3, JDR4 */
00675   /* bits in access mode read only, no direct reset applicable*/
00676   
00677   /* Reset register AWD2CR */
00678   CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
00679   
00680   /* Reset register AWD3CR */
00681   CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
00682   
00683   /* Reset register DIFSEL */
00684   CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
00685   
00686   /* Reset register CALFACT */
00687   CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
00688 
00689   
00690   
00691   
00692   
00693   
00694   /* ========== Reset common ADC registers ========== */
00695         
00696   /* Software is allowed to change common parameters only when all the other
00697      ADCs are disabled.   */
00698   if ((ADC_IS_ENABLE(hadc) == RESET)   &&
00699        (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
00700   {
00701     /* Reset configuration of ADC common register CCR:
00702       - clock mode: CKMODE, PRESCEN
00703       - multimode related parameters (when this feature is available): MDMA, 
00704         DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
00705       - internal measurement paths: Vbat, temperature sensor, Vref (set into
00706         HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
00707     */
00708     ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
00709   }
00710 
00711   /* DeInit the low level hardware. 
00712   
00713      For example:
00714     __HAL_RCC_ADC_FORCE_RESET();
00715     __HAL_RCC_ADC_RELEASE_RESET();
00716     __HAL_RCC_ADC_CLK_DISABLE();
00717     
00718     Keep in mind that all ADCs use the same clock: disabling
00719     the clock will reset all ADCs. 
00720     
00721   */ 
00722   HAL_ADC_MspDeInit(hadc);
00723     
00724   /* Set ADC error code to none */
00725   ADC_CLEAR_ERRORCODE(hadc);
00726     
00727   /* Reset injected channel configuration parameters */
00728   hadc->InjectionConfig.ContextQueue = 0;
00729   hadc->InjectionConfig.ChannelCount = 0; 
00730     
00731   /* Change ADC state */
00732   hadc->State = HAL_ADC_STATE_RESET;
00733   
00734   /* Process unlocked */
00735   __HAL_UNLOCK(hadc);
00736 
00737   
00738   /* Return function status */
00739   return HAL_OK;
00740 
00741 }
00742     
00743 /**
00744   * @brief  Initialize the ADC MSP.
00745   * @param  hadc: ADC handle
00746   * @retval None
00747   */
00748 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
00749 {
00750   /* Prevent unused argument(s) compilation warning */
00751   UNUSED(hadc);
00752 
00753   /* NOTE : This function should not be modified. When the callback is needed,
00754             function HAL_ADC_MspInit must be implemented in the user file.
00755    */ 
00756 }
00757 
00758 /**
00759   * @brief  DeInitialize the ADC MSP.
00760   * @param  hadc: ADC handle
00761   * @note   All ADCs use the same clock: disabling the clock will reset all ADCs.  
00762   * @retval None
00763   */
00764 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
00765 {
00766   /* Prevent unused argument(s) compilation warning */
00767   UNUSED(hadc);
00768 
00769   /* NOTE : This function should not be modified. When the callback is needed,
00770             function HAL_ADC_MspDeInit must be implemented in the user file.
00771    */ 
00772 }
00773 
00774 /**
00775   * @}
00776   */
00777 
00778 /** @defgroup ADC_Exported_Functions_Group2 Input and Output operation functions
00779  *  @brief    IO operation functions 
00780  *
00781 @verbatim   
00782  ===============================================================================
00783              ##### IO operation functions #####
00784  ===============================================================================  
00785     [..]  This section provides functions allowing to:
00786       (+) Start conversion of regular group.
00787       (+) Stop conversion of regular group.
00788       (+) Poll for conversion complete on regular group.
00789       (+) Poll for conversion event.
00790       (+) Get result of regular channel conversion.
00791       (+) Start conversion of regular group and enable interruptions.
00792       (+) Stop conversion of regular group and disable interruptions.
00793       (+) Handle ADC interrupt request
00794       (+) Start conversion of regular group and enable DMA transfer.
00795       (+) Stop conversion of regular group and disable ADC DMA transfer.
00796                
00797 @endverbatim
00798   * @{
00799   */
00800   
00801 /**
00802   * @brief  Enable ADC, start conversion of regular group.
00803   * @note   Interruptions enabled in this function: None.
00804   * @note   Case of multimode enabled (when multimode feature is available): 
00805   *           if ADC is Slave, ADC is enabled but conversion is not started, 
00806   *           if ADC is master, ADC is enabled and multimode conversion is started.
00807   * @param  hadc: ADC handle
00808   * @retval HAL status
00809   */
00810 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
00811 {
00812   ADC_TypeDef        *tmpADC_Master;
00813   HAL_StatusTypeDef tmp_status = HAL_OK;
00814 
00815   /* Check the parameters */
00816   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00817    
00818   
00819   /* if a regular conversion is already on-going (i.e. ADSTART is set),
00820      don't restart the conversion. */
00821   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
00822   {
00823     return HAL_BUSY;
00824   }
00825   else
00826   {
00827     /* Process locked */
00828     __HAL_LOCK(hadc);
00829     
00830     /* Enable the ADC peripheral */
00831     tmp_status = ADC_Enable(hadc);
00832   
00833     /* Start conversion if ADC is effectively enabled */
00834     if (tmp_status == HAL_OK)
00835     {
00836       /* State machine update: Check if an injected conversion is ongoing */
00837       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
00838       {
00839         /* Reset ADC error code fields related to regular conversions only */
00840         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));         
00841       }
00842       else
00843       {  
00844         /* Set ADC error code to none */
00845         ADC_CLEAR_ERRORCODE(hadc); 
00846       }
00847       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
00848       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
00849 
00850       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
00851         - by default if ADC is Master or Independent or if multimode feature is not available
00852         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
00853       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
00854       {
00855         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00856       }
00857     
00858       /* Clear regular group conversion flag and overrun flag                   */
00859       /* (To ensure of no unknown state from potential previous ADC operations) */
00860       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
00861     
00862       /* Enable conversion of regular group.                                  */
00863       /* If software start has been selected, conversion starts immediately.  */
00864       /* If external trigger has been selected, conversion starts at next     */
00865       /* trigger event.                                                       */
00866       /* Case of multimode enabled (when multimode feature is available):     */ 
00867       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
00868       /*    enabled only (conversion is not started),                         */
00869       /*  - if ADC is master, ADC is enabled and conversion is started.       */
00870       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
00871       {
00872         /* Multimode feature is not available or ADC Instance is Independent or Master, 
00873            or is not Slave ADC with dual regular conversions enabled. 
00874            Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */
00875         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
00876         {
00877           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
00878         }
00879         /* Process unlocked */
00880         __HAL_UNLOCK(hadc);
00881         /* Start ADC */
00882         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
00883       }
00884       else
00885       {
00886         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
00887         /* if Master ADC JAUTO bit is set, update Slave State in setting 
00888            HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
00889         tmpADC_Master = ADC_MASTER_REGISTER(hadc); 
00890         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
00891         {
00892           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
00893            
00894         }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
00895         /* Process unlocked */
00896         __HAL_UNLOCK(hadc);      
00897       } /* if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) */
00898     }
00899     else
00900     {
00901       /* Process unlocked */
00902       __HAL_UNLOCK(hadc);    
00903     }    
00904   
00905   /* Return function status */
00906   return tmp_status;
00907   }
00908 }
00909 
00910 /**  
00911   * @brief  Stop ADC conversion of regular and injected groups, disable ADC peripheral.
00912   * @param  hadc: ADC handle
00913   * @retval HAL status.
00914   */
00915 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
00916 { 
00917   HAL_StatusTypeDef tmp_status = HAL_OK;
00918   
00919   /* Check the parameters */
00920   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00921   
00922   /* Process locked */
00923   __HAL_LOCK(hadc);
00924   
00925   /* 1. Stop potential regular and injected on-going conversions */
00926   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
00927   
00928   /* Disable ADC peripheral if conversions are effectively stopped */
00929   if (tmp_status == HAL_OK)
00930   {
00931     /* 2. Disable the ADC peripheral */
00932     tmp_status = ADC_Disable(hadc);
00933     
00934     /* Check if ADC is effectively disabled */
00935     if (tmp_status == HAL_OK)
00936     {
00937       /* Change ADC state */
00938       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
00939       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);
00940     }
00941   }
00942 
00943   /* Process unlocked */
00944   __HAL_UNLOCK(hadc);
00945   
00946   /* Return function status */
00947   return tmp_status;
00948 }
00949 
00950 
00951 
00952 /**
00953   * @brief  Wait for regular group conversion to be completed.
00954   * @param  hadc: ADC handle
00955   * @param  Timeout: Timeout value in millisecond.
00956   * @note   Depending on hadc->Init.EOCSelection, EOS or EOC is 
00957   *         checked and cleared depending on AUTDLY bit status. 
00958   * @note   HAL_ADC_PollForConversion() returns HAL_ERROR if EOC is polled in a
00959   *         DMA-managed conversions configuration: indeed, EOC is immediately 
00960   *         reset by the DMA reading the DR register when the converted data is
00961   *         available. Therefore, EOC is set for a too short period to be 
00962   *         reliably polled.                    
00963   * @retval HAL status
00964   */
00965 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
00966 {
00967   uint32_t           tickstart;
00968   uint32_t           tmp_Flag_End   = 0x00;
00969   ADC_TypeDef        *tmpADC_Master;
00970   uint32_t           tmp_cfgr       = 0x00;
00971   uint32_t           tmp_eos_raised = 0x01; /* by default, assume that EOS is set, 
00972                                                tmp_eos_raised will be corrected
00973                                                accordingly during API execution */ 
00974  
00975   /* Check the parameters */
00976   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
00977 
00978   /* If end of sequence selected */
00979   if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
00980   {
00981     tmp_Flag_End = ADC_FLAG_EOS;
00982   }
00983   else /* end of conversion selected */
00984   {
00985     /* Check that the ADC is not in a DMA-based configuration. Otherwise,
00986        returns an error.  */
00987        
00988     /* Check whether dual regular conversions are disabled or unavailable. */
00989     if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)  
00990     {
00991       /* Check DMAEN bit in handle ADC CFGR register */
00992       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET)
00993       {
00994         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
00995         return HAL_ERROR;
00996       } 
00997     }
00998     else
00999     {
01000       /* Else need to check Common register CCR MDMA bit field. */
01001       if (ADC_MULTIMODE_DMA_ENABLED())
01002       {
01003         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 
01004         return HAL_ERROR;          
01005       }
01006     }  
01007     
01008     /* no DMA transfer detected, polling ADC_FLAG_EOC is possible */         
01009     tmp_Flag_End = ADC_FLAG_EOC;
01010   }
01011     
01012   /* Get timeout */
01013   tickstart = HAL_GetTick();  
01014      
01015   /* Wait until End of Conversion or Sequence flag is raised */
01016   while (HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End))
01017   {
01018     /* Check if timeout is disabled (set to infinite wait) */
01019     if(Timeout != HAL_MAX_DELAY)
01020     {
01021       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01022       { 
01023         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);       
01024         return HAL_TIMEOUT;
01025       }
01026     }
01027   }
01028   
01029   /* Next, to clear the polled flag as well as to update the handle State,
01030      EOS is checked and the relevant configuration register is retrieved. */
01031   /*   1. Check whether or not EOS is set */
01032   if (HAL_IS_BIT_CLR(hadc->Instance->ISR, ADC_FLAG_EOS))
01033   {
01034     tmp_eos_raised = 0;   
01035   }
01036   /*  2. Check whether or not hadc is the handle of a Slave ADC with dual
01037    regular conversions enabled. */
01038    if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 
01039   {
01040     /* Retrieve handle ADC CFGR register */
01041     tmp_cfgr = READ_REG(hadc->Instance->CFGR);  
01042   }
01043   else
01044   {
01045     /* Retrieve Master ADC CFGR register */
01046     tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01047     tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
01048   }        
01049 
01050   /* Clear polled flag */                         
01051   if (tmp_Flag_End == ADC_FLAG_EOS)
01052   {
01053     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);  
01054   }
01055   else
01056   {               
01057 
01058     /* Clear end of conversion EOC flag of regular group if low power feature */
01059     /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
01060     /* until data register is read using function HAL_ADC_GetValue().         */
01061     /* For regular groups, no new conversion will start before EOC is cleared.*/
01062     /* Note that 1. reading DR clears EOC.                                    */ 
01063     /*           2. in multimode with dual regular conversions enabled (when  */
01064     /*              multimode feature is available), Master AUTDLY bit is     */
01065     /*              checked.                                                  */
01066     if (READ_BIT (tmp_cfgr, ADC_CFGR_AUTDLY) == RESET)
01067     {
01068       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
01069     }
01070   }
01071 
01072   
01073   /* Update ADC state machine */
01074   SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
01075   /* If 1. EOS is set
01076         2. conversions are software-triggered
01077         3. CONT bit is reset (that of handle ADC or Master ADC if applicable)          
01078      Then regular conversions are over and HAL_ADC_STATE_REG_BUSY can be reset.
01079         4. additionally, if no injected conversions are on-going, HAL_ADC_STATE_READY
01080           can be set */
01081   if ((tmp_eos_raised)
01082    && (ADC_IS_SOFTWARE_START_REGULAR(hadc))
01083    && (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET))
01084    {
01085      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   
01086      /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
01087      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01088      { 
01089        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01090      }
01091    }                       
01092 
01093   
01094   /* Return API HAL status */
01095   return HAL_OK;
01096 }
01097 
01098 /**
01099   * @brief  Poll for ADC event.
01100   * @param  hadc: ADC handle
01101   * @param  EventType: the ADC event type.
01102   *          This parameter can be one of the following values:
01103   *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event            
01104   *            @arg @ref ADC_AWD_EVENT    ADC Analog watchdog 1 event
01105   *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event
01106   *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event
01107   *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
01108   *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
01109   * @param  Timeout: Timeout value in millisecond.
01110   * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
01111   *         Indeed, the latter is reset only if hadc->Init.Overrun field is set  
01112   *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, DR may be potentially overwritten 
01113   *         by a new converted data as soon as OVR is cleared.
01114   *         To reset OVR flag once the preserved data is retrieved, the user can resort
01115   *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 
01116   * @retval HAL status
01117   */
01118 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
01119 {
01120   uint32_t tickstart; 
01121 
01122   /* Check the parameters */
01123   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01124   assert_param(IS_ADC_EVENT_TYPE(EventType));
01125   
01126   tickstart = HAL_GetTick();   
01127       
01128   /* Check selected event flag */
01129   while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
01130   {
01131     /* Check if timeout is disabled (set to infinite wait) */
01132     if(Timeout != HAL_MAX_DELAY)
01133     {
01134       if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
01135       {
01136         /* Update ADC state machine to timeout */
01137         SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
01138         
01139         /* Process unlocked */
01140         __HAL_UNLOCK(hadc);
01141         
01142         return HAL_TIMEOUT;
01143       }
01144     }
01145   }
01146 
01147   
01148   switch(EventType)
01149   {
01150   /* End Of Sampling event */
01151   case ADC_EOSMP_EVENT:
01152     /* Change ADC state */
01153     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01154      
01155     /* Clear the End Of Sampling flag */
01156     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
01157        
01158     break;  
01159   
01160   /* Analog watchdog (level out of window) event                              */
01161   /* Note: In case of several analog watchdog enabled, if needed to know      */
01162   /* which one triggered and on which ADCx, test ADC state of Analog Watchdog */
01163   /* flags HAL_ADC_STATE_AWD/2/3 function.                                    */
01164   /* For example: "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD) "        */
01165   /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD2)"        */
01166   /*              "if (HAL_ADC_GetState(hadc1) == HAL_ADC_STATE_AWD3)"        */
01167   case ADC_AWD_EVENT:
01168     /* Change ADC state */
01169     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01170      
01171     /* Clear ADC analog watchdog flag */
01172     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01173        
01174     break;
01175   
01176   /* Check analog watchdog 2 flag */
01177   case ADC_AWD2_EVENT:
01178     /* Change ADC state */
01179     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01180       
01181     /* Clear ADC analog watchdog flag */
01182     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01183       
01184     break;
01185   
01186   /* Check analog watchdog 3 flag */
01187   case ADC_AWD3_EVENT:
01188     /* Change ADC state */
01189     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01190       
01191     /* Clear ADC analog watchdog flag */
01192     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01193       
01194     break;
01195   
01196   /* Injected context queue overflow event */
01197   case ADC_JQOVF_EVENT:
01198     /* Change ADC state */
01199     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01200       
01201     /* Set ADC error code to Injected context queue overflow */
01202     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01203     
01204     /* Clear ADC Injected context queue overflow flag */
01205     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01206     
01207     break;
01208      
01209   /* Overrun event */
01210   default: /* Case ADC_OVR_EVENT */
01211     /* If overrun is set to overwrite previous data, overrun event is not     */
01212     /* considered as an error.                                                */
01213     /* (cf ref manual "Managing conversions without using the DMA and without */
01214     /* overrun ")                                                             */
01215     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01216     {
01217       /* Change ADC state */
01218       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01219         
01220       /* Set ADC error code to overrun */
01221       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01222     }
01223     else
01224     {
01225       /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
01226          otherwise, DR is potentially overwritten by new converted data as soon
01227          as OVR is cleared. */
01228       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
01229     }
01230     break;
01231   }
01232   
01233   /* Return API HAL status */
01234   return HAL_OK;
01235 }
01236 
01237 
01238 /**
01239   * @brief  Enable ADC, start conversion of regular group with interruption.
01240   * @note   Interruptions enabled in this function according to initialization
01241   *         setting : EOC (end of conversion), EOS (end of sequence), 
01242   *         OVR overrun.
01243   *         Each of these interruptions has its dedicated callback function.
01244   * @note   Case of multimode enabled (when multimode feature is available): 
01245   *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
01246   *         ADC Master. 
01247   *         For ADC Slave, ADC is enabled only (conversion is not started).  
01248   *         For ADC Master, ADC is enabled and multimode conversion is started.
01249   * @note   To guarantee a proper reset of all interruptions once all the needed
01250   *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure 
01251   *         a correct stop of the IT-based conversions.  
01252   * @note   By default, HAL_ADC_Start_IT() doesn't enable the End Of Sampling 
01253   *         interruption. If required (e.g. in case of oversampling with trigger
01254   *         mode), the user must    
01255   *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)             
01256   *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)     
01257   *          before calling HAL_ADC_Start_IT().    
01258   * @param  hadc: ADC handle
01259   * @retval HAL status
01260   */
01261 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
01262 {
01263   HAL_StatusTypeDef tmp_status = HAL_OK;
01264   ADC_TypeDef        *tmpADC_Master;
01265   
01266   /* Check the parameters */
01267   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01268   
01269   /* if a regular conversion is already on-going (i.e. ADSTART is set),
01270      don't restart the conversion. */
01271   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
01272   {
01273     return HAL_BUSY;
01274   }
01275   else
01276   {  
01277     /* Process locked */
01278     __HAL_LOCK(hadc);
01279  
01280     /* Enable the ADC peripheral */
01281     tmp_status = ADC_Enable(hadc);
01282  
01283     /* Start conversion if ADC is effectively enabled */
01284     if (tmp_status == HAL_OK)
01285     {
01286       /* State machine update: Check if an injected conversion is ongoing */
01287       if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01288       {
01289         /* Reset ADC error code fields related to regular conversions only */
01290         CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));         
01291       }
01292       else
01293       {
01294         /* Set ADC error code to none */
01295         ADC_CLEAR_ERRORCODE(hadc); 
01296       } 
01297       /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01298       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
01299       
01300       /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01301         - by default if ADC is Master or Independent or if multimode feature is not available
01302         - if MultiMode setting is set to independent mode (no dual regular or injected conversions are configured) */
01303       if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01304       {
01305         CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01306       }      
01307   
01308       /* Clear regular group conversion flag and overrun flag */
01309       /* (To ensure of no unknown state from potential previous ADC operations) */
01310       __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01311    
01312       /* By default, disable all interruptions before enabling the desired ones */
01313       __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01314   
01315       /* Enable required interruptions */  
01316       switch(hadc->Init.EOCSelection)
01317       {
01318         case ADC_EOC_SEQ_CONV: 
01319           __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
01320          break;
01321         /* case ADC_EOC_SINGLE_CONV */
01322         default:
01323          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
01324          break;
01325       }
01326    
01327       /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
01328          ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
01329          behavior and no CPU time is lost for a non-processed interruption */
01330       if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01331       {
01332         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);  
01333       }   
01334       
01335       /* Enable conversion of regular group.                                  */
01336       /* If software start has been selected, conversion starts immediately.  */
01337       /* If external trigger has been selected, conversion starts at next     */
01338       /* trigger event.                                                       */
01339       /* Case of multimode enabled (when multimode feature is available):     */ 
01340       /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
01341       /*    enabled only (conversion is not started),                         */
01342       /*  - if ADC is master, ADC is enabled and conversion is started.       */
01343       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   )
01344       {
01345         /* Multimode feature is not available or ADC Instance is Independent or Master, 
01346            or is not Slave ADC with dual regular conversions enabled.         
01347            Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */
01348         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET)
01349         {
01350           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01351           
01352           /* Enable as well injected interruptions in case 
01353            HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
01354            allows to start regular and injected conversions when JAUTO is
01355            set with a single call to HAL_ADC_Start_IT() */
01356           switch(hadc->Init.EOCSelection)
01357           {
01358             case ADC_EOC_SEQ_CONV: 
01359               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01360               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01361             break;
01362             /* case ADC_EOC_SINGLE_CONV */
01363             default:
01364               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
01365               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01366             break;
01367           }  
01368         } /*  if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) */
01369         /* Process unlocked */
01370         __HAL_UNLOCK(hadc);           
01371         /* Start ADC */     
01372         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01373       }
01374       else
01375       {
01376         /* hadc is the handle of a Slave ADC with dual regular conversions
01377            enabled. Therefore, ADC_CR_ADSTART is NOT set */
01378         SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01379         /* if Master ADC JAUTO bit is set, Slave injected interruptions
01380            are enabled nevertheless (for same reason as above) */
01381         tmpADC_Master = ADC_MASTER_REGISTER(hadc); 
01382         if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET)
01383         {
01384           /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit 
01385              and in resetting HAL_ADC_STATE_INJ_EOC bit */
01386           ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
01387           /* Next, set Slave injected interruptions */
01388           switch(hadc->Init.EOCSelection)
01389           {
01390             case ADC_EOC_SEQ_CONV: 
01391               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
01392               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
01393             break;
01394             /* case ADC_EOC_SINGLE_CONV */
01395             default:
01396               __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);      
01397               __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
01398             break;
01399           }         
01400         }  /* if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) */
01401         /* Process unlocked */
01402         __HAL_UNLOCK(hadc);         
01403       } /*  if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)   ) */     
01404     }  /*  if (tmp_status == HAL_OK) */
01405     else
01406     {
01407       /* Process unlocked */
01408       __HAL_UNLOCK(hadc);    
01409     }
01410  
01411     /* Return function status */
01412     return tmp_status;
01413  
01414   }  
01415 }
01416 
01417 
01418 
01419 /**  
01420   * @brief  Stop ADC conversion of regular groups when interruptions are enabled.
01421   * @note   Stop as well injected conversions and disable ADC peripheral.
01422   * @param  hadc: ADC handle
01423   * @retval HAL status.
01424   */  
01425 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
01426 {
01427   HAL_StatusTypeDef tmp_status = HAL_OK;
01428   
01429   /* Check the parameters */
01430   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01431   
01432   /* Process locked */
01433   __HAL_LOCK(hadc);
01434   
01435   /* 1. Stop potential regular and injected on-going conversions */
01436   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01437   
01438   /* Disable ADC peripheral if conversions are effectively stopped */
01439   if (tmp_status == HAL_OK)
01440   {
01441     /* Disable all interrupts */
01442     __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
01443     
01444     /* 2. Disable the ADC peripheral */
01445     tmp_status = ADC_Disable(hadc);
01446     
01447     /* Check if ADC is effectively disabled */
01448     if (tmp_status == HAL_OK)
01449     {
01450       /* Change ADC state */
01451       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01452       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY); 
01453     }
01454   }
01455 
01456   /* Process unlocked */
01457   __HAL_UNLOCK(hadc);
01458   
01459   /* Return function status */
01460   return tmp_status;
01461 }
01462 
01463 
01464 /**
01465   * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
01466   * @note   Interruptions enabled in this function:
01467   *         overrun (if applicable), DMA half transfer, DMA transfer complete. 
01468   *         Each of these interruptions has its dedicated callback function.
01469   * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() 
01470   *         is designed for single-ADC mode only. For multimode, the dedicated 
01471   *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
01472   * @param  hadc: ADC handle
01473   * @param  pData: Destination Buffer address.
01474   * @param  Length: Length of data to be transferred from ADC peripheral to memory (in bytes)
01475   * @retval None
01476   */
01477 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
01478 {
01479   HAL_StatusTypeDef tmp_status = HAL_OK;
01480   
01481   /* Check the parameters */
01482   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01483   
01484   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc))
01485   {
01486     return HAL_BUSY;
01487   }
01488   else
01489   {
01490     
01491     /* Process locked */
01492     __HAL_LOCK(hadc);
01493   
01494     /* Ensure that dual regular conversions are not enabled or unavailable.   */
01495     /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
01496     if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET)
01497     {
01498       /* Enable the ADC peripheral */
01499       tmp_status = ADC_Enable(hadc);
01500     
01501       /* Start conversion if ADC is effectively enabled */
01502       if (tmp_status == HAL_OK)
01503       {
01504         /* State machine update: Check if an injected conversion is ongoing */
01505         if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01506         {
01507           /* Reset ADC error code fields related to regular conversions only */
01508           CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA));             
01509         }
01510         else
01511         {
01512           /* Set ADC error code to none */
01513           ADC_CLEAR_ERRORCODE(hadc);          
01514         }
01515         /* Clear HAL_ADC_STATE_READY and regular conversion results bits, set HAL_ADC_STATE_REG_BUSY bit */
01516         ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_READY|HAL_ADC_STATE_REG_EOC|HAL_ADC_STATE_REG_OVR|HAL_ADC_STATE_REG_EOSMP), HAL_ADC_STATE_REG_BUSY);
01517 
01518        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
01519         - by default if ADC is Master or Independent or if multimode feature is not available
01520         - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */
01521         if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
01522         {
01523           CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
01524         }
01525       
01526         /* Set the DMA transfer complete callback */
01527         hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
01528 
01529         /* Set the DMA half transfer complete callback */
01530         hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
01531       
01532         /* Set the DMA error callback */
01533         hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
01534 
01535             
01536         /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
01537         /* ADC start (in case of SW start):                                   */
01538       
01539         /* Clear regular group conversion flag and overrun flag               */
01540         /* (To ensure of no unknown state from potential previous ADC         */
01541         /* operations)                                                        */
01542         __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
01543       
01544         /* With DMA, overrun event is always considered as an error even if 
01545            hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,  
01546            ADC_IT_OVR is enabled.  */         
01547         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);  
01548      
01549       
01550         /* Enable ADC DMA mode */
01551         SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
01552       
01553         /* Start the DMA channel */
01554         HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
01555                
01556         /* Enable conversion of regular group.                                  */
01557         /* Process unlocked */
01558         __HAL_UNLOCK(hadc);          
01559         /* If software start has been selected, conversion starts immediately.  */
01560         /* If external trigger has been selected, conversion will start at next */
01561         /* trigger event.                                                       */
01562         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTART);
01563       
01564       }  
01565       else
01566       {
01567         /* Process unlocked */
01568         __HAL_UNLOCK(hadc);      
01569       }  /* if (tmp_status == HAL_OK) */
01570     }
01571     else
01572     {
01573       tmp_status = HAL_ERROR;
01574       /* Process unlocked */
01575       __HAL_UNLOCK(hadc);      
01576     } /* if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) */
01577   
01578 
01579   
01580   /* Return function status */
01581   return tmp_status;
01582   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc)) */
01583 }
01584 
01585 
01586 /**
01587   * @brief  Stop ADC conversion of regular groups and disable ADC DMA transfer. 
01588   * @note   Stop as well injected conversions and disable ADC peripheral.
01589   * @note   Case of multimode enabled (when multimode feature is available): 
01590   *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. 
01591   *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
01592   * @param  hadc: ADC handle
01593   * @retval HAL status.
01594   */
01595 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
01596 {  
01597   HAL_StatusTypeDef tmp_status = HAL_OK;
01598   
01599   /* Check the parameters */
01600   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01601 
01602   /* Process locked */
01603   __HAL_LOCK(hadc);
01604   
01605   /* 1. Stop potential regular conversion on going */
01606   tmp_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
01607   
01608   /* Disable ADC peripheral if conversions are effectively stopped */
01609   if (tmp_status == HAL_OK)
01610   {
01611     /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
01612     CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 
01613     
01614     /* Disable the DMA channel (in case of DMA in circular mode or stop while */
01615     /* while DMA transfer is on going)                                        */
01616     tmp_status = HAL_DMA_Abort(hadc->DMA_Handle);   
01617     
01618     /* Check if DMA channel effectively disabled */
01619     if (tmp_status != HAL_OK)
01620     {
01621       /* Update ADC state machine to error */
01622       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);  
01623     }
01624     
01625     /* Disable ADC overrun interrupt */
01626     __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
01627     
01628     /* 2. Disable the ADC peripheral */
01629     /* Update "tmp_status" only if DMA channel disabling passed, to keep in */
01630     /* memory a potential failing status.                                     */
01631     if (tmp_status == HAL_OK)
01632     {
01633       tmp_status = ADC_Disable(hadc);
01634     }
01635     else
01636     {
01637       ADC_Disable(hadc);
01638     }
01639 
01640     /* Check if ADC is effectively disabled */
01641     if (tmp_status == HAL_OK)
01642     {
01643       /* Change ADC state */
01644       /* Clear HAL_ADC_STATE_REG_BUSY and HAL_ADC_STATE_INJ_BUSY bits, set HAL_ADC_STATE_READY bit */
01645       ADC_STATE_CLR_SET(hadc->State, (HAL_ADC_STATE_REG_BUSY|HAL_ADC_STATE_INJ_BUSY), HAL_ADC_STATE_READY);     
01646     }
01647     
01648   }
01649 
01650   /* Process unlocked */
01651   __HAL_UNLOCK(hadc);
01652   
01653   /* Return function status */
01654   return tmp_status;
01655 }
01656 
01657 
01658 /**
01659   * @brief  Get ADC regular group conversion result.
01660   * @param  hadc: ADC handle
01661   * @note   Reading DR register automatically clears EOC flag. To reset EOS flag, 
01662   *         the user must resort to the macro 
01663   *         __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS)  
01664   * @retval Converted value
01665   */
01666 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
01667 {
01668   /* Check the parameters */
01669   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01670   
01671   /* Return ADC converted value */ 
01672   return hadc->Instance->DR;
01673 }
01674 
01675 
01676 /**
01677   * @brief  Handle ADC interrupt request.  
01678   * @param  hadc: ADC handle
01679   * @retval None
01680   */
01681 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
01682 {
01683   uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */
01684   ADC_TypeDef        *tmpADC_Master;  
01685   uint32_t tmp_isr      = hadc->Instance->ISR;
01686   uint32_t tmp_ier      = hadc->Instance->IER;
01687   uint32_t tmp_cfgr     = 0x0;
01688   uint32_t tmp_cfgr_jqm = 0x0;       
01689   
01690   
01691   /* Check the parameters */
01692   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
01693   assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
01694   
01695   
01696   /* ====== Check End of Sampling flag for regular group ===== */
01697   if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
01698   {
01699     /* Update state machine on end of sampling status if not in error state */
01700     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01701     {
01702       /* Change ADC state */
01703       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
01704     }
01705         
01706     /* End Of Sampling callback */
01707       HAL_ADCEx_EndOfSamplingCallback(hadc);
01708     
01709     /* Clear regular group conversion flag */
01710     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP );
01711   }  
01712   
01713   /* ====== Check End of Conversion or Sequence flags for regular group ===== */
01714   if( (((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
01715       (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))  )
01716   {
01717     /* Update state machine on conversion status if not in error state */
01718     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01719     {
01720       /* Change ADC state */    
01721       SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
01722     }
01723     
01724     /* Disable interruption if no further conversion upcoming by regular      */
01725     /* external trigger or by continuous mode,                                */
01726     /* and if scan sequence if completed.                                     */
01727     if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
01728     {
01729       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01730       {
01731         /* check CONT bit directly in handle ADC CFGR register */
01732         tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
01733       }
01734       else
01735       {
01736         /* else need to check Master ADC CONT bit */
01737         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01738         tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
01739       }
01740       
01741       /* Carry on if continuous mode is disabled */
01742       if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
01743       {
01744         /* If End of Sequence is reached, disable interrupts */
01745         if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) )
01746         {
01747           /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
01748           /* ADSTART==0 (no conversion on going)                                */
01749           if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
01750           {
01751             /* Disable ADC end of sequence conversion interrupt */
01752             /* Note: if Overrun interrupt was enabled with EOC or EOS interrupt */
01753             /* in HAL_Start_IT(), it isn't disabled here because it can be used */
01754             /* by overrun IRQ process below.                                    */
01755             __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
01756             /* Clear HAL_ADC_STATE_REG_BUSY bit */
01757              CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 
01758              /* If no injected conversion on-going, set HAL_ADC_STATE_READY bit */
01759              if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
01760              { 
01761                SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01762              }           
01763           }
01764           else
01765           {
01766             /* Change ADC state to error state */
01767             SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01768             
01769             /* Set ADC error code to ADC IP internal error */
01770             SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01771           }
01772         }
01773       } /* if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) */
01774     }   /* if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   */
01775     
01776     /* Conversion complete callback */
01777     /* Note:  HAL_ADC_ConvCpltCallback can resort to 
01778               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) or
01779               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOC)) to determine whether 
01780               interruption has been triggered by end of conversion or end of 
01781               sequence.    */
01782       HAL_ADC_ConvCpltCallback(hadc);
01783 
01784     
01785     /* Clear regular group conversion flag */
01786     __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) );
01787   }
01788   
01789   
01790   /* ========== Check End of Conversion flag for injected group ========== */
01791   if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
01792       (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS))  )      
01793   {
01794     /* Update state machine on conversion status if not in error state */
01795     if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
01796     {
01797       /* Change ADC state */
01798       SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
01799     }
01800     
01801 
01802     /* Check whether interruptions can be disabled only if
01803         - injected conversions are software-triggered when injected queue management is disabled
01804         OR
01805         - auto-injection is enabled, continuous mode is disabled (CONT = 0)
01806           and regular conversions are software-triggered */
01807           /* If End of Sequence is reached, disable interrupts */
01808     if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
01809     {
01810           
01811       /* First, retrieve proper registers to check */
01812       /* 1a. Are injected conversions that of a dual Slave ? */      
01813       if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc))
01814       {
01815         /* hadc is not the handle of a Slave ADC with dual injected conversions enabled:
01816            check JQM bit directly in ADC CFGR register */
01817         tmp_cfgr_jqm = READ_REG(hadc->Instance->CFGR); 
01818       }
01819       else
01820       {
01821         /* hadc is the handle of a Slave ADC with dual injected conversions enabled:
01822            need to check JQM bit of Master ADC CFGR register */
01823           tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01824           tmp_cfgr_jqm = READ_REG(tmpADC_Master->CFGR); 
01825       }
01826       /* 1b. Is hadc the handle of a Slave ADC with regular conversions enabled? */ 
01827       if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc))
01828       {
01829         /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
01830            check JAUTO and CONT bits directly in ADC CFGR register */        
01831           tmp_cfgr = READ_REG(hadc->Instance->CFGR); 
01832       }
01833       else
01834       {
01835         /* hadc is not the handle of a Slave ADC with dual regular conversions enabled:
01836            check JAUTO and CONT bits of Master ADC CFGR register */  
01837         tmpADC_Master = ADC_MASTER_REGISTER(hadc);
01838         tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 
01839       }
01840       
01841       /* Secondly, check whether JEOC and JEOS interruptions can be disabled */                                                 
01842       if ((ADC_IS_SOFTWARE_START_INJECTED(hadc) && (READ_BIT(tmp_cfgr_jqm, ADC_CFGR_JQM) != ADC_CFGR_JQM))  
01843          && (!((READ_BIT(tmp_cfgr, (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) == (ADC_CFGR_JAUTO|ADC_CFGR_CONT)) &&    
01844              (ADC_IS_SOFTWARE_START_REGULAR(hadc))))    )
01845       {
01846         /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit         */
01847         /* JADSTART==0 (no conversion on going)                               */
01848         if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET)
01849         {
01850           /* Disable ADC end of sequence conversion interrupt  */
01851           __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
01852           /* Clear HAL_ADC_STATE_INJ_BUSY bit */
01853            CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
01854            /* If no regular conversion on-going, set HAL_ADC_STATE_READY bit */                   
01855           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
01856           { 
01857             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
01858           }           
01859         }
01860         else
01861         {
01862           /* Change ADC state to error state */
01863           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
01864           
01865           /* Set ADC error code to ADC IP internal error */
01866           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
01867         }
01868       }
01869     } /* if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) */
01870     
01871     /* Injected Conversion complete callback */
01872     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to 
01873               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
01874               if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether 
01875               interruption has been triggered by end of conversion or end of 
01876               sequence.    */    
01877     HAL_ADCEx_InjectedConvCpltCallback(hadc);
01878     
01879     /* Clear injected group conversion flag */
01880     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
01881   }
01882   
01883    
01884   /* ========== Check Analog watchdog flags =================================================== */
01885   
01886   /* ========== Check Analog watchdog 1 flags ========== */
01887   if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))      
01888   {
01889     /* Change ADC state */
01890     SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
01891     
01892     /* Level out of window 1 callback */
01893     HAL_ADC_LevelOutOfWindowCallback(hadc);
01894     /* Clear ADC Analog watchdog flag */ 
01895     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
01896   }
01897   
01898   /* ========== Check Analog watchdog 2 flags ========== */
01899   if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))      
01900   {
01901     /* Change ADC state */
01902     SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
01903     
01904     /* Level out of window 2 callback */
01905     HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
01906     /* Clear ADC Analog watchdog flag */ 
01907     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
01908   } 
01909   
01910   /* ========== Check Analog watchdog 3 flags ========== */
01911   if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))      
01912   {
01913     /* Change ADC state */
01914     SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
01915     
01916     /* Level out of window 3 callback */
01917     HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
01918     /* Clear ADC Analog watchdog flag */ 
01919     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
01920   } 
01921   
01922   
01923   /* ========== Check Overrun flag ========== */
01924   if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) 
01925   {
01926     /* If overrun is set to overwrite previous data (default setting),        */
01927     /* overrun event is not considered as an error.                           */
01928     /* (cf ref manual "Managing conversions without using the DMA and without */
01929     /* overrun ")                                                             */
01930     /* Exception for usage with DMA overrun event always considered as an     */
01931     /* error.                                                                 */
01932     
01933     if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
01934     {
01935       overrun_error = 1;
01936     }
01937     else
01938     {
01939       /* check DMA configuration, depending on multimode set or not,
01940         or whether or not multimode feature is available */
01941       if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET)
01942       {
01943         /* Multimode not set or feature not available or ADC independent */
01944         if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN))
01945         {
01946           overrun_error = 1;  
01947         }      
01948       }
01949       else
01950       {
01951         /* Multimode (when feature is available) is enabled, 
01952            Common Control Register MDMA bits must be checked. */
01953         if (ADC_MULTIMODE_DMA_ENABLED())
01954         {
01955           overrun_error = 1;  
01956         }
01957       }
01958     }
01959         
01960     if (overrun_error == 1)
01961     {
01962       /* Change ADC state to error state */
01963       SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
01964       
01965       /* Set ADC error code to overrun */
01966       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
01967       
01968       /* Error callback */ 
01969       HAL_ADC_ErrorCallback(hadc);
01970     }
01971 
01972     /* Clear the Overrun flag, to be done AFTER HAL_ADC_ErrorCallback() since
01973        old data is preserved until OVR is reset */
01974     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);  
01975 
01976   }
01977   
01978   
01979   /* ========== Check Injected context queue overflow flag ========== */
01980   if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) 
01981   {
01982     /* Change ADC state to overrun state */
01983     SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
01984         
01985     /* Set ADC error code to Injected context queue overflow */
01986     SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
01987     
01988     /* Clear the Injected context queue overflow flag */
01989     __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
01990     
01991     /* Error callback */ 
01992     HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
01993   }
01994   
01995 }
01996 
01997 /**
01998   * @brief  Conversion complete callback in non-blocking mode.
01999   * @param  hadc: ADC handle
02000   * @retval None
02001   */
02002 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
02003 {
02004   /* Prevent unused argument(s) compilation warning */
02005   UNUSED(hadc);
02006 
02007   /* NOTE : This function should not be modified. When the callback is needed,
02008             function HAL_ADC_ConvCpltCallback must be implemented in the user file.
02009    */
02010 }
02011 
02012 /**
02013   * @brief  Conversion DMA half-transfer callback in non-blocking mode.
02014   * @param  hadc: ADC handle
02015   * @retval None
02016   */
02017 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
02018 {
02019   /* Prevent unused argument(s) compilation warning */
02020   UNUSED(hadc);
02021 
02022   /* NOTE : This function should not be modified. When the callback is needed,
02023             function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
02024   */
02025 }
02026 
02027 /**
02028   * @brief  Analog watchdog 1 callback in non-blocking mode.        
02029   * @param  hadc: ADC handle
02030   * @retval None
02031   */
02032 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
02033 {
02034   /* Prevent unused argument(s) compilation warning */
02035   UNUSED(hadc);
02036 
02037   /* NOTE : This function should not be modified. When the callback is needed,
02038             function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
02039   */
02040 }
02041 
02042 /**
02043   * @brief  ADC error callback in non-blocking mode
02044   *        (ADC conversion with interruption or transfer by DMA).
02045   * @param  hadc: ADC handle
02046   * @retval None
02047   */
02048 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
02049 {
02050   /* Prevent unused argument(s) compilation warning */
02051   UNUSED(hadc);
02052 
02053   /* NOTE : This function should not be modified. When the callback is needed,
02054             function HAL_ADC_ErrorCallback must be implemented in the user file.
02055   */
02056 }
02057 
02058 /**
02059   * @}
02060   */
02061 
02062 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
02063  *  @brief    Peripheral Control functions 
02064  *
02065 @verbatim   
02066  ===============================================================================
02067              ##### Peripheral Control functions #####
02068  ===============================================================================  
02069     [..]  This section provides functions allowing to:
02070       (+) Configure channels on regular group
02071       (+) Configure the analog watchdog
02072       
02073 @endverbatim
02074   * @{
02075   */
02076 
02077 
02078 /**
02079   * @brief  Configure the selected channel to be linked to the regular group.
02080   * @note   In case of usage of internal measurement channels (Vbat / VrefInt /
02081   *         TempSensor), the recommended sampling time is provided by the
02082   *         datasheet.  
02083   *         These internal paths can be disabled using function 
02084   *         HAL_ADC_DeInit().
02085   * @note   Possibility to update parameters on the fly:
02086   *         HAL_ADC_ConfigChannel() initializes channel into regular group, 
02087   *         consecutive calls to this function can be used to reconfigure some 
02088   *         parameters of structure "ADC_ChannelConfTypeDef" on the fly, without 
02089   *         resetting the ADC.
02090   *         The setting of these parameters is conditioned to ADC state.
02091   *         For parameters constraints, see comments of structure 
02092   *         "ADC_ChannelConfTypeDef".
02093   * @param  hadc: ADC handle
02094   * @param  sConfig: Structure ADC channel for regular group.
02095   * @retval HAL status
02096   */
02097 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
02098 {
02099   HAL_StatusTypeDef tmp_status = HAL_OK;
02100                                                                                                                      
02101   ADC_Common_TypeDef *tmpADC_Common;
02102   uint32_t tmpOffsetShifted;
02103   __IO uint32_t wait_loop_index = 0;
02104   
02105   /* Check the parameters */
02106   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02107   assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
02108   assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
02109   assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
02110   assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
02111   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
02112 
02113   /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is  
02114      ignored (considered as reset) */
02115   assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));  
02116   
02117   /* Verification of channel number */
02118   if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02119   {
02120      assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
02121   }
02122   else
02123   {
02124     assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
02125   }
02126   
02127   /* Process locked */
02128   __HAL_LOCK(hadc);
02129   
02130 
02131   /* Parameters update conditioned to ADC state:                              */
02132   /* Parameters that can be updated when ADC is disabled or enabled without   */
02133   /* conversion on going on regular group:                                    */
02134   /*  - Channel number                                                        */
02135   /*  - Channel rank                                                          */
02136   if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET)
02137   {
02138     
02139       /* Regular sequence configuration */
02140       /* Clear the old SQx bits then set the new ones for the selected rank */
02141       /* For Rank 1 to 4 */
02142       if (sConfig->Rank < 5)
02143       {      
02144         MODIFY_REG(hadc->Instance->SQR1, 
02145                   ADC_SQR1_RK(ADC_SQR2_SQ5, sConfig->Rank), 
02146                   ADC_SQR1_RK(sConfig->Channel, sConfig->Rank));      
02147       }
02148       /* For Rank 5 to 9 */
02149       else if (sConfig->Rank < 10)
02150       {
02151         MODIFY_REG(hadc->Instance->SQR2, 
02152                   ADC_SQR2_RK(ADC_SQR2_SQ5, sConfig->Rank), 
02153                   ADC_SQR2_RK(sConfig->Channel, sConfig->Rank));       
02154       }
02155       /* For Rank 10 to 14 */
02156       else if (sConfig->Rank < 15)
02157       {
02158         MODIFY_REG(hadc->Instance->SQR3, 
02159                   ADC_SQR3_RK(ADC_SQR3_SQ10, sConfig->Rank), 
02160                   ADC_SQR3_RK(sConfig->Channel, sConfig->Rank));        
02161       }
02162       /* For Rank 15 to 16 */
02163       else
02164       {   
02165         MODIFY_REG(hadc->Instance->SQR4, 
02166                   ADC_SQR4_RK(ADC_SQR4_SQ15, sConfig->Rank), 
02167                   ADC_SQR4_RK(sConfig->Channel, sConfig->Rank));         
02168       }
02169       
02170       
02171       /* Parameters update conditioned to ADC state:                              */
02172       /* Parameters that can be updated when ADC is disabled or enabled without   */
02173       /* conversion on going on regular group:                                    */
02174       /*  - Channel sampling time                                                 */
02175       /*  - Channel offset                                                        */
02176       if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02177       {
02178        
02179         /* Channel sampling time configuration */
02180         /* Clear the old sample time then set the new one for the selected channel */    
02181         /* For channels 10 to 18 */
02182         if (sConfig->Channel >= ADC_CHANNEL_10)
02183         {
02184           ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);                
02185         }
02186         else /* For channels 0 to 9 */
02187         {
02188           ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel);                       
02189         }
02190       
02191   
02192        /* Configure the offset: offset enable/disable, channel, offset value */
02193   
02194        /* Shift the offset with respect to the selected ADC resolution. */
02195        /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
02196        tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset);
02197       
02198        switch (sConfig->OffsetNumber)
02199        {
02200         /* Configure offset register i when applicable:                         */
02201         /* - Enable offset                                                      */
02202         /* - Set channel number                                                 */
02203         /* - Set offset value                                                   */    
02204        case ADC_OFFSET_1:                                
02205           MODIFY_REG(hadc->Instance->OFR1, 
02206                   ADC_OFR_FIELDS, 
02207                   ADC_OFR1_OFFSET1_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                   
02208          break;
02209       
02210        case ADC_OFFSET_2:
02211          MODIFY_REG(hadc->Instance->OFR2, 
02212                   ADC_OFR_FIELDS, 
02213                   ADC_OFR2_OFFSET2_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
02214          break;
02215           
02216        case ADC_OFFSET_3:
02217          MODIFY_REG(hadc->Instance->OFR3, 
02218                   ADC_OFR_FIELDS, 
02219                   ADC_OFR3_OFFSET3_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
02220          break;
02221       
02222        case ADC_OFFSET_4:
02223          MODIFY_REG(hadc->Instance->OFR4, 
02224                   ADC_OFR_FIELDS, 
02225                   ADC_OFR4_OFFSET4_EN | ADC_OFR_CHANNEL(sConfig->Channel) | tmpOffsetShifted);                                  
02226          break;
02227       
02228        /* Case ADC_OFFSET_NONE */
02229        default :
02230        /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled. 
02231           If this is the case, offset OFRx is disabled since 
02232           sConfig->OffsetNumber = ADC_OFFSET_NONE. */
02233          if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02234          {
02235            CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN);
02236          }
02237          if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02238          {
02239            CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN); 
02240          }
02241          if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02242          {
02243            CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN); 
02244          }
02245          if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(sConfig->Channel))
02246          {
02247            CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN);
02248          }
02249          break;
02250       }  /*  switch (sConfig->OffsetNumber) */
02251   
02252     }  /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */
02253    
02254   
02255   
02256     /* Parameters update conditioned to ADC state:                              */
02257     /* Parameters that can be updated only when ADC is disabled:                */
02258     /*  - Single or differential mode                                           */
02259     /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
02260     if (ADC_IS_ENABLE(hadc) == RESET)
02261     {
02262       /* Configuration of differential mode */
02263       if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
02264       {
02265         /* Disable differential mode (default mode: single-ended) */
02266         CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
02267       }
02268       else
02269       {
02270         /* Enable differential mode */
02271         SET_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_CHANNEL(sConfig->Channel));
02272         
02273         /* Sampling time configuration of channel ADC_IN+1 (negative input)     */
02274         /* Clear the old sample time then set the new one for the selected      */
02275         /* channel.                                                             */        
02276         /* Starting from channel 9, SMPR2 register must be configured           */
02277         if (sConfig->Channel >= ADC_CHANNEL_9)
02278         {
02279           ADC_SMPR2_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);                                
02280         }
02281         else /* For channels 0 to 8, SMPR1 must be configured */
02282         {
02283           ADC_SMPR1_SETTING(hadc, sConfig->SamplingTime, sConfig->Channel+1);      
02284         }
02285       }
02286     
02287     
02288       
02289       /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
02290       /* If internal channel selected, enable dedicated internal buffers and    */
02291       /*  paths.                                                                */
02292       /* Note: these internal measurement paths can be disabled using           */
02293       /* HAL_ADC_DeInit().                                                      */
02294          
02295       /* Configuration of common ADC parameters                                 */
02296       tmpADC_Common = ADC_COMMON_REGISTER(hadc);
02297     
02298   
02299       /* If the requested internal measurement path has already been enabled,   */
02300       /* bypass the configuration processing.                                   */
02301       if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
02302             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_TSEN))            ) ||
02303           ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
02304             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VBATEN))          ) ||
02305           ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
02306             (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_VREFEN)))
02307          )
02308       {
02309         /* Configuration of common ADC parameters (continuation)                */
02310   
02311         /* Software is allowed to change common parameters only when all ADCs   */
02312         /* of the common group are disabled.                                    */
02313         if ((ADC_IS_ENABLE(hadc) == RESET)   &&
02314            (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )              
02315         {
02316           if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
02317           {
02318             if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
02319             {
02320               SET_BIT(tmpADC_Common->CCR, ADC_CCR_TSEN);
02321             
02322               /* Delay for temperature sensor stabilization time */
02323               /* Wait loop initialization and execution */
02324               /* Note: Variable divided by 2 to compensate partially          */
02325               /*       CPU processing cycles.                                 */
02326               wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / (1000000 * 2)));
02327               while(wait_loop_index != 0)
02328               {
02329                 wait_loop_index--;
02330               }
02331             }
02332           }
02333           else if (sConfig->Channel == ADC_CHANNEL_VBAT)
02334           {
02335             if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
02336             {
02337               SET_BIT(tmpADC_Common->CCR, ADC_CCR_VBATEN);
02338             }
02339           }
02340           else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
02341           { 
02342             if (ADC_VREFINT_INSTANCE(hadc))
02343             {
02344               SET_BIT(tmpADC_Common->CCR, ADC_CCR_VREFEN);
02345             }        
02346           }
02347         }
02348         /* If the requested internal measurement path has already been          */
02349         /* enabled and other ADC of the common group are enabled, internal      */
02350         /* measurement paths cannot be enabled.                                 */
02351         else  
02352         {
02353           /* Update ADC state machine to error */
02354           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02355           
02356           tmp_status = HAL_ERROR;
02357         }
02358       }
02359   
02360     } /* if (ADC_IS_ENABLE(hadc) == RESET) */
02361 
02362   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) */
02363   
02364   /* If a conversion is on going on regular group, no update on regular       */
02365   /* channel could be done on neither of the channel configuration structure  */
02366   /* parameters.                                                              */
02367   else
02368   {
02369     /* Update ADC state machine to error */
02370     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02371     
02372     tmp_status = HAL_ERROR;
02373   }
02374   
02375   /* Process unlocked */
02376   __HAL_UNLOCK(hadc);
02377 
02378   /* Return function status */
02379   return tmp_status;
02380 }
02381   
02382 
02383 
02384 /**
02385   * @brief  Configure the analog watchdog.
02386   * @note   Possibility to update parameters on the fly:
02387   *         This function initializes the selected analog watchdog, successive  
02388   *         calls to this function can be used to reconfigure some parameters 
02389   *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting 
02390   *         the ADC, e.g. to set several channels to monitor simultaneously. 
02391   *         The setting of these parameters is conditioned to ADC state.
02392   *         For parameters constraints, see comments of structure 
02393   *         "ADC_AnalogWDGConfTypeDef".
02394   * @param  hadc: ADC handle
02395   * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
02396   * @retval HAL status
02397   */
02398 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
02399 {
02400   HAL_StatusTypeDef tmp_status = HAL_OK;
02401 
02402   
02403   uint32_t tmpAWDHighThresholdShifted;
02404   uint32_t tmpAWDLowThresholdShifted;
02405   
02406   uint32_t tmpADCFlagAWD2orAWD3;
02407   uint32_t tmpADCITAWD2orAWD3;
02408   
02409   /* Check the parameters */
02410   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02411   assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
02412   assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
02413   assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
02414   
02415   if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
02416      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
02417      (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
02418   {
02419     assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
02420   }
02421   
02422 
02423   /* Verify if threshold is within the selected ADC resolution */
02424   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
02425   assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
02426 
02427   /* Process locked */
02428   __HAL_LOCK(hadc);
02429   
02430   /* Parameters update conditioned to ADC state:                              */
02431   /* Parameters that can be updated when ADC is disabled or enabled without   */
02432   /* conversion on going on regular and injected groups:                      */
02433   /*  - Analog watchdog channels                                              */
02434   /*  - Analog watchdog thresholds                                            */
02435   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET)
02436   {
02437   
02438     /* Analog watchdogs configuration */
02439     if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
02440     {
02441       /* Configuration of analog watchdog:                                    */
02442       /*  - Set the analog watchdog enable mode: regular and/or injected      */
02443       /*    groups, one or overall group of channels.                         */
02444       /*  - Set the Analog watchdog channel (is not used if watchdog          */
02445       /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                         */
02446                                 
02447         MODIFY_REG(hadc->Instance->CFGR,  ADC_CFGR_WD_FIELDS, 
02448               AnalogWDGConfig->WatchdogMode | ADC_CFGR_SET_AWD1CH(AnalogWDGConfig->Channel) );                                  
02449 
02450       /* Shift the offset with respect to the selected ADC resolution:         */
02451       /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
02452       /* are set to 0                                                         */ 
02453       tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02454       tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02455       
02456       /* Set the high and low thresholds */                                
02457       MODIFY_REG(hadc->Instance->TR1,  ADC_TR1_HT1 | ADC_TR1_LT1, 
02458               ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                  
02459       
02460       /* Clear the ADC Analog watchdog flag (in case left enabled by          */
02461       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
02462       /* or HAL_ADC_PollForEvent().                                           */
02463       __HAL_ADC_CLEAR_FLAG(hadc, ADC_IT_AWD1);
02464       
02465       /* Configure ADC Analog watchdog interrupt */
02466       if(AnalogWDGConfig->ITMode == ENABLE)
02467       {
02468         /* Enable the ADC Analog watchdog interrupt */
02469         __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD1);
02470       }
02471       else
02472       {
02473         /* Disable the ADC Analog watchdog interrupt */
02474         __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD1);
02475       }
02476       
02477       /* Update state, clear previous result related to AWD1 */
02478       CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
02479     }
02480     /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
02481     else
02482     {
02483     /* Shift the threshold with respect to the selected ADC resolution         */
02484     /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0    */
02485       tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
02486       tmpAWDLowThresholdShifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
02487 
02488       if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
02489       {
02490         /* Set the Analog watchdog channel or group of channels. This also    */
02491         /* enables the watchdog.                                              */
02492         /* Note: Conditional register reset, because several channels can be */
02493         /*       set by successive calls of this function.                    */
02494         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) 
02495         {
02496           SET_BIT(hadc->Instance->AWD2CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
02497         }
02498         else
02499         {
02500           CLEAR_BIT(hadc->Instance->AWD2CR,  ADC_AWD2CR_AWD2CH);
02501         }
02502         
02503         /* Set the high and low thresholds */
02504         MODIFY_REG(hadc->Instance->TR2,  ADC_TR2_HT2 | ADC_TR2_LT2, 
02505               ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                      
02506         
02507         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
02508         /* settings.                                                          */
02509         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD2;
02510         tmpADCITAWD2orAWD3 = ADC_IT_AWD2;
02511         
02512         /* Update state, clear previous result related to AWD2 */
02513         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
02514       }
02515       /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
02516       else
02517       {
02518         /* Set the Analog watchdog channel or group of channels. This also    */
02519         /* enables the watchdog.                                              */
02520         /* Note: Conditional register reset, because several channels can be */
02521         /*       set by successive calls of this function.                    */
02522         if (AnalogWDGConfig->WatchdogMode != ADC_ANALOGWATCHDOG_NONE) 
02523         {
02524           SET_BIT(hadc->Instance->AWD3CR, ADC_CFGR_SET_AWD23CR(AnalogWDGConfig->Channel));
02525         }
02526         else
02527         {
02528           CLEAR_BIT(hadc->Instance->AWD3CR,  ADC_AWD3CR_AWD3CH);
02529         }
02530         
02531         /* Set the high and low thresholds */
02532         MODIFY_REG(hadc->Instance->TR3,  ADC_TR3_HT3 | ADC_TR3_LT3, 
02533               ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted) | tmpAWDLowThresholdShifted );                                    
02534         
02535         /* Set temporary variable to flag and IT of AWD2 or AWD3 for further  */
02536         /* settings.                                                          */
02537         tmpADCFlagAWD2orAWD3 = ADC_FLAG_AWD3;
02538         tmpADCITAWD2orAWD3 = ADC_IT_AWD3;
02539         
02540         /* Update state, clear previous result related to AWD3 */
02541         CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
02542       }
02543 
02544       /* Clear the ADC Analog watchdog flag (in case left enabled by          */
02545       /* previous ADC operations) to be ready to use for HAL_ADC_IRQHandler() */
02546       /* or HAL_ADC_PollForEvent().                                           */
02547       __HAL_ADC_CLEAR_FLAG(hadc, tmpADCFlagAWD2orAWD3);
02548 
02549       /* Configure ADC Analog watchdog interrupt */
02550       if(AnalogWDGConfig->ITMode == ENABLE)
02551       {
02552         __HAL_ADC_ENABLE_IT(hadc, tmpADCITAWD2orAWD3);
02553       }
02554       else
02555       {
02556         __HAL_ADC_DISABLE_IT(hadc, tmpADCITAWD2orAWD3);
02557       }
02558     }
02559   
02560   }
02561   /* If a conversion is on going on regular or injected groups, no update     */
02562   /* could be done on neither of the AWD configuration structure parameters.  */
02563   else
02564   {
02565     /* Update ADC state machine to error */
02566     SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
02567     
02568     tmp_status = HAL_ERROR;
02569   }
02570   
02571   
02572   /* Process unlocked */
02573   __HAL_UNLOCK(hadc);
02574   
02575 
02576   /* Return function status */
02577   return tmp_status;
02578 }
02579 
02580 
02581 /**
02582   * @}
02583   */
02584 
02585 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
02586  *  @brief   ADC Peripheral State functions 
02587  *
02588 @verbatim   
02589  ===============================================================================
02590             ##### Peripheral state and errors functions #####
02591  ===============================================================================
02592     [..]
02593     This subsection provides functions to get in run-time the status of the  
02594     peripheral.
02595       (+) Check the ADC state
02596       (+) Check the ADC error code
02597          
02598 @endverbatim
02599   * @{
02600   */
02601   
02602 /**
02603   * @brief  Return the ADC handle state.
02604   * @param  hadc: ADC handle
02605   * @retval HAL state  (uint32_t bit-map)
02606   */
02607 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
02608 {
02609   /* Check the parameters */
02610   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02611   
02612   /* Return ADC handle state */
02613   return hadc->State;
02614 }
02615 
02616 
02617 /**
02618   * @brief  Return the ADC error code.
02619   * @param  hadc: ADC handle
02620   * @retval ADC Error Code (uint32_t bit-map)
02621   */
02622 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
02623 {
02624   /* Check the parameters */
02625   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02626   
02627   return hadc->ErrorCode;
02628 }
02629 
02630 /**
02631   * @}
02632   */
02633 
02634 /**
02635   * @}
02636   */
02637 
02638 
02639 
02640 /** @defgroup ADC_Private_Functions ADC Private Functions
02641   * @{
02642   */
02643 
02644 /**
02645   * @brief  Stop ADC conversion.
02646   * @param  hadc: ADC handle
02647   * @param  ConversionGroup: ADC group regular and/or injected.
02648   *          This parameter can be one of the following values:
02649   *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
02650   *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
02651   *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
02652   * @retval HAL status.
02653   */
02654 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup)
02655 {
02656   uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0;
02657   uint32_t tickstart = 0;
02658   uint32_t Conversion_Timeout_CPU_cycles = 0;
02659 
02660   /* Check the parameters */
02661   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
02662   assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
02663     
02664   /* Verification if ADC is not already stopped (on regular and injected      */
02665   /* groups) to bypass this function if not needed.                           */
02666   if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc))
02667   {
02668     /* Particular case of continuous auto-injection mode combined with        */
02669     /* auto-delay mode.                                                       */
02670     /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
02671     /* injected group stop ADC_CR_JADSTP).                                    */
02672     /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
02673     /* (see reference manual).                                                */
02674     if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) 
02675          && (hadc->Init.ContinuousConvMode==ENABLE) 
02676          && (hadc->Init.LowPowerAutoWait==ENABLE))
02677     {
02678       /* Use stop of regular group */
02679       ConversionGroup = ADC_REGULAR_GROUP;
02680       
02681       /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
02682       while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET)
02683       {
02684         if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4))
02685         {
02686           /* Update ADC state machine to error */
02687           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02688           
02689           /* Set ADC error code to ADC IP internal error */
02690           SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02691           
02692           return HAL_ERROR;
02693         }
02694         Conversion_Timeout_CPU_cycles ++;
02695       }
02696 
02697       /* Clear JEOS */
02698       __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
02699     }
02700     
02701     /* Stop potential conversion on going on regular group */
02702     if (ConversionGroup != ADC_INJECTED_GROUP)
02703     {
02704       /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
02705       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 
02706           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)     )
02707       {
02708         /* Stop conversions on regular group */
02709         SET_BIT(hadc->Instance->CR, ADC_CR_ADSTP);
02710       }
02711     }
02712 
02713     /* Stop potential conversion on going on injected group */
02714     if (ConversionGroup != ADC_REGULAR_GROUP)
02715     {
02716       /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
02717       if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && 
02718           HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS)      )
02719       {
02720         /* Stop conversions on injected group */
02721         SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP);
02722       }   
02723     }
02724 
02725     /* Selection of start and stop bits with respect to the regular or injected group */
02726     switch(ConversionGroup)
02727     {
02728     case ADC_REGULAR_INJECTED_GROUP:
02729         tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
02730         break;
02731     case ADC_INJECTED_GROUP:
02732         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
02733         break;
02734     /* Case ADC_REGULAR_GROUP only*/
02735     default:
02736         tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
02737         break;
02738     }
02739     
02740     /* Wait for conversion effectively stopped */
02741 
02742     
02743     tickstart = HAL_GetTick();
02744       
02745     while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET)
02746     {
02747       if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
02748       {
02749         /* Update ADC state machine to error */
02750         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02751         
02752         /* Set ADC error code to ADC IP internal error */
02753         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02754         
02755         return HAL_ERROR;
02756       }
02757     }
02758     
02759   } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) */
02760    
02761   /* Return HAL status */
02762   return HAL_OK;
02763 }
02764 
02765 
02766 
02767 /**
02768   * @brief  Enable the selected ADC.
02769   * @note   Prerequisite condition to use this function: ADC must be disabled
02770   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
02771   * @param  hadc: ADC handle
02772   * @retval HAL status.
02773   */
02774 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
02775 {
02776   uint32_t tickstart = 0;
02777   
02778   /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
02779   /* enabling phase not yet completed: flag ADC ready not set yet).           */
02780   /* Timeout implemented not to be stuck if ADC cannot be enabled (possible   */
02781   /* causes: ADC clock not running, ...).                                     */
02782   if (ADC_IS_ENABLE(hadc) == RESET)
02783   {
02784     /* Check if conditions to enable the ADC are fulfilled */
02785     if (ADC_ENABLING_CONDITIONS(hadc) == RESET)
02786     {
02787       /* Update ADC state machine to error */
02788       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02789       
02790       /* Set ADC error code to ADC IP internal error */
02791       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02792       
02793       return HAL_ERROR;
02794     }
02795     
02796     /* Enable the ADC peripheral */
02797     ADC_ENABLE(hadc);
02798     
02799     
02800     /* Wait for ADC effectively enabled */
02801     tickstart = HAL_GetTick();  
02802     
02803     while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET)
02804     {
02805       /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit 
02806           has been cleared (after a calibration), ADEN bit is reset by the 
02807           calibration logic.
02808                 The workaround is to continue setting ADEN until ADRDY is becomes 1.
02809           Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
02810           4 ADC clock cycle duration */
02811       ADC_ENABLE(hadc);
02812 
02813       if((HAL_GetTick()-tickstart) > ADC_ENABLE_TIMEOUT)
02814       {  
02815         /* Update ADC state machine to error */
02816         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02817         
02818         /* Set ADC error code to ADC IP internal error */
02819        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02820       
02821         return HAL_ERROR;
02822       }
02823     } 
02824   }
02825    
02826   /* Return HAL status */
02827   return HAL_OK;
02828 }
02829 
02830 /**
02831   * @brief  Disable the selected ADC.
02832   * @note   Prerequisite condition to use this function: ADC conversions must be
02833   *         stopped.
02834   * @param  hadc: ADC handle
02835   * @retval HAL status.
02836   */
02837 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
02838 {
02839   uint32_t tickstart = 0;
02840   
02841   /* Verification if ADC is not already disabled:                             */
02842   /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
02843   /* disabled.                                                                */
02844   if (ADC_IS_ENABLE(hadc) != RESET )
02845   {
02846     /* Check if conditions to disable the ADC are fulfilled */
02847     if (ADC_DISABLING_CONDITIONS(hadc) != RESET)
02848     {
02849       /* Disable the ADC peripheral */
02850       ADC_DISABLE(hadc);
02851     }
02852     else
02853     {
02854       /* Update ADC state machine to error */
02855       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02856       
02857       /* Set ADC error code to ADC IP internal error */
02858       SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02859       
02860       return HAL_ERROR;
02861     }
02862      
02863     /* Wait for ADC effectively disabled */
02864     tickstart = HAL_GetTick();
02865     
02866     while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN))
02867     {
02868       if((HAL_GetTick()-tickstart) > ADC_DISABLE_TIMEOUT)
02869       { 
02870         /* Update ADC state machine to error */
02871         SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
02872         
02873         /* Set ADC error code to ADC IP internal error */
02874         SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
02875         
02876         return HAL_ERROR;
02877       }
02878     }
02879   }
02880   
02881   /* Return HAL status */
02882   return HAL_OK;
02883 }
02884 
02885 
02886 /**
02887   * @brief  DMA transfer complete callback. 
02888   * @param  hdma: pointer to DMA handle.
02889   * @retval None
02890   */
02891 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
02892 {
02893   /* Retrieve ADC handle corresponding to current DMA handle */
02894   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02895  
02896   /* Update state machine on conversion status if not in error state */
02897   if (HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL|HAL_ADC_STATE_ERROR_DMA)))
02898   {
02899     /* Update ADC state machine */
02900     SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
02901     /* Is it the end of the regular sequence ? */
02902     if (HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS))
02903     {
02904       /* Are conversions software-triggered ? */
02905       if(ADC_IS_SOFTWARE_START_REGULAR(hadc))
02906       {
02907         /* Is CONT bit set ? */
02908         if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET)
02909         {
02910           /* CONT bit is not set, no more conversions expected */
02911           CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02912           if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02913           { 
02914             SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02915           }
02916         }
02917       }
02918     }
02919     else
02920     {
02921       /* DMA End of Transfer interrupt was triggered but conversions sequence
02922          is not over. If DMACFG is set to 0, conversions are stopped. */
02923       if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET)
02924       {
02925         /* DMACFG bit is not set, conversions are stopped. */
02926         CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
02927         if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
02928         { 
02929           SET_BIT(hadc->State, HAL_ADC_STATE_READY);
02930         }
02931       }
02932     }
02933     
02934     /* Conversion complete callback */
02935     HAL_ADC_ConvCpltCallback(hadc);   
02936   }
02937   else /* DMA or internal error occurred (or both) */
02938   {
02939     /* In case of internal error, */
02940     if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
02941     {
02942       /* call Error Callback function */
02943       HAL_ADC_ErrorCallback(hadc);
02944     }
02945   
02946   }
02947   
02948 
02949 }
02950 
02951 /**
02952   * @brief  DMA half transfer complete callback. 
02953   * @param  hdma: pointer to DMA handle.
02954   * @retval None
02955   */
02956 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
02957 {
02958   /* Retrieve ADC handle corresponding to current DMA handle */
02959   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02960   
02961   /* Half conversion callback */
02962   HAL_ADC_ConvHalfCpltCallback(hadc); 
02963 }
02964 
02965 /**
02966   * @brief  DMA error callback.
02967   * @param  hdma: pointer to DMA handle.
02968   * @retval None
02969   */
02970 void ADC_DMAError(DMA_HandleTypeDef *hdma)   
02971 {
02972   /* Retrieve ADC handle corresponding to current DMA handle */
02973   ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
02974   
02975   /* Change ADC state */
02976   SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
02977   
02978   /* Set ADC error code to DMA error */
02979   SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
02980   
02981   /* Error callback */
02982   HAL_ADC_ErrorCallback(hadc); 
02983 }
02984 
02985 
02986 /**
02987   * @}
02988   */
02989 
02990 
02991 #endif /* HAL_ADC_MODULE_ENABLED */
02992 /**
02993   * @}
02994   */ 
02995 
02996 /**
02997   * @}
02998   */ 
02999 
03000 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/