Encoder3 - encoder

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Progetto STM32 / Mbed 2 deprecated Encoder3

encoder

Dependencies: mbed

stm32f4xx_hal_tim.h@0:5067873a2400, 2017-04-26 (annotated)

Committer:: schille
Date:: Wed Apr 26 08:26:20 2017 +0000
Revision:: 0:5067873a2400

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schille	0:5067873a2400	1	/**
schille	0:5067873a2400	2	******************************************************************************
schille	0:5067873a2400	3	* @file stm32f4xx_hal_tim.h
schille	0:5067873a2400	4	* @author MCD Application Team
schille	0:5067873a2400	5	* @version V1.3.2
schille	0:5067873a2400	6	* @date 26-June-2015
schille	0:5067873a2400	7	* @brief Header file of TIM HAL module.
schille	0:5067873a2400	8	******************************************************************************
schille	0:5067873a2400	9	* @attention
schille	0:5067873a2400	10	*
schille	0:5067873a2400	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
schille	0:5067873a2400	12	*
schille	0:5067873a2400	13	* Redistribution and use in source and binary forms, with or without modification,
schille	0:5067873a2400	14	* are permitted provided that the following conditions are met:
schille	0:5067873a2400	15	* 1. Redistributions of source code must retain the above copyright notice,
schille	0:5067873a2400	16	* this list of conditions and the following disclaimer.
schille	0:5067873a2400	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
schille	0:5067873a2400	18	* this list of conditions and the following disclaimer in the documentation
schille	0:5067873a2400	19	* and/or other materials provided with the distribution.
schille	0:5067873a2400	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
schille	0:5067873a2400	21	* may be used to endorse or promote products derived from this software
schille	0:5067873a2400	22	* without specific prior written permission.
schille	0:5067873a2400	23	*
schille	0:5067873a2400	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
schille	0:5067873a2400	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
schille	0:5067873a2400	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
schille	0:5067873a2400	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
schille	0:5067873a2400	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
schille	0:5067873a2400	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
schille	0:5067873a2400	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
schille	0:5067873a2400	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
schille	0:5067873a2400	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
schille	0:5067873a2400	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
schille	0:5067873a2400	34	*
schille	0:5067873a2400	35	******************************************************************************
schille	0:5067873a2400	36	*/
schille	0:5067873a2400	37
schille	0:5067873a2400	38	/* Define to prevent recursive inclusion -------------------------------------*/
schille	0:5067873a2400	39	#ifndef __STM32F4xx_HAL_TIM_H
schille	0:5067873a2400	40	#define __STM32F4xx_HAL_TIM_H
schille	0:5067873a2400	41
schille	0:5067873a2400	42	#ifdef __cplusplus
schille	0:5067873a2400	43	extern "C" {
schille	0:5067873a2400	44	#endif
schille	0:5067873a2400	45
schille	0:5067873a2400	46	/* Includes ------------------------------------------------------------------*/
schille	0:5067873a2400	47	#include "stm32f4xx_hal_def.h"
schille	0:5067873a2400	48
schille	0:5067873a2400	49	/** @addtogroup STM32F4xx_HAL_Driver
schille	0:5067873a2400	50	* @{
schille	0:5067873a2400	51	*/
schille	0:5067873a2400	52
schille	0:5067873a2400	53	/** @addtogroup TIM
schille	0:5067873a2400	54	* @{
schille	0:5067873a2400	55	*/
schille	0:5067873a2400	56
schille	0:5067873a2400	57	/* Exported types ------------------------------------------------------------*/
schille	0:5067873a2400	58	/** @defgroup TIM_Exported_Types TIM Exported Types
schille	0:5067873a2400	59	* @{
schille	0:5067873a2400	60	*/
schille	0:5067873a2400	61
schille	0:5067873a2400	62	/**
schille	0:5067873a2400	63	* @brief TIM Time base Configuration Structure definition
schille	0:5067873a2400	64	*/
schille	0:5067873a2400	65	typedef struct
schille	0:5067873a2400	66	{
schille	0:5067873a2400	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
schille	0:5067873a2400	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
schille	0:5067873a2400	69
schille	0:5067873a2400	70	uint32_t CounterMode; /*!< Specifies the counter mode.
schille	0:5067873a2400	71	This parameter can be a value of @ref TIM_Counter_Mode */
schille	0:5067873a2400	72
schille	0:5067873a2400	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
schille	0:5067873a2400	74	Auto-Reload Register at the next update event.
schille	0:5067873a2400	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
schille	0:5067873a2400	76
schille	0:5067873a2400	77	uint32_t ClockDivision; /*!< Specifies the clock division.
schille	0:5067873a2400	78	This parameter can be a value of @ref TIM_ClockDivision */
schille	0:5067873a2400	79
schille	0:5067873a2400	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
schille	0:5067873a2400	81	reaches zero, an update event is generated and counting restarts
schille	0:5067873a2400	82	from the RCR value (N).
schille	0:5067873a2400	83	This means in PWM mode that (N+1) corresponds to:
schille	0:5067873a2400	84	- the number of PWM periods in edge-aligned mode
schille	0:5067873a2400	85	- the number of half PWM period in center-aligned mode
schille	0:5067873a2400	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
schille	0:5067873a2400	87	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	88	} TIM_Base_InitTypeDef;
schille	0:5067873a2400	89
schille	0:5067873a2400	90	/**
schille	0:5067873a2400	91	* @brief TIM Output Compare Configuration Structure definition
schille	0:5067873a2400	92	*/
schille	0:5067873a2400	93
schille	0:5067873a2400	94	typedef struct
schille	0:5067873a2400	95	{
schille	0:5067873a2400	96	uint32_t OCMode; /*!< Specifies the TIM mode.
schille	0:5067873a2400	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
schille	0:5067873a2400	98
schille	0:5067873a2400	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
schille	0:5067873a2400	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
schille	0:5067873a2400	101
schille	0:5067873a2400	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
schille	0:5067873a2400	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
schille	0:5067873a2400	104
schille	0:5067873a2400	105	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
schille	0:5067873a2400	106	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
schille	0:5067873a2400	107	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	108
schille	0:5067873a2400	109	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
schille	0:5067873a2400	110	This parameter can be a value of @ref TIM_Output_Fast_State
schille	0:5067873a2400	111	@note This parameter is valid only in PWM1 and PWM2 mode. */
schille	0:5067873a2400	112
schille	0:5067873a2400	113
schille	0:5067873a2400	114	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
schille	0:5067873a2400	115	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
schille	0:5067873a2400	116	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	117
schille	0:5067873a2400	118	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
schille	0:5067873a2400	119	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
schille	0:5067873a2400	120	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	121	} TIM_OC_InitTypeDef;
schille	0:5067873a2400	122
schille	0:5067873a2400	123	/**
schille	0:5067873a2400	124	* @brief TIM One Pulse Mode Configuration Structure definition
schille	0:5067873a2400	125	*/
schille	0:5067873a2400	126	typedef struct
schille	0:5067873a2400	127	{
schille	0:5067873a2400	128	uint32_t OCMode; /*!< Specifies the TIM mode.
schille	0:5067873a2400	129	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
schille	0:5067873a2400	130
schille	0:5067873a2400	131	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
schille	0:5067873a2400	132	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
schille	0:5067873a2400	133
schille	0:5067873a2400	134	uint32_t OCPolarity; /*!< Specifies the output polarity.
schille	0:5067873a2400	135	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
schille	0:5067873a2400	136
schille	0:5067873a2400	137	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
schille	0:5067873a2400	138	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
schille	0:5067873a2400	139	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	140
schille	0:5067873a2400	141	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
schille	0:5067873a2400	142	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
schille	0:5067873a2400	143	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	144
schille	0:5067873a2400	145	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
schille	0:5067873a2400	146	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
schille	0:5067873a2400	147	@note This parameter is valid only for TIM1 and TIM8. */
schille	0:5067873a2400	148
schille	0:5067873a2400	149	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
schille	0:5067873a2400	150	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
schille	0:5067873a2400	151
schille	0:5067873a2400	152	uint32_t ICSelection; /*!< Specifies the input.
schille	0:5067873a2400	153	This parameter can be a value of @ref TIM_Input_Capture_Selection */
schille	0:5067873a2400	154
schille	0:5067873a2400	155	uint32_t ICFilter; /*!< Specifies the input capture filter.
schille	0:5067873a2400	156	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	157	} TIM_OnePulse_InitTypeDef;
schille	0:5067873a2400	158
schille	0:5067873a2400	159
schille	0:5067873a2400	160	/**
schille	0:5067873a2400	161	* @brief TIM Input Capture Configuration Structure definition
schille	0:5067873a2400	162	*/
schille	0:5067873a2400	163
schille	0:5067873a2400	164	typedef struct
schille	0:5067873a2400	165	{
schille	0:5067873a2400	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
schille	0:5067873a2400	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
schille	0:5067873a2400	168
schille	0:5067873a2400	169	uint32_t ICSelection; /*!< Specifies the input.
schille	0:5067873a2400	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
schille	0:5067873a2400	171
schille	0:5067873a2400	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
schille	0:5067873a2400	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
schille	0:5067873a2400	174
schille	0:5067873a2400	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
schille	0:5067873a2400	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	177	} TIM_IC_InitTypeDef;
schille	0:5067873a2400	178
schille	0:5067873a2400	179	/**
schille	0:5067873a2400	180	* @brief TIM Encoder Configuration Structure definition
schille	0:5067873a2400	181	*/
schille	0:5067873a2400	182
schille	0:5067873a2400	183	typedef struct
schille	0:5067873a2400	184	{
schille	0:5067873a2400	185	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
schille	0:5067873a2400	186	This parameter can be a value of @ref TIM_Encoder_Mode */
schille	0:5067873a2400	187
schille	0:5067873a2400	188	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
schille	0:5067873a2400	189	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
schille	0:5067873a2400	190
schille	0:5067873a2400	191	uint32_t IC1Selection; /*!< Specifies the input.
schille	0:5067873a2400	192	This parameter can be a value of @ref TIM_Input_Capture_Selection */
schille	0:5067873a2400	193
schille	0:5067873a2400	194	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
schille	0:5067873a2400	195	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
schille	0:5067873a2400	196
schille	0:5067873a2400	197	uint32_t IC1Filter; /*!< Specifies the input capture filter.
schille	0:5067873a2400	198	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	199
schille	0:5067873a2400	200	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
schille	0:5067873a2400	201	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
schille	0:5067873a2400	202
schille	0:5067873a2400	203	uint32_t IC2Selection; /*!< Specifies the input.
schille	0:5067873a2400	204	This parameter can be a value of @ref TIM_Input_Capture_Selection */
schille	0:5067873a2400	205
schille	0:5067873a2400	206	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
schille	0:5067873a2400	207	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
schille	0:5067873a2400	208
schille	0:5067873a2400	209	uint32_t IC2Filter; /*!< Specifies the input capture filter.
schille	0:5067873a2400	210	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	211	} TIM_Encoder_InitTypeDef;
schille	0:5067873a2400	212
schille	0:5067873a2400	213	/**
schille	0:5067873a2400	214	* @brief Clock Configuration Handle Structure definition
schille	0:5067873a2400	215	*/
schille	0:5067873a2400	216	typedef struct
schille	0:5067873a2400	217	{
schille	0:5067873a2400	218	uint32_t ClockSource; /*!< TIM clock sources.
schille	0:5067873a2400	219	This parameter can be a value of @ref TIM_Clock_Source */
schille	0:5067873a2400	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
schille	0:5067873a2400	221	This parameter can be a value of @ref TIM_Clock_Polarity */
schille	0:5067873a2400	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
schille	0:5067873a2400	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
schille	0:5067873a2400	224	uint32_t ClockFilter; /*!< TIM clock filter.
schille	0:5067873a2400	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	226	}TIM_ClockConfigTypeDef;
schille	0:5067873a2400	227
schille	0:5067873a2400	228	/**
schille	0:5067873a2400	229	* @brief Clear Input Configuration Handle Structure definition
schille	0:5067873a2400	230	*/
schille	0:5067873a2400	231	typedef struct
schille	0:5067873a2400	232	{
schille	0:5067873a2400	233	uint32_t ClearInputState; /*!< TIM clear Input state.
schille	0:5067873a2400	234	This parameter can be ENABLE or DISABLE */
schille	0:5067873a2400	235	uint32_t ClearInputSource; /*!< TIM clear Input sources.
schille	0:5067873a2400	236	This parameter can be a value of @ref TIM_ClearInput_Source */
schille	0:5067873a2400	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
schille	0:5067873a2400	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
schille	0:5067873a2400	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
schille	0:5067873a2400	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
schille	0:5067873a2400	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
schille	0:5067873a2400	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	243	}TIM_ClearInputConfigTypeDef;
schille	0:5067873a2400	244
schille	0:5067873a2400	245	/**
schille	0:5067873a2400	246	* @brief TIM Slave configuration Structure definition
schille	0:5067873a2400	247	*/
schille	0:5067873a2400	248	typedef struct {
schille	0:5067873a2400	249	uint32_t SlaveMode; /*!< Slave mode selection
schille	0:5067873a2400	250	This parameter can be a value of @ref TIM_Slave_Mode */
schille	0:5067873a2400	251	uint32_t InputTrigger; /*!< Input Trigger source
schille	0:5067873a2400	252	This parameter can be a value of @ref TIM_Trigger_Selection */
schille	0:5067873a2400	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
schille	0:5067873a2400	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
schille	0:5067873a2400	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
schille	0:5067873a2400	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
schille	0:5067873a2400	257	uint32_t TriggerFilter; /*!< Input trigger filter
schille	0:5067873a2400	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
schille	0:5067873a2400	259
schille	0:5067873a2400	260	}TIM_SlaveConfigTypeDef;
schille	0:5067873a2400	261
schille	0:5067873a2400	262	/**
schille	0:5067873a2400	263	* @brief HAL State structures definition
schille	0:5067873a2400	264	*/
schille	0:5067873a2400	265	typedef enum
schille	0:5067873a2400	266	{
schille	0:5067873a2400	267	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
schille	0:5067873a2400	268	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
schille	0:5067873a2400	269	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
schille	0:5067873a2400	270	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
schille	0:5067873a2400	271	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
schille	0:5067873a2400	272	}HAL_TIM_StateTypeDef;
schille	0:5067873a2400	273
schille	0:5067873a2400	274	/**
schille	0:5067873a2400	275	* @brief HAL Active channel structures definition
schille	0:5067873a2400	276	*/
schille	0:5067873a2400	277	typedef enum
schille	0:5067873a2400	278	{
schille	0:5067873a2400	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
schille	0:5067873a2400	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
schille	0:5067873a2400	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
schille	0:5067873a2400	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
schille	0:5067873a2400	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
schille	0:5067873a2400	284	}HAL_TIM_ActiveChannel;
schille	0:5067873a2400	285
schille	0:5067873a2400	286	/**
schille	0:5067873a2400	287	* @brief TIM Time Base Handle Structure definition
schille	0:5067873a2400	288	*/
schille	0:5067873a2400	289	typedef struct
schille	0:5067873a2400	290	{
schille	0:5067873a2400	291	TIM_TypeDef Instance; /!< Register base address */
schille	0:5067873a2400	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
schille	0:5067873a2400	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
schille	0:5067873a2400	294	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
schille	0:5067873a2400	295	This array is accessed by a @ref DMA_Handle_index */
schille	0:5067873a2400	296	HAL_LockTypeDef Lock; /!< Locking object /
schille	0:5067873a2400	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
schille	0:5067873a2400	298	}TIM_HandleTypeDef;
schille	0:5067873a2400	299	/**
schille	0:5067873a2400	300	* @}
schille	0:5067873a2400	301	*/
schille	0:5067873a2400	302
schille	0:5067873a2400	303	/* Exported constants --------------------------------------------------------*/
schille	0:5067873a2400	304	/** @defgroup TIM_Exported_Constants TIM Exported Constants
schille	0:5067873a2400	305	* @{
schille	0:5067873a2400	306	*/
schille	0:5067873a2400	307
schille	0:5067873a2400	308	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
schille	0:5067873a2400	309	* @{
schille	0:5067873a2400	310	*/
schille	0:5067873a2400	311	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
schille	0:5067873a2400	312	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
schille	0:5067873a2400	313	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
schille	0:5067873a2400	314	/**
schille	0:5067873a2400	315	* @}
schille	0:5067873a2400	316	*/
schille	0:5067873a2400	317
schille	0:5067873a2400	318	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
schille	0:5067873a2400	319	* @{
schille	0:5067873a2400	320	*/
schille	0:5067873a2400	321	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
schille	0:5067873a2400	322	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
schille	0:5067873a2400	323	/**
schille	0:5067873a2400	324	* @}
schille	0:5067873a2400	325	*/
schille	0:5067873a2400	326
schille	0:5067873a2400	327	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
schille	0:5067873a2400	328	* @{
schille	0:5067873a2400	329	*/
schille	0:5067873a2400	330	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
schille	0:5067873a2400	331	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
schille	0:5067873a2400	332	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
schille	0:5067873a2400	333	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
schille	0:5067873a2400	334	/**
schille	0:5067873a2400	335	* @}
schille	0:5067873a2400	336	*/
schille	0:5067873a2400	337
schille	0:5067873a2400	338	/** @defgroup TIM_Counter_Mode TIM Counter Mode
schille	0:5067873a2400	339	* @{
schille	0:5067873a2400	340	*/
schille	0:5067873a2400	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
schille	0:5067873a2400	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
schille	0:5067873a2400	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
schille	0:5067873a2400	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
schille	0:5067873a2400	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
schille	0:5067873a2400	346	/**
schille	0:5067873a2400	347	* @}
schille	0:5067873a2400	348	*/
schille	0:5067873a2400	349
schille	0:5067873a2400	350	/** @defgroup TIM_ClockDivision TIM Clock Division
schille	0:5067873a2400	351	* @{
schille	0:5067873a2400	352	*/
schille	0:5067873a2400	353	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
schille	0:5067873a2400	354	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
schille	0:5067873a2400	355	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
schille	0:5067873a2400	356	/**
schille	0:5067873a2400	357	* @}
schille	0:5067873a2400	358	*/
schille	0:5067873a2400	359
schille	0:5067873a2400	360	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
schille	0:5067873a2400	361	* @{
schille	0:5067873a2400	362	*/
schille	0:5067873a2400	363	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
schille	0:5067873a2400	364	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
schille	0:5067873a2400	365	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
schille	0:5067873a2400	366	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
schille	0:5067873a2400	367	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
schille	0:5067873a2400	368	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
schille	0:5067873a2400	369	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
schille	0:5067873a2400	370	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
schille	0:5067873a2400	371
schille	0:5067873a2400	372	/**
schille	0:5067873a2400	373	* @}
schille	0:5067873a2400	374	*/
schille	0:5067873a2400	375
schille	0:5067873a2400	376	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
schille	0:5067873a2400	377	* @{
schille	0:5067873a2400	378	*/
schille	0:5067873a2400	379	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	380	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
schille	0:5067873a2400	381	/**
schille	0:5067873a2400	382	* @}
schille	0:5067873a2400	383	*/
schille	0:5067873a2400	384
schille	0:5067873a2400	385	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
schille	0:5067873a2400	386	* @{
schille	0:5067873a2400	387	*/
schille	0:5067873a2400	388	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
schille	0:5067873a2400	389	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
schille	0:5067873a2400	390	/**
schille	0:5067873a2400	391	* @}
schille	0:5067873a2400	392	*/
schille	0:5067873a2400	393
schille	0:5067873a2400	394	/** @defgroup TIM_Output_Compare_N_Polarity TIM Output CompareN Polarity
schille	0:5067873a2400	395	* @{
schille	0:5067873a2400	396	*/
schille	0:5067873a2400	397	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
schille	0:5067873a2400	398	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
schille	0:5067873a2400	399	/**
schille	0:5067873a2400	400	* @}
schille	0:5067873a2400	401	*/
schille	0:5067873a2400	402
schille	0:5067873a2400	403	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
schille	0:5067873a2400	404	* @{
schille	0:5067873a2400	405	*/
schille	0:5067873a2400	406	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
schille	0:5067873a2400	407	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
schille	0:5067873a2400	408	/**
schille	0:5067873a2400	409	* @}
schille	0:5067873a2400	410	*/
schille	0:5067873a2400	411
schille	0:5067873a2400	412	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
schille	0:5067873a2400	413	* @{
schille	0:5067873a2400	414	*/
schille	0:5067873a2400	415	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
schille	0:5067873a2400	416	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
schille	0:5067873a2400	417	/**
schille	0:5067873a2400	418	* @}
schille	0:5067873a2400	419	*/
schille	0:5067873a2400	420
schille	0:5067873a2400	421	/** @defgroup TIM_Channel TIM Channel
schille	0:5067873a2400	422	* @{
schille	0:5067873a2400	423	*/
schille	0:5067873a2400	424	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
schille	0:5067873a2400	425	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
schille	0:5067873a2400	426	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
schille	0:5067873a2400	427	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
schille	0:5067873a2400	428	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
schille	0:5067873a2400	429
schille	0:5067873a2400	430	/**
schille	0:5067873a2400	431	* @}
schille	0:5067873a2400	432	*/
schille	0:5067873a2400	433
schille	0:5067873a2400	434	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
schille	0:5067873a2400	435	* @{
schille	0:5067873a2400	436	*/
schille	0:5067873a2400	437	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
schille	0:5067873a2400	438	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
schille	0:5067873a2400	439	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
schille	0:5067873a2400	440	/**
schille	0:5067873a2400	441	* @}
schille	0:5067873a2400	442	*/
schille	0:5067873a2400	443
schille	0:5067873a2400	444	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
schille	0:5067873a2400	445	* @{
schille	0:5067873a2400	446	*/
schille	0:5067873a2400	447	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
schille	0:5067873a2400	448	connected to IC1, IC2, IC3 or IC4, respectively */
schille	0:5067873a2400	449	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
schille	0:5067873a2400	450	connected to IC2, IC1, IC4 or IC3, respectively */
schille	0:5067873a2400	451	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
schille	0:5067873a2400	452
schille	0:5067873a2400	453	/**
schille	0:5067873a2400	454	* @}
schille	0:5067873a2400	455	*/
schille	0:5067873a2400	456
schille	0:5067873a2400	457	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
schille	0:5067873a2400	458	* @{
schille	0:5067873a2400	459	*/
schille	0:5067873a2400	460	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
schille	0:5067873a2400	461	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
schille	0:5067873a2400	462	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
schille	0:5067873a2400	463	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
schille	0:5067873a2400	464	/**
schille	0:5067873a2400	465	* @}
schille	0:5067873a2400	466	*/
schille	0:5067873a2400	467
schille	0:5067873a2400	468	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
schille	0:5067873a2400	469	* @{
schille	0:5067873a2400	470	*/
schille	0:5067873a2400	471	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
schille	0:5067873a2400	472	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
schille	0:5067873a2400	473	/**
schille	0:5067873a2400	474	* @}
schille	0:5067873a2400	475	*/
schille	0:5067873a2400	476
schille	0:5067873a2400	477	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
schille	0:5067873a2400	478	* @{
schille	0:5067873a2400	479	*/
schille	0:5067873a2400	480	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
schille	0:5067873a2400	481	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
schille	0:5067873a2400	482	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
schille	0:5067873a2400	483
schille	0:5067873a2400	484	/**
schille	0:5067873a2400	485	* @}
schille	0:5067873a2400	486	*/
schille	0:5067873a2400	487
schille	0:5067873a2400	488	/** @defgroup TIM_Interrupt_definition TIM Interrupt definition
schille	0:5067873a2400	489	* @{
schille	0:5067873a2400	490	*/
schille	0:5067873a2400	491	#define TIM_IT_UPDATE (TIM_DIER_UIE)
schille	0:5067873a2400	492	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
schille	0:5067873a2400	493	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
schille	0:5067873a2400	494	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
schille	0:5067873a2400	495	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
schille	0:5067873a2400	496	#define TIM_IT_COM (TIM_DIER_COMIE)
schille	0:5067873a2400	497	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
schille	0:5067873a2400	498	#define TIM_IT_BREAK (TIM_DIER_BIE)
schille	0:5067873a2400	499	/**
schille	0:5067873a2400	500	* @}
schille	0:5067873a2400	501	*/
schille	0:5067873a2400	502
schille	0:5067873a2400	503	/** @defgroup TIM_Commutation_Source TIM Commutation Source
schille	0:5067873a2400	504	* @{
schille	0:5067873a2400	505	*/
schille	0:5067873a2400	506	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
schille	0:5067873a2400	507	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
schille	0:5067873a2400	508	/**
schille	0:5067873a2400	509	* @}
schille	0:5067873a2400	510	*/
schille	0:5067873a2400	511
schille	0:5067873a2400	512	/** @defgroup TIM_DMA_sources TIM DMA sources
schille	0:5067873a2400	513	* @{
schille	0:5067873a2400	514	*/
schille	0:5067873a2400	515	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
schille	0:5067873a2400	516	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
schille	0:5067873a2400	517	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
schille	0:5067873a2400	518	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
schille	0:5067873a2400	519	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
schille	0:5067873a2400	520	#define TIM_DMA_COM (TIM_DIER_COMDE)
schille	0:5067873a2400	521	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
schille	0:5067873a2400	522	/**
schille	0:5067873a2400	523	* @}
schille	0:5067873a2400	524	*/
schille	0:5067873a2400	525
schille	0:5067873a2400	526	/** @defgroup TIM_Event_Source TIM Event Source
schille	0:5067873a2400	527	* @{
schille	0:5067873a2400	528	*/
schille	0:5067873a2400	529	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
schille	0:5067873a2400	530	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
schille	0:5067873a2400	531	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
schille	0:5067873a2400	532	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
schille	0:5067873a2400	533	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
schille	0:5067873a2400	534	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
schille	0:5067873a2400	535	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
schille	0:5067873a2400	536	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
schille	0:5067873a2400	537
schille	0:5067873a2400	538	/**
schille	0:5067873a2400	539	* @}
schille	0:5067873a2400	540	*/
schille	0:5067873a2400	541
schille	0:5067873a2400	542	/** @defgroup TIM_Flag_definition TIM Flag definition
schille	0:5067873a2400	543	* @{
schille	0:5067873a2400	544	*/
schille	0:5067873a2400	545	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
schille	0:5067873a2400	546	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
schille	0:5067873a2400	547	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
schille	0:5067873a2400	548	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
schille	0:5067873a2400	549	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
schille	0:5067873a2400	550	#define TIM_FLAG_COM (TIM_SR_COMIF)
schille	0:5067873a2400	551	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
schille	0:5067873a2400	552	#define TIM_FLAG_BREAK (TIM_SR_BIF)
schille	0:5067873a2400	553	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
schille	0:5067873a2400	554	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
schille	0:5067873a2400	555	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
schille	0:5067873a2400	556	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
schille	0:5067873a2400	557	/**
schille	0:5067873a2400	558	* @}
schille	0:5067873a2400	559	*/
schille	0:5067873a2400	560
schille	0:5067873a2400	561	/** @defgroup TIM_Clock_Source TIM Clock Source
schille	0:5067873a2400	562	* @{
schille	0:5067873a2400	563	*/
schille	0:5067873a2400	564	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
schille	0:5067873a2400	565	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
schille	0:5067873a2400	566	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
schille	0:5067873a2400	567	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
schille	0:5067873a2400	568	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
schille	0:5067873a2400	569	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
schille	0:5067873a2400	570	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
schille	0:5067873a2400	571	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
schille	0:5067873a2400	572	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
schille	0:5067873a2400	573	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
schille	0:5067873a2400	574	/**
schille	0:5067873a2400	575	* @}
schille	0:5067873a2400	576	*/
schille	0:5067873a2400	577
schille	0:5067873a2400	578	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
schille	0:5067873a2400	579	* @{
schille	0:5067873a2400	580	*/
schille	0:5067873a2400	581	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
schille	0:5067873a2400	582	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
schille	0:5067873a2400	583	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
schille	0:5067873a2400	584	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
schille	0:5067873a2400	585	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
schille	0:5067873a2400	586	/**
schille	0:5067873a2400	587	* @}
schille	0:5067873a2400	588	*/
schille	0:5067873a2400	589
schille	0:5067873a2400	590	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
schille	0:5067873a2400	591	* @{
schille	0:5067873a2400	592	*/
schille	0:5067873a2400	593	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
schille	0:5067873a2400	594	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
schille	0:5067873a2400	595	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
schille	0:5067873a2400	596	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
schille	0:5067873a2400	597	/**
schille	0:5067873a2400	598	* @}
schille	0:5067873a2400	599	*/
schille	0:5067873a2400	600
schille	0:5067873a2400	601	/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
schille	0:5067873a2400	602	* @{
schille	0:5067873a2400	603	*/
schille	0:5067873a2400	604	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
schille	0:5067873a2400	605	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
schille	0:5067873a2400	606	/**
schille	0:5067873a2400	607	* @}
schille	0:5067873a2400	608	*/
schille	0:5067873a2400	609
schille	0:5067873a2400	610	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
schille	0:5067873a2400	611	* @{
schille	0:5067873a2400	612	*/
schille	0:5067873a2400	613	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
schille	0:5067873a2400	614	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
schille	0:5067873a2400	615	/**
schille	0:5067873a2400	616	* @}
schille	0:5067873a2400	617	*/
schille	0:5067873a2400	618
schille	0:5067873a2400	619	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
schille	0:5067873a2400	620	* @{
schille	0:5067873a2400	621	*/
schille	0:5067873a2400	622	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
schille	0:5067873a2400	623	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
schille	0:5067873a2400	624	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
schille	0:5067873a2400	625	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
schille	0:5067873a2400	626	/**
schille	0:5067873a2400	627	* @}
schille	0:5067873a2400	628	*/
schille	0:5067873a2400	629
schille	0:5067873a2400	630	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
schille	0:5067873a2400	631	* @{
schille	0:5067873a2400	632	*/
schille	0:5067873a2400	633	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
schille	0:5067873a2400	634	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	635	/**
schille	0:5067873a2400	636	* @}
schille	0:5067873a2400	637	*/
schille	0:5067873a2400	638
schille	0:5067873a2400	639	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
schille	0:5067873a2400	640	* @{
schille	0:5067873a2400	641	*/
schille	0:5067873a2400	642	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
schille	0:5067873a2400	643	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	644	/**
schille	0:5067873a2400	645	* @}
schille	0:5067873a2400	646	*/
schille	0:5067873a2400	647
schille	0:5067873a2400	648	/** @defgroup TIM_Lock_level TIM Lock level
schille	0:5067873a2400	649	* @{
schille	0:5067873a2400	650	*/
schille	0:5067873a2400	651	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
schille	0:5067873a2400	652	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
schille	0:5067873a2400	653	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
schille	0:5067873a2400	654	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
schille	0:5067873a2400	655	/**
schille	0:5067873a2400	656	* @}
schille	0:5067873a2400	657	*/
schille	0:5067873a2400	658	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
schille	0:5067873a2400	659	* @{
schille	0:5067873a2400	660	*/
schille	0:5067873a2400	661	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
schille	0:5067873a2400	662	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	663	/**
schille	0:5067873a2400	664	* @}
schille	0:5067873a2400	665	*/
schille	0:5067873a2400	666
schille	0:5067873a2400	667	/** @defgroup TIM_Break_Polarity TIM Break Polarity
schille	0:5067873a2400	668	* @{
schille	0:5067873a2400	669	*/
schille	0:5067873a2400	670	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
schille	0:5067873a2400	671	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
schille	0:5067873a2400	672	/**
schille	0:5067873a2400	673	* @}
schille	0:5067873a2400	674	*/
schille	0:5067873a2400	675
schille	0:5067873a2400	676	/** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
schille	0:5067873a2400	677	* @{
schille	0:5067873a2400	678	*/
schille	0:5067873a2400	679	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
schille	0:5067873a2400	680	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	681	/**
schille	0:5067873a2400	682	* @}
schille	0:5067873a2400	683	*/
schille	0:5067873a2400	684
schille	0:5067873a2400	685	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
schille	0:5067873a2400	686	* @{
schille	0:5067873a2400	687	*/
schille	0:5067873a2400	688	#define TIM_TRGO_RESET ((uint32_t)0x0000)
schille	0:5067873a2400	689	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
schille	0:5067873a2400	690	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
schille	0:5067873a2400	691	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
schille	0:5067873a2400	692	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
schille	0:5067873a2400	693	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
schille	0:5067873a2400	694	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
schille	0:5067873a2400	695	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
schille	0:5067873a2400	696	/**
schille	0:5067873a2400	697	* @}
schille	0:5067873a2400	698	*/
schille	0:5067873a2400	699
schille	0:5067873a2400	700	/** @defgroup TIM_Slave_Mode TIM Slave Mode
schille	0:5067873a2400	701	* @{
schille	0:5067873a2400	702	*/
schille	0:5067873a2400	703	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	704	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
schille	0:5067873a2400	705	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
schille	0:5067873a2400	706	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
schille	0:5067873a2400	707	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
schille	0:5067873a2400	708	/**
schille	0:5067873a2400	709	* @}
schille	0:5067873a2400	710	*/
schille	0:5067873a2400	711
schille	0:5067873a2400	712	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
schille	0:5067873a2400	713	* @{
schille	0:5067873a2400	714	*/
schille	0:5067873a2400	715	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
schille	0:5067873a2400	716	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	717	/**
schille	0:5067873a2400	718	* @}
schille	0:5067873a2400	719	*/
schille	0:5067873a2400	720
schille	0:5067873a2400	721	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
schille	0:5067873a2400	722	* @{
schille	0:5067873a2400	723	*/
schille	0:5067873a2400	724	#define TIM_TS_ITR0 ((uint32_t)0x0000)
schille	0:5067873a2400	725	#define TIM_TS_ITR1 ((uint32_t)0x0010)
schille	0:5067873a2400	726	#define TIM_TS_ITR2 ((uint32_t)0x0020)
schille	0:5067873a2400	727	#define TIM_TS_ITR3 ((uint32_t)0x0030)
schille	0:5067873a2400	728	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
schille	0:5067873a2400	729	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
schille	0:5067873a2400	730	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
schille	0:5067873a2400	731	#define TIM_TS_ETRF ((uint32_t)0x0070)
schille	0:5067873a2400	732	#define TIM_TS_NONE ((uint32_t)0xFFFF)
schille	0:5067873a2400	733	/**
schille	0:5067873a2400	734	* @}
schille	0:5067873a2400	735	*/
schille	0:5067873a2400	736
schille	0:5067873a2400	737	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
schille	0:5067873a2400	738	* @{
schille	0:5067873a2400	739	*/
schille	0:5067873a2400	740	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
schille	0:5067873a2400	741	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
schille	0:5067873a2400	742	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
schille	0:5067873a2400	743	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
schille	0:5067873a2400	744	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
schille	0:5067873a2400	745	/**
schille	0:5067873a2400	746	* @}
schille	0:5067873a2400	747	*/
schille	0:5067873a2400	748
schille	0:5067873a2400	749	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
schille	0:5067873a2400	750	* @{
schille	0:5067873a2400	751	*/
schille	0:5067873a2400	752	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
schille	0:5067873a2400	753	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
schille	0:5067873a2400	754	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
schille	0:5067873a2400	755	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
schille	0:5067873a2400	756	/**
schille	0:5067873a2400	757	* @}
schille	0:5067873a2400	758	*/
schille	0:5067873a2400	759
schille	0:5067873a2400	760
schille	0:5067873a2400	761	/** @defgroup TIM_TI1_Selection TIM TI1 Selection
schille	0:5067873a2400	762	* @{
schille	0:5067873a2400	763	*/
schille	0:5067873a2400	764	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
schille	0:5067873a2400	765	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
schille	0:5067873a2400	766	/**
schille	0:5067873a2400	767	* @}
schille	0:5067873a2400	768	*/
schille	0:5067873a2400	769
schille	0:5067873a2400	770	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
schille	0:5067873a2400	771	* @{
schille	0:5067873a2400	772	*/
schille	0:5067873a2400	773	#define TIM_DMABASE_CR1 (0x00000000)
schille	0:5067873a2400	774	#define TIM_DMABASE_CR2 (0x00000001)
schille	0:5067873a2400	775	#define TIM_DMABASE_SMCR (0x00000002)
schille	0:5067873a2400	776	#define TIM_DMABASE_DIER (0x00000003)
schille	0:5067873a2400	777	#define TIM_DMABASE_SR (0x00000004)
schille	0:5067873a2400	778	#define TIM_DMABASE_EGR (0x00000005)
schille	0:5067873a2400	779	#define TIM_DMABASE_CCMR1 (0x00000006)
schille	0:5067873a2400	780	#define TIM_DMABASE_CCMR2 (0x00000007)
schille	0:5067873a2400	781	#define TIM_DMABASE_CCER (0x00000008)
schille	0:5067873a2400	782	#define TIM_DMABASE_CNT (0x00000009)
schille	0:5067873a2400	783	#define TIM_DMABASE_PSC (0x0000000A)
schille	0:5067873a2400	784	#define TIM_DMABASE_ARR (0x0000000B)
schille	0:5067873a2400	785	#define TIM_DMABASE_RCR (0x0000000C)
schille	0:5067873a2400	786	#define TIM_DMABASE_CCR1 (0x0000000D)
schille	0:5067873a2400	787	#define TIM_DMABASE_CCR2 (0x0000000E)
schille	0:5067873a2400	788	#define TIM_DMABASE_CCR3 (0x0000000F)
schille	0:5067873a2400	789	#define TIM_DMABASE_CCR4 (0x00000010)
schille	0:5067873a2400	790	#define TIM_DMABASE_BDTR (0x00000011)
schille	0:5067873a2400	791	#define TIM_DMABASE_DCR (0x00000012)
schille	0:5067873a2400	792	#define TIM_DMABASE_OR (0x00000013)
schille	0:5067873a2400	793	/**
schille	0:5067873a2400	794	* @}
schille	0:5067873a2400	795	*/
schille	0:5067873a2400	796
schille	0:5067873a2400	797	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
schille	0:5067873a2400	798	* @{
schille	0:5067873a2400	799	*/
schille	0:5067873a2400	800	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
schille	0:5067873a2400	801	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
schille	0:5067873a2400	802	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
schille	0:5067873a2400	803	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
schille	0:5067873a2400	804	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
schille	0:5067873a2400	805	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
schille	0:5067873a2400	806	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
schille	0:5067873a2400	807	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
schille	0:5067873a2400	808	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
schille	0:5067873a2400	809	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
schille	0:5067873a2400	810	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
schille	0:5067873a2400	811	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
schille	0:5067873a2400	812	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
schille	0:5067873a2400	813	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
schille	0:5067873a2400	814	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
schille	0:5067873a2400	815	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
schille	0:5067873a2400	816	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
schille	0:5067873a2400	817	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
schille	0:5067873a2400	818	/**
schille	0:5067873a2400	819	* @}
schille	0:5067873a2400	820	*/
schille	0:5067873a2400	821
schille	0:5067873a2400	822	/** @defgroup DMA_Handle_index DMA Handle index
schille	0:5067873a2400	823	* @{
schille	0:5067873a2400	824	*/
schille	0:5067873a2400	825	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
schille	0:5067873a2400	826	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
schille	0:5067873a2400	827	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
schille	0:5067873a2400	828	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
schille	0:5067873a2400	829	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
schille	0:5067873a2400	830	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
schille	0:5067873a2400	831	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
schille	0:5067873a2400	832	/**
schille	0:5067873a2400	833	* @}
schille	0:5067873a2400	834	*/
schille	0:5067873a2400	835
schille	0:5067873a2400	836	/** @defgroup Channel_CC_State Channel CC State
schille	0:5067873a2400	837	* @{
schille	0:5067873a2400	838	*/
schille	0:5067873a2400	839	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
schille	0:5067873a2400	840	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	841	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
schille	0:5067873a2400	842	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
schille	0:5067873a2400	843	/**
schille	0:5067873a2400	844	* @}
schille	0:5067873a2400	845	*/
schille	0:5067873a2400	846
schille	0:5067873a2400	847	/**
schille	0:5067873a2400	848	* @}
schille	0:5067873a2400	849	*/
schille	0:5067873a2400	850
schille	0:5067873a2400	851	/* Exported macro ------------------------------------------------------------*/
schille	0:5067873a2400	852	/** @defgroup TIM_Exported_Macros TIM Exported Macros
schille	0:5067873a2400	853	* @{
schille	0:5067873a2400	854	*/
schille	0:5067873a2400	855	/** @brief Reset TIM handle state
schille	0:5067873a2400	856	* @param __HANDLE__: TIM handle
schille	0:5067873a2400	857	* @retval None
schille	0:5067873a2400	858	*/
schille	0:5067873a2400	859	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
schille	0:5067873a2400	860
schille	0:5067873a2400	861	/**
schille	0:5067873a2400	862	* @brief Enable the TIM peripheral.
schille	0:5067873a2400	863	* @param __HANDLE__: TIM handle
schille	0:5067873a2400	864	* @retval None
schille	0:5067873a2400	865	*/
schille	0:5067873a2400	866	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
schille	0:5067873a2400	867
schille	0:5067873a2400	868	/**
schille	0:5067873a2400	869	* @brief Enable the TIM main Output.
schille	0:5067873a2400	870	* @param __HANDLE__: TIM handle
schille	0:5067873a2400	871	* @retval None
schille	0:5067873a2400	872	*/
schille	0:5067873a2400	873	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
schille	0:5067873a2400	874
schille	0:5067873a2400	875
schille	0:5067873a2400	876	/**
schille	0:5067873a2400	877	* @brief Disable the TIM peripheral.
schille	0:5067873a2400	878	* @param __HANDLE__: TIM handle
schille	0:5067873a2400	879	* @retval None
schille	0:5067873a2400	880	*/
schille	0:5067873a2400	881	#define __HAL_TIM_DISABLE(__HANDLE__) \
schille	0:5067873a2400	882	do { \
schille	0:5067873a2400	883	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
schille	0:5067873a2400	884	{ \
schille	0:5067873a2400	885	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
schille	0:5067873a2400	886	{ \
schille	0:5067873a2400	887	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
schille	0:5067873a2400	888	} \
schille	0:5067873a2400	889	} \
schille	0:5067873a2400	890	} while(0)
schille	0:5067873a2400	891
schille	0:5067873a2400	892	/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
schille	0:5067873a2400	893	channels have been disabled */
schille	0:5067873a2400	894	/**
schille	0:5067873a2400	895	* @brief Disable the TIM main Output.
schille	0:5067873a2400	896	* @param __HANDLE__: TIM handle
schille	0:5067873a2400	897	* @retval None
schille	0:5067873a2400	898	*/
schille	0:5067873a2400	899	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
schille	0:5067873a2400	900	do { \
schille	0:5067873a2400	901	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
schille	0:5067873a2400	902	{ \
schille	0:5067873a2400	903	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
schille	0:5067873a2400	904	{ \
schille	0:5067873a2400	905	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
schille	0:5067873a2400	906	} \
schille	0:5067873a2400	907	} \
schille	0:5067873a2400	908	} while(0)
schille	0:5067873a2400	909
schille	0:5067873a2400	910	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
schille	0:5067873a2400	911	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
schille	0:5067873a2400	912	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
schille	0:5067873a2400	913	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
schille	0:5067873a2400	914	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
schille	0:5067873a2400	915	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
schille	0:5067873a2400	916
schille	0:5067873a2400	917	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
schille	0:5067873a2400	918	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
schille	0:5067873a2400	919
schille	0:5067873a2400	920	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
schille	0:5067873a2400	921	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
schille	0:5067873a2400	922
schille	0:5067873a2400	923	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
schille	0:5067873a2400	924	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
schille	0:5067873a2400	925	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
schille	0:5067873a2400	926	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
schille	0:5067873a2400	927	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
schille	0:5067873a2400	928
schille	0:5067873a2400	929	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
schille	0:5067873a2400	930	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
schille	0:5067873a2400	931	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
schille	0:5067873a2400	932	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
schille	0:5067873a2400	933	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
schille	0:5067873a2400	934
schille	0:5067873a2400	935	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
schille	0:5067873a2400	936	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
schille	0:5067873a2400	937	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
schille	0:5067873a2400	938	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
schille	0:5067873a2400	939	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
schille	0:5067873a2400	940
schille	0:5067873a2400	941	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
schille	0:5067873a2400	942	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
schille	0:5067873a2400	943	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
schille	0:5067873a2400	944	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
schille	0:5067873a2400	945	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
schille	0:5067873a2400	946
schille	0:5067873a2400	947	/**
schille	0:5067873a2400	948	* @brief Sets the TIM Capture Compare Register value on runtime without
schille	0:5067873a2400	949	* calling another time ConfigChannel function.
schille	0:5067873a2400	950	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	951	* @param __CHANNEL__ : TIM Channels to be configured.
schille	0:5067873a2400	952	* This parameter can be one of the following values:
schille	0:5067873a2400	953	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
schille	0:5067873a2400	954	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
schille	0:5067873a2400	955	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
schille	0:5067873a2400	956	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
schille	0:5067873a2400	957	* @param __COMPARE__: specifies the Capture Compare register new value.
schille	0:5067873a2400	958	* @retval None
schille	0:5067873a2400	959	*/
schille	0:5067873a2400	960	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
schille	0:5067873a2400	961	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
schille	0:5067873a2400	962
schille	0:5067873a2400	963	/**
schille	0:5067873a2400	964	* @brief Gets the TIM Capture Compare Register value on runtime
schille	0:5067873a2400	965	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	966	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
schille	0:5067873a2400	967	* This parameter can be one of the following values:
schille	0:5067873a2400	968	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
schille	0:5067873a2400	969	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
schille	0:5067873a2400	970	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
schille	0:5067873a2400	971	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
schille	0:5067873a2400	972	* @retval None
schille	0:5067873a2400	973	*/
schille	0:5067873a2400	974	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
schille	0:5067873a2400	975	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
schille	0:5067873a2400	976
schille	0:5067873a2400	977	/**
schille	0:5067873a2400	978	* @brief Sets the TIM Counter Register value on runtime.
schille	0:5067873a2400	979	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	980	* @param __COUNTER__: specifies the Counter register new value.
schille	0:5067873a2400	981	* @retval None
schille	0:5067873a2400	982	*/
schille	0:5067873a2400	983	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
schille	0:5067873a2400	984
schille	0:5067873a2400	985	/**
schille	0:5067873a2400	986	* @brief Gets the TIM Counter Register value on runtime.
schille	0:5067873a2400	987	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	988	* @retval None
schille	0:5067873a2400	989	*/
schille	0:5067873a2400	990	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
schille	0:5067873a2400	991
schille	0:5067873a2400	992	/**
schille	0:5067873a2400	993	* @brief Sets the TIM Autoreload Register value on runtime without calling
schille	0:5067873a2400	994	* another time any Init function.
schille	0:5067873a2400	995	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	996	* @param __AUTORELOAD__: specifies the Counter register new value.
schille	0:5067873a2400	997	* @retval None
schille	0:5067873a2400	998	*/
schille	0:5067873a2400	999	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
schille	0:5067873a2400	1000	do{ \
schille	0:5067873a2400	1001	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
schille	0:5067873a2400	1002	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
schille	0:5067873a2400	1003	} while(0)
schille	0:5067873a2400	1004	/**
schille	0:5067873a2400	1005	* @brief Gets the TIM Autoreload Register value on runtime
schille	0:5067873a2400	1006	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1007	* @retval None
schille	0:5067873a2400	1008	*/
schille	0:5067873a2400	1009	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
schille	0:5067873a2400	1010
schille	0:5067873a2400	1011	/**
schille	0:5067873a2400	1012	* @brief Sets the TIM Clock Division value on runtime without calling
schille	0:5067873a2400	1013	* another time any Init function.
schille	0:5067873a2400	1014	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1015	* @param __CKD__: specifies the clock division value.
schille	0:5067873a2400	1016	* This parameter can be one of the following value:
schille	0:5067873a2400	1017	* @arg TIM_CLOCKDIVISION_DIV1
schille	0:5067873a2400	1018	* @arg TIM_CLOCKDIVISION_DIV2
schille	0:5067873a2400	1019	* @arg TIM_CLOCKDIVISION_DIV4
schille	0:5067873a2400	1020	* @retval None
schille	0:5067873a2400	1021	*/
schille	0:5067873a2400	1022	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
schille	0:5067873a2400	1023	do{ \
schille	0:5067873a2400	1024	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
schille	0:5067873a2400	1025	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
schille	0:5067873a2400	1026	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
schille	0:5067873a2400	1027	} while(0)
schille	0:5067873a2400	1028	/**
schille	0:5067873a2400	1029	* @brief Gets the TIM Clock Division value on runtime
schille	0:5067873a2400	1030	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1031	* @retval None
schille	0:5067873a2400	1032	*/
schille	0:5067873a2400	1033	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
schille	0:5067873a2400	1034
schille	0:5067873a2400	1035	/**
schille	0:5067873a2400	1036	* @brief Sets the TIM Input Capture prescaler on runtime without calling
schille	0:5067873a2400	1037	* another time HAL_TIM_IC_ConfigChannel() function.
schille	0:5067873a2400	1038	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1039	* @param __CHANNEL__ : TIM Channels to be configured.
schille	0:5067873a2400	1040	* This parameter can be one of the following values:
schille	0:5067873a2400	1041	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
schille	0:5067873a2400	1042	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
schille	0:5067873a2400	1043	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
schille	0:5067873a2400	1044	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
schille	0:5067873a2400	1045	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
schille	0:5067873a2400	1046	* This parameter can be one of the following values:
schille	0:5067873a2400	1047	* @arg TIM_ICPSC_DIV1: no prescaler
schille	0:5067873a2400	1048	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
schille	0:5067873a2400	1049	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
schille	0:5067873a2400	1050	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
schille	0:5067873a2400	1051	* @retval None
schille	0:5067873a2400	1052	*/
schille	0:5067873a2400	1053	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
schille	0:5067873a2400	1054	do{ \
schille	0:5067873a2400	1055	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
schille	0:5067873a2400	1056	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
schille	0:5067873a2400	1057	} while(0)
schille	0:5067873a2400	1058
schille	0:5067873a2400	1059	/**
schille	0:5067873a2400	1060	* @brief Gets the TIM Input Capture prescaler on runtime
schille	0:5067873a2400	1061	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1062	* @param __CHANNEL__ : TIM Channels to be configured.
schille	0:5067873a2400	1063	* This parameter can be one of the following values:
schille	0:5067873a2400	1064	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
schille	0:5067873a2400	1065	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
schille	0:5067873a2400	1066	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
schille	0:5067873a2400	1067	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
schille	0:5067873a2400	1068	* @retval None
schille	0:5067873a2400	1069	*/
schille	0:5067873a2400	1070	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
schille	0:5067873a2400	1071	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
schille	0:5067873a2400	1072	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
schille	0:5067873a2400	1073	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
schille	0:5067873a2400	1074	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
schille	0:5067873a2400	1075
schille	0:5067873a2400	1076	/**
schille	0:5067873a2400	1077	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
schille	0:5067873a2400	1078	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1079	* @note When the USR bit of the TIMx_CR1 register is set, only counter
schille	0:5067873a2400	1080	* overflow/underflow generates an update interrupt or DMA request (if
schille	0:5067873a2400	1081	* enabled)
schille	0:5067873a2400	1082	* @retval None
schille	0:5067873a2400	1083	*/
schille	0:5067873a2400	1084	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
schille	0:5067873a2400	1085	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
schille	0:5067873a2400	1086
schille	0:5067873a2400	1087	/**
schille	0:5067873a2400	1088	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
schille	0:5067873a2400	1089	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1090	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
schille	0:5067873a2400	1091	* following events generate an update interrupt or DMA request (if
schille	0:5067873a2400	1092	* enabled):
schille	0:5067873a2400	1093	* Counter overflow/underflow
schille	0:5067873a2400	1094	* Setting the UG bit
schille	0:5067873a2400	1095	* Update generation through the slave mode controller
schille	0:5067873a2400	1096	* @retval None
schille	0:5067873a2400	1097	*/
schille	0:5067873a2400	1098	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
schille	0:5067873a2400	1099	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
schille	0:5067873a2400	1100
schille	0:5067873a2400	1101	/**
schille	0:5067873a2400	1102	* @brief Sets the TIM Capture x input polarity on runtime.
schille	0:5067873a2400	1103	* @param __HANDLE__: TIM handle.
schille	0:5067873a2400	1104	* @param __CHANNEL__: TIM Channels to be configured.
schille	0:5067873a2400	1105	* This parameter can be one of the following values:
schille	0:5067873a2400	1106	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
schille	0:5067873a2400	1107	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
schille	0:5067873a2400	1108	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
schille	0:5067873a2400	1109	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
schille	0:5067873a2400	1110	* @param __POLARITY__: Polarity for TIx source
schille	0:5067873a2400	1111	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
schille	0:5067873a2400	1112	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
schille	0:5067873a2400	1113	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
schille	0:5067873a2400	1114	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
schille	0:5067873a2400	1115	* @retval None
schille	0:5067873a2400	1116	*/
schille	0:5067873a2400	1117	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
schille	0:5067873a2400	1118	do{ \
schille	0:5067873a2400	1119	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
schille	0:5067873a2400	1120	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
schille	0:5067873a2400	1121	}while(0)
schille	0:5067873a2400	1122	/**
schille	0:5067873a2400	1123	* @}
schille	0:5067873a2400	1124	*/
schille	0:5067873a2400	1125
schille	0:5067873a2400	1126	/* Include TIM HAL Extension module */
schille	0:5067873a2400	1127	#include "stm32f4xx_hal_tim_ex.h"
schille	0:5067873a2400	1128
schille	0:5067873a2400	1129	/* Exported functions --------------------------------------------------------*/
schille	0:5067873a2400	1130	/** @addtogroup TIM_Exported_Functions
schille	0:5067873a2400	1131	* @{
schille	0:5067873a2400	1132	*/
schille	0:5067873a2400	1133
schille	0:5067873a2400	1134	/** @addtogroup TIM_Exported_Functions_Group1
schille	0:5067873a2400	1135	* @{
schille	0:5067873a2400	1136	*/
schille	0:5067873a2400	1137
schille	0:5067873a2400	1138	/* Time Base functions ********************************************************/
schille	0:5067873a2400	1139	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1140	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1141	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1142	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1143	/* Blocking mode: Polling */
schille	0:5067873a2400	1144	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1145	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1146	/* Non-Blocking mode: Interrupt */
schille	0:5067873a2400	1147	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1148	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1149	/* Non-Blocking mode: DMA */
schille	0:5067873a2400	1150	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
schille	0:5067873a2400	1151	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1152	/**
schille	0:5067873a2400	1153	* @}
schille	0:5067873a2400	1154	*/
schille	0:5067873a2400	1155
schille	0:5067873a2400	1156	/** @addtogroup TIM_Exported_Functions_Group2
schille	0:5067873a2400	1157	* @{
schille	0:5067873a2400	1158	*/
schille	0:5067873a2400	1159	/* Timer Output Compare functions **********************************************/
schille	0:5067873a2400	1160	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1161	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1162	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1163	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1164	/* Blocking mode: Polling */
schille	0:5067873a2400	1165	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1166	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1167	/* Non-Blocking mode: Interrupt */
schille	0:5067873a2400	1168	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1169	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1170	/* Non-Blocking mode: DMA */
schille	0:5067873a2400	1171	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
schille	0:5067873a2400	1172	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1173
schille	0:5067873a2400	1174	/**
schille	0:5067873a2400	1175	* @}
schille	0:5067873a2400	1176	*/
schille	0:5067873a2400	1177
schille	0:5067873a2400	1178	/** @addtogroup TIM_Exported_Functions_Group3
schille	0:5067873a2400	1179	* @{
schille	0:5067873a2400	1180	*/
schille	0:5067873a2400	1181	/* Timer PWM functions *********************************************************/
schille	0:5067873a2400	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1186	/* Blocking mode: Polling */
schille	0:5067873a2400	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1189	/* Non-Blocking mode: Interrupt */
schille	0:5067873a2400	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1192	/* Non-Blocking mode: DMA */
schille	0:5067873a2400	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
schille	0:5067873a2400	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1195
schille	0:5067873a2400	1196	/**
schille	0:5067873a2400	1197	* @}
schille	0:5067873a2400	1198	*/
schille	0:5067873a2400	1199
schille	0:5067873a2400	1200	/** @addtogroup TIM_Exported_Functions_Group4
schille	0:5067873a2400	1201	* @{
schille	0:5067873a2400	1202	*/
schille	0:5067873a2400	1203	/* Timer Input Capture functions ***********************************************/
schille	0:5067873a2400	1204	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1205	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1206	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1207	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1208	/* Blocking mode: Polling */
schille	0:5067873a2400	1209	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1210	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1211	/* Non-Blocking mode: Interrupt */
schille	0:5067873a2400	1212	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1213	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1214	/* Non-Blocking mode: DMA */
schille	0:5067873a2400	1215	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
schille	0:5067873a2400	1216	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1217
schille	0:5067873a2400	1218	/**
schille	0:5067873a2400	1219	* @}
schille	0:5067873a2400	1220	*/
schille	0:5067873a2400	1221
schille	0:5067873a2400	1222	/** @addtogroup TIM_Exported_Functions_Group5
schille	0:5067873a2400	1223	* @{
schille	0:5067873a2400	1224	*/
schille	0:5067873a2400	1225	/* Timer One Pulse functions ***************************************************/
schille	0:5067873a2400	1226	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
schille	0:5067873a2400	1227	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1228	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1229	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1230	/* Blocking mode: Polling */
schille	0:5067873a2400	1231	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
schille	0:5067873a2400	1232	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
schille	0:5067873a2400	1233
schille	0:5067873a2400	1234	/* Non-Blocking mode: Interrupt */
schille	0:5067873a2400	1235	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
schille	0:5067873a2400	1236	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
schille	0:5067873a2400	1237
schille	0:5067873a2400	1238	/**
schille	0:5067873a2400	1239	* @}
schille	0:5067873a2400	1240	*/
schille	0:5067873a2400	1241
schille	0:5067873a2400	1242	/** @addtogroup TIM_Exported_Functions_Group6
schille	0:5067873a2400	1243	* @{
schille	0:5067873a2400	1244	*/
schille	0:5067873a2400	1245	/* Timer Encoder functions *****************************************************/
schille	0:5067873a2400	1246	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
schille	0:5067873a2400	1247	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1248	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1249	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1250	/* Blocking mode: Polling */
schille	0:5067873a2400	1251	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1252	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1253	/* Non-Blocking mode: Interrupt */
schille	0:5067873a2400	1254	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1255	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1256	/* Non-Blocking mode: DMA */
schille	0:5067873a2400	1257	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
schille	0:5067873a2400	1258	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1259
schille	0:5067873a2400	1260	/**
schille	0:5067873a2400	1261	* @}
schille	0:5067873a2400	1262	*/
schille	0:5067873a2400	1263
schille	0:5067873a2400	1264	/** @addtogroup TIM_Exported_Functions_Group7
schille	0:5067873a2400	1265	* @{
schille	0:5067873a2400	1266	*/
schille	0:5067873a2400	1267	/* Interrupt Handler functions **********************************************/
schille	0:5067873a2400	1268	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1269
schille	0:5067873a2400	1270	/**
schille	0:5067873a2400	1271	* @}
schille	0:5067873a2400	1272	*/
schille	0:5067873a2400	1273
schille	0:5067873a2400	1274	/** @addtogroup TIM_Exported_Functions_Group8
schille	0:5067873a2400	1275	* @{
schille	0:5067873a2400	1276	*/
schille	0:5067873a2400	1277	/* Control functions *********************************************************/
schille	0:5067873a2400	1278	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
schille	0:5067873a2400	1279	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
schille	0:5067873a2400	1280	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
schille	0:5067873a2400	1281	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
schille	0:5067873a2400	1282	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
schille	0:5067873a2400	1283	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
schille	0:5067873a2400	1284	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
schille	0:5067873a2400	1285	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
schille	0:5067873a2400	1286	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
schille	0:5067873a2400	1287	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
schille	0:5067873a2400	1288	uint32_t *BurstBuffer, uint32_t BurstLength);
schille	0:5067873a2400	1289	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
schille	0:5067873a2400	1290	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
schille	0:5067873a2400	1291	uint32_t *BurstBuffer, uint32_t BurstLength);
schille	0:5067873a2400	1292	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
schille	0:5067873a2400	1293	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
schille	0:5067873a2400	1294	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
schille	0:5067873a2400	1295
schille	0:5067873a2400	1296	/**
schille	0:5067873a2400	1297	* @}
schille	0:5067873a2400	1298	*/
schille	0:5067873a2400	1299
schille	0:5067873a2400	1300	/** @addtogroup TIM_Exported_Functions_Group9
schille	0:5067873a2400	1301	* @{
schille	0:5067873a2400	1302	*/
schille	0:5067873a2400	1303	/* Callback in non blocking modes (Interrupt and DMA) *************************/
schille	0:5067873a2400	1304	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1305	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1306	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1307	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1308	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1309	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1310
schille	0:5067873a2400	1311	/**
schille	0:5067873a2400	1312	* @}
schille	0:5067873a2400	1313	*/
schille	0:5067873a2400	1314
schille	0:5067873a2400	1315	/** @addtogroup TIM_Exported_Functions_Group10
schille	0:5067873a2400	1316	* @{
schille	0:5067873a2400	1317	*/
schille	0:5067873a2400	1318	/* Peripheral State functions **************************************************/
schille	0:5067873a2400	1319	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1320	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1321	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1322	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1323	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1324	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
schille	0:5067873a2400	1325
schille	0:5067873a2400	1326	/**
schille	0:5067873a2400	1327	* @}
schille	0:5067873a2400	1328	*/
schille	0:5067873a2400	1329
schille	0:5067873a2400	1330	/**
schille	0:5067873a2400	1331	* @}
schille	0:5067873a2400	1332	*/
schille	0:5067873a2400	1333
schille	0:5067873a2400	1334	/* Private macros ------------------------------------------------------------*/
schille	0:5067873a2400	1335	/** @defgroup TIM_Private_Macros TIM Private Macros
schille	0:5067873a2400	1336	* @{
schille	0:5067873a2400	1337	*/
schille	0:5067873a2400	1338
schille	0:5067873a2400	1339	/** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
schille	0:5067873a2400	1340	* @{
schille	0:5067873a2400	1341	*/
schille	0:5067873a2400	1342	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
schille	0:5067873a2400	1343	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
schille	0:5067873a2400	1344	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
schille	0:5067873a2400	1345	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
schille	0:5067873a2400	1346	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
schille	0:5067873a2400	1347
schille	0:5067873a2400	1348	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
schille	0:5067873a2400	1349	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
schille	0:5067873a2400	1350	((DIV) == TIM_CLOCKDIVISION_DIV4))
schille	0:5067873a2400	1351
schille	0:5067873a2400	1352	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
schille	0:5067873a2400	1353	((MODE) == TIM_OCMODE_PWM2))
schille	0:5067873a2400	1354
schille	0:5067873a2400	1355	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
schille	0:5067873a2400	1356	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
schille	0:5067873a2400	1357	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
schille	0:5067873a2400	1358	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
schille	0:5067873a2400	1359	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
schille	0:5067873a2400	1360	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
schille	0:5067873a2400	1361
schille	0:5067873a2400	1362	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
schille	0:5067873a2400	1363	((STATE) == TIM_OCFAST_ENABLE))
schille	0:5067873a2400	1364
schille	0:5067873a2400	1365	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
schille	0:5067873a2400	1366	((POLARITY) == TIM_OCPOLARITY_LOW))
schille	0:5067873a2400	1367
schille	0:5067873a2400	1368	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
schille	0:5067873a2400	1369	((POLARITY) == TIM_OCNPOLARITY_LOW))
schille	0:5067873a2400	1370
schille	0:5067873a2400	1371	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
schille	0:5067873a2400	1372	((STATE) == TIM_OCIDLESTATE_RESET))
schille	0:5067873a2400	1373
schille	0:5067873a2400	1374	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
schille	0:5067873a2400	1375	((STATE) == TIM_OCNIDLESTATE_RESET))
schille	0:5067873a2400	1376
schille	0:5067873a2400	1377	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
schille	0:5067873a2400	1378	((CHANNEL) == TIM_CHANNEL_2) \|\| \
schille	0:5067873a2400	1379	((CHANNEL) == TIM_CHANNEL_3) \|\| \
schille	0:5067873a2400	1380	((CHANNEL) == TIM_CHANNEL_4) \|\| \
schille	0:5067873a2400	1381	((CHANNEL) == TIM_CHANNEL_ALL))
schille	0:5067873a2400	1382
schille	0:5067873a2400	1383	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
schille	0:5067873a2400	1384	((CHANNEL) == TIM_CHANNEL_2))
schille	0:5067873a2400	1385
schille	0:5067873a2400	1386	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
schille	0:5067873a2400	1387	((CHANNEL) == TIM_CHANNEL_2) \|\| \
schille	0:5067873a2400	1388	((CHANNEL) == TIM_CHANNEL_3))
schille	0:5067873a2400	1389
schille	0:5067873a2400	1390	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
schille	0:5067873a2400	1391	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
schille	0:5067873a2400	1392	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
schille	0:5067873a2400	1393
schille	0:5067873a2400	1394	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
schille	0:5067873a2400	1395	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
schille	0:5067873a2400	1396	((SELECTION) == TIM_ICSELECTION_TRC))
schille	0:5067873a2400	1397
schille	0:5067873a2400	1398	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
schille	0:5067873a2400	1399	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
schille	0:5067873a2400	1400	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
schille	0:5067873a2400	1401	((PRESCALER) == TIM_ICPSC_DIV8))
schille	0:5067873a2400	1402
schille	0:5067873a2400	1403	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
schille	0:5067873a2400	1404	((MODE) == TIM_OPMODE_REPETITIVE))
schille	0:5067873a2400	1405
schille	0:5067873a2400	1406	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
schille	0:5067873a2400	1407
schille	0:5067873a2400	1408	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
schille	0:5067873a2400	1409	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
schille	0:5067873a2400	1410	((MODE) == TIM_ENCODERMODE_TI12))
schille	0:5067873a2400	1411
schille	0:5067873a2400	1412	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
schille	0:5067873a2400	1413
schille	0:5067873a2400	1414	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
schille	0:5067873a2400	1415	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
schille	0:5067873a2400	1416	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
schille	0:5067873a2400	1417	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
schille	0:5067873a2400	1418	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
schille	0:5067873a2400	1419	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
schille	0:5067873a2400	1420	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
schille	0:5067873a2400	1421	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
schille	0:5067873a2400	1422	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
schille	0:5067873a2400	1423	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
schille	0:5067873a2400	1424
schille	0:5067873a2400	1425	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
schille	0:5067873a2400	1426	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
schille	0:5067873a2400	1427	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
schille	0:5067873a2400	1428	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
schille	0:5067873a2400	1429	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
schille	0:5067873a2400	1430
schille	0:5067873a2400	1431	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
schille	0:5067873a2400	1432	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
schille	0:5067873a2400	1433	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
schille	0:5067873a2400	1434	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
schille	0:5067873a2400	1435
schille	0:5067873a2400	1436	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
schille	0:5067873a2400	1437
schille	0:5067873a2400	1438	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
schille	0:5067873a2400	1439	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
schille	0:5067873a2400	1440
schille	0:5067873a2400	1441	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
schille	0:5067873a2400	1442	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
schille	0:5067873a2400	1443
schille	0:5067873a2400	1444	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
schille	0:5067873a2400	1445	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
schille	0:5067873a2400	1446	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
schille	0:5067873a2400	1447	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
schille	0:5067873a2400	1448
schille	0:5067873a2400	1449	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
schille	0:5067873a2400	1450
schille	0:5067873a2400	1451	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
schille	0:5067873a2400	1452	((STATE) == TIM_OSSR_DISABLE))
schille	0:5067873a2400	1453
schille	0:5067873a2400	1454	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
schille	0:5067873a2400	1455	((STATE) == TIM_OSSI_DISABLE))
schille	0:5067873a2400	1456
schille	0:5067873a2400	1457	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
schille	0:5067873a2400	1458	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
schille	0:5067873a2400	1459	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
schille	0:5067873a2400	1460	((LEVEL) == TIM_LOCKLEVEL_3))
schille	0:5067873a2400	1461
schille	0:5067873a2400	1462	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
schille	0:5067873a2400	1463	((STATE) == TIM_BREAK_DISABLE))
schille	0:5067873a2400	1464
schille	0:5067873a2400	1465	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
schille	0:5067873a2400	1466	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
schille	0:5067873a2400	1467
schille	0:5067873a2400	1468	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
schille	0:5067873a2400	1469	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
schille	0:5067873a2400	1470
schille	0:5067873a2400	1471	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
schille	0:5067873a2400	1472	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
schille	0:5067873a2400	1473	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
schille	0:5067873a2400	1474	((SOURCE) == TIM_TRGO_OC1) \|\| \
schille	0:5067873a2400	1475	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
schille	0:5067873a2400	1476	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
schille	0:5067873a2400	1477	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
schille	0:5067873a2400	1478	((SOURCE) == TIM_TRGO_OC4REF))
schille	0:5067873a2400	1479
schille	0:5067873a2400	1480	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
schille	0:5067873a2400	1481	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
schille	0:5067873a2400	1482	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
schille	0:5067873a2400	1483	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
schille	0:5067873a2400	1484	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
schille	0:5067873a2400	1485
schille	0:5067873a2400	1486	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
schille	0:5067873a2400	1487	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
schille	0:5067873a2400	1488
schille	0:5067873a2400	1489	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
schille	0:5067873a2400	1490	((SELECTION) == TIM_TS_ITR1) \|\| \
schille	0:5067873a2400	1491	((SELECTION) == TIM_TS_ITR2) \|\| \
schille	0:5067873a2400	1492	((SELECTION) == TIM_TS_ITR3) \|\| \
schille	0:5067873a2400	1493	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
schille	0:5067873a2400	1494	((SELECTION) == TIM_TS_TI1FP1) \|\| \
schille	0:5067873a2400	1495	((SELECTION) == TIM_TS_TI2FP2) \|\| \
schille	0:5067873a2400	1496	((SELECTION) == TIM_TS_ETRF))
schille	0:5067873a2400	1497
schille	0:5067873a2400	1498	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
schille	0:5067873a2400	1499	((SELECTION) == TIM_TS_ITR1) \|\| \
schille	0:5067873a2400	1500	((SELECTION) == TIM_TS_ITR2) \|\| \
schille	0:5067873a2400	1501	((SELECTION) == TIM_TS_ITR3) \|\| \
schille	0:5067873a2400	1502	((SELECTION) == TIM_TS_NONE))
schille	0:5067873a2400	1503	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
schille	0:5067873a2400	1504	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
schille	0:5067873a2400	1505	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
schille	0:5067873a2400	1506	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
schille	0:5067873a2400	1507	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
schille	0:5067873a2400	1508
schille	0:5067873a2400	1509	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
schille	0:5067873a2400	1510	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
schille	0:5067873a2400	1511	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
schille	0:5067873a2400	1512	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
schille	0:5067873a2400	1513
schille	0:5067873a2400	1514	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
schille	0:5067873a2400	1515
schille	0:5067873a2400	1516	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
schille	0:5067873a2400	1517	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
schille	0:5067873a2400	1518
schille	0:5067873a2400	1519	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
schille	0:5067873a2400	1520	((BASE) == TIM_DMABASE_CR2) \|\| \
schille	0:5067873a2400	1521	((BASE) == TIM_DMABASE_SMCR) \|\| \
schille	0:5067873a2400	1522	((BASE) == TIM_DMABASE_DIER) \|\| \
schille	0:5067873a2400	1523	((BASE) == TIM_DMABASE_SR) \|\| \
schille	0:5067873a2400	1524	((BASE) == TIM_DMABASE_EGR) \|\| \
schille	0:5067873a2400	1525	((BASE) == TIM_DMABASE_CCMR1) \|\| \
schille	0:5067873a2400	1526	((BASE) == TIM_DMABASE_CCMR2) \|\| \
schille	0:5067873a2400	1527	((BASE) == TIM_DMABASE_CCER) \|\| \
schille	0:5067873a2400	1528	((BASE) == TIM_DMABASE_CNT) \|\| \
schille	0:5067873a2400	1529	((BASE) == TIM_DMABASE_PSC) \|\| \
schille	0:5067873a2400	1530	((BASE) == TIM_DMABASE_ARR) \|\| \
schille	0:5067873a2400	1531	((BASE) == TIM_DMABASE_RCR) \|\| \
schille	0:5067873a2400	1532	((BASE) == TIM_DMABASE_CCR1) \|\| \
schille	0:5067873a2400	1533	((BASE) == TIM_DMABASE_CCR2) \|\| \
schille	0:5067873a2400	1534	((BASE) == TIM_DMABASE_CCR3) \|\| \
schille	0:5067873a2400	1535	((BASE) == TIM_DMABASE_CCR4) \|\| \
schille	0:5067873a2400	1536	((BASE) == TIM_DMABASE_BDTR) \|\| \
schille	0:5067873a2400	1537	((BASE) == TIM_DMABASE_DCR) \|\| \
schille	0:5067873a2400	1538	((BASE) == TIM_DMABASE_OR))
schille	0:5067873a2400	1539
schille	0:5067873a2400	1540	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
schille	0:5067873a2400	1541	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
schille	0:5067873a2400	1542	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
schille	0:5067873a2400	1543	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
schille	0:5067873a2400	1544	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
schille	0:5067873a2400	1545	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
schille	0:5067873a2400	1546	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
schille	0:5067873a2400	1547	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
schille	0:5067873a2400	1548	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
schille	0:5067873a2400	1549	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
schille	0:5067873a2400	1550	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
schille	0:5067873a2400	1551	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
schille	0:5067873a2400	1552	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
schille	0:5067873a2400	1553	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
schille	0:5067873a2400	1554	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
schille	0:5067873a2400	1555	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
schille	0:5067873a2400	1556	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
schille	0:5067873a2400	1557	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
schille	0:5067873a2400	1558
schille	0:5067873a2400	1559	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
schille	0:5067873a2400	1560	/**
schille	0:5067873a2400	1561	* @}
schille	0:5067873a2400	1562	*/
schille	0:5067873a2400	1563
schille	0:5067873a2400	1564	/** @defgroup TIM_Mask_Definitions TIM Mask Definition
schille	0:5067873a2400	1565	* @{
schille	0:5067873a2400	1566	*/
schille	0:5067873a2400	1567	/* The counter of a timer instance is disabled only if all the CCx and CCxN
schille	0:5067873a2400	1568	channels have been disabled */
schille	0:5067873a2400	1569	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
schille	0:5067873a2400	1570	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
schille	0:5067873a2400	1571	/**
schille	0:5067873a2400	1572	* @}
schille	0:5067873a2400	1573	*/
schille	0:5067873a2400	1574
schille	0:5067873a2400	1575	/**
schille	0:5067873a2400	1576	* @}
schille	0:5067873a2400	1577	*/
schille	0:5067873a2400	1578
schille	0:5067873a2400	1579	/* Private functions ---------------------------------------------------------*/
schille	0:5067873a2400	1580	/** @defgroup TIM_Private_Functions TIM Private Functions
schille	0:5067873a2400	1581	* @{
schille	0:5067873a2400	1582	*/
schille	0:5067873a2400	1583	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
schille	0:5067873a2400	1584	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
schille	0:5067873a2400	1585	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
schille	0:5067873a2400	1586	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
schille	0:5067873a2400	1587	void TIM_DMAError(DMA_HandleTypeDef *hdma);
schille	0:5067873a2400	1588	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
schille	0:5067873a2400	1589	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
schille	0:5067873a2400	1590	/**
schille	0:5067873a2400	1591	* @}
schille	0:5067873a2400	1592	*/
schille	0:5067873a2400	1593
schille	0:5067873a2400	1594	/**
schille	0:5067873a2400	1595	* @}
schille	0:5067873a2400	1596	*/
schille	0:5067873a2400	1597
schille	0:5067873a2400	1598	/**
schille	0:5067873a2400	1599	* @}
schille	0:5067873a2400	1600	*/
schille	0:5067873a2400	1601
schille	0:5067873a2400	1602	#ifdef __cplusplus
schille	0:5067873a2400	1603	}
schille	0:5067873a2400	1604	#endif
schille	0:5067873a2400	1605
schille	0:5067873a2400	1606	#endif /* __STM32F4xx_HAL_TIM_H */
schille	0:5067873a2400	1607
schille	0:5067873a2400	1608	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Apr 2017
Imports:	3
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	3

stm32f4xx_hal_tim.h@0:5067873a2400, 2017-04-26 (annotated)

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