Revision 0:5f1d66c85ae0, committed 2015-04-09

Comitter:

fredqian

Date:

Thu Apr 09 16:42:51 2015 +0800

Commit message:

init commit

Changed in this revision

diff -r 000000000000 -r 5f1d66c85ae0 MxRadio.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MxRadio.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,847 @@
+/* Copyright (c) 2011 Frank Zhao
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+ * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+ * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+#include "MxRadio.h"
+#include "MxRadioEvents.h"
+//#define radio_set_state radio_force_state
+
+// the write function checks if beginTransmission was called prior to write
+// in order to determine whether to use immediate or non-immediate transmission
+
+const uint8_t HeadSize=9;
+
+// a busy indicator so transmit functions can wait until the last transmission has finished
+volatile uint8_t txIsBusy = 0;
+
+
+cMxRadio::~cMxRadio()
+{
+}
+// empty constructor, should not be called by user
+cMxRadio::cMxRadio(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName slp, PinName irq)
+:m_spi(mosi, miso, sclk), m_cs(cs), reset_pin(rst), sleep_pin(slp),irq_pin(irq)
+{
+	// default event handlers
+	
+	zrEventTxDone=0;
+	zrEventReceiveFrame=0;
+	temprssi=0;
+	setautotx=false;
+	setautorx=false;
+	needack=false;
+	usedBeginTransmission = 0;
+	hasAttachedTxEvent = 0;
+	hasAttachedRxEvent = 0;
+	lastLqi = 0;
+	lastRssi = 0;
+	txTmpBufferLength = 0;
+	rxRingBufferHead = 0;
+	rxRingBufferTail = 0;
+	/*
+	user_radio_tx_done=0;
+	user_radio_receive_frame=0;
+	user_radio_irq=0;
+	user_radio_error=0;
+	*/
+	zr_attach_receive_frame(&cMxRadio::onReceiveFrame);
+	zr_attach_tx_done(&cMxRadio::onTxDone);
+
+}
+
+/**
+ * @brief Radio Initialization
+ *
+ * The function initializes all IO ressources,
+ * needed for the usage of the radio and performs
+ * a reset to the radio.
+ * It prepares the frame header.
+ * Then it sets the channel number and defaults to RX state.
+ *
+ * @param chan the channel number for the radio to use, 11 to 26
+ */
+void cMxRadio::begin(channel_t chan)
+{
+	begin(chan, 0);
+}
+
+void cMxRadio::begin(channel_t chan,uint16_t panid,uint16_t localaddress,bool needackval,bool autotxval,bool autorxval,char autoretrycount)
+{
+	setautotx=autotxval;
+	setautorx=autorxval;
+	needack=needackval;
+	radio_init(rxFrameBuffer, MAX_FRAME_SIZE);
+
+	//////////////////////////////
+#ifdef SR_MAX_FRAME_RETRES
+	trx_bit_write(SR_MAX_FRAME_RETRES,autoretrycount & 0Xf);//for auto wake up
+	//////////////////////////////
+#endif
+
+
+	if(!needack)
+		txTmpBuffer[0] = 0x41;
+	else
+		txTmpBuffer[0] = 0x61; //ack required
+	txTmpBuffer[1] = 0x88;
+	txTmpBuffer[2] =  0;
+	txTmpBuffer[3]=(uint8_t)(panid & 0xFF );
+	txTmpBuffer[4]=(uint8_t)((panid>>8) & 0xFF );
+	txTmpBuffer[5] = 0xFF; //dest address low byte
+	txTmpBuffer[6] = 0xFF; //dest address hight byte
+	txTmpBuffer[7] = (uint8_t)(localaddress & 0xFF );
+	txTmpBuffer[8] = (uint8_t)((localaddress>>8) & 0xFF );
+	setParam(phyPanId,(uint16_t)panid );
+	setParam(phyShortAddr,(uint16_t)localaddress );
+
+	radio_set_param(RP_CHANNEL(chan));
+
+	// default to receiver
+	if (setautorx)
+		radio_set_state(STATE_RXAUTO);
+	else
+		radio_set_state(STATE_RX);
+#ifdef ENABLE_DIG3_DIG4
+	trx_bit_write(SR_PA_EXT_EN, 1);
+#endif
+}
+void cMxRadio::begin(channel_t chan,uint16_t panid,uint16_t localaddress,bool needackval,bool autotxval,bool autorxval)
+{
+	cMxRadio::begin(chan,panid,localaddress,needackval,autotxval,autorxval,4);
+
+}
+void cMxRadio::sendFrame(uint16_t destaddress,bool needackval,uint8_t* frm, uint8_t len)
+{
+	uint8_t oldvalue=txTmpBuffer[0];
+	if(!needackval)
+		txTmpBuffer[0] = 0x41;
+	else
+		txTmpBuffer[0] = 0x61;
+	beginTransmission(destaddress);
+	write(frm,len);
+	endTransmission();
+	txTmpBuffer[0]=oldvalue;
+
+}
+/**
+ * @brief Radio Initialization
+ *
+ * Overload for radio initalization that allows for the user to set a custom frame header
+ *
+ * @param chan channel number for the radio to use, 11 to 26
+ * @param frameHeader HeadSize byte custom frame header
+ */
+void cMxRadio::begin(channel_t chan, uint8_t* frameHeader)
+{
+	radio_init(rxFrameBuffer, MAX_FRAME_SIZE);
+
+	if (frameHeader)
+	{
+		// copy custom frame header
+		int i;
+		for (i = 0; i < HeadSize; i++)
+			txTmpBuffer[i] = frameHeader[i];
+	}
+	else
+	{
+		txTmpBuffer[0] = 0x41;
+		txTmpBuffer[1] = 0x88;
+		txTmpBuffer[2] =  0;
+		txTmpBuffer[3]=0xCD;
+		txTmpBuffer[4]=0xAB;
+		txTmpBuffer[5] = 0xFF; //dest address low byte
+		txTmpBuffer[6] = 0xFF; //dest address hight byte
+		txTmpBuffer[7] = 0x01;;
+		txTmpBuffer[8] = 0x00;;
+	}
+
+	// set the channel
+	radio_set_param(RP_CHANNEL(chan));
+
+	// default to receiver
+	if (setautorx)
+		radio_set_state(STATE_RXAUTO);
+	else
+		radio_set_state(STATE_RX);
+
+#ifdef ENABLE_DIG3_DIG4
+	trx_bit_write(SR_PA_EXT_EN, 1);
+#endif
+
+}
+
+/**
+ * @brief Set Frame Header
+ *
+ * changes the custom frame header
+ *
+ * @param frameHeader HeadSize byte custom frame header
+ */
+void cMxRadio::setFrameHeader(uint8_t* frameHeader)
+{
+	// copy custom frame header
+	int i;
+	for (i = 0; i < HeadSize; i++)
+		txTmpBuffer[i] = frameHeader[i];
+}
+
+/**
+ * @brief Attach Error Event Handler
+ *
+ * Allows the user to set a error handling function
+ * An empty one is used if none is set
+ *
+ * @param funct the function pointer to the event handler
+ */
+void cMxRadio::attachError(void (*funct)(radio_error_t))
+{
+	user_radio_error = funct;
+}
+
+/**
+ * @brief Attach IRQ Event Handler
+ *
+ * Allows the user to set a IRQ handling function
+ * An empty one is used if none is set
+ *
+ * @param funct the function pointer to the event handler
+ */
+void cMxRadio::attachIrq(void (*funct)(uint8_t))
+{
+	user_radio_irq = funct;
+}
+
+/**
+ * @brief Attach RX Event Handler
+ *
+ * Allows the user to set a RX handling function
+ * The default handler will read in the received frame and place it into the RX FIFO ring buffer
+ * If the user chooses to use this attach function, then the default handler will not be used
+ * This means read/peek/available/flush will stop working
+ *
+ * @param funct the function pointer to the event handler
+ */
+void cMxRadio::attachReceiveFrame(uint8_t* (*funct)(uint8_t, uint8_t*, uint8_t,int8_t, uint8_t))
+{
+	zrEventReceiveFrame = funct;
+	hasAttachedRxEvent = (funct == 0) ? 0 : 1;
+}
+
+/**
+ * @brief Attach TX Complete Event Handler
+ *
+ * Allows the user to set a TX complete handling function
+ * An empty one is used if none is set
+ * The event will occur before the busy flag is reset and returning to RX state
+ *
+ * @param funct the function pointer to the event handler
+ */
+void cMxRadio::attachTxDone(void (*funct)(radio_tx_done_t))
+{
+	zrEventTxDone = funct;
+	hasAttachedTxEvent = (funct == 0) ? 0 : 1;
+}
+
+/**
+ * @brief Default RX Event Handler
+ *
+ * If the user has not attached a custom event handler, then the bytes are placed into the FIFO ring buffer
+ * If the frame contains a header, then the frame header is ignored, only the payload is read
+ * The above does not occur if a user handler is attached, which will be called instead
+ * The LQI and RSSI is always remembered
+ *
+ * This should not be called by the user
+ *
+ * @param len length of the frame
+ * @param frm array containing frame data
+ * @param lqi link quality indicator
+ * @param crc_fail boolean indicating whether the received frame failed FCS verification, not used
+ */
+uint8_t* cMxRadio::onReceiveFrame(uint8_t len, uint8_t* frm, uint8_t lqi, int8_t ed,uint8_t crc_fail)
+{
+	if (crc_fail)
+		return rxRingBuffer;
+	lastLqi = lqi;
+	//lastRssi=ed;
+	if (hasAttachedRxEvent == 0)
+	{
+		// no event handler, so write it into the FIFO
+
+		if (len >= HeadSize-1)
+		{
+			// frame header exists
+			// copy only payload
+
+			for (uint8_t i = HeadSize; i < len - 2; i++)
+			{
+				uint16_t j = ((uint16_t)((uint16_t)rxRingBufferHead + 1)) % ZR_FIFO_SIZE;
+				if (j != rxRingBufferTail)
+				{
+					// push into FIFO
+					rxRingBuffer[rxRingBufferHead] = frm[i];
+					rxRingBufferHead = j;
+				}
+				else
+				{
+					// FIFO full
+					break;
+				}
+			}
+		}
+		else
+		{
+			// frame header does not exist
+			// copy everything
+
+			for (uint8_t i = 0; i < len; i++)
+			{
+				uint16_t j = ((uint16_t)((uint16_t)rxRingBufferHead + 1)) % ZR_FIFO_SIZE;
+				if (j != rxRingBufferTail)
+				{
+					// push into FIFO
+					rxRingBuffer[rxRingBufferHead] = frm[i];
+					rxRingBufferHead = j;
+				}
+				else
+				{
+					// FIFO full
+					break;
+				}
+			}
+		}
+
+		return rxRingBuffer;
+	}
+	else
+	{
+		// user event is attached so call it
+		return zrEventReceiveFrame(len, frm, lqi, ed,crc_fail);
+	}
+}
+
+/**
+ * @brief RX Buffer Flush
+ *
+ * Flush the RX FIFO ring buffer
+ */
+void cMxRadio::flush()
+{
+	rxRingBufferHead = rxRingBufferTail;
+}
+
+/**
+ * @brief RX Buffer Read
+ *
+ * pops and returns the next byte from the FIFO ring buffer
+ *
+ * @return the next byte, or -1 if buffer is empty
+ */
+int16_t cMxRadio::read()
+{
+	// if the head isn't ahead of the tail, we don't have any characters
+	if (rxRingBufferHead == rxRingBufferTail)
+	{
+		return -1;
+	}
+	else
+	{
+		uint8_t c = rxRingBuffer[rxRingBufferTail];
+		rxRingBufferTail = (rxRingBufferTail + 1) % ZR_FIFO_SIZE; // pop
+		return c;
+	}
+}
+
+/**
+ * @brief RX Buffer Peek
+ *
+ * returns the next byte from the FIFO ring buffer without removing it
+ *
+ * @return the next byte, or -1 if buffer is empty
+ */
+int16_t cMxRadio::peek()
+{
+	// if the head isn't ahead of the tail, we don't have any characters
+	if (rxRingBufferHead == rxRingBufferTail)
+	{
+		return -1;
+	}
+	else
+	{
+		uint8_t c = rxRingBuffer[rxRingBufferTail];
+		return c;
+	}
+}
+
+/**
+ * @brief RX Buffer Size
+ *
+ * Shows how many bytes are in the RX FIFO ring buffer
+ *
+ * @return how many bytes are in the RX FIFO ring buffer
+ */
+int8_t cMxRadio::available()
+{
+	return ((int16_t)((int16_t)ZR_FIFO_SIZE + (int16_t)rxRingBufferHead - (int16_t)rxRingBufferTail)) % ZR_FIFO_SIZE;
+}
+
+/**
+ * @brief Raw Frame Transmit
+ *
+ * Transmits a frame
+ * Warning: no frame header or FCS is added
+ *
+ * @param frm array containing frame data
+ * @param len length of the frame
+ */
+void cMxRadio::txFrame(uint8_t* frm, uint8_t len)
+{
+#ifdef ZR_TXWAIT_BEFORE
+	waitTxDone(0xFFFF);
+#endif
+	txIsBusy = 1;
+	if (setautotx)
+		radio_set_state(STATE_TXAUTO);
+	else
+		radio_set_state(STATE_TX);
+	ZR_RFTX_LED_ON();
+	radio_send_frame(len, frm, 0);
+#ifdef ZR_TXWAIT_AFTER
+	waitTxDone(0xFFFF);
+	if (setautorx)
+		radio_set_state(STATE_RXAUTO);
+	else
+		radio_set_state(STATE_RX);
+	txIsBusy = 0;
+#endif
+}
+
+/**
+ * @brief Prepare for Trasmission
+ *
+ * Goes into non-immediate transmit mode, resets the transmit payload
+ * Non-immediate mode sends multiple bytes per frame
+ *
+ */
+void cMxRadio::beginTransmission()
+{
+	usedBeginTransmission = 1;
+	txTmpBuffer[5]= 0xFF;
+	txTmpBuffer[6]= 0XFF;
+	// add frame header
+	txTmpBufferLength = HeadSize;
+}
+
+void cMxRadio::beginTransmission(uint16_t destaddress)
+{
+	txTmpBuffer[5]=(uint8_t)(destaddress & 0xFF );
+	txTmpBuffer[6]=(uint8_t)((destaddress>>8) & 0xFF );
+	usedBeginTransmission = 1;
+
+	// add frame header
+	txTmpBufferLength = HeadSize;
+}
+
+/**
+ * @brief Finalize Trasmission
+ *
+ * Finalize the payload and transmits it when ready
+ *
+ */
+void cMxRadio::endTransmission()
+{
+	usedBeginTransmission = 0;
+
+	// empty FCS field
+	txTmpBufferLength += 2;
+
+#ifdef ZR_TXWAIT_BEFORE
+	waitTxDone(0xFFFF);
+#endif
+	txIsBusy = 1;
+	if (setautotx)
+		radio_set_state(STATE_TXAUTO);
+	else
+		radio_set_state(STATE_TX);
+	ZR_RFTX_LED_ON();
+	//if broadcase ,cant need ack
+	if(txTmpBuffer[5]==0xff && txTmpBuffer[5]==0xff)
+		txTmpBuffer[0]=txTmpBuffer[0]&0xdf;
+	else
+	{
+		if(!needack)
+			txTmpBuffer[0] = 0x41;
+		else
+			txTmpBuffer[0] = 0x61; //ack required
+	}
+	radio_send_frame(txTmpBufferLength, txTmpBuffer, 0);
+#ifdef ZR_TXWAIT_AFTER
+	waitTxDone(0xFFFF);
+	if (setautorx)
+		radio_set_state(STATE_RXAUTO);
+	else
+		radio_set_state(STATE_RX);
+	txIsBusy = 0;
+#endif
+}
+
+/**
+ * @brief Cancel Trasmission
+ *
+ * Clears payload buffer
+ *
+ * Warning: does not actually cancel a transmission in progress
+ *
+ */
+void cMxRadio::cancelTransmission()
+{
+	usedBeginTransmission = 0;
+
+	// add frame header
+	txTmpBufferLength = HeadSize;
+}
+/**
+ * @brief TX a Byte
+ *
+ * Wrapper for "write", since the "Wire" library uses "send"
+ *
+ */
+void cMxRadio::send(uint8_t c)
+{
+	write(c);
+}
+
+/**
+ * @brief TX a Byte
+ *
+ * If "beginTrasmission" was used, then it writes into the transmit buffer for non-immediate mode
+ * If "beginTrasmission" was not used, then it transmits the single byte immediately (slower for multiple bytes)
+ *
+ * @param c character to be sent
+ */
+void cMxRadio::write(uint8_t c)
+{
+	if (usedBeginTransmission)
+	{
+		if (txTmpBufferLength < ZR_TXTMPBUFF_SIZE - 2)
+		{
+			txTmpBuffer[txTmpBufferLength] = c;
+			txTmpBufferLength++;
+
+			if (txTmpBufferLength >= ZR_TXTMPBUFF_SIZE - 2)
+			{
+				// buffer is now full
+				// just send it all out so we have more room
+				endTransmission();
+				beginTransmission();
+			}
+		}
+	}
+	else
+	{
+		txTmpBuffer[HeadSize] = c; // set payload
+		txTmpBuffer[HeadSize+1] = 0; // empty FCS
+		txTmpBuffer[HeadSize+2] = 0; // empty FCS
+
+#ifdef ZR_TXWAIT_BEFORE
+		waitTxDone(0xFFFF);
+#endif
+		txIsBusy = 1;
+		if (setautotx)
+			radio_set_state(STATE_TXAUTO);
+		else
+			radio_set_state(STATE_TX);
+		ZR_RFTX_LED_ON();
+		radio_send_frame(10, txTmpBuffer, 0);
+#ifdef ZR_TXWAIT_AFTER
+		waitTxDone(0xFFFF);
+		if (setautorx)
+			radio_set_state(STATE_RXAUTO);
+		else
+			radio_set_state(STATE_RX);
+		txIsBusy = 0;
+#endif
+	}
+}
+/**
+ * @brief TX a String
+ *
+ * A overload for "write" that sends a null-terminated string
+ *
+ * @param str null-terminated string to be sent
+ */
+void cMxRadio::write(char* str)
+{
+	while (*str)
+		write(*str++);
+}
+
+/**
+ * @brief TX an Array
+ *
+ * A overload for "write" that sends an array
+ *
+ * @param arr data array to be sent
+ * @param len length of data array
+ */
+void cMxRadio::write(uint8_t* arr, uint8_t len)
+{
+	uint8_t i;
+	for (i = 0; i < len; i++)
+		write(arr[i]);
+}
+
+/**
+ * @brief Default TX Complete Event Handler
+ *
+ * Calls the user event function if one is attached
+ * Clear the TX busy status flag
+ * Defaults back to RX state
+ *
+ * this should not be called by the user
+ *
+ * @param x one of the radio_tx_done_t enumerations indicating transmission success
+ */
+void cMxRadio::onTxDone(radio_tx_done_t x)
+{
+	if (hasAttachedTxEvent)
+	{
+		zrEventTxDone(x);
+	}
+
+	txIsBusy = 0;
+}
+
+/**
+ * @brief radio_set_param Wrapper
+ *
+ * set a radio parameter
+ *
+ * see radio.h for more info
+ */
+void cMxRadio::setParam(radio_attribute_t attr, radio_param_t parm)
+{
+	radio_set_param(attr, parm);
+}
+
+/**
+ * @brief radio_do_cca Wrapper
+ *
+ * perform CCA measure
+ *
+ * see radio.h for more info
+ */
+radio_cca_t cMxRadio::doCca()
+{
+	return radio_do_cca();
+}
+
+/**
+ * @brief Set Radio State Wrapper
+ *
+ * sets or forces the radio into a state
+ *
+ * see radio.h for more info
+ *
+ * @param state requested radio state
+ * @param force boolean indicating to force the state
+ */
+void cMxRadio::setState(radio_state_t state, uint8_t force)
+{
+	if (force)
+		radio_force_state(state);
+	else
+		radio_set_state(state);
+}
+
+/**
+ * @brief radio_set_state Wrapper
+ *
+ * bring the the radio in the requested state
+ *
+ * see radio.h for more info
+ */
+void cMxRadio::setState(radio_state_t state)
+{
+	radio_set_state(state);
+}
+
+/**
+ * @brief radio_set_state to STATE_RX
+ *
+ * bring the the radio in the requested state of STATE_RX
+ *
+ * the radio state does not return to STATE_RX automatically if ZR_TXWAIT_AFTER is not used
+ * thus why this is provided
+ *
+ * see radio.h for more info
+ */
+void cMxRadio::setStateRx()
+{
+	if (setautorx)
+		radio_set_state(STATE_RXAUTO);
+	else
+		radio_set_state(STATE_RX);
+}
+
+/**
+ * @brief radio_force_state Wrapper
+ *
+ * force the radio to the requested state
+ *
+ * see radio.h for more info
+ */
+void cMxRadio::forceState(radio_state_t state)
+{
+	radio_force_state(state);
+}
+
+/**
+ * @brief Sets Radio Channel
+ *
+ * changes the radio channel by setting the radio channel state
+ *
+ * @param chan channel number, 11 to 26
+ */
+void cMxRadio::setChannel(channel_t chan)
+{
+	radio_set_param(RP_CHANNEL(chan));
+}
+uint8_t cMxRadio::getChannel()
+{
+	trx_param_t p;
+	trx_parms_get(&p);
+	channel_t chan= p.chan;
+	return (uint8_t)chan;
+}
+
+
+/**
+ * @brief Read Receiver Signal Strength Indicator Now
+ *
+ * returns the current RSSI
+ *
+ * range is between -91 and -9 dBm
+ * where -9 is the best
+ *
+ * @return RSSI of the last transmission received
+ */
+int8_t cMxRadio::getRssiNow()
+{
+	int16_t rssi = ((int16_t)(trx_reg_read(RG_PHY_RSSI) & 0x1F)); // mask only important bits
+	rssi = (rssi == 0) ? (RSSI_BASE_VAL - 1) : ((rssi < 28) ? ((rssi - 1) * 3 + RSSI_BASE_VAL) : -9);
+	// if 0, then rssi < RSSI_BASE_VAL, if 28, then >= -10
+
+	return rssi;
+}
+
+
+
+/**
+ * @brief Read Last Receiver Signal Strength Indicator
+ *
+ * returns the RSSI of the last transmission
+ *
+ * range is between -91 and -9 dBm
+ * where -9 is the best
+ *
+ * @return RSSI of the last transmission received
+ */
+int8_t cMxRadio::getLastRssi()
+{
+	int16_t rssi = ((int16_t)(temprssi & 0x1F)); // mask only important bits
+	rssi = (rssi == 0) ? (RSSI_BASE_VAL - 1) : ((rssi < 28) ? ((rssi - 1) * 3 + RSSI_BASE_VAL) : -9);
+	// if 0, then rssi < RSSI_BASE_VAL, if 28, then >= -10
+
+	return rssi;
+}
+
+
+/**
+ * @brief Read Link Quality Indicator
+ *
+ * returns the LQI of the last transmission received
+ *
+ * range is from 0 to 255
+ * 255 is the best
+ *
+ * @return LQI of the last transmission received
+ */
+uint8_t cMxRadio::getLqi()
+{
+	return lastLqi;
+}
+
+/**
+ * @brief Read Last Energy Detection Level
+ *
+ * returns the ED level of the last transmission received
+ *
+ * range is between -90 and -6 dBm
+ * where -6 is the best
+ *
+ * @return ED level of the last transmission received
+ */
+int8_t cMxRadio::getLastEd()
+{
+	int8_t ed = trx_reg_read(RG_PHY_ED_LEVEL);
+
+	return ed == 0xFF ? 0 : (ed + RSSI_BASE_VAL);
+	//return lastRssi == 0xFF ? 0 : (lastRssi + RSSI_BASE_VAL);
+
+}
+
+/**
+ * @brief Read Energy Detection Level Now
+ *
+ * forces a reading of the ED level
+ *
+ * range is between -90 and -6 dBm
+ * where -6 is the best
+ *
+ * @return ED level
+ */
+int8_t cMxRadio::getEdNow()
+{
+	trx_reg_write(RG_PHY_ED_LEVEL, 0); // forces a reading
+
+	return getLastEd();
+}
+
+/**
+ * @brief Wait for TX to Complete
+ *
+ * waits until the last transmission is complete, or timed out
+ *
+ * @param timeout iterations to countdown before timeout
+ */
+void cMxRadio::waitTxDone(uint16_t timeout)
+{
+	volatile uint16_t cnt = timeout;
+	while (txIsBusy && cnt--);
+}
+
+

diff -r 000000000000 -r 5f1d66c85ae0 MxRadio.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MxRadio.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,313 @@
+/* Copyright (c) 2011 Frank Zhao
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+ * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+ * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+#ifndef MxRadio_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "uracolib/board.h"
+#include "MxRadioCfg.h"
+#include "uracolib/radio.h"
+#include "uracolib/transceiver.h"
+#include <stdint.h>
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#include "mbed.h"
+#define ZR_RXFRMBUFF_SIZE MAX_FRAME_SIZE
+#define ZR_FIFO_SIZE 128 // size for the RX FIFO ring buffer
+#define ZR_TXTMPBUFF_SIZE MAX_FRAME_SIZE // size for the TX non-immediate transmit buffer
+
+#define ZR_TXWAIT_BEFORE // when you call any TX functions, it will wait until the previous transmission has finished before initiating a new transmission
+#define ZR_TXWAIT_AFTER // when you call any TX functions, it will transmit and then wait until that transmission finished
+
+// just a class definition, for usage and comments, see the cpp file
+class cMxRadio
+{
+private:
+
+	uint8_t temprssi;
+	radio_status_t radiostatus;
+	SPI m_spi;
+	DigitalOut m_cs;
+	DigitalOut reset_pin;
+	DigitalOut sleep_pin;
+
+protected:
+	InterruptIn irq_pin;
+private:
+	 uint8_t rxFrameBuffer[ZR_RXFRMBUFF_SIZE];
+	 uint8_t rxRingBuffer[ZR_FIFO_SIZE];
+	 uint8_t rxRingBufferHead;
+	 uint8_t rxRingBufferTail;
+	 uint8_t txTmpBuffer[ZR_TXTMPBUFF_SIZE];
+	 uint8_t txTmpBufferLength;
+	 uint8_t lastLqi;
+	 uint8_t lastRssi;
+	 uint8_t hasAttachedRxEvent;
+	 uint8_t hasAttachedTxEvent;
+	 uint8_t usedBeginTransmission;
+	volatile  uint8_t txIsBusy;
+
+	 uint8_t* (*zrEventReceiveFrame)(uint8_t, uint8_t*, uint8_t, int8_t,uint8_t);
+	 void (*zrEventTxDone)(radio_tx_done_t);
+
+	 uint8_t* onReceiveFrame(uint8_t, uint8_t*, uint8_t, int8_t,uint8_t);
+	 void onTxDone(radio_tx_done_t);
+	 bool setautotx,setautorx,needack;
+
+	//come from radio.h
+	void radio_init(uint8_t * rxbuf, uint8_t rxbufsz);
+	void radio_force_state(radio_state_t state);
+	void radio_set_state(radio_state_t state);
+	void radio_set_param(radio_attribute_t attr, radio_param_t parm);
+	void radio_send_frame(uint8_t len, uint8_t *frm, uint8_t compcrc);
+	radio_cca_t radio_do_cca(void);
+	int radio_putchar(int c);
+	int radio_getchar(void);
+	void usr_radio_error(radio_error_t err);
+	void usr_radio_irq(uint8_t cause);
+	uint8_t * usr_radio_receive_frame(uint8_t len, uint8_t *frm, uint8_t lqi, int8_t ed, uint8_t crc_fail);
+	void usr_radio_tx_done(radio_tx_done_t status);
+	//come from transciever
+	void trx_io_init (int spirate);
+	void trx_reg_write(trx_regaddr_t addr, trx_regval_t val);
+	uint8_t trx_reg_read(trx_regaddr_t addr);
+	trx_regval_t trx_bit_read(trx_regaddr_t addr, trx_regval_t mask, uint8_t pos);
+	void trx_bit_write(trx_regaddr_t addr, trx_regval_t mask, uint8_t pos, trx_regval_t value);
+	void trx_frame_write(uint8_t length, uint8_t *data);
+	uint8_t trx_frame_read(uint8_t *data, uint8_t datasz, uint8_t *lqi);
+	//uint8_t trx_frame_read_crc(uint8_t *data, uint8_t datasz, bool *crc_ok);
+	//uint8_t trx_frame_read_data_crc(uint8_t *data, uint8_t datasz, uint8_t *lqi, bool *crc_ok);
+	uint8_t trx_frame_get_length(void);
+	void trx_sram_write(trx_ramaddr_t addr, uint8_t length, uint8_t *data);
+	void trx_sram_read(trx_ramaddr_t addr, uint8_t length, uint8_t *data);
+	void trx_parms_get(trx_param_t *p);
+	uint8_t trx_parms_set(trx_param_t *p);
+	uint8_t trx_set_datarate(uint8_t rate_type);
+	uint8_t trx_get_datarate(void);
+	uint8_t trx_get_number_datarates(void);
+	//void * trx_get_datarate_str_p(uint8_t idx);
+	//void * trx_decode_datarate_p(uint8_t rhash);
+	//uint8_t trx_get_datarate_str(uint8_t idx, char * rstr, uint8_t nlen);
+	//uint8_t trx_decode_datarate(uint8_t rhash, char * rstr, uint8_t nlen);
+	/**
+	 * @brief Basic radio initialization function,
+	 */
+	 inline uint8_t trx_init(void)
+	{
+		uint8_t val;
+		/* reset transceiver */
+		reset_pin=0;//TRX_RESET_LOW();
+		sleep_pin=0;//TRX_SLPTR_LOW();
+		DELAY_US(TRX_RESET_TIME_US);
+		reset_pin=1;//TRX_RESET_HIGH();
+		/* set TRX_OFF (for the case we come from P_ON) */
+		trx_reg_write(RG_TRX_STATE, CMD_TRX_OFF);
+
+#if RADIO_TYPE == RADIO_AT86RF212
+		trx_reg_write(RG_TRX_CTRL_0, 0x19);
+#ifdef CHINABAND
+		trx_reg_write(RG_CC_CTRL_1, CCBAND );
+		trx_reg_write(RG_CC_CTRL_0, 11);//channel 0
+		trx_reg_write(RG_TRX_CTRL_2, TRX_OQPSK250);
+		DELAY_US(510);
+#endif
+#endif
+
+		DELAY_US(TRX_INIT_TIME_US);
+		val = trx_reg_read(RG_TRX_STATUS);
+		return (val != TRX_OFF) ? TRX_OK : TRX_INIT_FAIL;
+	}
+	 inline uint8_t trx_check_pll_lock(void)
+	{
+	uint8_t val, cnt = 255;
+
+	    trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
+	    trx_reg_write(RG_IRQ_MASK, TRX_IRQ_PLL_LOCK);
+	    trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
+	    cnt = 255;
+	    do
+	    {
+	        DELAY_US(TRX_PLL_LOCK_TIME_US);
+	        val = trx_reg_read(RG_IRQ_STATUS);
+	        if (val & TRX_IRQ_PLL_LOCK)
+	        {
+	            break;
+	        }
+	    }
+	    while(--cnt);
+
+	    /* clear pending IRQs*/
+	    trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
+	    trx_reg_read(RG_IRQ_STATUS);
+	    return (cnt > 0) ? TRX_OK : TRX_PLL_FAIL;
+	}
+
+	/**
+	 * @brief Verify that correct radio type is used.
+	 *
+	 * @return status value, with the following meaning:
+	 *        - 0 if part and revision number match
+	 *        - 1 if revision number does @b not match
+	 *        - 2 if part number does @b not match
+	 *        - 3 if part and revision number does @b not match
+	 */
+	 inline int trx_identify(void)
+	{
+	    int ret = 0;
+
+	    if(RADIO_PART_NUM != trx_reg_read(RG_PART_NUM))
+	    {
+	        ret |= INVALID_PART_NUM;
+	    }
+
+	    if(RADIO_VERSION_NUM != trx_reg_read(RG_VERSION_NUM))
+	    {
+	        ret |= INVALID_REV_NUM;
+	    }
+	    return ret;
+	}
+
+	/**
+	 * @brief Write the PANID to the address filter registers
+	 */
+	 inline void trx_set_panid(uint16_t panid)
+	{
+	    trx_reg_write(RG_PAN_ID_0,(panid&0xff));
+	    trx_reg_write(RG_PAN_ID_1,(panid>>8));
+	}
+
+	/**
+	 * @brief Write the 16 bit short address to the
+	 * address filter registers
+	 */
+	 inline void trx_set_shortaddr(uint16_t shortaddr)
+	{
+	    trx_reg_write(RG_SHORT_ADDR_0,(shortaddr&0xff));
+	    trx_reg_write(RG_SHORT_ADDR_1,(shortaddr>>8));
+	}
+
+	/**
+	 * @brief Write the 64 bit long address (MAC address) to the
+	 * address filter registers
+	 */
+	 inline void trx_set_longaddr(uint64_t longaddr)
+	{
+	    trx_reg_write(RG_IEEE_ADDR_0, (uint8_t)(longaddr>>0) );
+	    trx_reg_write(RG_IEEE_ADDR_1, (uint8_t)(longaddr>>8) );
+	    trx_reg_write(RG_IEEE_ADDR_2, (uint8_t)(longaddr>>16));
+	    trx_reg_write(RG_IEEE_ADDR_3, (uint8_t)(longaddr>>24));
+	    trx_reg_write(RG_IEEE_ADDR_4, (uint8_t)(longaddr>>32));
+	    trx_reg_write(RG_IEEE_ADDR_5, (uint8_t)(longaddr>>40));
+	    trx_reg_write(RG_IEEE_ADDR_6, (uint8_t)(longaddr>>48));
+	    trx_reg_write(RG_IEEE_ADDR_7, (uint8_t)(longaddr>>56));
+	}
+
+	 inline uint16_t crc16_update(uint16_t crc, uint8_t a)
+	     {
+	         int i;
+
+	         crc ^= a;
+	         for (i = 0; i < 8; ++i)
+	         {
+	             if (crc & 1)
+	                 crc = (crc >> 1) ^ 0xA001;
+	             else
+	                 crc = (crc >> 1);
+	         }
+
+	         return crc;
+	     }
+
+	void rf_irq_callback();
+
+	//rf230.cpp
+	void radio_error(radio_error_t err);
+	void radio_receive_frame(void);
+	void radio_irq_handler(uint8_t cause);
+	//events
+	void zr_attach_error(void (*)(radio_error_t));
+	void zr_attach_irq(void (*)(uint8_t));
+	void zr_attach_receive_frame(uint8_t* (cMxRadio::*)(uint8_t, uint8_t*, uint8_t, int8_t,uint8_t));
+	void zr_attach_tx_done(void (cMxRadio::*)(radio_tx_done_t));
+
+	 void (*user_radio_error)(radio_error_t);
+	 void (*user_radio_irq)(uint8_t);
+	 uint8_t* (cMxRadio::*user_radio_receive_frame)(uint8_t, uint8_t*, uint8_t, int8_t,uint8_t);
+	 void (cMxRadio::*user_radio_tx_done)(radio_tx_done_t);
+
+
+public:
+	cMxRadio(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName slp, PinName irq);
+	~cMxRadio();
+	void begin(channel_t);
+	void begin(channel_t,uint16_t,uint16_t,bool,bool,bool,char);
+	void begin(channel_t,uint16_t,uint16_t,bool,bool,bool);
+	void begin(channel_t, uint8_t*);
+	void setFrameHeader(uint8_t*);
+	void attachError(void(*)(radio_error_t));
+	void attachIrq(void(*)(uint8_t));
+	void attachReceiveFrame(uint8_t* (*)(uint8_t, uint8_t*, uint8_t, int8_t,uint8_t));
+	void sendFrame(uint16_t ,bool ,uint8_t* , uint8_t );
+	void attachTxDone(void(*)(radio_tx_done_t));
+	int8_t available();
+	int16_t peek();
+	int16_t read();
+	void flush();
+	void write(uint8_t);
+	void write(char*);
+	void write(uint8_t*, uint8_t);
+	void send(uint8_t);
+	void txFrame(uint8_t*, uint8_t);
+	void beginTransmission();
+	void beginTransmission(uint16_t);
+	void endTransmission();
+	void cancelTransmission();
+	void setParam(radio_attribute_t, radio_param_t);
+	radio_cca_t doCca();
+	void setState(radio_state_t, uint8_t);
+	void setState(radio_state_t);
+	void setStateRx();
+	void setChannel(channel_t);
+	uint8_t getChannel();
+	void forceState(radio_state_t);
+	void waitTxDone(uint16_t);
+	int8_t getRssiNow();
+	int8_t getLastRssi();
+	uint8_t getLqi();
+	int8_t getLastEd();
+	int8_t getEdNow();
+};
+
+extern cMxRadio MxRadio; // make single instance accessible
+
+#define MxRadio_h
+#endif

diff -r 000000000000 -r 5f1d66c85ae0 MxRadioCfg.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MxRadioCfg.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,48 @@
+/* Copyright (c) 2011 Frank Zhao
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+#ifndef MxRadioCfg_h
+
+#define RADIO_TYPE  RADIO_AT86RF231 //RADIO_AT86RF212
+//#define CHINABAND
+#define MxRadioCfg_h
+
+//#define ENABLE_DIG3_DIG4 // this enables the DIG3 and DIG4 indicators by enabling PA_EXT_EN
+
+// define the LED behaviour macros here
+// leave them blank if you want to disable the LEDs
+// PD5 and PD6 are used on the Zigduino
+#define ZR_RFRX_LED_OUTPUT() //do{DDRD|=_BV(6);}while(0)
+#define ZR_RFTX_LED_OUTPUT() //do{DDRD|=_BV(5);}while(0)
+#define ZR_RFRX_LED_ON() //do{PORTD|=_BV(6);}while(0)
+#define ZR_RFTX_LED_ON() //do{PORTD|=_BV(5);}while(0)
+#define ZR_RFRX_LED_OFF() //do{PORTD&=~_BV(6);}while(0)
+#define ZR_RFTX_LED_OFF() //do{PORTD&=~_BV(5);}while(0)
+
+#define MxRadioCfg_h
+#endif

diff -r 000000000000 -r 5f1d66c85ae0 MxRadioEvents.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MxRadioEvents.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,47 @@
+/* Copyright (c) 2011 Frank Zhao
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+#ifndef MxRadioEvents_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern void (*user_radio_error)(radio_error_t);
+extern void (*user_radio_irq)(uint8_t);
+extern uint8_t* (*user_radio_receive_frame)(uint8_t, uint8_t*, uint8_t, int8_t,uint8_t);
+extern void (*user_radio_tx_done)(radio_tx_done_t);
+
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#define MxRadioEvents_h
+#endif

diff -r 000000000000 -r 5f1d66c85ae0 MxRadio_Events.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/MxRadio_Events.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,76 @@
+/* Copyright (c) 2011 Frank Zhao
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+ * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+ * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+#include "MxRadio.h"
+
+
+void (*user_radio_error)(radio_error_t) = 0;
+void (*user_radio_irq)(uint8_t) = 0;
+uint8_t* (*user_radio_receive_frame)(uint8_t, uint8_t*, uint8_t,int8_t, uint8_t) = 0;
+void (*user_radio_tx_done)(radio_tx_done_t) = 0;
+
+void cMxRadio::zr_attach_error(void (*funct)(radio_error_t))
+{
+	user_radio_error = funct;
+}
+
+void cMxRadio::zr_attach_irq(void (*funct)(uint8_t))
+{
+	user_radio_irq = funct;
+}
+
+void cMxRadio::zr_attach_receive_frame(uint8_t* (cMxRadio::*funct)(uint8_t, uint8_t*, uint8_t, int8_t, uint8_t))
+{
+	user_radio_receive_frame = funct;
+}
+
+void cMxRadio::zr_attach_tx_done(void (cMxRadio::*funct)(radio_tx_done_t))
+{
+	user_radio_tx_done = funct;
+}
+void cMxRadio::usr_radio_error(radio_error_t err)
+{
+	if (user_radio_error) user_radio_error(err);
+}
+
+void cMxRadio::usr_radio_irq(uint8_t cause)
+{
+	if (user_radio_irq) user_radio_irq(cause);
+}
+
+uint8_t* cMxRadio::usr_radio_receive_frame(uint8_t len, uint8_t *frm, uint8_t lqi, int8_t ed,uint8_t crc_fail)
+{
+	if (user_radio_receive_frame)
+		return (this->*user_radio_receive_frame)(len, frm, lqi,ed, crc_fail);
+	else return frm;
+}
+
+void cMxRadio::usr_radio_tx_done(radio_tx_done_t status)
+{
+	if (user_radio_tx_done) (this->*user_radio_tx_done)(status);
+}

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_radio_rf230.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_radio_rf230.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,582 @@
+/* Copyright (c) 2007-2010 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+ * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+ * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief
+ * Implementation of high level radio functions for AT86RF230 chip
+ *
+ */
+
+/* === includes ============================================================ */
+#include <stdbool.h>
+
+
+#include <MxRadio.h>
+
+
+/* === functions ============================================================ */
+
+/* === internal functions ====================================================*/
+/**
+ * @brief Error handler
+ *
+ * @param  err error value (see enumeration radio_error_t)
+ * @ingroup grpRadio
+ */
+
+void cMxRadio::radio_error(radio_error_t err)
+{
+	usr_radio_error(err);
+}
+
+
+/**
+ * @brief Frame reception
+ *
+ */
+void cMxRadio::radio_receive_frame(void)
+{
+
+	uint8_t len, lqi, crc_fail;
+	int8_t ed;
+
+	/* @todo add RSSI_BASE_VALUE to get a dBm value */
+	ed = (int8_t)trx_reg_read(RG_PHY_ED_LEVEL);
+	len = trx_frame_read(radiostatus.rxframe, radiostatus.rxframesz, &lqi);
+	len &= ~0x80;
+
+#if defined(SR_RX_CRC_VALID)
+	crc_fail = trx_bit_read(SR_RX_CRC_VALID) ? 0 : 1;
+#else
+	uint8_t *frm, i;
+	uint16_t crc;
+	crc = 0;
+	frm = radiostatus.rxframe;
+	for (i=0; i < len; i++)
+	{
+		crc = CRC_CCITT_UPDATE(crc, *frm++);
+	}
+	crc_fail = (crc == 0)? 0: 1;
+#endif
+radiostatus.rxframe = usr_radio_receive_frame(len, radiostatus.rxframe,
+		lqi, ed, crc_fail);
+}
+
+/**
+ * @brief IRQ handler for radio functions.
+ *
+ * This function is called in the transceiver interrupt routine.
+ * Keep the implementation of the callback functions
+ * (usr_radio_irq, usr_radio_receive_frame) short and efficient.
+ *
+ * @parm cause  value of the interrupt status register
+ *
+ */
+void cMxRadio::radio_irq_handler(uint8_t cause)
+{
+	if (cause & TRX_IRQ_TRX_END)
+	{
+		if (STATE_RX == radiostatus.state ||
+				STATE_RXAUTO == radiostatus.state)
+		{
+			radio_receive_frame();
+		}
+		else if (STATE_TX == radiostatus.state)
+		{
+#ifdef TRX_TX_PA_EI
+TRX_TX_PA_DI();
+#endif
+usr_radio_tx_done(TX_OK);
+radio_set_state(radiostatus.idle_state);
+		}
+		else if (STATE_TXAUTO == radiostatus.state)
+		{
+#ifdef TRX_TX_PA_EI
+			TRX_TX_PA_DI();
+#endif
+			uint8_t trac_status = trx_bit_read(SR_TRAC_STATUS);
+			radio_tx_done_t result;
+			switch (trac_status)
+			{
+			case TRAC_SUCCESS:
+#if defined TRAC_SUCCESS_DATA_PENDING
+			case TRAC_SUCCESS_DATA_PENDING:
+#endif
+#if defined TRAC_SUCCESS_WAIT_FOR_ACK
+			case TRAC_SUCCESS_WAIT_FOR_ACK:
+#endif
+				result = TX_OK;
+				break;
+
+			case TRAC_CHANNEL_ACCESS_FAILURE:
+				result = TX_CCA_FAIL;
+				break;
+
+			case TRAC_NO_ACK:
+				result = TX_NO_ACK;
+				break;
+
+			default:
+				result = TX_FAIL;
+			}
+			usr_radio_tx_done(result);
+			radio_set_state(radiostatus.idle_state);
+		}
+	}
+	usr_radio_irq(cause);
+}
+
+
+/* === external functions ====================================================*/
+
+void cMxRadio::radio_init(uint8_t * rxbuf, uint8_t rxbufsz)
+{
+	trx_regval_t status;
+	/* init cpu peripherals and global IRQ enable */
+	radiostatus.rxframe = rxbuf;
+	radiostatus.rxframesz = rxbufsz;
+	trx_io_init(1000000);
+	/* transceiver initialization */
+
+	reset_pin=0;//TRX_RESET_LOW();
+	sleep_pin=0;//TRX_SLPTR_LOW();
+	DELAY_US(TRX_RESET_TIME_US);
+#if defined(CUSTOM_RESET_TIME_MS)
+	DELAY_MS(CUSTOM_RESET_TIME_MS);
+#endif
+	reset_pin=1;//TRX_RESET_HIGH();
+
+
+//	if (trx_reg_read(RG_MAN_ID_0)==31) //atmel
+//		m_myled=0;
+	/* disable IRQ and clear any pending IRQs */
+	trx_reg_write(RG_IRQ_MASK, 0);
+
+	trx_reg_read(RG_IRQ_STATUS);
+
+#if RADIO_TYPE == RADIO_AT86RF212
+	trx_reg_write(RG_TRX_CTRL_0, 0x19);
+#ifdef CHINABAND
+	trx_reg_write(RG_CC_CTRL_1, CCBAND );
+	trx_reg_write(RG_CC_CTRL_0, CCNUMBER);//channel 0
+	trx_reg_write(RG_TRX_CTRL_2, TRX_OQPSK250);
+	/*trx_bit_write(SR_OQPSK_SUB1_RC_EN,1);
+	trx_bit_write(SR_BPSK_OQPSK,1);
+	trx_bit_write(SR_SUB_MODE,1);
+	trx_bit_write(SR_OQPSK_DATA_RATE,0);
+	trx_bit_write(SR_CC_BAND,CCBAND);
+	 */
+	DELAY_US(510);
+#endif
+	trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
+	DELAY_US(510);
+#else
+	trx_bit_write(SR_TRX_CMD, CMD_TRX_OFF);
+	DELAY_US(510);
+#endif
+
+	do
+	{
+		status = trx_bit_read(SR_TRX_STATUS);
+	}
+	while (status != TRX_OFF);
+	trx_bit_write(SR_TX_AUTO_CRC_ON, 1);
+	trx_reg_write(RG_IRQ_MASK, TRX_IRQ_RX_START | TRX_IRQ_TRX_END);
+
+	radiostatus.state = STATE_OFF;
+	radiostatus.idle_state = STATE_OFF;
+}
+
+
+void cMxRadio::radio_force_state(radio_state_t state)
+{
+	trx_bit_write(SR_TRX_CMD, CMD_FORCE_TRX_OFF);
+	radio_set_state(state);
+}
+
+void cMxRadio::radio_set_state(volatile radio_state_t state)
+{
+	volatile trx_regval_t cmd, expstatus, currstatus;
+	uint8_t retries;
+	bool do_sleep = false;
+
+	switch(state)
+	{
+	case STATE_OFF:
+#ifdef TRX_TX_PA_EI
+		TRX_TX_PA_DI();
+#endif
+#ifdef TRX_RX_LNA_EI
+		TRX_RX_LNA_DI();
+#endif
+		expstatus = TRX_OFF;
+		cmd = CMD_TRX_OFF;
+		break;
+
+	case STATE_RX:
+#ifdef TRX_RX_LNA_EI
+		if (radiostatus.rx_lna)
+		{
+			TRX_RX_LNA_EI();
+		}
+#endif
+expstatus = RX_ON;
+cmd = CMD_RX_ON;
+break;
+
+	case STATE_TX:
+		expstatus = PLL_ON;
+		cmd = CMD_PLL_ON;
+		break;
+
+	case STATE_RXAUTO:
+#ifdef TRX_RX_LNA_EI
+if (radiostatus.rx_lna)
+{
+	TRX_RX_LNA_EI();
+}
+#endif
+expstatus = RX_AACK_ON;
+cmd = CMD_RX_AACK_ON;
+break;
+
+	case STATE_TXAUTO:
+		expstatus = TX_ARET_ON;
+		cmd = CMD_TX_ARET_ON;
+		break;
+
+	case STATE_SLEEP:
+#ifdef TRX_TX_PA_EI
+		TRX_TX_PA_DI();
+#endif
+#ifdef TRX_RX_LNA_EI
+		TRX_RX_LNA_DI();
+#endif
+		expstatus = TRX_OFF;
+		cmd = CMD_FORCE_TRX_OFF;
+		do_sleep = true;
+		break;
+
+	default:
+		radio_error(GENERAL_ERROR);
+		expstatus = TRX_OFF;
+		cmd = CMD_TRX_OFF;
+		break;
+
+	}
+
+	if (STATE_SLEEP == radiostatus.state)
+	{
+		if (do_sleep)
+		{
+			return;
+		}
+		sleep_pin=0;//TRX_SLPTR_LOW();
+		/*
+		 * Give the xosc some time to start up.  Once it started, the
+		 * SPI interface is operational, and the transceiver state can
+		 * be polled.  The state reads as 0b0011111 ("state transition
+		 * in progress") while the transceiver is still in its startup
+		 * phase, which does not match any of the "expstatus" values,
+		 * so polling just continues.
+		 */
+		DELAY_US(500);
+
+		/*
+		 * The exact wake-up timing is very board-dependent.
+		 * Contributing parameters are the effective series resitance
+		 * of the crystal, and the external bypass capacitor that has
+		 * to be charged by the voltage regulator.  Give the crystal
+		 * oscillator some time to start up.  5 ms (100 * 50 us) ought
+		 * to be enough under all circumstances.
+		 */
+		retries = 100;
+		do
+		{
+			currstatus = trx_bit_read(SR_TRX_STATUS);
+			/*
+			 * Sleep could only be entered from TRX_OFF, so that's
+			 * what is expected again.
+			 */
+			if (TRX_OFF == currstatus)
+			{
+				break;
+			}
+			DELAY_US(50);
+		}
+		while (--retries);
+
+		if (currstatus != TRX_OFF)
+		{
+			/* radio didn't wake up */
+			radio_error(STATE_SET_FAILED);
+		}
+	}
+	trx_bit_write(SR_TRX_CMD, cmd);
+
+	retries = 140;              /* enough to await an ongoing frame
+	 * reception */
+	do
+	{
+		currstatus = trx_bit_read(SR_TRX_STATUS);
+		if (expstatus == currstatus)
+		{
+			break;
+		}
+		/** @todo must wait longer for 790/868/900 MHz radios */
+		DELAY_US(32);
+	}
+	while (--retries);
+
+	if (expstatus != currstatus)
+	{
+		radio_error(STATE_SET_FAILED);
+	}
+
+	if (do_sleep)
+	{
+		sleep_pin=1;//TRX_SLPTR_HIGH();
+	}
+
+	radiostatus.state = state;
+}
+
+void cMxRadio::radio_set_param(radio_attribute_t attr, radio_param_t parm)
+{
+	switch (attr)
+	{
+	case phyCurrentChannel:
+		if (((int)parm.channel >= TRX_MIN_CHANNEL) &&
+				((int)parm.channel <= TRX_MAX_CHANNEL))
+		{
+#ifdef CHINABAND
+			trx_reg_write(RG_CC_CTRL_1, CCBAND);
+			trx_reg_write(RG_CC_CTRL_0, parm.channel*2+CCNUMBER);
+#else
+			trx_bit_write(SR_CHANNEL, parm.channel);
+#endif
+			radiostatus.channel = parm.channel;
+		}
+		else
+		{
+			radio_error(SET_PARM_FAILED);
+		}
+		break;
+
+	case phyTransmitPower:
+#if RADIO_TYPE == RADIO_AT86RF212
+#ifdef CHINABAND
+		if (parm.tx_pwr >= -11 && parm.tx_pwr <= 8)
+		{
+			/** @todo move this into a radio-specific header file */
+			static const uint8_t pwrtable[] =
+			{
+					0x0A, 0x09, 0x08,             /* -11...-9 dBm */
+					0x07, 0x06, 0x05,			/* -8...-6 dBm */
+					0x04, 0x03, 0x25,                   /* -5...-3 dBm */
+					0x46, 0xAC, 0xAB,                   /* -2...0 dBm */
+					0xAA,                         /* 1 dBm */
+					0xCA,                         /* 2 dBm */
+					0xEA,                         /* 3 dBm */
+					0xE9,                         /* 4 dBm */
+					0xE8,                         /* 5 dBm */
+					0xE6,                         /* 6 dBm */
+					0xE5,                         /* 7 dBm */
+					0xE4,                         /* 8 dBm */
+			};
+			radiostatus.tx_pwr = parm.tx_pwr;
+			uint8_t idx = parm.tx_pwr + 11;
+			uint8_t pwrval = pgm_read_byte(pwrtable[idx]);
+			trx_reg_write(RG_PHY_TX_PWR, pwrval);
+		}
+		else
+		{
+			radio_error(SET_PARM_FAILED);
+		}
+#endif//chinaband
+#else
+		if (parm.tx_pwr >= -17 && parm.tx_pwr <= 3)
+		{
+			/** @todo move this into a radio-specific header file */
+			static const uint8_t pwrtable[] =
+			{
+					0x0F, 0x0F, 0x0F, 0x0F, 0x0F, /* -17...-13 dBm */
+					0x0E, 0x0E, 0x0E,             /* -12...-10 dBm */
+					0x0D, 0x0D,                   /* -9...-8 dBm */
+					0x0C, 0x0C,                   /* -7...-6 dBm */
+					0x0B,                         /* -5 dBm */
+					0x0A,                         /* -4 dBm */
+					0x09,                         /* -3 dBm */
+					0x08,                         /* -2 dBm */
+					0x07,                         /* -1 dBm */
+					0x06,                         /* 0 dBm */
+					0x04,                         /* 1 dBm */
+					0x02,                         /* 2 dBm */
+					0x00                          /* 3 dBm */
+			};
+			radiostatus.tx_pwr = parm.tx_pwr;
+			uint8_t idx = parm.tx_pwr + 17;
+			uint8_t pwrval = pwrtable[idx];
+			trx_bit_write(SR_TX_PWR, pwrval);
+
+		}
+
+		else
+		{
+			radio_error(SET_PARM_FAILED);
+		}
+
+#endif//rf212
+		break;
+	case phyCCAMode:
+		if (parm.cca_mode <= 3)
+		{
+			radiostatus.cca_mode = parm.cca_mode;
+			trx_bit_write(SR_CCA_MODE, radiostatus.cca_mode);
+		}
+		else
+		{
+			radio_error(SET_PARM_FAILED);
+		}
+		break;
+
+	case phyIdleState:
+		radiostatus.idle_state = parm.idle_state;
+		radio_set_state(parm.idle_state);
+		break;
+
+	case phyChannelsSupported:
+		break;
+
+	case phyPanId:
+		trx_set_panid(parm.pan_id);
+		break;
+
+	case phyShortAddr:
+		trx_set_shortaddr(parm.short_addr);
+		break;
+
+	case phyLongAddr:
+	{
+		uint8_t regno, *ap;
+		for (regno = RG_IEEE_ADDR_0, ap = (uint8_t *)parm.long_addr;
+				regno <= RG_IEEE_ADDR_7;
+				regno++, ap++)
+			trx_reg_write(regno, *ap);
+		break;
+	}
+
+	case phyDataRate:
+		trx_set_datarate(parm.data_rate);
+		break;
+
+#ifdef TRX_TX_PA_EI
+	case phyTxPa:
+		radiostatus.tx_pa = parm.tx_pa;
+		break;
+#endif
+#ifdef TRX_RX_LNA_EI
+	case phyRxLna:
+		radiostatus.rx_lna = parm.rx_lna;
+		break;
+#endif
+
+	default:
+		radio_error(SET_PARM_FAILED);
+		break;
+	}
+}
+
+
+void cMxRadio::radio_send_frame(uint8_t len, uint8_t *frm, uint8_t compcrc)
+{
+#ifdef TRX_TX_PA_EI
+	if (radiostatus.tx_pa)
+	{
+		TRX_TX_PA_EI();
+	}
+#endif
+/* this block should be made atomic */
+	frm[2]++;
+	sleep_pin=1;//TRX_SLPTR_HIGH();
+	sleep_pin=0;//TRX_SLPTR_LOW();
+	trx_frame_write(len, frm);
+	/***********************************/
+}
+
+radio_cca_t cMxRadio::radio_do_cca(void)
+{
+	uint8_t tmp, trxcmd, trxstatus;
+	radio_cca_t ret = RADIO_CCA_FREE;
+
+	trxcmd = trx_reg_read(RG_TRX_STATE);
+	trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
+	tmp = 130;
+	do
+	{
+		trxstatus = trx_bit_read(SR_TRX_STATUS);
+		if ((RX_ON == trxstatus) || (BUSY_RX == trxstatus))
+		{
+			break;
+		}
+		DELAY_US(32); /* wait for one octett */
+	}
+	while(--tmp);
+
+	trx_reg_write(RG_TRX_STATE, CMD_PLL_ON);
+	trx_reg_write(RG_TRX_STATE, CMD_RX_ON);
+
+	trx_bit_write(SR_CCA_REQUEST,1);
+	DELAY_US(140);
+	/* we need to read the whole status register
+	 * because CCA_DONE and CCA_STATUS are valid
+	 * only for one read, after the read they are reset
+	 */
+	tmp = trx_reg_read(RG_TRX_STATUS);
+
+	if(0 == (tmp & 0x80))
+	{
+		ret = RADIO_CCA_FAIL;
+	}
+	else if (tmp & 0x40)
+	{
+		ret = RADIO_CCA_FREE;
+	}
+	else
+	{
+		ret = RADIO_CCA_BUSY;
+	}
+
+	trx_reg_write(RG_TRX_STATE, trxcmd);
+
+	return ret;
+}
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_datarate.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_datarate.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,162 @@
+/* Copyright (c) 2009 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief Chip dependent implementation of functions for setting and getting
+ * the data rate of the transceiver.
+ * @_addtogroup grpApp
+ */
+
+
+/* === includes ============================================================ */
+
+
+#include <MxRadio.h>
+
+/* === functions =========================================================== */
+#if RADIO_TYPE ==  RADIO_AT86RF212
+uint8_t cMxRadio::trx_set_datarate(uint8_t rate_type)
+{
+trx_regval_t regval = TRX_NONE;
+
+    switch(rate_type)
+    {
+        case BPSK20: regval = TRX_BPSK20; break;
+        case BPSK40: regval = TRX_BPSK40; break;
+        case OQPSK100: regval = TRX_OQPSK100; break;
+        case OQPSK200: regval = TRX_OQPSK200; break;
+        case OQPSK250: regval = TRX_OQPSK250; break;
+        case OQPSK400: regval = TRX_OQPSK400; break;
+        case OQPSK500: regval = TRX_OQPSK500; break;
+        case OQPSK1000: regval = TRX_OQPSK1000; break;
+        default: break;
+    }
+    if (regval != TRX_NONE)
+    {
+        trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
+        regval |=  trx_reg_read(RG_TRX_CTRL_2) & 0xf0 ;
+        trx_reg_write(RG_TRX_CTRL_2, regval);
+
+    }
+    else
+    {
+        rate_type = TRX_NONE;
+    }
+    return rate_type;
+}
+
+uint8_t cMxRadio::trx_get_datarate(void)
+{
+	uint8_t rate_type, rate_code;
+#ifdef CHINABAND
+	rate_code = trx_reg_read(RG_TRX_CTRL_2) & 0x1f;
+#else
+	rate_code = trx_reg_read(RG_TRX_CTRL_2) & 0x0f;
+#endif
+	switch(rate_code)
+    {
+        case TRX_BPSK20: rate_type = BPSK20; break;
+        case TRX_BPSK40: rate_type = BPSK40; break;
+        case TRX_OQPSK100: rate_type = OQPSK100; break;
+        case TRX_OQPSK200: rate_type = OQPSK200; break;
+        case TRX_OQPSK250: rate_type = OQPSK250; break;
+        case TRX_OQPSK400: /* fall through */
+        case TRX_OQPSK400_1: rate_type = OQPSK400; break;
+        case TRX_OQPSK500: rate_type = OQPSK500; break;
+        case TRX_OQPSK1000: /* fall through */
+        case TRX_OQPSK1000_1: rate_type = OQPSK1000; break;
+        default: rate_type = RATE_NONE; break;
+    }
+    return rate_type;
+}
+
+#elif RADIO_TYPE == RADIO_AT86RF231
+
+uint8_t cMxRadio::trx_set_datarate(uint8_t rate_type)
+{
+trx_regval_t regval = TRX_NONE;
+
+    switch(rate_type)
+    {
+        case OQPSK250: regval = TRX_OQPSK250; break;
+        case OQPSK500: regval = TRX_OQPSK500; break;
+        case OQPSK1000: regval = TRX_OQPSK1000; break;
+        case OQPSK2000: regval = TRX_OQPSK2000; break;
+        default: break;
+    }
+    if (regval != TRX_NONE)
+    {
+        trx_reg_write(RG_TRX_STATE, CMD_FORCE_TRX_OFF);
+        regval |=  trx_reg_read(RG_TRX_CTRL_2) & 0xfc ;
+        trx_reg_write(RG_TRX_CTRL_2, regval);
+    }
+    else
+    {
+        rate_type = TRX_NONE;
+    }
+    return rate_type;
+}
+
+uint8_t cMxRadio::trx_get_datarate(void)
+{
+uint8_t rate_type, rate_code;
+
+    rate_code = trx_reg_read(RG_TRX_CTRL_2) & 0x03;
+
+    switch(rate_code)
+    {
+        case TRX_OQPSK250: rate_type = OQPSK250; break;
+        case TRX_OQPSK500: rate_type = OQPSK500; break;
+        case TRX_OQPSK1000: rate_type = OQPSK1000; break;
+        case TRX_OQPSK2000: rate_type = OQPSK2000; break;
+        default: rate_type = RATE_NONE; break;
+    }
+    return rate_type;
+}
+
+#else
+
+uint8_t cMxRadio::trx_set_datarate(uint8_t rate_type)
+{
+
+    if(rate_type != OQPSK250)
+    {
+        rate_type = TRX_NONE;
+    }
+    return rate_type;
+}
+
+uint8_t cMxRadio::trx_get_datarate(void)
+{
+    return OQPSK250;
+}
+
+
+#endif /* RADIO_TYPE == AT86RF212 */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,129 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+ * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+ * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * ===========================================================================
+ * This file contains refactored code from hif_rf230.c,
+ * which is part of Atmels software package "IEEE 802.15.4 MAC for AVR Z-Link"
+ * ===========================================================================
+ */
+/*
+ * Copyright (c) 2006, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief Implementation of the host interface for the AT86RF230
+ *
+ * Hardware interface implementation for radio-dependant functions of
+ * the AT86RF230 radio chip.
+ *
+ */
+
+/* === Includes ============================================================ */
+#include <MxRadio.h>
+
+
+/* === external functions =================================================== */
+void cMxRadio::trx_io_init (int spirate)
+{
+	m_cs = 1;
+	m_spi.format(8, 0);
+	m_spi.frequency(spirate);
+	irq_pin.rise(this,&cMxRadio::rf_irq_callback);
+
+	/* set the SLPTR and RESET
+	TRX_RESET_INIT();
+	TRX_SLPTR_INIT();
+	SPI_INIT(spirate);
+	TRX_IRQ_INIT();
+	EI_TRX_IRQ();
+	*/
+}
+
+void cMxRadio::trx_reg_write(uint8_t addr, trx_regval_t val)
+{
+
+	addr = TRX_CMD_RW | (TRX_CMD_RADDR_MASK & addr);
+
+	m_cs = 0;//SPI_SELN_LOW();
+	m_spi.write(addr);//SPI_DATA_REG = addr;
+	//SPI_WAITFOR();
+	m_spi.write(val);//SPI_DATA_REG = val;
+	//SPI_WAITFOR();
+	m_cs = 1;//SPI_SELN_HIGH();
+}
+
+trx_regval_t cMxRadio::trx_reg_read(uint8_t addr)
+{
+
+	uint8_t val;
+
+	addr=TRX_CMD_RR | (TRX_CMD_RADDR_MASK & addr);
+
+	// Select transceiver
+	m_cs = 0;//SPI_SELN_LOW();
+
+	m_spi.write(addr);//SPI_DATA_REG = addr;
+	//SPI_WAITFOR();
+	val=m_spi.write(addr);//SPI_DATA_REG = addr;        /* dummy out */
+	//SPI_WAITFOR();
+	//val = SPI_DATA_REG;
+
+	m_cs=1;//SPI_SELN_HIGH();
+
+	return (trx_regval_t)val;
+}
+
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_bitrd.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_bitrd.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,90 @@
+/* Copyright (c) 2008 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * ===========================================================================
+ * This file contains refactored code from hif_rf230.c,
+ * which is part of Atmels software package "IEEE 802.15.4 MAC for AVR Z-Link"
+ * ===========================================================================
+ */
+/*
+ * Copyright (c) 2006, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* $Id$ */
+/**
+ * @file
+ * @brief ....
+ * @addtogroup grpApp...
+ */
+
+
+/* === includes ========================================== */
+
+
+
+#include <MxRadio.h>
+
+
+/* === functions ========================================= */
+trx_regval_t cMxRadio::trx_bit_read(uint8_t addr, trx_regval_t mask, uint8_t pos)
+{
+trx_regval_t data;
+    data = trx_reg_read(addr);
+    data &= mask;
+    data >>= pos;
+    return data;
+}
+
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_bitwr.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_bitwr.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,91 @@
+/* Copyright (c) 2008 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * ===========================================================================
+ * This file contains refactored code from hif_rf230.c,
+ * which is part of Atmels software package "IEEE 802.15.4 MAC for AVR Z-Link"
+ * ===========================================================================
+ */
+/*
+ * Copyright (c) 2006, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* $Id$ */
+/**
+ * @file
+ * @brief ....
+ * @addtogroup grpApp...
+ */
+
+
+/* === includes ========================================== */
+
+#include <MxRadio.h>
+
+/* === functions ========================================= */
+void cMxRadio::trx_bit_write(uint8_t addr, trx_regval_t mask, uint8_t pos, trx_regval_t value)
+{
+
+trx_regval_t tmp;
+    tmp = trx_reg_read(addr);
+    tmp &= ~mask;
+    value <<= pos;
+    value &=mask;
+    value |= tmp;
+    trx_reg_write(addr, value);
+    return;
+}
+
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_frame.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_frame.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,145 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * ===========================================================================
+ * This file contains refactored code from hif_rf230.c,
+ * which is part of Atmels software package "IEEE 802.15.4 MAC for AVR Z-Link"
+ * ===========================================================================
+ */
+/*
+ * Copyright (c) 2006, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* $Id$ */
+/**
+ * @file
+ * @brief ....
+ * @addtogroup grpApp...
+ */
+
+
+/* === includes ========================================== */
+
+#include <MxRadio.h>
+
+/* === functions ========================================= */
+
+void cMxRadio::trx_frame_write(uint8_t length, uint8_t *data)
+{
+
+    // Select transceiver
+    m_cs=0;//SPI_SELN_LOW();
+
+    m_spi.write(TRX_CMD_FW);//SPI_DATA_REG = TRX_CMD_FW;
+    //SPI_WAITFOR();
+    m_spi.write(length);//SPI_DATA_REG = length;
+
+    do
+    {
+        //SPI_WAITFOR();
+    	m_spi.write(*data++);//SPI_DATA_REG = *data++;
+    }
+    while (--length > 0);
+
+    //SPI_WAITFOR(); /* wait here until last byte is out otherwise underrun irq */
+
+    // Deselect Slave
+    m_cs=1;//SPI_SELN_HIGH();
+}
+
+uint8_t cMxRadio::trx_frame_read(uint8_t *data, uint8_t datasz, uint8_t *lqi)
+{
+    uint8_t length = 0;
+    uint8_t i;
+
+    /* Select transceiver */
+    m_cs=0;//SPI_SELN_LOW();
+
+    /* start frame read */
+    m_spi.write(TRX_CMD_FR);//SPI_DATA_REG = TRX_CMD_FR;
+    //SPI_WAITFOR();
+
+    /* read length */
+    length= m_spi.write(0);//SPI_DATA_REG = 0;
+    //SPI_WAITFOR();
+    //length = SPI_DATA_REG;
+
+    if (length <= datasz)
+    {
+        i = length;
+        do
+        {
+            //SPI_DATA_REG = 0;   /* dummy out */
+            //SPI_WAITFOR();
+            *data++ = m_spi.write(0);//SPI_DATA_REG;
+        }
+        while(--i);
+
+        if (lqi!= NULL)
+        {
+            //SPI_DATA_REG = 0;   /* dummy out */
+            //SPI_WAITFOR();
+            *lqi = m_spi.write(0);//SPI_DATA_REG;
+        }
+    }
+    else
+    {
+        /* we drop the frame */
+        length = 0x80 | length;
+    }
+    m_cs=1;//SPI_SELN_HIGH();
+    return length;
+}
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_irq.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_irq.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,60 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* === Includes ============================================================ */
+#include <MxRadio.h>
+
+
+/* === globals ============================================================= */
+
+void cMxRadio::rf_irq_callback()
+{
+
+uint8_t cause;
+    //DI_TRX_IRQ();
+    //sei();
+    cause = trx_reg_read(RG_IRQ_STATUS);
+
+    if (cause & TRX_IRQ_RX_START)
+    {
+    	temprssi = trx_reg_read(RG_PHY_RSSI);
+    	//temped = trx_reg_read(RG_PHY_ED_LEVEL);
+    }
+
+    if (cause & TRX_IRQ_TRX_END)
+    {
+    	if (temprssi==0)
+    		temprssi = trx_reg_read(RG_PHY_RSSI);
+    	//temped = trx_reg_read(RG_PHY_ED_LEVEL);
+    }
+    radio_irq_handler(cause);
+    //cli();
+    //EI_TRX_IRQ();
+}
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_misc.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_misc.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,95 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * ===========================================================================
+ * This file contains refactored code from hif_rf230.c,
+ * which is part of Atmels software package "IEEE 802.15.4 MAC for AVR Z-Link"
+ * ===========================================================================
+ */
+/*
+ * Copyright (c) 2006, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* $Id$ */
+/**
+ * @file
+ * @brief ....
+ * @addtogroup grpApp...
+ */
+
+/* === includes ============================================================ */
+#include <MxRadio.h>
+
+/* === functions =========================================================== */
+uint8_t cMxRadio::trx_frame_get_length(void)
+{
+uint8_t length = 0;
+
+    /* Select transceiver */
+    m_cs=0;//SPI_SELN_LOW();
+
+    /* start frame read */
+    m_spi.write(TRX_CMD_FR);//SPI_DATA_REG = TRX_CMD_FR;
+    //SPI_WAITFOR();
+
+    /* read length */
+    //SPI_DATA_REG = 0;
+    //SPI_WAITFOR();
+    length =  m_spi.write(0);//SPI_DATA_REG;
+
+    m_cs=1;//SPI_SELN_HIGH();
+    return length;
+}
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_param.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_param.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,77 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief ....
+ * @_addtogroup grpApp...
+ */
+
+
+/* === includes ============================================================ */
+#include <MxRadio.h>
+
+void cMxRadio::trx_parms_get(trx_param_t *p)
+{
+#ifdef CHINABAND
+	p->chan = (trx_bit_read(SR_CC_NUMBER)-11)/2;
+#else
+	p->chan = trx_bit_read(SR_CHANNEL);
+#endif
+    p->txp  = trx_bit_read(SR_TX_PWR);
+    p->cca  = trx_bit_read(SR_CCA_MODE);
+    p->clkm = trx_bit_read(SR_CLKM_CTRL);    
+}
+
+uint8_t cMxRadio::trx_parms_set(trx_param_t *p)
+{
+uint8_t ret;
+
+    ret = 1;
+#ifdef CHINABAND
+    trx_reg_write(RG_CC_CTRL_1, CCBAND);
+    trx_reg_write(RG_CC_CTRL_0, 11+p->chan*2);
+
+#else
+    trx_bit_write(SR_CHANNEL, p->chan);
+#endif
+    trx_bit_write(SR_TX_PWR, p->txp);
+    trx_bit_write(SR_CCA_MODE, p->cca);
+
+    #ifdef CLKM_CHANGE_SAVE
+    # error "not yet implemented"
+    #else
+        trx_bit_write(SR_CLKM_CTRL, p->clkm);
+    #endif
+    ret = 0;
+
+    return ret;
+}
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/MxRadio_trx_rf230_sram.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/MxRadio_trx_rf230_sram.cpp	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,123 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * ===========================================================================
+ * This file is a copy of the file hif_rf230.c, which is part of
+ * Atmels software package "IEEE 802.15.4 MAC for AVR Z-Link"
+ * ===========================================================================
+ */
+/*
+ * Copyright (c) 2006, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* $Id$ */
+/**
+ * @file
+ * @brief SRAM access functionds for AT86RF230.
+ *
+ * This functions are moved to this module, in order to
+ * make librf230 more scaleable.
+ *
+ *
+ */
+
+
+/* === Includes ============================================================ */
+#include <MxRadio.h>
+
+void cMxRadio::trx_sram_write(trx_ramaddr_t addr, uint8_t length, uint8_t *data)
+{
+
+    // Select transceiver
+    m_cs=0;//SPI_SELN_LOW();
+
+    m_spi.write(TRX_CMD_SW);//SPI_DATA_REG = TRX_CMD_SW;
+    //SPI_WAITFOR();
+    m_spi.write(addr);//SPI_DATA_REG = addr;
+    //SPI_WAITFOR();
+    do
+    {
+    	 m_spi.write(*data++);//SPI_DATA_REG = *data++;
+        //SPI_WAITFOR();
+    }
+    while (--length > 0);
+
+    // Deselect Slave
+    m_cs=1;//SPI_SELN_HIGH();
+}
+
+
+void cMxRadio::trx_sram_read(trx_ramaddr_t addr, uint8_t length, uint8_t *data)
+{
+
+    // Select transceiver
+	m_cs=0;//SPI_SELN_LOW();
+
+	m_spi.write(TRX_CMD_SR);//SPI_DATA_REG = TRX_CMD_SR;
+    //SPI_WAITFOR();
+	 m_spi.write(addr);//SPI_DATA_REG = addr;
+    //SPI_WAITFOR();
+    do
+    {
+        //SPI_DATA_REG = 0;   /* dummy out */
+        //SPI_WAITFOR();
+        *data++ = m_spi.write(0);//SPI_DATA_REG;
+    }
+    while (--length > 0);
+
+    // Deselect Slave
+    m_cs=1;//SPI_SELN_HIGH();
+}
+
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/at86rf212.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/at86rf212.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,563 @@
+/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf212.txt */
+
+/* Copyright (c) 2008 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief AT86RF212 - 700/868/900MHz IEEE 802.15.4-2006-Transceiver.
+ */
+#ifndef AT86RF212_H
+#define AT86RF212_H (1)
+#include <stdint.h>
+#define _BV(bit) (1 << (bit))
+/* === Includes ============================================================== */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+typedef uint8_t trx_ramaddr_t;
+typedef uint8_t trx_regval_t;
+typedef uint8_t trx_regaddr_t;
+
+/* === Macros ================================================================ */
+/** Offset for register TRX_STATUS */
+#define RG_TRX_STATUS (0x1)
+  /** Access parameters for sub-register CCA_DONE in register TRX_STATUS */
+  #define SR_CCA_DONE 0x1,0x80,7
+  /** Access parameters for sub-register CCA_STATUS in register TRX_STATUS */
+  #define SR_CCA_STATUS 0x1,0x40,6
+  /** Access parameters for sub-register TRX_STATUS in register TRX_STATUS */
+  #define SR_TRX_STATUS 0x1,0x1f,0
+//for rfa1 or rfr2 with rf212
+#undef P_ON
+#undef BUSY_RX
+#undef BUSY_TX
+#undef RX_ON
+#undef TRX_OFF
+#undef PLL_ON
+#undef TRX_SLEEP
+#undef BUSY_RX_AACK
+#undef BUSY_TX_ARET
+#undef RX_AACK_ON
+#undef TX_ARET_ON
+#undef RX_ON_NOCLK
+#undef RX_AACK_ON_NOCLK
+#undef BUSY_RX_AACK_NOCLK
+
+#define P_ON (0)
+#define BUSY_RX (1)
+#define BUSY_TX (2)
+#define RX_ON (6)
+#define TRX_OFF (8)
+#define PLL_ON (9)
+#define TRX_SLEEP (15)
+#define BUSY_RX_AACK (17)
+#define BUSY_TX_ARET (18)
+#define RX_AACK_ON (22)
+#define TX_ARET_ON (25)
+#define RX_ON_NOCLK (28)
+#define RX_AACK_ON_NOCLK (29)
+#define BUSY_RX_AACK_NOCLK (30)
+/** Offset for register TRX_STATE */
+#define RG_TRX_STATE (0x2)
+  /** Access parameters for sub-register TRAC_STATUS in register TRX_STATE */
+  #define SR_TRAC_STATUS 0x2,0xe0,5
+
+#undef TRAC_SUCCESS
+#undef TRAC_SUCCESS_DATA_PENDING
+#undef TRAC_SUCCESS_WAIT_FOR_ACK
+#undef TRAC_CHANNEL_ACCESS_FAILURE
+#undef TRAC_NO_ACK
+#undef TRAC_INVALID
+
+#define TRAC_SUCCESS (0)
+#define TRAC_SUCCESS_DATA_PENDING (1)
+#define TRAC_SUCCESS_WAIT_FOR_ACK (2)
+#define TRAC_CHANNEL_ACCESS_FAILURE (3)
+#define TRAC_NO_ACK (5)
+#define TRAC_INVALID (7)
+/** Access parameters for sub-register TRX_CMD in register TRX_STATE */
+#define SR_TRX_CMD 0x2,0x1f,0
+
+#undef CMD_NOP
+#undef CMD_TX_START
+#undef CMD_FORCE_TRX_OFF
+#undef CMD_RX_ON
+#undef CMD_TRX_OFF
+#undef CMD_PLL_ON
+#undef CMD_RX_AACK_ON
+#undef CMD_TX_ARET_ON
+
+#define CMD_NOP (0)
+#define CMD_TX_START (2)
+#define CMD_FORCE_TRX_OFF (3)
+#define CMD_RX_ON (6)
+#define CMD_TRX_OFF (8)
+#define CMD_PLL_ON (9)
+#define CMD_RX_AACK_ON (22)
+#define CMD_TX_ARET_ON (25)
+/** Offset for register TRX_CTRL_0 */
+#define RG_TRX_CTRL_0 (0x3)
+  /** Access parameters for sub-register PAD_IO in register TRX_CTRL_0 */
+  #define SR_PAD_IO 0x3,0xc0,6
+  /** Access parameters for sub-register PAD_IO_CLKM in register TRX_CTRL_0 */
+  #define SR_PAD_IO_CLKM 0x3,0x30,4
+    #define CLKM_2mA (0)
+    #define CLKM_4mA (1)
+    #define CLKM_6mA (2)
+    #define CLKM_8mA (3)
+  /** Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0 */
+  #define SR_CLKM_SHA_SEL 0x3,0x8,3
+  /** Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0 */
+  #define SR_CLKM_CTRL 0x3,0x7,0
+    #define CLKM_no_clock (0)
+    #define CLKM_1MHz (1)
+    #define CLKM_2MHz (2)
+    #define CLKM_4MHz (3)
+    #define CLKM_8MHz (4)
+    #define CLKM_16MHz (5)
+/** Offset for register TRX_CTRL_1 */
+#define RG_TRX_CTRL_1 (0x4)
+  /** Access parameters for sub-register PA_EXT_EN in register TRX_CTRL_1 */
+  #define SR_PA_EXT_EN 0x4,0x80,7
+  /** Access parameters for sub-register IRQ_2_EXT_EN in register TRX_CTRL_1 */
+  #define SR_IRQ_2_EXT_EN 0x4,0x40,6
+  /** Access parameters for sub-register TX_AUTO_CRC_ON in register TRX_CTRL_1 */
+  #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
+  /** Access parameters for sub-register RX_BL_CTRL in register TRX_CTRL_1 */
+  #define SR_RX_BL_CTRL 0x4,0x10,4
+  /** Access parameters for sub-register SPI_CMD_MODE in register TRX_CTRL_1 */
+  #define SR_SPI_CMD_MODE 0x4,0xc,2
+  /** Access parameters for sub-register IRQ_POLARITY in register TRX_CTRL_1 */
+  #define SR_IRQ_POLARITY 0x4,0x1,0
+  /** Access parameters for sub-register IRQ_MASK_MODE in register TRX_CTRL_1 */
+  #define SR_IRQ_MASK_MODE 0x4,0x2,1
+/** Offset for register PHY_TX_PWR */
+#define RG_PHY_TX_PWR (0x5)
+  /** Access parameters for sub-register PA_BOOST in register PHY_TX_PWR */
+  #define SR_PA_BOOST 0x5,0x80,7
+  /** Access parameters for sub-register GC_PA in register PHY_TX_PWR */
+  #define SR_GC_PA 0x5,0x60,5
+  /** Access parameters for sub-register TX_PWR in register PHY_TX_PWR */
+  #define SR_TX_PWR 0x5,0xff,0
+/** Offset for register PHY_RSSI */
+#define RG_PHY_RSSI (0x6)
+  /** Access parameters for sub-register RX_CRC_VALID in register PHY_RSSI */
+  #define SR_RX_CRC_VALID 0x6,0x80,7
+  /** Access parameters for sub-register RND_VALUE in register PHY_RSSI */
+  #define SR_RND_VALUE 0x6,0x60,5
+  /** Access parameters for sub-register RSSI in register PHY_RSSI */
+  #define SR_RSSI 0x6,0x1f,0
+/** Offset for register PHY_ED_LEVEL */
+#define RG_PHY_ED_LEVEL (0x7)
+  /** Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL */
+  #define SR_ED_LEVEL 0x7,0xff,0
+/** Offset for register PHY_CC_CCA */
+#define RG_PHY_CC_CCA (0x8)
+  /** Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA */
+  #define SR_CCA_REQUEST 0x8,0x80,7
+  /** Access parameters for sub-register CCA_MODE in register PHY_CC_CCA */
+  #define SR_CCA_MODE 0x8,0x60,5
+  /** Access parameters for sub-register CHANNEL in register PHY_CC_CCA */
+  #define SR_CHANNEL 0x8,0x1f,0
+/** Offset for register CCA_THRES */
+#define RG_CCA_THRES (0x9)
+  /** Access parameters for sub-register CCA_ED_THRES in register CCA_THRES */
+  #define SR_CCA_ED_THRES 0x9,0xf,0
+/** Offset for register SFD_VALUE */
+#define RG_SFD_VALUE (0xb)
+  /** Access parameters for sub-register SFD_VALUE in register SFD_VALUE */
+  #define SR_SFD_VALUE 0xb,0xff,0
+/** Offset for register TRX_CTRL_2 */
+#define RG_TRX_CTRL_2 (0xc)
+  /** Access parameters for sub-register RX_SAFE_MODE in register TRX_CTRL_2 */
+  #define SR_RX_SAFE_MODE 0xc,0x80,7
+  /** Access parameters for sub-register TRX_OFF_AVDD_EN in register TRX_CTRL_2 */
+  #define SR_TRX_OFF_AVDD_EN 0xc,0x40,6
+/** Access parameters for sub-register TRX_SUB1_RC_EN in register TRX_CTRL_2 */
+  #define SR_OQPSK_SUB1_RC_EN 0xc,0x10,4
+  /** Access parameters for sub-register BPSK_OQPSK in register TRX_CTRL_2 */
+  #define SR_BPSK_OQPSK 0xc,0x8,3
+  /** Access parameters for sub-register SUB_MODE in register TRX_CTRL_2 */
+  #define SR_SUB_MODE 0xc,0x4,2
+  /** Access parameters for sub-register OQPSK_DATA_RATE in register TRX_CTRL_2 */
+  #define SR_OQPSK_DATA_RATE 0xc,0x3,0
+/** Offset for register ANT_DIV */
+#define RG_ANT_DIV (0xd)
+  /** Access parameters for sub-register ANT_SEL in register ANT_DIV */
+  #define SR_ANT_SEL 0xd,0x80,7
+  /** Access parameters for sub-register ANT_EXT_SW_EN in register ANT_DIV */
+  #define SR_ANT_EXT_SW_EN 0xd,0x4,2
+  /** Access parameters for sub-register ANT_CTRL in register ANT_DIV */
+  #define SR_ANT_CTRL 0xd,0x3,0
+/** Offset for register IRQ_MASK */
+#define RG_IRQ_MASK (0xe)
+  /** Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK */
+  #define SR_MASK_BAT_LOW 0xe,0x80,7
+  /** Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK */
+  #define SR_MASK_TRX_UR 0xe,0x40,6
+  /** Access parameters for sub-register MASK_AMI in register IRQ_MASK */
+  #define SR_MASK_AMI 0xe,0x20,5
+  /** Access parameters for sub-register MASK_CCA_ED_READY in register IRQ_MASK */
+  #define SR_MASK_CCA_ED_READY 0xe,0x10,4
+  /** Access parameters for sub-register MASK_TRX_END in register IRQ_MASK */
+  #define SR_MASK_TRX_END 0xe,0x8,3
+  /** Access parameters for sub-register MASK_RX_START in register IRQ_MASK */
+  #define SR_MASK_RX_START 0xe,0x4,2
+  /** Access parameters for sub-register MASK_PLL_LOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_LOCK 0xe,0x1,0
+  /** Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
+/** Offset for register IRQ_STATUS */
+#define RG_IRQ_STATUS (0xf)
+  /** Access parameters for sub-register BAT_LOW in register IRQ_STATUS */
+  #define SR_BAT_LOW 0xf,0x80,7
+  /** Access parameters for sub-register TRX_UR in register IRQ_STATUS */
+  #define SR_TRX_UR 0xf,0x40,6
+  /** Access parameters for sub-register AMI in register IRQ_STATUS */
+  #define SR_AMI 0xf,0x20,5
+  /** Access parameters for sub-register CCA_ED_READY in register IRQ_STATUS */
+  #define SR_CCA_ED_READY 0xf,0x10,4
+  /** Access parameters for sub-register TRX_END in register IRQ_STATUS */
+  #define SR_TRX_END 0xf,0x8,3
+  /** Access parameters for sub-register RX_START in register IRQ_STATUS */
+  #define SR_RX_START 0xf,0x4,2
+  /** Access parameters for sub-register PLL_LOCK in register IRQ_STATUS */
+  #define SR_PLL_LOCK 0xf,0x1,0
+  /** Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS */
+  #define SR_PLL_UNLOCK 0xf,0x2,1
+/** Offset for register VREG_CTRL */
+#define RG_VREG_CTRL (0x10)
+  /** Access parameters for sub-register AVREG_EXT in register VREG_CTRL */
+  #define SR_AVREG_EXT 0x10,0x80,7
+  /** Access parameters for sub-register AVDD_OK in register VREG_CTRL */
+  #define SR_AVDD_OK 0x10,0x40,6
+  /** Access parameters for sub-register DVREG_EXT in register VREG_CTRL */
+  #define SR_DVREG_EXT 0x10,0x8,3
+  /** Access parameters for sub-register DVDD_OK in register VREG_CTRL */
+  #define SR_DVDD_OK 0x10,0x4,2
+/** Offset for register BATMON */
+#define RG_BATMON (0x11)
+  /** Access parameters for sub-register BATMON_OK in register BATMON */
+  #define SR_BATMON_OK 0x11,0x20,5
+  /** Access parameters for sub-register BATMON_HR in register BATMON */
+  #define SR_BATMON_HR 0x11,0x10,4
+  /** Access parameters for sub-register BATMON_VTH in register BATMON */
+  #define SR_BATMON_VTH 0x11,0xf,0
+/** Offset for register XOSC_CTRL */
+#define RG_XOSC_CTRL (0x12)
+  /** Access parameters for sub-register XTAL_MODE in register XOSC_CTRL */
+  #define SR_XTAL_MODE 0x12,0xf0,4
+  /** Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL */
+  #define SR_XTAL_TRIM 0x12,0xf,0
+/** Offset for register CC_CTRL_0 */
+#define RG_CC_CTRL_0 (0x13)
+  /** Access parameters for sub-register CC_NUMBER in register CC_CTRL_0 */
+  #define SR_CC_NUMBER 0x13,0xff,0
+/** Offset for register CC_CTRL_1 */
+#define RG_CC_CTRL_1 (0x14)
+  /** Access parameters for sub-register CC_BAND in register CC_CTRL_1 */
+  #define SR_CC_BAND 0x14,0x4,2
+  /** Access parameters for sub-register BAND in register CC_CTRL_1 */
+  #define SR_BAND 0x14,0x1,0
+  /** Access parameters for sub-register CC_ in register CC_CTRL_1 */
+  #define SR_CC_ 0x14,0x2,1
+/** Offset for register RX_SYN */
+#define RG_RX_SYN (0x15)
+  /** Access parameters for sub-register RX_PDT_DIS in register RX_SYN */
+  #define SR_RX_PDT_DIS 0x15,0x80,7
+  /** Access parameters for sub-register RX_PDT_LEVEL in register RX_SYN */
+  #define SR_RX_PDT_LEVEL 0x15,0xf,0
+/** Offset for register RF_CTRL_0 */
+#define RG_RF_CTRL_0 (0x16)
+  /** Access parameters for sub-register PA_LT in register RF_CTRL_0 */
+  #define SR_PA_LT 0x16,0xc0,6
+  /** Access parameters for sub-register GC_TX_OFFS in register RF_CTRL_0 */
+  #define SR_GC_TX_OFFS 0x16,0x3,0
+/** Offset for register XAH_CTRL_1 */
+#define RG_XAH_CTRL_1 (0x17)
+  /** Access parameters for sub-register CSMA_LBT_MODE in register XAH_CTRL_1 */
+  #define SR_CSMA_LBT_MODE 0x17,0x80,7
+  /** Access parameters for sub-register AACK_FLTR_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
+  /** Access parameters for sub-register AACK_UPLD_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
+  /** Access parameters for sub-register AACK_ACK_TIME in register XAH_CTRL_1 */
+  #define SR_AACK_ACK_TIME 0x17,0x4,2
+  /** Access parameters for sub-register AACK_PROM_MODE in register XAH_CTRL_1 */
+  #define SR_AACK_PROM_MODE 0x17,0x2,1
+/** Offset for register FTN_CTRL */
+#define RG_FTN_CTRL (0x18)
+  /** Access parameters for sub-register FTN_START in register FTN_CTRL */
+  #define SR_FTN_START 0x18,0x80,7
+/** Offset for register RF_CTRL_1 */
+#define RG_RF_CTRL_1 (0x19)
+  /** Access parameters for sub-register RF_MC in register RF_CTRL_1 */
+  #define SR_RF_MC 0x19,0xf0,4
+/** Offset for register PLL_CF */
+#define RG_PLL_CF (0x1a)
+  /** Access parameters for sub-register PLL_CF_START in register PLL_CF */
+  #define SR_PLL_CF_START 0x1a,0x80,7
+/** Offset for register PLL_DCU */
+#define RG_PLL_DCU (0x1b)
+  /** Access parameters for sub-register PLL_DCU_START in register PLL_DCU */
+  #define SR_PLL_DCU_START 0x1b,0x80,7
+/** Offset for register PART_NUM */
+#define RG_PART_NUM (0x1c)
+  /** Access parameters for sub-register PART_NUM in register PART_NUM */
+  #define SR_PART_NUM 0x1c,0xff,0
+    #define RF212A_PART_NUM (7)
+/** Offset for register VERSION_NUM */
+#define RG_VERSION_NUM (0x1d)
+  /** Access parameters for sub-register VERSION_NUM in register VERSION_NUM */
+  #define SR_VERSION_NUM 0x1d,0xff,0
+    #define RF212A_VERSION_NUM (1)
+/** Offset for register MAN_ID_0 */
+#define RG_MAN_ID_0 (0x1e)
+  /** Access parameters for sub-register MAN_ID_0 in register MAN_ID_0 */
+  #define SR_MAN_ID_0 0x1e,0xff,0
+/** Offset for register MAN_ID_1 */
+#define RG_MAN_ID_1 (0x1f)
+  /** Access parameters for sub-register MAN_ID_1 in register MAN_ID_1 */
+  #define SR_MAN_ID_1 0x1f,0xff,0
+/** Offset for register SHORT_ADDR_0 */
+#define RG_SHORT_ADDR_0 (0x20)
+  /** Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0 */
+  #define SR_SHORT_ADDR_0 0x20,0xff,0
+/** Offset for register SHORT_ADDR_1 */
+#define RG_SHORT_ADDR_1 (0x21)
+  /** Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1 */
+  #define SR_SHORT_ADDR_1 0x21,0xff,0
+/** Offset for register PAN_ID_0 */
+#define RG_PAN_ID_0 (0x22)
+  /** Access parameters for sub-register PAN_ID_0 in register PAN_ID_0 */
+  #define SR_PAN_ID_0 0x22,0xff,0
+/** Offset for register PAN_ID_1 */
+#define RG_PAN_ID_1 (0x23)
+  /** Access parameters for sub-register PAN_ID_1 in register PAN_ID_1 */
+  #define SR_PAN_ID_1 0x23,0xff,0
+/** Offset for register IEEE_ADDR_0 */
+#define RG_IEEE_ADDR_0 (0x24)
+  /** Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0 */
+  #define SR_IEEE_ADDR_0 0x24,0xff,0
+/** Offset for register IEEE_ADDR_1 */
+#define RG_IEEE_ADDR_1 (0x25)
+  /** Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1 */
+  #define SR_IEEE_ADDR_1 0x25,0xff,0
+/** Offset for register IEEE_ADDR_2 */
+#define RG_IEEE_ADDR_2 (0x26)
+  /** Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2 */
+  #define SR_IEEE_ADDR_2 0x26,0xff,0
+/** Offset for register IEEE_ADDR_3 */
+#define RG_IEEE_ADDR_3 (0x27)
+  /** Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3 */
+  #define SR_IEEE_ADDR_3 0x27,0xff,0
+/** Offset for register IEEE_ADDR_4 */
+#define RG_IEEE_ADDR_4 (0x28)
+  /** Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4 */
+  #define SR_IEEE_ADDR_4 0x28,0xff,0
+/** Offset for register IEEE_ADDR_5 */
+#define RG_IEEE_ADDR_5 (0x29)
+  /** Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5 */
+  #define SR_IEEE_ADDR_5 0x29,0xff,0
+/** Offset for register IEEE_ADDR_6 */
+#define RG_IEEE_ADDR_6 (0x2a)
+  /** Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6 */
+  #define SR_IEEE_ADDR_6 0x2a,0xff,0
+/** Offset for register IEEE_ADDR_7 */
+#define RG_IEEE_ADDR_7 (0x2b)
+  /** Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7 */
+  #define SR_IEEE_ADDR_7 0x2b,0xff,0
+/** Offset for register XAH_CTRL_0 */
+#define RG_XAH_CTRL_0 (0x2c)
+  /** Access parameters for sub-register MAX_FRAME_RETRIES in register XAH_CTRL_0 */
+  #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
+  /** Access parameters for sub-register SLOTTED_OPERATION in register XAH_CTRL_0 */
+  #define SR_SLOTTED_OPERATION 0x2c,0x1,0
+  /** Access parameters for sub-register MAX_CSMA_RETRIES in register XAH_CTRL_0 */
+  #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
+/** Offset for register CSMA_SEED_0 */
+#define RG_CSMA_SEED_0 (0x2d)
+  /** Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0 */
+  #define SR_CSMA_SEED_0 0x2d,0xff,0
+/** Offset for register CSMA_SEED_1 */
+#define RG_CSMA_SEED_1 (0x2e)
+  /** Access parameters for sub-register AACK_FVN_MODE in register CSMA_SEED_1 */
+  #define SR_AACK_FVN_MODE 0x2e,0xc0,6
+  /** Access parameters for sub-register AACK_SET_PD in register CSMA_SEED_1 */
+  #define SR_AACK_SET_PD 0x2e,0x20,5
+  /** Access parameters for sub-register AACK_DIS_ACK in register CSMA_SEED_1 */
+  #define SR_AACK_DIS_ACK 0x2e,0x10,4
+  /** Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1 */
+  #define SR_AACK_I_AM_COORD 0x2e,0x8,3
+  /** Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1 */
+  #define SR_CSMA_SEED_1 0x2e,0x7,0
+/** Offset for register CSMA_BE */
+#define RG_CSMA_BE (0x2f)
+  /** Access parameters for sub-register MAX_BE in register CSMA_BE */
+  #define SR_MAX_BE 0x2f,0xf0,4
+  /** Access parameters for sub-register MIN_BE in register CSMA_BE */
+  #define SR_MIN_BE 0x2f,0xf,0
+/** name string of the radio */
+#define RADIO_NAME "AT86RF212"
+/** contents of the RG_PART_NUM register */
+#define RADIO_PART_NUM (RF212A_PART_NUM)
+/** contents of the RG_VERSION_NUM register */
+#define RADIO_VERSION_NUM (RF212A_VERSION_NUM)
+
+/** SPI command code for register write */
+#define TRX_CMD_RW           (_BV(7) | _BV(6))
+/** SPI command code for register read */
+#define TRX_CMD_RR           (_BV(7))
+/** SPI command code for frame write */
+#define TRX_CMD_FW           (_BV(6) | _BV(5))
+/** SPI command code for frame read */
+#define TRX_CMD_FR           (_BV(5))
+/** SPI command code for sram write */
+#define TRX_CMD_SW           (_BV(6))
+/** SPI command code for sram read */
+#define TRX_CMD_SR           (0)
+
+#define TRX_CMD_RADDR_MASK   (0x3f)
+
+/** duration while reset=low is asserted */
+#define TRX_RESET_TIME_US    (6)
+
+/** duration transceiver reaches TRX_OFF for the first time */
+#define TRX_INIT_TIME_US     (510)
+
+/** maximum duration, which PLL needs to lock */
+#define TRX_PLL_LOCK_TIME_US     (180)
+
+
+/** duration of a CCA measurement */
+#define TRX_CCA_TIME_US     (140)
+
+/** Mask for PLL lock interrupt */
+#define TRX_IRQ_PLL_LOCK   _BV(0)
+
+/** Mask for PLL unlock interrupt */
+#define TRX_IRQ_PLL_UNLOCK _BV(1)
+
+/** Mask for RX Start interrupt */
+#define TRX_IRQ_RX_START   _BV(2)
+
+/** Mask for RX/TX end interrupt */
+#define TRX_IRQ_TRX_END    _BV(3)
+
+/** Mask for CCA_ED interrupt */
+#define TRX_IRQ_CCA_ED     _BV(4)
+
+/** Mask for AMI interrupt */
+#define TRX_IRQ_AMI        _BV(5)
+
+/** Mask for RX/TX underrun interrupt */
+#define TRX_IRQ_UR         _BV(6)
+
+/** Mask for battery low interrupt */
+#define TRX_IRQ_BAT_LOW    _BV(7)
+
+/** TX ARET status for successful transmission */
+#define TRAC_SUCCESS (0)
+/** TX ARET status for unsuccessful transmission due to no channel access */
+#define TRAC_CHANNEL_ACCESS_FAILURE (3)
+/** TX ARET status for unsuccessful transmission due no ACK frame was received */
+#define TRAC_NO_ACK (5)
+
+
+/** lowest supported channel number */
+#define TRX_MIN_CHANNEL (0)
+
+/** highest supported channel number */
+#ifdef CHINABAND
+#define TRX_MAX_CHANNEL (3)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (4)
+#define TRX_SUPPORTED_CHANNELS  (0x000000fUL)
+#else
+#define TRX_MAX_CHANNEL (10)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (11)
+#define TRX_SUPPORTED_CHANNELS  (0x00007ffUL)
+#endif
+/**
+ * @brief Mask for supported channels of this radio.
+ * The AT86RF212 supports channels 0 ... 10 of IEEE 802.15.4
+ * (currently no support for free configurable frequencies here)
+ */
+
+
+/**
+ * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
+ * The AT86RF230 supports channel page ???? OQPSK_250
+ */
+#define TRX_SUPPORTED_PAGES     (42)
+#define TRX_SUPPORTS_BAND_700 (1)
+#define TRX_SUPPORTS_BAND_800 (1)
+#define TRX_SUPPORTS_BAND_900 (1)
+
+/** Rate code for BPSK20, xx kchip/s, yy kbit/s */
+#define TRX_BPSK20    (0)
+
+/** Rate code for BPSK40, xx kchip/s, yy kbit/s */
+#define TRX_BPSK40    (4)
+
+/** Rate code for OQPSK100, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK100  (8)
+
+/** Rate code for OQPSK200, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK200  (9)
+
+/** Rate code for OQPSK400, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK400  (10)
+#define TRX_OQPSK400_1  (11)
+
+/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
+#ifdef CHINABAND
+#define TRX_OQPSK250  (28)
+#define CCBAND  (4)
+#define CCNUMBER  (11)
+#else
+#define TRX_OQPSK250  (12)
+#endif
+
+/** Rate code for OQPSK500, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK500  (13)
+
+/** Rate code for OQPSK1000, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK1000 (14)
+#define TRX_OQPSK1000_1 (15)
+/** undefined data rate */
+#define TRX_NONE      (255)
+
+#endif /* ifndef AT86RF212_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/at86rf230a.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/at86rf230a.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,368 @@
+/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf230a.txt */
+
+/* Copyright (c) 2008 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief AT86RF230 Rev.A 2.4GHz IEEE 802.15.4-Transceiver.
+ */
+#ifndef AT86RF230A_H
+#define AT86RF230A_H (1)
+#include <stdint.h>
+#define _BV(bit) (1 << (bit))
+
+/* === Includes ============================================================== */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+typedef uint8_t trx_ramaddr_t;
+typedef uint8_t trx_regval_t;
+typedef uint8_t trx_regaddr_t;
+
+/* === Macros ================================================================ */
+/** Offset for register TRX_STATUS */
+#define RG_TRX_STATUS (0x1)
+  /** Access parameters for sub-register CCA_DONE in register TRX_STATUS */
+  #define SR_CCA_DONE 0x1,0x80,7
+  /** Access parameters for sub-register CCA_STATUS in register TRX_STATUS */
+  #define SR_CCA_STATUS 0x1,0x40,6
+  /** Access parameters for sub-register TRX_STATUS in register TRX_STATUS */
+  #define SR_TRX_STATUS 0x1,0x1f,0
+    #define P_ON (0)
+    #define BUSY_RX (1)
+    #define BUSY_TX (2)
+    #define RX_ON (6)
+    #define TRX_OFF (8)
+    #define PLL_ON (9)
+    #define TRX_SLEEP (15)
+    #define BUSY_RX_AACK (17)
+    #define BUSY_TX_ARET (18)
+    #define RX_AACK_ON (22)
+    #define TX_ARET_ON (25)
+    #define RX_ON_NOCLK (28)
+    #define RX_AACK_ON_NOCLK (29)
+    #define BUSY_RX_AACK_NOCLK (30)
+/** Offset for register TRX_STATE */
+#define RG_TRX_STATE (0x2)
+  /** Access parameters for sub-register TRAC_STATUS in register TRX_STATE */
+  #define SR_TRAC_STATUS 0x2,0xe0,5
+    #define TRAC_SUCCESS (0)
+    #define TRAC_CHANNEL_ACCESS_FAILURE (3)
+    #define TRAC_NO_ACK (5)
+  /** Access parameters for sub-register TRX_CMD in register TRX_STATE */
+  #define SR_TRX_CMD 0x2,0x1f,0
+    #define CMD_NOP (0)
+    #define CMD_TX_START (2)
+    #define CMD_FORCE_TRX_OFF (3)
+    #define CMD_RX_ON (6)
+    #define CMD_TRX_OFF (8)
+    #define CMD_PLL_ON (9)
+    #define CMD_RX_AACK_ON (22)
+    #define CMD_TX_ARET_ON (25)
+/** Offset for register TRX_CTRL_0 */
+#define RG_TRX_CTRL_0 (0x3)
+  /** Access parameters for sub-register PAD_IO in register TRX_CTRL_0 */
+  #define SR_PAD_IO 0x3,0xc0,6
+  /** Access parameters for sub-register PAD_IO_CLKM in register TRX_CTRL_0 */
+  #define SR_PAD_IO_CLKM 0x3,0x30,4
+    #define CLKM_2mA (0)
+    #define CLKM_4mA (1)
+    #define CLKM_6mA (2)
+    #define CLKM_8mA (3)
+  /** Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0 */
+  #define SR_CLKM_SHA_SEL 0x3,0x8,3
+  /** Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0 */
+  #define SR_CLKM_CTRL 0x3,0x7,0
+    #define CLKM_no_clock (0)
+    #define CLKM_1MHz (1)
+    #define CLKM_2MHz (2)
+    #define CLKM_4MHz (3)
+    #define CLKM_8MHz (4)
+    #define CLKM_16MHz (5)
+/** Offset for register PHY_TX_PWR */
+#define RG_PHY_TX_PWR (0x5)
+  /** Access parameters for sub-register TX_AUTO_CRC_ON in register PHY_TX_PWR */
+  #define SR_TX_AUTO_CRC_ON 0x5,0x80,7
+  /** Access parameters for sub-register TX_PWR in register PHY_TX_PWR */
+  #define SR_TX_PWR 0x5,0xf,0
+/** Offset for register PHY_RSSI */
+#define RG_PHY_RSSI (0x6)
+  /** Access parameters for sub-register RSSI in register PHY_RSSI */
+  #define SR_RSSI 0x6,0x1f,0
+/** Offset for register PHY_ED_LEVEL */
+#define RG_PHY_ED_LEVEL (0x7)
+  /** Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL */
+  #define SR_ED_LEVEL 0x7,0xff,0
+/** Offset for register PHY_CC_CCA */
+#define RG_PHY_CC_CCA (0x8)
+  /** Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA */
+  #define SR_CCA_REQUEST 0x8,0x80,7
+  /** Access parameters for sub-register CCA_MODE in register PHY_CC_CCA */
+  #define SR_CCA_MODE 0x8,0x60,5
+  /** Access parameters for sub-register CHANNEL in register PHY_CC_CCA */
+  #define SR_CHANNEL 0x8,0x1f,0
+/** Offset for register CCA_THRES */
+#define RG_CCA_THRES (0x9)
+  /** Access parameters for sub-register CCA_ED_THRES in register CCA_THRES */
+  #define SR_CCA_ED_THRES 0x9,0xf,0
+/** Offset for register IRQ_MASK */
+#define RG_IRQ_MASK (0xe)
+  /** Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK */
+  #define SR_MASK_BAT_LOW 0xe,0x80,7
+  /** Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK */
+  #define SR_MASK_TRX_UR 0xe,0x40,6
+  /** Access parameters for sub-register MASK_TRX_END in register IRQ_MASK */
+  #define SR_MASK_TRX_END 0xe,0x8,3
+  /** Access parameters for sub-register MASK_TRX_START in register IRQ_MASK */
+  #define SR_MASK_TRX_START 0xe,0x4,2
+  /** Access parameters for sub-register MASK_PLL_LOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_LOCK 0xe,0x1,0
+  /** Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
+/** Offset for register IRQ_STATUS */
+#define RG_IRQ_STATUS (0xf)
+  /** Access parameters for sub-register BAT_LOW in register IRQ_STATUS */
+  #define SR_BAT_LOW 0xf,0x80,7
+  /** Access parameters for sub-register TRX_UR in register IRQ_STATUS */
+  #define SR_TRX_UR 0xf,0x40,6
+  /** Access parameters for sub-register RX_END in register IRQ_STATUS */
+  #define SR_RX_END 0xf,0x8,3
+  /** Access parameters for sub-register RX_START in register IRQ_STATUS */
+  #define SR_RX_START 0xf,0x4,2
+  /** Access parameters for sub-register PLL_LOCK in register IRQ_STATUS */
+  #define SR_PLL_LOCK 0xf,0x1,0
+  /** Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS */
+  #define SR_PLL_UNLOCK 0xf,0x2,1
+/** Offset for register VREG_CTRL */
+#define RG_VREG_CTRL (0x10)
+  /** Access parameters for sub-register AVREG_EXT in register VREG_CTRL */
+  #define SR_AVREG_EXT 0x10,0x80,7
+  /** Access parameters for sub-register AVDD_OK in register VREG_CTRL */
+  #define SR_AVDD_OK 0x10,0x40,6
+  /** Access parameters for sub-register DVREG_EXT in register VREG_CTRL */
+  #define SR_DVREG_EXT 0x10,0x8,3
+  /** Access parameters for sub-register DVDD_OK in register VREG_CTRL */
+  #define SR_DVDD_OK 0x10,0x4,2
+/** Offset for register BATMON */
+#define RG_BATMON (0x11)
+  /** Access parameters for sub-register BATMON_OK in register BATMON */
+  #define SR_BATMON_OK 0x11,0x20,5
+  /** Access parameters for sub-register BATMON_HR in register BATMON */
+  #define SR_BATMON_HR 0x11,0x10,4
+  /** Access parameters for sub-register BATMON_VTH in register BATMON */
+  #define SR_BATMON_VTH 0x11,0xf,0
+/** Offset for register XOSC_CTRL */
+#define RG_XOSC_CTRL (0x12)
+  /** Access parameters for sub-register XTAL_MODE in register XOSC_CTRL */
+  #define SR_XTAL_MODE 0x12,0xf0,4
+  /** Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL */
+  #define SR_XTAL_TRIM 0x12,0xf,0
+/** Offset for register PLL_CF */
+#define RG_PLL_CF (0x1a)
+  /** Access parameters for sub-register PLL_CF_START in register PLL_CF */
+  #define SR_PLL_CF_START 0x1a,0x80,7
+/** Offset for register PLL_DCU */
+#define RG_PLL_DCU (0x1b)
+  /** Access parameters for sub-register PLL_DCU_START in register PLL_DCU */
+  #define SR_PLL_DCU_START 0x1b,0x80,7
+/** Offset for register PART_NUM */
+#define RG_PART_NUM (0x1c)
+  /** Access parameters for sub-register PART_NUM in register PART_NUM */
+  #define SR_PART_NUM 0x1c,0xff,0
+    #define RF230A_PART_NUM (2)
+/** Offset for register VERSION_NUM */
+#define RG_VERSION_NUM (0x1d)
+  /** Access parameters for sub-register VERSION_NUM in register VERSION_NUM */
+  #define SR_VERSION_NUM 0x1d,0xff,0
+    #define RF230A_VERSION_NUM (1)
+/** Offset for register MAN_ID_0 */
+#define RG_MAN_ID_0 (0x1e)
+  /** Access parameters for sub-register MAN_ID_0 in register MAN_ID_0 */
+  #define SR_MAN_ID_0 0x1e,0xff,0
+/** Offset for register MAN_ID_1 */
+#define RG_MAN_ID_1 (0x1f)
+  /** Access parameters for sub-register MAN_ID_1 in register MAN_ID_1 */
+  #define SR_MAN_ID_1 0x1f,0xff,0
+/** Offset for register SHORT_ADDR_0 */
+#define RG_SHORT_ADDR_0 (0x20)
+  /** Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0 */
+  #define SR_SHORT_ADDR_0 0x20,0xff,0
+/** Offset for register SHORT_ADDR_1 */
+#define RG_SHORT_ADDR_1 (0x21)
+  /** Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1 */
+  #define SR_SHORT_ADDR_1 0x21,0xff,0
+/** Offset for register PAN_ID_0 */
+#define RG_PAN_ID_0 (0x22)
+  /** Access parameters for sub-register PAN_ID_0 in register PAN_ID_0 */
+  #define SR_PAN_ID_0 0x22,0xff,0
+/** Offset for register PAN_ID_1 */
+#define RG_PAN_ID_1 (0x23)
+  /** Access parameters for sub-register PAN_ID_1 in register PAN_ID_1 */
+  #define SR_PAN_ID_1 0x23,0xff,0
+/** Offset for register IEEE_ADDR_0 */
+#define RG_IEEE_ADDR_0 (0x24)
+  /** Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0 */
+  #define SR_IEEE_ADDR_0 0x24,0xff,0
+/** Offset for register IEEE_ADDR_1 */
+#define RG_IEEE_ADDR_1 (0x25)
+  /** Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1 */
+  #define SR_IEEE_ADDR_1 0x25,0xff,0
+/** Offset for register IEEE_ADDR_2 */
+#define RG_IEEE_ADDR_2 (0x26)
+  /** Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2 */
+  #define SR_IEEE_ADDR_2 0x26,0xff,0
+/** Offset for register IEEE_ADDR_3 */
+#define RG_IEEE_ADDR_3 (0x27)
+  /** Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3 */
+  #define SR_IEEE_ADDR_3 0x27,0xff,0
+/** Offset for register IEEE_ADDR_4 */
+#define RG_IEEE_ADDR_4 (0x28)
+  /** Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4 */
+  #define SR_IEEE_ADDR_4 0x28,0xff,0
+/** Offset for register IEEE_ADDR_5 */
+#define RG_IEEE_ADDR_5 (0x29)
+  /** Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5 */
+  #define SR_IEEE_ADDR_5 0x29,0xff,0
+/** Offset for register IEEE_ADDR_6 */
+#define RG_IEEE_ADDR_6 (0x2a)
+  /** Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6 */
+  #define SR_IEEE_ADDR_6 0x2a,0xff,0
+/** Offset for register IEEE_ADDR_7 */
+#define RG_IEEE_ADDR_7 (0x2b)
+  /** Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7 */
+  #define SR_IEEE_ADDR_7 0x2b,0xff,0
+/** Offset for register XAH_CTRL */
+#define RG_XAH_CTRL (0x2c)
+  /** Access parameters for sub-register MAX_FRAME_RETRIES in register XAH_CTRL */
+  #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
+  /** Access parameters for sub-register MAX_CSMA_RETRIES in register XAH_CTRL */
+  #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
+/** Offset for register CSMA_SEED_0 */
+#define RG_CSMA_SEED_0 (0x2d)
+  /** Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0 */
+  #define SR_CSMA_SEED_0 0x2d,0xff,0
+/** Offset for register CSMA_SEED_1 */
+#define RG_CSMA_SEED_1 (0x2e)
+  /** Access parameters for sub-register MIN_BE in register CSMA_SEED_1 */
+  #define SR_MIN_BE 0x2e,0xc0,6
+  /** Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1 */
+  #define SR_AACK_I_AM_COORD 0x2e,0x8,3
+  /** Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1 */
+  #define SR_CSMA_SEED_1 0x2e,0x7,0
+/** name string of the radio */
+#define RADIO_NAME "AT86RF230A"
+/** contents of the RG_PART_NUM register */
+#define RADIO_PART_NUM (RF230A_PART_NUM)
+/** contents of the RG_VERSION_NUM register */
+#define RADIO_VERSION_NUM (RF230A_VERSION_NUM)
+
+
+/** SPI command code for register write */
+#define TRX_CMD_RW           (_BV(7) | _BV(6))
+/** SPI command code for register read */
+#define TRX_CMD_RR           (_BV(7))
+/** SPI command code for frame write */
+#define TRX_CMD_FW           (_BV(6) | _BV(5))
+/** SPI command code for frame read */
+#define TRX_CMD_FR           (_BV(5))
+/** SPI command code for sram write */
+#define TRX_CMD_SW           (_BV(6))
+/** SPI command code for sram read */
+#define TRX_CMD_SR           (0)
+
+#define TRX_CMD_RADDR_MASK   (0x3f)
+
+/** duration while reset=low is asserted */
+#define TRX_RESET_TIME_US    (6)
+
+/** duration transceiver reaches TRX_OFF for the first time */
+#define TRX_INIT_TIME_US     (510)
+
+/** maximum duration, which PLL needs to lock */
+#define TRX_PLL_LOCK_TIME_US     (180)
+
+/** duration of a CCA measurement */
+#define TRX_CCA_TIME_US     (140)
+
+/** Mask for PLL lock interrupt */
+#define TRX_IRQ_PLL_LOCK   _BV(0)
+
+/** Mask for PLL unlock interrupt */
+#define TRX_IRQ_PLL_UNLOCK _BV(1)
+
+/** Mask for RX Start interrupt */
+#define TRX_IRQ_RX_START   _BV(2)
+
+/** Mask for RX/TX end interrupt */
+#define TRX_IRQ_TRX_END    _BV(3)
+
+/** Mask for RX/TX underrun interrupt */
+#define TRX_IRQ_UR         _BV(6)
+
+/** Mask for battery low interrupt */
+#define TRX_IRQ_BAT_LOW    _BV(7)
+
+/** lowest supported channel number */
+#define TRX_MIN_CHANNEL (11)
+
+/** highest supported channel number */
+#define TRX_MAX_CHANNEL (26)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (16)
+
+/**
+ * @brief Mask for supported channels of this radio.
+ * The AT86RF230 supports channels 11 ... 26 of IEEE 802.15.4
+ */
+#define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
+
+/**
+ * @brief Mask for supported modulation schemes of this radio.
+ */
+#define TRX_SUPPORTED_MODULATIONS (MODULATION_OQPSK_250)
+
+/**
+ * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
+ * The AT86RF230 supports channel page ???? OQPSK_250
+ */
+#define TRX_SUPPORTED_PAGES     (42)
+
+#define TRX_SUPPORTS_BAND_2400 (1)
+
+/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK250  (0)
+
+/** undefined data rate */
+#define TRX_NONE      (255)
+
+#endif /* ifndef AT86RF230A_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/at86rf230b.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/at86rf230b.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,371 @@
+/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf230b.txt */
+
+/* Copyright (c) 2008 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief AT86RF230 Rev.B 2.4GHz IEEE 802.15.4-Transceiver.
+ */
+#ifndef AT86RF230B_H
+#define AT86RF230B_H (1)
+#include <stdint.h>
+#define _BV(bit) (1 << (bit))
+
+/* === Includes ============================================================== */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+typedef uint8_t trx_ramaddr_t;
+typedef uint8_t trx_regval_t;
+typedef uint8_t trx_regaddr_t;
+
+/* === Macros ================================================================ */
+/** Offset for register TRX_STATUS */
+#define RG_TRX_STATUS (0x1)
+  /** Access parameters for sub-register CCA_DONE in register TRX_STATUS */
+  #define SR_CCA_DONE 0x1,0x80,7
+  /** Access parameters for sub-register CCA_STATUS in register TRX_STATUS */
+  #define SR_CCA_STATUS 0x1,0x40,6
+  /** Access parameters for sub-register TRX_STATUS in register TRX_STATUS */
+  #define SR_TRX_STATUS 0x1,0x1f,0
+    #define P_ON (0)
+    #define BUSY_RX (1)
+    #define BUSY_TX (2)
+    #define RX_ON (6)
+    #define TRX_OFF (8)
+    #define PLL_ON (9)
+    #define TRX_SLEEP (15)
+    #define BUSY_RX_AACK (17)
+    #define BUSY_TX_ARET (18)
+    #define RX_AACK_ON (22)
+    #define TX_ARET_ON (25)
+    #define RX_ON_NOCLK (28)
+    #define RX_AACK_ON_NOCLK (29)
+    #define BUSY_RX_AACK_NOCLK (30)
+/** Offset for register TRX_STATE */
+#define RG_TRX_STATE (0x2)
+  /** Access parameters for sub-register TRAC_STATUS in register TRX_STATE */
+  #define SR_TRAC_STATUS 0x2,0xe0,5
+    #define TRAC_SUCCESS (0)
+    #define TRAC_SUCCESS_DATA_PENDING (1)
+    #define TRAC_CHANNEL_ACCESS_FAILURE (3)
+    #define TRAC_NO_ACK (5)
+    #define TRAC_INVALID (7)
+  /** Access parameters for sub-register TRX_CMD in register TRX_STATE */
+  #define SR_TRX_CMD 0x2,0x1f,0
+    #define CMD_NOP (0)
+    #define CMD_TX_START (2)
+    #define CMD_FORCE_TRX_OFF (3)
+    #define CMD_RX_ON (6)
+    #define CMD_TRX_OFF (8)
+    #define CMD_PLL_ON (9)
+    #define CMD_RX_AACK_ON (22)
+    #define CMD_TX_ARET_ON (25)
+/** Offset for register TRX_CTRL_0 */
+#define RG_TRX_CTRL_0 (0x3)
+  /** Access parameters for sub-register PAD_IO in register TRX_CTRL_0 */
+  #define SR_PAD_IO 0x3,0xc0,6
+  /** Access parameters for sub-register PAD_IO_CLKM in register TRX_CTRL_0 */
+  #define SR_PAD_IO_CLKM 0x3,0x30,4
+    #define CLKM_2mA (0)
+    #define CLKM_4mA (1)
+    #define CLKM_6mA (2)
+    #define CLKM_8mA (3)
+  /** Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0 */
+  #define SR_CLKM_SHA_SEL 0x3,0x8,3
+  /** Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0 */
+  #define SR_CLKM_CTRL 0x3,0x7,0
+    #define CLKM_no_clock (0)
+    #define CLKM_1MHz (1)
+    #define CLKM_2MHz (2)
+    #define CLKM_4MHz (3)
+    #define CLKM_8MHz (4)
+    #define CLKM_16MHz (5)
+/** Offset for register PHY_TX_PWR */
+#define RG_PHY_TX_PWR (0x5)
+  /** Access parameters for sub-register TX_AUTO_CRC_ON in register PHY_TX_PWR */
+  #define SR_TX_AUTO_CRC_ON 0x5,0x80,7
+  /** Access parameters for sub-register TX_PWR in register PHY_TX_PWR */
+  #define SR_TX_PWR 0x5,0xf,0
+/** Offset for register PHY_RSSI */
+#define RG_PHY_RSSI (0x6)
+  /** Access parameters for sub-register RX_CRC_VALID in register PHY_RSSI */
+  #define SR_RX_CRC_VALID 0x6,0x80,7
+  /** Access parameters for sub-register RSSI in register PHY_RSSI */
+  #define SR_RSSI 0x6,0x1f,0
+/** Offset for register PHY_ED_LEVEL */
+#define RG_PHY_ED_LEVEL (0x7)
+  /** Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL */
+  #define SR_ED_LEVEL 0x7,0xff,0
+/** Offset for register PHY_CC_CCA */
+#define RG_PHY_CC_CCA (0x8)
+  /** Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA */
+  #define SR_CCA_REQUEST 0x8,0x80,7
+  /** Access parameters for sub-register CCA_MODE in register PHY_CC_CCA */
+  #define SR_CCA_MODE 0x8,0x60,5
+  /** Access parameters for sub-register CHANNEL in register PHY_CC_CCA */
+  #define SR_CHANNEL 0x8,0x1f,0
+/** Offset for register CCA_THRES */
+#define RG_CCA_THRES (0x9)
+  /** Access parameters for sub-register CCA_ED_THRES in register CCA_THRES */
+  #define SR_CCA_ED_THRES 0x9,0xf,0
+/** Offset for register IRQ_MASK */
+#define RG_IRQ_MASK (0xe)
+  /** Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK */
+  #define SR_MASK_BAT_LOW 0xe,0x80,7
+  /** Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK */
+  #define SR_MASK_TRX_UR 0xe,0x40,6
+  /** Access parameters for sub-register MASK_TRX_END in register IRQ_MASK */
+  #define SR_MASK_TRX_END 0xe,0x8,3
+  /** Access parameters for sub-register MASK_TRX_START in register IRQ_MASK */
+  #define SR_MASK_TRX_START 0xe,0x4,2
+  /** Access parameters for sub-register MASK_PLL_LOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_LOCK 0xe,0x1,0
+  /** Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
+/** Offset for register IRQ_STATUS */
+#define RG_IRQ_STATUS (0xf)
+  /** Access parameters for sub-register BAT_LOW in register IRQ_STATUS */
+  #define SR_BAT_LOW 0xf,0x80,7
+  /** Access parameters for sub-register TRX_UR in register IRQ_STATUS */
+  #define SR_TRX_UR 0xf,0x40,6
+  /** Access parameters for sub-register RX_END in register IRQ_STATUS */
+  #define SR_RX_END 0xf,0x8,3
+  /** Access parameters for sub-register RX_START in register IRQ_STATUS */
+  #define SR_RX_START 0xf,0x4,2
+  /** Access parameters for sub-register PLL_LOCK in register IRQ_STATUS */
+  #define SR_PLL_LOCK 0xf,0x1,0
+  /** Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS */
+  #define SR_PLL_UNLOCK 0xf,0x2,1
+/** Offset for register VREG_CTRL */
+#define RG_VREG_CTRL (0x10)
+  /** Access parameters for sub-register AVREG_EXT in register VREG_CTRL */
+  #define SR_AVREG_EXT 0x10,0x80,7
+  /** Access parameters for sub-register AVDD_OK in register VREG_CTRL */
+  #define SR_AVDD_OK 0x10,0x40,6
+  /** Access parameters for sub-register DVREG_EXT in register VREG_CTRL */
+  #define SR_DVREG_EXT 0x10,0x8,3
+  /** Access parameters for sub-register DVDD_OK in register VREG_CTRL */
+  #define SR_DVDD_OK 0x10,0x4,2
+/** Offset for register BATMON */
+#define RG_BATMON (0x11)
+  /** Access parameters for sub-register BATMON_OK in register BATMON */
+  #define SR_BATMON_OK 0x11,0x20,5
+  /** Access parameters for sub-register BATMON_HR in register BATMON */
+  #define SR_BATMON_HR 0x11,0x10,4
+  /** Access parameters for sub-register BATMON_VTH in register BATMON */
+  #define SR_BATMON_VTH 0x11,0xf,0
+/** Offset for register XOSC_CTRL */
+#define RG_XOSC_CTRL (0x12)
+  /** Access parameters for sub-register XTAL_MODE in register XOSC_CTRL */
+  #define SR_XTAL_MODE 0x12,0xf0,4
+  /** Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL */
+  #define SR_XTAL_TRIM 0x12,0xf,0
+/** Offset for register PLL_CF */
+#define RG_PLL_CF (0x1a)
+  /** Access parameters for sub-register PLL_CF_START in register PLL_CF */
+  #define SR_PLL_CF_START 0x1a,0x80,7
+/** Offset for register PLL_DCU */
+#define RG_PLL_DCU (0x1b)
+  /** Access parameters for sub-register PLL_DCU_START in register PLL_DCU */
+  #define SR_PLL_DCU_START 0x1b,0x80,7
+/** Offset for register PART_NUM */
+#define RG_PART_NUM (0x1c)
+  /** Access parameters for sub-register PART_NUM in register PART_NUM */
+  #define SR_PART_NUM 0x1c,0xff,0
+    #define RF230B_PART_NUM (2)
+/** Offset for register VERSION_NUM */
+#define RG_VERSION_NUM (0x1d)
+  /** Access parameters for sub-register VERSION_NUM in register VERSION_NUM */
+  #define SR_VERSION_NUM 0x1d,0xff,0
+    #define RF230B_VERSION_NUM (2)
+/** Offset for register MAN_ID_0 */
+#define RG_MAN_ID_0 (0x1e)
+  /** Access parameters for sub-register MAN_ID_0 in register MAN_ID_0 */
+  #define SR_MAN_ID_0 0x1e,0xff,0
+/** Offset for register MAN_ID_1 */
+#define RG_MAN_ID_1 (0x1f)
+  /** Access parameters for sub-register MAN_ID_1 in register MAN_ID_1 */
+  #define SR_MAN_ID_1 0x1f,0xff,0
+/** Offset for register SHORT_ADDR_0 */
+#define RG_SHORT_ADDR_0 (0x20)
+  /** Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0 */
+  #define SR_SHORT_ADDR_0 0x20,0xff,0
+/** Offset for register SHORT_ADDR_1 */
+#define RG_SHORT_ADDR_1 (0x21)
+  /** Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1 */
+  #define SR_SHORT_ADDR_1 0x21,0xff,0
+/** Offset for register PAN_ID_0 */
+#define RG_PAN_ID_0 (0x22)
+  /** Access parameters for sub-register PAN_ID_0 in register PAN_ID_0 */
+  #define SR_PAN_ID_0 0x22,0xff,0
+/** Offset for register PAN_ID_1 */
+#define RG_PAN_ID_1 (0x23)
+  /** Access parameters for sub-register PAN_ID_1 in register PAN_ID_1 */
+  #define SR_PAN_ID_1 0x23,0xff,0
+/** Offset for register IEEE_ADDR_0 */
+#define RG_IEEE_ADDR_0 (0x24)
+  /** Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0 */
+  #define SR_IEEE_ADDR_0 0x24,0xff,0
+/** Offset for register IEEE_ADDR_1 */
+#define RG_IEEE_ADDR_1 (0x25)
+  /** Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1 */
+  #define SR_IEEE_ADDR_1 0x25,0xff,0
+/** Offset for register IEEE_ADDR_2 */
+#define RG_IEEE_ADDR_2 (0x26)
+  /** Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2 */
+  #define SR_IEEE_ADDR_2 0x26,0xff,0
+/** Offset for register IEEE_ADDR_3 */
+#define RG_IEEE_ADDR_3 (0x27)
+  /** Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3 */
+  #define SR_IEEE_ADDR_3 0x27,0xff,0
+/** Offset for register IEEE_ADDR_4 */
+#define RG_IEEE_ADDR_4 (0x28)
+  /** Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4 */
+  #define SR_IEEE_ADDR_4 0x28,0xff,0
+/** Offset for register IEEE_ADDR_5 */
+#define RG_IEEE_ADDR_5 (0x29)
+  /** Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5 */
+  #define SR_IEEE_ADDR_5 0x29,0xff,0
+/** Offset for register IEEE_ADDR_6 */
+#define RG_IEEE_ADDR_6 (0x2a)
+  /** Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6 */
+  #define SR_IEEE_ADDR_6 0x2a,0xff,0
+/** Offset for register IEEE_ADDR_7 */
+#define RG_IEEE_ADDR_7 (0x2b)
+  /** Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7 */
+  #define SR_IEEE_ADDR_7 0x2b,0xff,0
+/** Offset for register XAH_CTRL */
+#define RG_XAH_CTRL (0x2c)
+  /** Access parameters for sub-register MAX_FRAME_RETRIES in register XAH_CTRL */
+  #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
+  /** Access parameters for sub-register MAX_CSMA_RETRIES in register XAH_CTRL */
+  #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
+/** Offset for register CSMA_SEED_0 */
+#define RG_CSMA_SEED_0 (0x2d)
+  /** Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0 */
+  #define SR_CSMA_SEED_0 0x2d,0xff,0
+/** Offset for register CSMA_SEED_1 */
+#define RG_CSMA_SEED_1 (0x2e)
+  /** Access parameters for sub-register MIN_BE in register CSMA_SEED_1 */
+  #define SR_MIN_BE 0x2e,0xc0,6
+  /** Access parameters for sub-register AACK_SET_PD in register CSMA_SEED_1 */
+  #define SR_AACK_SET_PD 0x2e,0x20,5
+  /** Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1 */
+  #define SR_AACK_I_AM_COORD 0x2e,0x8,3
+  /** Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1 */
+  #define SR_CSMA_SEED_1 0x2e,0x7,0
+/** name string of the radio */
+#define RADIO_NAME "AT86RF230B"
+/** contents of the RG_PART_NUM register */
+#define RADIO_PART_NUM (RF230B_PART_NUM)
+/** contents of the RG_VERSION_NUM register */
+#define RADIO_VERSION_NUM (RF230B_VERSION_NUM)
+
+/** SPI command code for register write */
+#define TRX_CMD_RW           (_BV(7) | _BV(6))
+/** SPI command code for register read */
+#define TRX_CMD_RR           (_BV(7))
+/** SPI command code for frame write */
+#define TRX_CMD_FW           (_BV(6) | _BV(5))
+/** SPI command code for frame read */
+#define TRX_CMD_FR           (_BV(5))
+/** SPI command code for sram write */
+#define TRX_CMD_SW           (_BV(6))
+/** SPI command code for sram read */
+#define TRX_CMD_SR           (0)
+
+#define TRX_CMD_RADDR_MASK   (0x3f)
+
+/** duration while reset=low is asserted */
+#define TRX_RESET_TIME_US    (6)
+
+/** duration transceiver reaches TRX_OFF for the first time */
+#define TRX_INIT_TIME_US     (510)
+
+/** maximum duration, which PLL needs to lock */
+#define TRX_PLL_LOCK_TIME_US     (180)
+
+/** duration of a CCA measurement */
+#define TRX_CCA_TIME_US     (140)
+
+/** Mask for PLL lock interrupt */
+#define TRX_IRQ_PLL_LOCK   _BV(0)
+
+/** Mask for PLL unlock interrupt */
+#define TRX_IRQ_PLL_UNLOCK _BV(1)
+
+/** Mask for RX Start interrupt */
+#define TRX_IRQ_RX_START   _BV(2)
+
+/** Mask for RX/TX end interrupt */
+#define TRX_IRQ_TRX_END    _BV(3)
+
+/** Mask for RX/TX underrun interrupt */
+#define TRX_IRQ_UR         _BV(6)
+
+/** Mask for battery low interrupt */
+#define TRX_IRQ_BAT_LOW    _BV(7)
+
+
+
+/** lowest supported channel number */
+#define TRX_MIN_CHANNEL (11)
+
+/** highest supported channel number */
+#define TRX_MAX_CHANNEL (26)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (16)
+
+/**
+ * @brief Mask for supported channels of this radio.
+ * The AT86RF230 supports channels 11 ... 26 of IEEE 802.15.4
+ */
+#define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
+
+#define TRX_SUPPORTS_BAND_2400 (1)
+
+/**
+ * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
+ * The AT86RF230 supports channel page ???? OQPSK_250
+ */
+#define TRX_SUPPORTED_PAGES     (42)
+
+
+/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK250  (0)
+
+/** undefined data rate */
+#define TRX_NONE      (255)
+
+#endif /* ifndef AT86RF230B_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/at86rf231.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/at86rf231.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,476 @@
+/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf231.txt */
+
+/* Copyright (c) 2008 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief AT86RF231 2.4GHz IEEE 802.15.4-2006-Transceiver.
+ */
+#ifndef AT86RF231_H
+#define AT86RF231_H (1)
+
+#include <stdint.h>
+
+#define _BV(bit) (1 << (bit))
+
+/* === Includes ============================================================== */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+typedef uint8_t trx_ramaddr_t;
+typedef uint8_t trx_regval_t;
+typedef uint8_t trx_regaddr_t;
+
+/* === Macros ================================================================ */
+/** Offset for register TRX_STATUS */
+#define RG_TRX_STATUS (0x1)
+  /** Access parameters for sub-register CCA_DONE in register TRX_STATUS */
+  #define SR_CCA_DONE 0x1,0x80,7
+  /** Access parameters for sub-register CCA_STATUS in register TRX_STATUS */
+  #define SR_CCA_STATUS 0x1,0x40,6
+  /** Access parameters for sub-register TRX_STATUS in register TRX_STATUS */
+  #define SR_TRX_STATUS 0x1,0x1f,0
+    #define P_ON (0)
+    #define BUSY_RX (1)
+    #define BUSY_TX (2)
+    #define RX_ON (6)
+    #define TRX_OFF (8)
+    #define PLL_ON (9)
+    #define TRX_SLEEP (15)
+    #define BUSY_RX_AACK (17)
+    #define BUSY_TX_ARET (18)
+    #define RX_AACK_ON (22)
+    #define TX_ARET_ON (25)
+    #define RX_ON_NOCLK (28)
+    #define RX_AACK_ON_NOCLK (29)
+    #define BUSY_RX_AACK_NOCLK (30)
+/** Offset for register TRX_STATE */
+#define RG_TRX_STATE (0x2)
+  /** Access parameters for sub-register TRAC_STATUS in register TRX_STATE */
+  #define SR_TRAC_STATUS 0x2,0xe0,5
+    #define TRAC_SUCCESS (0)
+    #define TRAC_SUCCESS_DATA_PENDING (1)
+    #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
+    #define TRAC_CHANNEL_ACCESS_FAILURE (3)
+    #define TRAC_NO_ACK (5)
+    #define TRAC_INVALID (7)
+  /** Access parameters for sub-register TRX_CMD in register TRX_STATE */
+  #define SR_TRX_CMD 0x2,0x1f,0
+    #define CMD_NOP (0)
+    #define CMD_TX_START (2)
+    #define CMD_FORCE_TRX_OFF (3)
+    #define CMD_RX_ON (6)
+    #define CMD_TRX_OFF (8)
+    #define CMD_PLL_ON (9)
+    #define CMD_RX_AACK_ON (22)
+    #define CMD_TX_ARET_ON (25)
+/** Offset for register TRX_CTRL_0 */
+#define RG_TRX_CTRL_0 (0x3)
+  /** Access parameters for sub-register PAD_IO in register TRX_CTRL_0 */
+  #define SR_PAD_IO 0x3,0xe0,5
+  /** Access parameters for sub-register PAD_IO_CLKM in register TRX_CTRL_0 */
+  #define SR_PAD_IO_CLKM 0x3,0x10,4
+    #define CLKM_2mA (0)
+    #define CLKM_4mA (1)
+    #define CLKM_6mA (2)
+    #define CLKM_8mA (3)
+  /** Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0 */
+  #define SR_CLKM_SHA_SEL 0x3,0x8,3
+  /** Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0 */
+  #define SR_CLKM_CTRL 0x3,0x7,0
+    #define CLKM_no_clock (0)
+    #define CLKM_1MHz (1)
+    #define CLKM_2MHz (2)
+    #define CLKM_4MHz (3)
+    #define CLKM_8MHz (4)
+    #define CLKM_16MHz (5)
+/** Offset for register TRX_CTRL_1 */
+#define RG_TRX_CTRL_1 (0x4)
+  /** Access parameters for sub-register PA_EXT_EN in register TRX_CTRL_1 */
+  #define SR_PA_EXT_EN 0x4,0x80,7
+  /** Access parameters for sub-register IRQ_2_EXT_EN in register TRX_CTRL_1 */
+  #define SR_IRQ_2_EXT_EN 0x4,0x40,6
+  /** Access parameters for sub-register TX_AUTO_CRC_ON in register TRX_CTRL_1 */
+  #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
+  /** Access parameters for sub-register RX_BL_CTRL in register TRX_CTRL_1 */
+  #define SR_RX_BL_CTRL 0x4,0x10,4
+  /** Access parameters for sub-register SPI_CMD_MODE in register TRX_CTRL_1 */
+  #define SR_SPI_CMD_MODE 0x4,0xc,2
+  /** Access parameters for sub-register IRQ_POLARITY in register TRX_CTRL_1 */
+  #define SR_IRQ_POLARITY 0x4,0x1,0
+  /** Access parameters for sub-register IRQ_MASK_MODE in register TRX_CTRL_1 */
+  #define SR_IRQ_MASK_MODE 0x4,0x2,1
+/** Offset for register PHY_TX_PWR */
+#define RG_PHY_TX_PWR (0x5)
+  /** Access parameters for sub-register PA_BUF_LT in register PHY_TX_PWR */
+  #define SR_PA_BUF_LT 0x5,0xc0,6
+  /** Access parameters for sub-register PA_LT in register PHY_TX_PWR */
+  #define SR_PA_LT 0x5,0x30,4
+  /** Access parameters for sub-register TX_PWR in register PHY_TX_PWR */
+  #define SR_TX_PWR 0x5,0xf,0
+/** Offset for register PHY_RSSI */
+#define RG_PHY_RSSI (0x6)
+  /** Access parameters for sub-register RX_CRC_VALID in register PHY_RSSI */
+  #define SR_RX_CRC_VALID 0x6,0x80,7
+  /** Access parameters for sub-register RND_VALUE in register PHY_RSSI */
+  #define SR_RND_VALUE 0x6,0x60,5
+  /** Access parameters for sub-register RSSI in register PHY_RSSI */
+  #define SR_RSSI 0x6,0x1f,0
+/** Offset for register PHY_ED_LEVEL */
+#define RG_PHY_ED_LEVEL (0x7)
+  /** Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL */
+  #define SR_ED_LEVEL 0x7,0xff,0
+/** Offset for register PHY_CC_CCA */
+#define RG_PHY_CC_CCA (0x8)
+  /** Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA */
+  #define SR_CCA_REQUEST 0x8,0x80,7
+  /** Access parameters for sub-register CCA_MODE in register PHY_CC_CCA */
+  #define SR_CCA_MODE 0x8,0x60,5
+  /** Access parameters for sub-register CHANNEL in register PHY_CC_CCA */
+  #define SR_CHANNEL 0x8,0x1f,0
+/** Offset for register CCA_THRES */
+#define RG_CCA_THRES (0x9)
+  /** Access parameters for sub-register CCA_ED_THRES in register CCA_THRES */
+  #define SR_CCA_ED_THRES 0x9,0xf,0
+/** Offset for register RX_CTRL */
+#define RG_RX_CTRL (0xa)
+  /** Access parameters for sub-register PDT_THRES in register RX_CTRL */
+  #define SR_PDT_THRES 0xa,0xf,0
+/** Offset for register SFD_VALUE */
+#define RG_SFD_VALUE (0xb)
+  /** Access parameters for sub-register SFD_VALUE in register SFD_VALUE */
+  #define SR_SFD_VALUE 0xb,0xff,0
+/** Offset for register TRX_CTRL_2 */
+#define RG_TRX_CTRL_2 (0xc)
+  /** Access parameters for sub-register RX_SAFE_MODE in register TRX_CTRL_2 */
+  #define SR_RX_SAFE_MODE 0xc,0x80,7
+  /** Access parameters for sub-register OQPSK_DATA_RATE in register TRX_CTRL_2 */
+  #define SR_OQPSK_DATA_RATE 0xc,0x3,0
+/** Offset for register ANT_DIV */
+#define RG_ANT_DIV (0xd)
+  /** Access parameters for sub-register ANT_SEL in register ANT_DIV */
+  #define SR_ANT_SEL 0xd,0x80,7
+  /** Access parameters for sub-register ANT_DIV_EN in register ANT_DIV */
+  #define SR_ANT_DIV_EN 0xd,0x8,3
+  /** Access parameters for sub-register ANT_EXT_SW_EN in register ANT_DIV */
+  #define SR_ANT_EXT_SW_EN 0xd,0x4,2
+  /** Access parameters for sub-register ANT_CTRL in register ANT_DIV */
+  #define SR_ANT_CTRL 0xd,0x3,0
+/** Offset for register IRQ_MASK */
+#define RG_IRQ_MASK (0xe)
+  /** Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK */
+  #define SR_MASK_BAT_LOW 0xe,0x80,7
+  /** Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK */
+  #define SR_MASK_TRX_UR 0xe,0x40,6
+  /** Access parameters for sub-register MASK_AMI in register IRQ_MASK */
+  #define SR_MASK_AMI 0xe,0x20,5
+  /** Access parameters for sub-register MASK_CCA_ED_READY in register IRQ_MASK */
+  #define SR_MASK_CCA_ED_READY 0xe,0x10,4
+  /** Access parameters for sub-register MASK_TRX_END in register IRQ_MASK */
+  #define SR_MASK_TRX_END 0xe,0x8,3
+  /** Access parameters for sub-register MASK_TRX_START in register IRQ_MASK */
+  #define SR_MASK_TRX_START 0xe,0x4,2
+  /** Access parameters for sub-register MASK_PLL_LOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_LOCK 0xe,0x1,0
+  /** Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
+/** Offset for register IRQ_STATUS */
+#define RG_IRQ_STATUS (0xf)
+  /** Access parameters for sub-register BAT_LOW in register IRQ_STATUS */
+  #define SR_BAT_LOW 0xf,0x80,7
+  /** Access parameters for sub-register TRX_UR in register IRQ_STATUS */
+  #define SR_TRX_UR 0xf,0x40,6
+  /** Access parameters for sub-register AMI in register IRQ_STATUS */
+  #define SR_AMI 0xf,0x20,5
+  /** Access parameters for sub-register CCA_ED_READY in register IRQ_STATUS */
+  #define SR_CCA_ED_READY 0xf,0x10,4
+  /** Access parameters for sub-register RX_END in register IRQ_STATUS */
+  #define SR_RX_END 0xf,0x8,3
+  /** Access parameters for sub-register RX_START in register IRQ_STATUS */
+  #define SR_RX_START 0xf,0x4,2
+  /** Access parameters for sub-register PLL_LOCK in register IRQ_STATUS */
+  #define SR_PLL_LOCK 0xf,0x1,0
+  /** Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS */
+  #define SR_PLL_UNLOCK 0xf,0x2,1
+/** Offset for register VREG_CTRL */
+#define RG_VREG_CTRL (0x10)
+  /** Access parameters for sub-register AVREG_EXT in register VREG_CTRL */
+  #define SR_AVREG_EXT 0x10,0x80,7
+  /** Access parameters for sub-register AVDD_OK in register VREG_CTRL */
+  #define SR_AVDD_OK 0x10,0x40,6
+  /** Access parameters for sub-register DVREG_EXT in register VREG_CTRL */
+  #define SR_DVREG_EXT 0x10,0x8,3
+  /** Access parameters for sub-register DVDD_OK in register VREG_CTRL */
+  #define SR_DVDD_OK 0x10,0x4,2
+/** Offset for register BATMON */
+#define RG_BATMON (0x11)
+  /** Access parameters for sub-register BATMON_OK in register BATMON */
+  #define SR_BATMON_OK 0x11,0x20,5
+  /** Access parameters for sub-register BATMON_HR in register BATMON */
+  #define SR_BATMON_HR 0x11,0x10,4
+  /** Access parameters for sub-register BATMON_VTH in register BATMON */
+  #define SR_BATMON_VTH 0x11,0xf,0
+/** Offset for register XOSC_CTRL */
+#define RG_XOSC_CTRL (0x12)
+  /** Access parameters for sub-register XTAL_MODE in register XOSC_CTRL */
+  #define SR_XTAL_MODE 0x12,0xf0,4
+  /** Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL */
+  #define SR_XTAL_TRIM 0x12,0xf,0
+/** Offset for register RX_SYN */
+#define RG_RX_SYN (0x15)
+  /** Access parameters for sub-register RX_PDT_DIS in register RX_SYN */
+  #define SR_RX_PDT_DIS 0x15,0x80,7
+  /** Access parameters for sub-register RX_PDT_LEVEL in register RX_SYN */
+  #define SR_RX_PDT_LEVEL 0x15,0xf,0
+/** Offset for register XAH_CTRL_1 */
+#define RG_XAH_CTRL_1 (0x17)
+  /** Access parameters for sub-register AACK_FLTR_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
+  /** Access parameters for sub-register AACK_UPLD_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
+  /** Access parameters for sub-register AACK_ACK_TIME in register XAH_CTRL_1 */
+  #define SR_AACK_ACK_TIME 0x17,0x4,2
+  /** Access parameters for sub-register AACK_PROM_MODE in register XAH_CTRL_1 */
+  #define SR_AACK_PROM_MODE 0x17,0x2,1
+/** Offset for register FTN_CTRL */
+#define RG_FTN_CTRL (0x18)
+  /** Access parameters for sub-register FTN_START in register FTN_CTRL */
+  #define SR_FTN_START 0x18,0x80,7
+/** Offset for register PLL_CF */
+#define RG_PLL_CF (0x1a)
+  /** Access parameters for sub-register PLL_CF_START in register PLL_CF */
+  #define SR_PLL_CF_START 0x1a,0x80,7
+/** Offset for register PLL_DCU */
+#define RG_PLL_DCU (0x1b)
+  /** Access parameters for sub-register PLL_DCU_START in register PLL_DCU */
+  #define SR_PLL_DCU_START 0x1b,0x80,7
+/** Offset for register PART_NUM */
+#define RG_PART_NUM (0x1c)
+  /** Access parameters for sub-register PART_NUM in register PART_NUM */
+  #define SR_PART_NUM 0x1c,0xff,0
+    #define RF231A_PART_NUM (3)
+/** Offset for register VERSION_NUM */
+#define RG_VERSION_NUM (0x1d)
+  /** Access parameters for sub-register VERSION_NUM in register VERSION_NUM */
+  #define SR_VERSION_NUM 0x1d,0xff,0
+    #define RF231A_VERSION_NUM (2)
+/** Offset for register MAN_ID_0 */
+#define RG_MAN_ID_0 (0x1e)
+  /** Access parameters for sub-register MAN_ID_0 in register MAN_ID_0 */
+  #define SR_MAN_ID_0 0x1e,0xff,0
+/** Offset for register MAN_ID_1 */
+#define RG_MAN_ID_1 (0x1f)
+  /** Access parameters for sub-register MAN_ID_1 in register MAN_ID_1 */
+  #define SR_MAN_ID_1 0x1f,0xff,0
+/** Offset for register SHORT_ADDR_0 */
+#define RG_SHORT_ADDR_0 (0x20)
+  /** Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0 */
+  #define SR_SHORT_ADDR_0 0x20,0xff,0
+/** Offset for register SHORT_ADDR_1 */
+#define RG_SHORT_ADDR_1 (0x21)
+  /** Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1 */
+  #define SR_SHORT_ADDR_1 0x21,0xff,0
+/** Offset for register PAN_ID_0 */
+#define RG_PAN_ID_0 (0x22)
+  /** Access parameters for sub-register PAN_ID_0 in register PAN_ID_0 */
+  #define SR_PAN_ID_0 0x22,0xff,0
+/** Offset for register PAN_ID_1 */
+#define RG_PAN_ID_1 (0x23)
+  /** Access parameters for sub-register PAN_ID_1 in register PAN_ID_1 */
+  #define SR_PAN_ID_1 0x23,0xff,0
+/** Offset for register IEEE_ADDR_0 */
+#define RG_IEEE_ADDR_0 (0x24)
+  /** Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0 */
+  #define SR_IEEE_ADDR_0 0x24,0xff,0
+/** Offset for register IEEE_ADDR_1 */
+#define RG_IEEE_ADDR_1 (0x25)
+  /** Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1 */
+  #define SR_IEEE_ADDR_1 0x25,0xff,0
+/** Offset for register IEEE_ADDR_2 */
+#define RG_IEEE_ADDR_2 (0x26)
+  /** Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2 */
+  #define SR_IEEE_ADDR_2 0x26,0xff,0
+/** Offset for register IEEE_ADDR_3 */
+#define RG_IEEE_ADDR_3 (0x27)
+  /** Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3 */
+  #define SR_IEEE_ADDR_3 0x27,0xff,0
+/** Offset for register IEEE_ADDR_4 */
+#define RG_IEEE_ADDR_4 (0x28)
+  /** Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4 */
+  #define SR_IEEE_ADDR_4 0x28,0xff,0
+/** Offset for register IEEE_ADDR_5 */
+#define RG_IEEE_ADDR_5 (0x29)
+  /** Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5 */
+  #define SR_IEEE_ADDR_5 0x29,0xff,0
+/** Offset for register IEEE_ADDR_6 */
+#define RG_IEEE_ADDR_6 (0x2a)
+  /** Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6 */
+  #define SR_IEEE_ADDR_6 0x2a,0xff,0
+/** Offset for register IEEE_ADDR_7 */
+#define RG_IEEE_ADDR_7 (0x2b)
+  /** Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7 */
+  #define SR_IEEE_ADDR_7 0x2b,0xff,0
+/** Offset for register XAH_CTRL_0 */
+#define RG_XAH_CTRL_0 (0x2c)
+  /** Access parameters for sub-register MAX_FRAME_RETRES in register XAH_CTRL_0 */
+  #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
+  /** Access parameters for sub-register SLOTTED_OPERATION in register XAH_CTRL_0 */
+  #define SR_SLOTTED_OPERATION 0x2c,0x1,0
+  /** Access parameters for sub-register MAX_CSMA_RETRES in register XAH_CTRL_0 */
+  #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
+/** Offset for register CSMA_SEED_0 */
+#define RG_CSMA_SEED_0 (0x2d)
+  /** Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0 */
+  #define SR_CSMA_SEED_0 0x2d,0xff,0
+/** Offset for register CSMA_SEED_1 */
+#define RG_CSMA_SEED_1 (0x2e)
+  /** Access parameters for sub-register AACK_FVN_MODE in register CSMA_SEED_1 */
+  #define SR_AACK_FVN_MODE 0x2e,0xc0,6
+  /** Access parameters for sub-register AACK_SET_PD in register CSMA_SEED_1 */
+  #define SR_AACK_SET_PD 0x2e,0x20,5
+  /** Access parameters for sub-register AACK_DIS_ACK in register CSMA_SEED_1 */
+  #define SR_AACK_DIS_ACK 0x2e,0x10,4
+  /** Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1 */
+  #define SR_AACK_I_AM_COORD 0x2e,0x8,3
+  /** Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1 */
+  #define SR_CSMA_SEED_1 0x2e,0x7,0
+/** Offset for register CSMA_BE */
+#define RG_CSMA_BE (0x2f)
+  /** Access parameters for sub-register MAX_BE in register CSMA_BE */
+  #define SR_MAX_BE 0x2f,0xf0,4
+  /** Access parameters for sub-register MIN_BE in register CSMA_BE */
+  #define SR_MIN_BE 0x2f,0xf,0
+/** name string of the radio */
+#define RADIO_NAME "AT86RF231"
+/** contents of the RG_PART_NUM register */
+#define RADIO_PART_NUM (RF231A_PART_NUM)
+/** contents of the RG_VERSION_NUM register */
+#define RADIO_VERSION_NUM (RF231A_VERSION_NUM)
+
+/** SPI command code for register write */
+#define TRX_CMD_RW           (_BV(7) | _BV(6))
+/** SPI command code for register read */
+#define TRX_CMD_RR           (_BV(7))
+/** SPI command code for frame write */
+#define TRX_CMD_FW           (_BV(6) | _BV(5))
+/** SPI command code for frame read */
+#define TRX_CMD_FR           (_BV(5))
+/** SPI command code for sram write */
+#define TRX_CMD_SW           (_BV(6))
+/** SPI command code for sram read */
+#define TRX_CMD_SR           (0)
+
+#define TRX_CMD_RADDR_MASK   (0x3f)
+
+/** duration while reset=low is asserted */
+#define TRX_RESET_TIME_US    (6)
+
+/** duration transceiver reaches TRX_OFF for the first time */
+#define TRX_INIT_TIME_US     (510)
+
+/** maximum duration, which PLL needs to lock */
+#define TRX_PLL_LOCK_TIME_US     (180)
+
+
+/** duration of a CCA measurement */
+#define TRX_CCA_TIME_US     (140)
+
+
+
+/** Mask for PLL lock interrupt */
+#define TRX_IRQ_PLL_LOCK   _BV(0)
+
+/** Mask for PLL unlock interrupt */
+#define TRX_IRQ_PLL_UNLOCK _BV(1)
+
+/** Mask for RX Start interrupt */
+#define TRX_IRQ_RX_START   _BV(2)
+
+/** Mask for RX/TX end interrupt */
+#define TRX_IRQ_TRX_END    _BV(3)
+
+/** Mask for CCA_ED interrupt */
+#define TRX_IRQ_CCA_ED     _BV(4)
+
+/** Mask for AMI interrupt */
+#define TRX_IRQ_AMI        _BV(5)
+
+/** Mask for RX/TX underrun interrupt */
+#define TRX_IRQ_UR         _BV(6)
+
+/** Mask for battery low interrupt */
+#define TRX_IRQ_BAT_LOW    _BV(7)
+
+/** TX ARET status for successful transmission */
+#define TRAC_SUCCESS (0)
+/** TX ARET status for unsuccessful transmission due to no channel access */
+#define TRAC_CHANNEL_ACCESS_FAILURE (3)
+/** TX ARET status for unsuccessful transmission due no ACK frame was received */
+#define TRAC_NO_ACK (5)
+
+
+/** lowest supported channel number */
+#define TRX_MIN_CHANNEL (11)
+
+/** highest supported channel number */
+#define TRX_MAX_CHANNEL (26)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (16)
+
+/**
+ * @brief Mask for supported channels of this radio.
+ * The AT86RF230 supports channels 11 ... 26 of IEEE 802.15.4
+ */
+#define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
+
+#define TRX_SUPPORTS_BAND_2400 (1)
+/**
+ * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
+ * The AT86RF230 supports channel page ???? OQPSK_250
+ */
+#define TRX_SUPPORTED_PAGES     (42)
+
+/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK250  (0)
+
+/** Rate code for OQPSK500, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK500  (1)
+
+/** Rate code for OQPSK1000, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK1000 (2)
+/** Rate code for OQPSK2000, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK2000 (3)
+/** undefined data rate */
+#define TRX_NONE      (255)
+
+#endif /* ifndef AT86RF231_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/at86rf232.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/at86rf232.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,459 @@
+/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf232.txt */
+
+/* Copyright (c) 2011 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief AT86RF232 2.4GHz IEEE 802.15.4-2006-Transceiver.
+ */
+#ifndef AT86RF232_H
+#define AT86RF232_H (1)
+#include <stdint.h>
+#define _BV(bit) (1 << (bit))
+
+/* === Includes ============================================================== */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+typedef uint8_t trx_ramaddr_t;
+typedef uint8_t trx_regval_t;
+typedef uint8_t trx_regaddr_t;
+
+/* === Macros ================================================================ */
+/** Offset for register TRX_STATUS */
+#define RG_TRX_STATUS (0x1)
+  /** Access parameters for sub-register CCA_DONE in register TRX_STATUS */
+  #define SR_CCA_DONE 0x1,0x80,7
+  /** Access parameters for sub-register CCA_STATUS in register TRX_STATUS */
+  #define SR_CCA_STATUS 0x1,0x40,6
+  /** Access parameters for sub-register TRX_STATUS in register TRX_STATUS */
+  #define SR_TRX_STATUS 0x1,0x1f,0
+    #define P_ON (0)
+    #define BUSY_RX (1)
+    #define BUSY_TX (2)
+    #define RX_ON (6)
+    #define TRX_OFF (8)
+    #define PLL_ON (9)
+    #define TRX_SLEEP (15)
+    #define BUSY_RX_AACK (17)
+    #define BUSY_TX_ARET (18)
+    #define RX_AACK_ON (22)
+    #define TX_ARET_ON (25)
+    #define RX_ON_NOCLK (28)
+    #define RX_AACK_ON_NOCLK (29)
+    #define BUSY_RX_AACK_NOCLK (30)
+/** Offset for register TRX_STATE */
+#define RG_TRX_STATE (0x2)
+  /** Access parameters for sub-register TRAC_STATUS in register TRX_STATE */
+  #define SR_TRAC_STATUS 0x2,0xe0,5
+    #define TRAC_SUCCESS (0)
+    #define TRAC_SUCCESS_DATA_PENDING (1)
+    #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
+    #define TRAC_CHANNEL_ACCESS_FAILURE (3)
+    #define TRAC_NO_ACK (5)
+    #define TRAC_INVALID (7)
+  /** Access parameters for sub-register TRX_CMD in register TRX_STATE */
+  #define SR_TRX_CMD 0x2,0x1f,0
+    #define CMD_NOP (0)
+    #define CMD_TX_START (2)
+    #define CMD_FORCE_TRX_OFF (3)
+    #define CMD_RX_ON (6)
+    #define CMD_TRX_OFF (8)
+    #define CMD_PLL_ON (9)
+    #define CMD_RX_AACK_ON (22)
+    #define CMD_TX_ARET_ON (25)
+/** Offset for register TRX_CTRL_0 */
+#define RG_TRX_CTRL_0 (0x3)
+  /** Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0 */
+  #define SR_CLKM_SHA_SEL 0x3,0x8,3
+  /** Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0 */
+  #define SR_CLKM_CTRL 0x3,0x7,0
+    #define CLKM_no_clock (0)
+    #define CLKM_1MHz (1)
+    #define CLKM_2MHz (2)
+    #define CLKM_4MHz (3)
+    #define CLKM_8MHz (4)
+    #define CLKM_16MHz (5)
+/** Offset for register TRX_CTRL_1 */
+#define RG_TRX_CTRL_1 (0x4)
+  /** Access parameters for sub-register IRQ_2_EXT_EN in register TRX_CTRL_1 */
+  #define SR_IRQ_2_EXT_EN 0x4,0x40,6
+  /** Access parameters for sub-register TX_AUTO_CRC_ON in register TRX_CTRL_1 */
+  #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
+  /** Access parameters for sub-register RX_BL_CTRL in register TRX_CTRL_1 */
+  #define SR_RX_BL_CTRL 0x4,0x10,4
+  /** Access parameters for sub-register SPI_CMD_MODE in register TRX_CTRL_1 */
+  #define SR_SPI_CMD_MODE 0x4,0xc,2
+  /** Access parameters for sub-register IRQ_POLARITY in register TRX_CTRL_1 */
+  #define SR_IRQ_POLARITY 0x4,0x1,0
+  /** Access parameters for sub-register IRQ_MASK_MODE in register TRX_CTRL_1 */
+  #define SR_IRQ_MASK_MODE 0x4,0x2,1
+/** Offset for register PHY_TX_PWR */
+#define RG_PHY_TX_PWR (0x5)
+  /** Access parameters for sub-register TX_PWR in register PHY_TX_PWR */
+  #define SR_TX_PWR 0x5,0xf,0
+/** Offset for register PHY_RSSI */
+#define RG_PHY_RSSI (0x6)
+  /** Access parameters for sub-register RX_CRC_VALID in register PHY_RSSI */
+  #define SR_RX_CRC_VALID 0x6,0x80,7
+  /** Access parameters for sub-register RND_VALUE in register PHY_RSSI */
+  #define SR_RND_VALUE 0x6,0x60,5
+  /** Access parameters for sub-register RSSI in register PHY_RSSI */
+  #define SR_RSSI 0x6,0x1f,0
+/** Offset for register PHY_ED_LEVEL */
+#define RG_PHY_ED_LEVEL (0x7)
+  /** Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL */
+  #define SR_ED_LEVEL 0x7,0xff,0
+/** Offset for register PHY_CC_CCA */
+#define RG_PHY_CC_CCA (0x8)
+  /** Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA */
+  #define SR_CCA_REQUEST 0x8,0x80,7
+  /** Access parameters for sub-register CCA_MODE in register PHY_CC_CCA */
+  #define SR_CCA_MODE 0x8,0x60,5
+  /** Access parameters for sub-register CHANNEL in register PHY_CC_CCA */
+  #define SR_CHANNEL 0x8,0x1f,0
+/** Offset for register CCA_THRES */
+#define RG_CCA_THRES (0x9)
+  /** Access parameters for sub-register CCA_ED_THRES in register CCA_THRES */
+  #define SR_CCA_ED_THRES 0x9,0xf,0
+/** Offset for register RX_CTRL */
+#define RG_RX_CTRL (0xa)
+  /** Access parameters for sub-register PDT_THRES in register RX_CTRL */
+  #define SR_PDT_THRES 0xa,0xf,0
+/** Offset for register TRX_CTRL_2 */
+#define RG_TRX_CTRL_2 (0xc)
+  /** Access parameters for sub-register RX_SAFE_MODE in register TRX_CTRL_2 */
+  #define SR_RX_SAFE_MODE 0xc,0x80,7
+/** Offset for register ANT_DIV */
+#define RG_ANT_DIV (0xd)
+  /** Access parameters for sub-register ANT_SEL in register ANT_DIV */
+  #define SR_ANT_SEL 0xd,0x80,7
+  /** Access parameters for sub-register ANT_DIV_EN in register ANT_DIV */
+  #define SR_ANT_DIV_EN 0xd,0x8,3
+  /** Access parameters for sub-register ANT_EXT_SW_EN in register ANT_DIV */
+  #define SR_ANT_EXT_SW_EN 0xd,0x4,2
+  /** Access parameters for sub-register ANT_CTRL in register ANT_DIV */
+  #define SR_ANT_CTRL 0xd,0x3,0
+/** Offset for register IRQ_MASK */
+#define RG_IRQ_MASK (0xe)
+  /** Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK */
+  #define SR_MASK_BAT_LOW 0xe,0x80,7
+  /** Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK */
+  #define SR_MASK_TRX_UR 0xe,0x40,6
+  /** Access parameters for sub-register MASK_AMI in register IRQ_MASK */
+  #define SR_MASK_AMI 0xe,0x20,5
+  /** Access parameters for sub-register MASK_CCA_ED_READY in register IRQ_MASK */
+  #define SR_MASK_CCA_ED_READY 0xe,0x10,4
+  /** Access parameters for sub-register MASK_TRX_END in register IRQ_MASK */
+  #define SR_MASK_TRX_END 0xe,0x8,3
+  /** Access parameters for sub-register MASK_TRX_START in register IRQ_MASK */
+  #define SR_MASK_TRX_START 0xe,0x4,2
+  /** Access parameters for sub-register MASK_PLL_LOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_LOCK 0xe,0x1,0
+  /** Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
+/** Offset for register IRQ_STATUS */
+#define RG_IRQ_STATUS (0xf)
+  /** Access parameters for sub-register BAT_LOW in register IRQ_STATUS */
+  #define SR_BAT_LOW 0xf,0x80,7
+  /** Access parameters for sub-register TRX_UR in register IRQ_STATUS */
+  #define SR_TRX_UR 0xf,0x40,6
+  /** Access parameters for sub-register AMI in register IRQ_STATUS */
+  #define SR_AMI 0xf,0x20,5
+  /** Access parameters for sub-register CCA_ED_READY in register IRQ_STATUS */
+  #define SR_CCA_ED_READY 0xf,0x10,4
+  /** Access parameters for sub-register RX_END in register IRQ_STATUS */
+  #define SR_RX_END 0xf,0x8,3
+  /** Access parameters for sub-register RX_START in register IRQ_STATUS */
+  #define SR_RX_START 0xf,0x4,2
+  /** Access parameters for sub-register PLL_LOCK in register IRQ_STATUS */
+  #define SR_PLL_LOCK 0xf,0x1,0
+  /** Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS */
+  #define SR_PLL_UNLOCK 0xf,0x2,1
+/** Offset for register VREG_CTRL */
+#define RG_VREG_CTRL (0x10)
+  /** Access parameters for sub-register AVREG_EXT in register VREG_CTRL */
+  #define SR_AVREG_EXT 0x10,0x80,7
+  /** Access parameters for sub-register AVDD_OK in register VREG_CTRL */
+  #define SR_AVDD_OK 0x10,0x40,6
+  /** Access parameters for sub-register DVREG_EXT in register VREG_CTRL */
+  #define SR_DVREG_EXT 0x10,0x8,3
+  /** Access parameters for sub-register DVDD_OK in register VREG_CTRL */
+  #define SR_DVDD_OK 0x10,0x4,2
+/** Offset for register BATMON */
+#define RG_BATMON (0x11)
+  /** Access parameters for sub-register BATMON_OK in register BATMON */
+  #define SR_BATMON_OK 0x11,0x20,5
+  /** Access parameters for sub-register BATMON_HR in register BATMON */
+  #define SR_BATMON_HR 0x11,0x10,4
+  /** Access parameters for sub-register BATMON_VTH in register BATMON */
+  #define SR_BATMON_VTH 0x11,0xf,0
+/** Offset for register XOSC_CTRL */
+#define RG_XOSC_CTRL (0x12)
+  /** Access parameters for sub-register XTAL_MODE in register XOSC_CTRL */
+  #define SR_XTAL_MODE 0x12,0xf0,4
+  /** Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL */
+  #define SR_XTAL_TRIM 0x12,0xf,0
+/** Offset for register RX_SYN */
+#define RG_RX_SYN (0x15)
+  /** Access parameters for sub-register RX_PDT_DIS in register RX_SYN */
+  #define SR_RX_PDT_DIS 0x15,0x80,7
+  /** Access parameters for sub-register RX_PDT_LEVEL in register RX_SYN */
+  #define SR_RX_PDT_LEVEL 0x15,0xf,0
+/** Offset for register XAH_CTRL_1 */
+#define RG_XAH_CTRL_1 (0x17)
+  /** Access parameters for sub-register ARET_TX_TS in register XAH_CTRL_1 */
+  #define SR_ARET_TX_TS 0x17,0x80,7
+  /** Access parameters for sub-register AACK_FLTR_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
+  /** Access parameters for sub-register AACK_UPLD_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
+  /** Access parameters for sub-register AACK_ACK_TIME in register XAH_CTRL_1 */
+  #define SR_AACK_ACK_TIME 0x17,0x4,2
+  /** Access parameters for sub-register AACK_PROM_MODE in register XAH_CTRL_1 */
+  #define SR_AACK_PROM_MODE 0x17,0x2,1
+/** Offset for register FTN_CTRL */
+#define RG_FTN_CTRL (0x18)
+  /** Access parameters for sub-register FTN_START in register FTN_CTRL */
+  #define SR_FTN_START 0x18,0x80,7
+/** Offset for register XAH_CTRL_2 */
+#define RG_XAH_CTRL_2 (0x19)
+  /** Access parameters for sub-register ARET_FRAME_RETRIES in register XAH_CTRL_2 */
+  #define SR_ARET_FRAME_RETRIES 0x19,0xf0,4
+  /** Access parameters for sub-register ARET_CSMA_RETRIES in register XAH_CTRL_2 */
+  #define SR_ARET_CSMA_RETRIES 0x19,0xe,1
+/** Offset for register PLL_CF */
+#define RG_PLL_CF (0x1a)
+  /** Access parameters for sub-register PLL_CF_START in register PLL_CF */
+  #define SR_PLL_CF_START 0x1a,0x80,7
+  /** Access parameters for sub-register PLL_CF in register PLL_CF */
+  #define SR_PLL_CF 0x1a,0xf,0
+/** Offset for register PLL_DCU */
+#define RG_PLL_DCU (0x1b)
+  /** Access parameters for sub-register PLL_DCU_START in register PLL_DCU */
+  #define SR_PLL_DCU_START 0x1b,0x80,7
+/** Offset for register PART_NUM */
+#define RG_PART_NUM (0x1c)
+  /** Access parameters for sub-register PART_NUM in register PART_NUM */
+  #define SR_PART_NUM 0x1c,0xff,0
+    #define RF232_PART_NUM (10)
+/** Offset for register VERSION_NUM */
+#define RG_VERSION_NUM (0x1d)
+  /** Access parameters for sub-register VERSION_NUM in register VERSION_NUM */
+  #define SR_VERSION_NUM 0x1d,0xff,0
+    #define RF232_VERSION_NUM (2)
+/** Offset for register MAN_ID_0 */
+#define RG_MAN_ID_0 (0x1e)
+  /** Access parameters for sub-register MAN_ID_0 in register MAN_ID_0 */
+  #define SR_MAN_ID_0 0x1e,0xff,0
+/** Offset for register MAN_ID_1 */
+#define RG_MAN_ID_1 (0x1f)
+  /** Access parameters for sub-register MAN_ID_1 in register MAN_ID_1 */
+  #define SR_MAN_ID_1 0x1f,0xff,0
+/** Offset for register SHORT_ADDR_0 */
+#define RG_SHORT_ADDR_0 (0x20)
+  /** Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0 */
+  #define SR_SHORT_ADDR_0 0x20,0xff,0
+/** Offset for register SHORT_ADDR_1 */
+#define RG_SHORT_ADDR_1 (0x21)
+  /** Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1 */
+  #define SR_SHORT_ADDR_1 0x21,0xff,0
+/** Offset for register PAN_ID_0 */
+#define RG_PAN_ID_0 (0x22)
+  /** Access parameters for sub-register PAN_ID_0 in register PAN_ID_0 */
+  #define SR_PAN_ID_0 0x22,0xff,0
+/** Offset for register PAN_ID_1 */
+#define RG_PAN_ID_1 (0x23)
+  /** Access parameters for sub-register PAN_ID_1 in register PAN_ID_1 */
+  #define SR_PAN_ID_1 0x23,0xff,0
+/** Offset for register IEEE_ADDR_0 */
+#define RG_IEEE_ADDR_0 (0x24)
+  /** Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0 */
+  #define SR_IEEE_ADDR_0 0x24,0xff,0
+/** Offset for register IEEE_ADDR_1 */
+#define RG_IEEE_ADDR_1 (0x25)
+  /** Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1 */
+  #define SR_IEEE_ADDR_1 0x25,0xff,0
+/** Offset for register IEEE_ADDR_2 */
+#define RG_IEEE_ADDR_2 (0x26)
+  /** Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2 */
+  #define SR_IEEE_ADDR_2 0x26,0xff,0
+/** Offset for register IEEE_ADDR_3 */
+#define RG_IEEE_ADDR_3 (0x27)
+  /** Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3 */
+  #define SR_IEEE_ADDR_3 0x27,0xff,0
+/** Offset for register IEEE_ADDR_4 */
+#define RG_IEEE_ADDR_4 (0x28)
+  /** Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4 */
+  #define SR_IEEE_ADDR_4 0x28,0xff,0
+/** Offset for register IEEE_ADDR_5 */
+#define RG_IEEE_ADDR_5 (0x29)
+  /** Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5 */
+  #define SR_IEEE_ADDR_5 0x29,0xff,0
+/** Offset for register IEEE_ADDR_6 */
+#define RG_IEEE_ADDR_6 (0x2a)
+  /** Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6 */
+  #define SR_IEEE_ADDR_6 0x2a,0xff,0
+/** Offset for register IEEE_ADDR_7 */
+#define RG_IEEE_ADDR_7 (0x2b)
+  /** Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7 */
+  #define SR_IEEE_ADDR_7 0x2b,0xff,0
+/** Offset for register XAH_CTRL_0 */
+#define RG_XAH_CTRL_0 (0x2c)
+  /** Access parameters for sub-register MAX_FRAME_RETRES in register XAH_CTRL_0 */
+  #define SR_MAX_FRAME_RETRES 0x2c,0xf0,4
+  /** Access parameters for sub-register SLOTTED_OPERATION in register XAH_CTRL_0 */
+  #define SR_SLOTTED_OPERATION 0x2c,0x1,0
+  /** Access parameters for sub-register MAX_CSMA_RETRES in register XAH_CTRL_0 */
+  #define SR_MAX_CSMA_RETRES 0x2c,0xe,1
+/** Offset for register CSMA_SEED_0 */
+#define RG_CSMA_SEED_0 (0x2d)
+  /** Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0 */
+  #define SR_CSMA_SEED_0 0x2d,0xff,0
+/** Offset for register CSMA_SEED_1 */
+#define RG_CSMA_SEED_1 (0x2e)
+  /** Access parameters for sub-register AACK_FVN_MODE in register CSMA_SEED_1 */
+  #define SR_AACK_FVN_MODE 0x2e,0xc0,6
+  /** Access parameters for sub-register AACK_SET_PD in register CSMA_SEED_1 */
+  #define SR_AACK_SET_PD 0x2e,0x20,5
+  /** Access parameters for sub-register AACK_DIS_ACK in register CSMA_SEED_1 */
+  #define SR_AACK_DIS_ACK 0x2e,0x10,4
+  /** Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1 */
+  #define SR_AACK_I_AM_COORD 0x2e,0x8,3
+  /** Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1 */
+  #define SR_CSMA_SEED_1 0x2e,0x7,0
+/** Offset for register CSMA_BE */
+#define RG_CSMA_BE (0x2f)
+  /** Access parameters for sub-register MAX_BE in register CSMA_BE */
+  #define SR_MAX_BE 0x2f,0xf0,4
+  /** Access parameters for sub-register MIN_BE in register CSMA_BE */
+  #define SR_MIN_BE 0x2f,0xf,0
+/** Offset for register TST_CTRL_DIGI */
+#define RG_TST_CTRL_DIGI (0x36)
+  /** Access parameters for sub-register TST_CTRL_DIG in register TST_CTRL_DIGI */
+  #define SR_TST_CTRL_DIG 0x36,0xf,0
+/** name string of the radio */
+#define RADIO_NAME "AT86RF232"
+/** contents of the RG_PART_NUM register */
+#define RADIO_PART_NUM (RF232_PART_NUM)
+/** contents of the RG_VERSION_NUM register */
+#define RADIO_VERSION_NUM (RF232_VERSION_NUM)
+
+/** SPI command code for register write */
+#define TRX_CMD_RW           (_BV(7) | _BV(6))
+/** SPI command code for register read */
+#define TRX_CMD_RR           (_BV(7))
+/** SPI command code for frame write */
+#define TRX_CMD_FW           (_BV(6) | _BV(5))
+/** SPI command code for frame read */
+#define TRX_CMD_FR           (_BV(5))
+/** SPI command code for sram write */
+#define TRX_CMD_SW           (_BV(6))
+/** SPI command code for sram read */
+#define TRX_CMD_SR           (0)
+
+#define TRX_CMD_RADDR_MASK   (0x3f)
+
+/** duration while reset=low is asserted */
+#define TRX_RESET_TIME_US    (6)
+
+/** duration transceiver reaches TRX_OFF for the first time */
+#define TRX_INIT_TIME_US     (510)
+
+/** maximum duration, which PLL needs to lock */
+#define TRX_PLL_LOCK_TIME_US     (180)
+
+
+/** duration of a CCA measurement */
+#define TRX_CCA_TIME_US     (140)
+
+/** Mask for PLL lock interrupt */
+#define TRX_IRQ_PLL_LOCK   _BV(0)
+
+/** Mask for PLL unlock interrupt */
+#define TRX_IRQ_PLL_UNLOCK _BV(1)
+
+/** Mask for RX Start interrupt */
+#define TRX_IRQ_RX_START   _BV(2)
+
+/** Mask for RX/TX end interrupt */
+#define TRX_IRQ_TRX_END    _BV(3)
+
+/** Mask for CCA_ED interrupt */
+#define TRX_IRQ_CCA_ED     _BV(4)
+
+/** Mask for AMI interrupt */
+#define TRX_IRQ_AMI        _BV(5)
+
+/** Mask for RX/TX underrun interrupt */
+#define TRX_IRQ_UR         _BV(6)
+
+/** Mask for battery low interrupt */
+#define TRX_IRQ_BAT_LOW    _BV(7)
+
+/** TX ARET status for successful transmission */
+#define TRAC_SUCCESS (0)
+/** TX ARET status for unsuccessful transmission due to no channel access */
+#define TRAC_CHANNEL_ACCESS_FAILURE (3)
+/** TX ARET status for unsuccessful transmission due no ACK frame was received */
+#define TRAC_NO_ACK (5)
+
+
+/** lowest supported channel number */
+#define TRX_MIN_CHANNEL (11)
+
+/** highest supported channel number */
+#define TRX_MAX_CHANNEL (26)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (16)
+
+/**
+ * @brief Mask for supported channels of this radio.
+ * The AT86RF232 supports channels 11 ... 26 of IEEE 802.15.4
+ */
+#define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
+
+#define TRX_SUPPORTS_BAND_2400 (1)
+/**
+ * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
+ * The AT86RF230 supports channel page ???? OQPSK_250
+ */
+#define TRX_SUPPORTED_PAGES     (42)
+
+/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK250  (0)
+
+/** undefined data rate */
+#define TRX_NONE      (255)
+
+#endif /* ifndef AT86RF232_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/at86rf233.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/at86rf233.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,494 @@
+/* THIS FILE IS GENERATED by ds2reg.py FROM INPUT Templates/at86rf233.txt */
+
+/* Copyright (c) 2011 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief AT86RF233 2.4GHz IEEE 802.15.4-2006-Transceiver.
+ */
+#ifndef AT86RF233_H
+#define AT86RF233_H (1)
+#include <stdint.h>
+#define _BV(bit) (1 << (bit))
+/* === Includes ============================================================== */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+typedef uint8_t trx_ramaddr_t;
+typedef uint8_t trx_regval_t;
+typedef uint8_t trx_regaddr_t;
+
+/* === Macros ================================================================ */
+/** Offset for register TRX_STATUS */
+#define RG_TRX_STATUS (0x1)
+  /** Access parameters for sub-register CCA_DONE in register TRX_STATUS */
+  #define SR_CCA_DONE 0x1,0x80,7
+  /** Access parameters for sub-register CCA_STATUS in register TRX_STATUS */
+  #define SR_CCA_STATUS 0x1,0x40,6
+  /** Access parameters for sub-register TRX_STATUS in register TRX_STATUS */
+  #define SR_TRX_STATUS 0x1,0x1f,0
+    #define P_ON (0)
+    #define BUSY_RX (1)
+    #define BUSY_TX (2)
+    #define RX_ON (6)
+    #define TRX_OFF (8)
+    #define PLL_ON (9)
+    #define TRX_SLEEP (15)
+    #define BUSY_RX_AACK (17)
+    #define BUSY_TX_ARET (18)
+    #define RX_AACK_ON (22)
+    #define TX_ARET_ON (25)
+    #define RX_ON_NOCLK (28)
+    #define RX_AACK_ON_NOCLK (29)
+    #define BUSY_RX_AACK_NOCLK (30)
+/** Offset for register TRX_STATE */
+#define RG_TRX_STATE (0x2)
+  /** Access parameters for sub-register TRAC_STATUS in register TRX_STATE */
+  #define SR_TRAC_STATUS 0x2,0xe0,5
+    #define TRAC_SUCCESS (0)
+    #define TRAC_SUCCESS_DATA_PENDING (1)
+    #define TRAC_SUCCESS_WAIT_FOR_ACK (2)
+    #define TRAC_CHANNEL_ACCESS_FAILURE (3)
+    #define TRAC_NO_ACK (5)
+    #define TRAC_INVALID (7)
+  /** Access parameters for sub-register TRX_CMD in register TRX_STATE */
+  #define SR_TRX_CMD 0x2,0x1f,0
+    #define CMD_NOP (0)
+    #define CMD_TX_START (2)
+    #define CMD_FORCE_TRX_OFF (3)
+    #define CMD_RX_ON (6)
+    #define CMD_TRX_OFF (8)
+    #define CMD_PLL_ON (9)
+    #define CMD_RX_AACK_ON (22)
+    #define CMD_TX_ARET_ON (25)
+/** Offset for register TRX_CTRL_0 */
+#define RG_TRX_CTRL_0 (0x3)
+  /** Access parameters for sub-register CLKM_SHA_SEL in register TRX_CTRL_0 */
+  #define SR_CLKM_SHA_SEL 0x3,0x8,3
+  /** Access parameters for sub-register CLKM_CTRL in register TRX_CTRL_0 */
+  #define SR_CLKM_CTRL 0x3,0x7,0
+    #define CLKM_no_clock (0)
+    #define CLKM_1MHz (1)
+    #define CLKM_2MHz (2)
+    #define CLKM_4MHz (3)
+    #define CLKM_8MHz (4)
+    #define CLKM_16MHz (5)
+    #define CLKM_250kHz (6)
+    #define CLKM_62500Hz (7)
+/** Offset for register TRX_CTRL_1 */
+#define RG_TRX_CTRL_1 (0x4)
+  /** Access parameters for sub-register PA_EXT_EN in register TRX_CTRL_1 */
+  #define SR_PA_EXT_EN 0x4,0x80,7
+  /** Access parameters for sub-register IRQ_2_EXT_EN in register TRX_CTRL_1 */
+  #define SR_IRQ_2_EXT_EN 0x4,0x40,6
+  /** Access parameters for sub-register TX_AUTO_CRC_ON in register TRX_CTRL_1 */
+  #define SR_TX_AUTO_CRC_ON 0x4,0x20,5
+  /** Access parameters for sub-register RX_BL_CTRL in register TRX_CTRL_1 */
+  #define SR_RX_BL_CTRL 0x4,0x10,4
+  /** Access parameters for sub-register SPI_CMD_MODE in register TRX_CTRL_1 */
+  #define SR_SPI_CMD_MODE 0x4,0xc,2
+  /** Access parameters for sub-register IRQ_POLARITY in register TRX_CTRL_1 */
+  #define SR_IRQ_POLARITY 0x4,0x1,0
+  /** Access parameters for sub-register IRQ_MASK_MODE in register TRX_CTRL_1 */
+  #define SR_IRQ_MASK_MODE 0x4,0x2,1
+/** Offset for register PHY_TX_PWR */
+#define RG_PHY_TX_PWR (0x5)
+  /** Access parameters for sub-register TX_PWR in register PHY_TX_PWR */
+  #define SR_TX_PWR 0x5,0xf,0
+/** Offset for register PHY_RSSI */
+#define RG_PHY_RSSI (0x6)
+  /** Access parameters for sub-register RX_CRC_VALID in register PHY_RSSI */
+  #define SR_RX_CRC_VALID 0x6,0x80,7
+  /** Access parameters for sub-register RND_VALUE in register PHY_RSSI */
+  #define SR_RND_VALUE 0x6,0x60,5
+  /** Access parameters for sub-register RSSI in register PHY_RSSI */
+  #define SR_RSSI 0x6,0x1f,0
+/** Offset for register PHY_ED_LEVEL */
+#define RG_PHY_ED_LEVEL (0x7)
+  /** Access parameters for sub-register ED_LEVEL in register PHY_ED_LEVEL */
+  #define SR_ED_LEVEL 0x7,0xff,0
+/** Offset for register PHY_CC_CCA */
+#define RG_PHY_CC_CCA (0x8)
+  /** Access parameters for sub-register CCA_REQUEST in register PHY_CC_CCA */
+  #define SR_CCA_REQUEST 0x8,0x80,7
+  /** Access parameters for sub-register CCA_MODE in register PHY_CC_CCA */
+  #define SR_CCA_MODE 0x8,0x60,5
+  /** Access parameters for sub-register CHANNEL in register PHY_CC_CCA */
+  #define SR_CHANNEL 0x8,0x1f,0
+/** Offset for register CCA_THRES */
+#define RG_CCA_THRES (0x9)
+  /** Access parameters for sub-register CCA_ED_THRES in register CCA_THRES */
+  #define SR_CCA_ED_THRES 0x9,0xf,0
+/** Offset for register RX_CTRL */
+#define RG_RX_CTRL (0xa)
+  /** Access parameters for sub-register PDT_THRES in register RX_CTRL */
+  #define SR_PDT_THRES 0xa,0xf,0
+/** Offset for register SFD_VALUE */
+#define RG_SFD_VALUE (0xb)
+  /** Access parameters for sub-register SFD_VALUE in register SFD_VALUE */
+  #define SR_SFD_VALUE 0xb,0xff,0
+/** Offset for register TRX_CTRL_2 */
+#define RG_TRX_CTRL_2 (0xc)
+  /** Access parameters for sub-register RX_SAFE_MODE in register TRX_CTRL_2 */
+  #define SR_RX_SAFE_MODE 0xc,0x80,7
+  /** Access parameters for sub-register OQPSK_SCRAM_EN in register TRX_CTRL_2 */
+  #define SR_OQPSK_SCRAM_EN 0xc,0x20,5
+  /** Access parameters for sub-register OQPSK_DATA_RATE in register TRX_CTRL_2 */
+  #define SR_OQPSK_DATA_RATE 0xc,0x7,0
+/** Offset for register ANT_DIV */
+#define RG_ANT_DIV (0xd)
+  /** Access parameters for sub-register ANT_SEL in register ANT_DIV */
+  #define SR_ANT_SEL 0xd,0x80,7
+  /** Access parameters for sub-register ANT_DIV_EN in register ANT_DIV */
+  #define SR_ANT_DIV_EN 0xd,0x8,3
+  /** Access parameters for sub-register ANT_EXT_SW_EN in register ANT_DIV */
+  #define SR_ANT_EXT_SW_EN 0xd,0x4,2
+  /** Access parameters for sub-register ANT_CTRL in register ANT_DIV */
+  #define SR_ANT_CTRL 0xd,0x3,0
+/** Offset for register IRQ_MASK */
+#define RG_IRQ_MASK (0xe)
+  /** Access parameters for sub-register MASK_BAT_LOW in register IRQ_MASK */
+  #define SR_MASK_BAT_LOW 0xe,0x80,7
+  /** Access parameters for sub-register MASK_TRX_UR in register IRQ_MASK */
+  #define SR_MASK_TRX_UR 0xe,0x40,6
+  /** Access parameters for sub-register MASK_AMI in register IRQ_MASK */
+  #define SR_MASK_AMI 0xe,0x20,5
+  /** Access parameters for sub-register MASK_CCA_ED_READY in register IRQ_MASK */
+  #define SR_MASK_CCA_ED_READY 0xe,0x10,4
+  /** Access parameters for sub-register MASK_TRX_END in register IRQ_MASK */
+  #define SR_MASK_TRX_END 0xe,0x8,3
+  /** Access parameters for sub-register MASK_TRX_START in register IRQ_MASK */
+  #define SR_MASK_TRX_START 0xe,0x4,2
+  /** Access parameters for sub-register MASK_PLL_LOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_LOCK 0xe,0x1,0
+  /** Access parameters for sub-register MASK_PLL_UNLOCK in register IRQ_MASK */
+  #define SR_MASK_PLL_UNLOCK 0xe,0x2,1
+/** Offset for register IRQ_STATUS */
+#define RG_IRQ_STATUS (0xf)
+  /** Access parameters for sub-register BAT_LOW in register IRQ_STATUS */
+  #define SR_BAT_LOW 0xf,0x80,7
+  /** Access parameters for sub-register TRX_UR in register IRQ_STATUS */
+  #define SR_TRX_UR 0xf,0x40,6
+  /** Access parameters for sub-register AMI in register IRQ_STATUS */
+  #define SR_AMI 0xf,0x20,5
+  /** Access parameters for sub-register CCA_ED_READY in register IRQ_STATUS */
+  #define SR_CCA_ED_READY 0xf,0x10,4
+  /** Access parameters for sub-register RX_END in register IRQ_STATUS */
+  #define SR_RX_END 0xf,0x8,3
+  /** Access parameters for sub-register RX_START in register IRQ_STATUS */
+  #define SR_RX_START 0xf,0x4,2
+  /** Access parameters for sub-register PLL_LOCK in register IRQ_STATUS */
+  #define SR_PLL_LOCK 0xf,0x1,0
+  /** Access parameters for sub-register PLL_UNLOCK in register IRQ_STATUS */
+  #define SR_PLL_UNLOCK 0xf,0x2,1
+/** Offset for register VREG_CTRL */
+#define RG_VREG_CTRL (0x10)
+  /** Access parameters for sub-register AVREG_EXT in register VREG_CTRL */
+  #define SR_AVREG_EXT 0x10,0x80,7
+  /** Access parameters for sub-register AVDD_OK in register VREG_CTRL */
+  #define SR_AVDD_OK 0x10,0x40,6
+  /** Access parameters for sub-register DVREG_EXT in register VREG_CTRL */
+  #define SR_DVREG_EXT 0x10,0x8,3
+  /** Access parameters for sub-register DVDD_OK in register VREG_CTRL */
+  #define SR_DVDD_OK 0x10,0x4,2
+/** Offset for register BATMON */
+#define RG_BATMON (0x11)
+  /** Access parameters for sub-register BATMON_OK in register BATMON */
+  #define SR_BATMON_OK 0x11,0x20,5
+  /** Access parameters for sub-register BATMON_HR in register BATMON */
+  #define SR_BATMON_HR 0x11,0x10,4
+  /** Access parameters for sub-register BATMON_VTH in register BATMON */
+  #define SR_BATMON_VTH 0x11,0xf,0
+/** Offset for register XOSC_CTRL */
+#define RG_XOSC_CTRL (0x12)
+  /** Access parameters for sub-register XTAL_MODE in register XOSC_CTRL */
+  #define SR_XTAL_MODE 0x12,0xf0,4
+  /** Access parameters for sub-register XTAL_TRIM in register XOSC_CTRL */
+  #define SR_XTAL_TRIM 0x12,0xf,0
+/** Offset for register CC_CTRL_0 */
+#define RG_CC_CTRL_0 (0x13)
+  /** Access parameters for sub-register CC_NUMBER in register CC_CTRL_0 */
+  #define SR_CC_NUMBER 0x13,0xff,0
+/** Offset for register CC_CTRL_1 */
+#define RG_CC_CTRL_1 (0x14)
+  /** Access parameters for sub-register CC_BAND in register CC_CTRL_1 */
+  #define SR_CC_BAND 0x14,0xf,0
+/** Offset for register RX_SYN */
+#define RG_RX_SYN (0x15)
+  /** Access parameters for sub-register RX_PDT_DIS in register RX_SYN */
+  #define SR_RX_PDT_DIS 0x15,0x80,7
+  /** Access parameters for sub-register RX_PDT_LEVEL in register RX_SYN */
+  #define SR_RX_PDT_LEVEL 0x15,0xf,0
+/** Offset for register TRX_RPC */
+#define RG_TRX_RPC (0x16)
+  /** Access parameters for sub-register RX_RPC_CTRL in register TRX_RPC */
+  #define SR_RX_RPC_CTRL 0x16,0xc0,6
+  /** Access parameters for sub-register RX_RPC_EN in register TRX_RPC */
+  #define SR_RX_RPC_EN 0x16,0x20,5
+  /** Access parameters for sub-register PDT_RPC_EN in register TRX_RPC */
+  #define SR_PDT_RPC_EN 0x16,0x10,4
+  /** Access parameters for sub-register PLL_RPC_EN in register TRX_RPC */
+  #define SR_PLL_RPC_EN 0x16,0x8,3
+  /** Access parameters for sub-register XAH_TX_RPC_EN in register TRX_RPC */
+  #define SR_XAH_TX_RPC_EN 0x16,0x4,2
+  /** Access parameters for sub-register IPAN_RPC_EN in register TRX_RPC */
+  #define SR_IPAN_RPC_EN 0x16,0x2,1
+/** Offset for register XAH_CTRL_1 */
+#define RG_XAH_CTRL_1 (0x17)
+  /** Access parameters for sub-register ARET_TX_TS in register XAH_CTRL_1 */
+  #define SR_ARET_TX_TS 0x17,0x80,7
+  /** Access parameters for sub-register AACK_FLTR_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_FLTR_RES_FT 0x17,0x20,5
+  /** Access parameters for sub-register AACK_UPLD_RES_FT in register XAH_CTRL_1 */
+  #define SR_AACK_UPLD_RES_FT 0x17,0x10,4
+  /** Access parameters for sub-register AACK_ACK_TIME in register XAH_CTRL_1 */
+  #define SR_AACK_ACK_TIME 0x17,0x4,2
+  /** Access parameters for sub-register AACK_SPC_EN in register XAH_CTRL_1 */
+  #define SR_AACK_SPC_EN 0x17,0x1,0
+  /** Access parameters for sub-register AACK_PROM_MODE in register XAH_CTRL_1 */
+  #define SR_AACK_PROM_MODE 0x17,0x2,1
+/** Offset for register FTN_CTRL */
+#define RG_FTN_CTRL (0x18)
+  /** Access parameters for sub-register FTN_START in register FTN_CTRL */
+  #define SR_FTN_START 0x18,0x80,7
+/** Offset for register XAH_CTRL_2 */
+#define RG_XAH_CTRL_2 (0x19)
+  /** Access parameters for sub-register ARET_FRAME_RETRIES in register XAH_CTRL_2 */
+  #define SR_ARET_FRAME_RETRIES 0x19,0xf0,4
+  /** Access parameters for sub-register ARET_CSMA_RETRIES in register XAH_CTRL_2 */
+  #define SR_ARET_CSMA_RETRIES 0x19,0xe,1
+/** Offset for register PLL_CF */
+#define RG_PLL_CF (0x1a)
+  /** Access parameters for sub-register PLL_CF_START in register PLL_CF */
+  #define SR_PLL_CF_START 0x1a,0x80,7
+  /** Access parameters for sub-register PLL_CF in register PLL_CF */
+  #define SR_PLL_CF 0x1a,0xf,0
+/** Offset for register PLL_DCU */
+#define RG_PLL_DCU (0x1b)
+  /** Access parameters for sub-register PLL_DCU_START in register PLL_DCU */
+  #define SR_PLL_DCU_START 0x1b,0x80,7
+/** Offset for register PART_NUM */
+#define RG_PART_NUM (0x1c)
+  /** Access parameters for sub-register PART_NUM in register PART_NUM */
+  #define SR_PART_NUM 0x1c,0xff,0
+    #define RF233_PART_NUM (11)
+/** Offset for register VERSION_NUM */
+#define RG_VERSION_NUM (0x1d)
+  /** Access parameters for sub-register VERSION_NUM in register VERSION_NUM */
+  #define SR_VERSION_NUM 0x1d,0xff,0
+    #define RF233_VERSION_NUM (1)
+/** Offset for register MAN_ID_0 */
+#define RG_MAN_ID_0 (0x1e)
+  /** Access parameters for sub-register MAN_ID_0 in register MAN_ID_0 */
+  #define SR_MAN_ID_0 0x1e,0xff,0
+/** Offset for register MAN_ID_1 */
+#define RG_MAN_ID_1 (0x1f)
+  /** Access parameters for sub-register MAN_ID_1 in register MAN_ID_1 */
+  #define SR_MAN_ID_1 0x1f,0xff,0
+/** Offset for register SHORT_ADDR_0 */
+#define RG_SHORT_ADDR_0 (0x20)
+  /** Access parameters for sub-register SHORT_ADDR_0 in register SHORT_ADDR_0 */
+  #define SR_SHORT_ADDR_0 0x20,0xff,0
+/** Offset for register SHORT_ADDR_1 */
+#define RG_SHORT_ADDR_1 (0x21)
+  /** Access parameters for sub-register SHORT_ADDR_1 in register SHORT_ADDR_1 */
+  #define SR_SHORT_ADDR_1 0x21,0xff,0
+/** Offset for register PAN_ID_0 */
+#define RG_PAN_ID_0 (0x22)
+  /** Access parameters for sub-register PAN_ID_0 in register PAN_ID_0 */
+  #define SR_PAN_ID_0 0x22,0xff,0
+/** Offset for register PAN_ID_1 */
+#define RG_PAN_ID_1 (0x23)
+  /** Access parameters for sub-register PAN_ID_1 in register PAN_ID_1 */
+  #define SR_PAN_ID_1 0x23,0xff,0
+/** Offset for register IEEE_ADDR_0 */
+#define RG_IEEE_ADDR_0 (0x24)
+  /** Access parameters for sub-register IEEE_ADDR_0 in register IEEE_ADDR_0 */
+  #define SR_IEEE_ADDR_0 0x24,0xff,0
+/** Offset for register IEEE_ADDR_1 */
+#define RG_IEEE_ADDR_1 (0x25)
+  /** Access parameters for sub-register IEEE_ADDR_1 in register IEEE_ADDR_1 */
+  #define SR_IEEE_ADDR_1 0x25,0xff,0
+/** Offset for register IEEE_ADDR_2 */
+#define RG_IEEE_ADDR_2 (0x26)
+  /** Access parameters for sub-register IEEE_ADDR_2 in register IEEE_ADDR_2 */
+  #define SR_IEEE_ADDR_2 0x26,0xff,0
+/** Offset for register IEEE_ADDR_3 */
+#define RG_IEEE_ADDR_3 (0x27)
+  /** Access parameters for sub-register IEEE_ADDR_3 in register IEEE_ADDR_3 */
+  #define SR_IEEE_ADDR_3 0x27,0xff,0
+/** Offset for register IEEE_ADDR_4 */
+#define RG_IEEE_ADDR_4 (0x28)
+  /** Access parameters for sub-register IEEE_ADDR_4 in register IEEE_ADDR_4 */
+  #define SR_IEEE_ADDR_4 0x28,0xff,0
+/** Offset for register IEEE_ADDR_5 */
+#define RG_IEEE_ADDR_5 (0x29)
+  /** Access parameters for sub-register IEEE_ADDR_5 in register IEEE_ADDR_5 */
+  #define SR_IEEE_ADDR_5 0x29,0xff,0
+/** Offset for register IEEE_ADDR_6 */
+#define RG_IEEE_ADDR_6 (0x2a)
+  /** Access parameters for sub-register IEEE_ADDR_6 in register IEEE_ADDR_6 */
+  #define SR_IEEE_ADDR_6 0x2a,0xff,0
+/** Offset for register IEEE_ADDR_7 */
+#define RG_IEEE_ADDR_7 (0x2b)
+  /** Access parameters for sub-register IEEE_ADDR_7 in register IEEE_ADDR_7 */
+  #define SR_IEEE_ADDR_7 0x2b,0xff,0
+/** Offset for register XAH_CTRL_0 */
+#define RG_XAH_CTRL_0 (0x2c)
+  /** Access parameters for sub-register MAX_FRAME_RETRIES in register XAH_CTRL_0 */
+  #define SR_MAX_FRAME_RETRIES 0x2c,0xf0,4
+  /** Access parameters for sub-register SLOTTED_OPERATION in register XAH_CTRL_0 */
+  #define SR_SLOTTED_OPERATION 0x2c,0x1,0
+  /** Access parameters for sub-register MAX_CSMA_RETRIES in register XAH_CTRL_0 */
+  #define SR_MAX_CSMA_RETRIES 0x2c,0xe,1
+/** Offset for register CSMA_SEED_0 */
+#define RG_CSMA_SEED_0 (0x2d)
+  /** Access parameters for sub-register CSMA_SEED_0 in register CSMA_SEED_0 */
+  #define SR_CSMA_SEED_0 0x2d,0xff,0
+/** Offset for register CSMA_SEED_1 */
+#define RG_CSMA_SEED_1 (0x2e)
+  /** Access parameters for sub-register AACK_FVN_MODE in register CSMA_SEED_1 */
+  #define SR_AACK_FVN_MODE 0x2e,0xc0,6
+  /** Access parameters for sub-register AACK_SET_PD in register CSMA_SEED_1 */
+  #define SR_AACK_SET_PD 0x2e,0x20,5
+  /** Access parameters for sub-register AACK_DIS_ACK in register CSMA_SEED_1 */
+  #define SR_AACK_DIS_ACK 0x2e,0x10,4
+  /** Access parameters for sub-register AACK_I_AM_COORD in register CSMA_SEED_1 */
+  #define SR_AACK_I_AM_COORD 0x2e,0x8,3
+  /** Access parameters for sub-register CSMA_SEED_1 in register CSMA_SEED_1 */
+  #define SR_CSMA_SEED_1 0x2e,0x7,0
+/** Offset for register CSMA_BE */
+#define RG_CSMA_BE (0x2f)
+  /** Access parameters for sub-register MAX_BE in register CSMA_BE */
+  #define SR_MAX_BE 0x2f,0xf0,4
+  /** Access parameters for sub-register MIN_BE in register CSMA_BE */
+  #define SR_MIN_BE 0x2f,0xf,0
+/** Offset for register TST_CTRL_DIGI */
+#define RG_TST_CTRL_DIGI (0x36)
+  /** Access parameters for sub-register TST_CTRL_DIG in register TST_CTRL_DIGI */
+  #define SR_TST_CTRL_DIG 0x36,0xf,0
+/** name string of the radio */
+#define RADIO_NAME "AT86RF233"
+/** contents of the RG_PART_NUM register */
+#define RADIO_PART_NUM (RF233_PART_NUM)
+/** contents of the RG_VERSION_NUM register */
+#define RADIO_VERSION_NUM (RF233_VERSION_NUM)
+
+/** SPI command code for register write */
+#define TRX_CMD_RW           (_BV(7) | _BV(6))
+/** SPI command code for register read */
+#define TRX_CMD_RR           (_BV(7))
+/** SPI command code for frame write */
+#define TRX_CMD_FW           (_BV(6) | _BV(5))
+/** SPI command code for frame read */
+#define TRX_CMD_FR           (_BV(5))
+/** SPI command code for sram write */
+#define TRX_CMD_SW           (_BV(6))
+/** SPI command code for sram read */
+#define TRX_CMD_SR           (0)
+
+#define TRX_CMD_RADDR_MASK   (0x3f)
+
+/** duration while reset=low is asserted */
+#define TRX_RESET_TIME_US    (6)
+
+/** duration transceiver reaches TRX_OFF for the first time */
+#define TRX_INIT_TIME_US     (510)
+
+/** maximum duration, which PLL needs to lock */
+#define TRX_PLL_LOCK_TIME_US     (180)
+
+
+/** duration of a CCA measurement */
+#define TRX_CCA_TIME_US     (140)
+
+/** Mask for PLL lock interrupt */
+#define TRX_IRQ_PLL_LOCK   _BV(0)
+
+/** Mask for PLL unlock interrupt */
+#define TRX_IRQ_PLL_UNLOCK _BV(1)
+
+/** Mask for RX Start interrupt */
+#define TRX_IRQ_RX_START   _BV(2)
+
+/** Mask for RX/TX end interrupt */
+#define TRX_IRQ_TRX_END    _BV(3)
+
+/** Mask for CCA_ED interrupt */
+#define TRX_IRQ_CCA_ED     _BV(4)
+
+/** Mask for AMI interrupt */
+#define TRX_IRQ_AMI        _BV(5)
+
+/** Mask for RX/TX underrun interrupt */
+#define TRX_IRQ_UR         _BV(6)
+
+/** Mask for battery low interrupt */
+#define TRX_IRQ_BAT_LOW    _BV(7)
+
+/** TX ARET status for successful transmission */
+#define TRAC_SUCCESS (0)
+/** TX ARET status for unsuccessful transmission due to no channel access */
+#define TRAC_CHANNEL_ACCESS_FAILURE (3)
+/** TX ARET status for unsuccessful transmission due no ACK frame was received */
+#define TRAC_NO_ACK (5)
+
+
+/** lowest supported channel number */
+#define TRX_MIN_CHANNEL (11)
+
+/** highest supported channel number */
+#define TRX_MAX_CHANNEL (26)
+
+/** number of channels */
+#define TRX_NB_CHANNELS (16)
+
+/**
+ * @brief Mask for supported channels of this radio.
+ * The AT86RF233 supports channels 11 ... 26 of IEEE 802.15.4
+ */
+#define TRX_SUPPORTED_CHANNELS  (0x7fff800UL)
+
+#define TRX_SUPPORTS_BAND_2400 (1)
+/**
+ * @brief Mask for supported channel pages (a.k.a. modulation schemes) of this radio.
+ * The AT86RF230 supports channel page ???? OQPSK_250
+ */
+#define TRX_SUPPORTED_PAGES     (42)
+
+/** Rate code for OQPSK250, xx kchip/s, yy kbit/s */
+#define TRX_OQPSK250  (0)
+
+/** undefined data rate */
+#define TRX_NONE      (255)
+
+#endif /* ifndef AT86RF233_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/board.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/board.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,63 @@
+/* Copyright (c) 2007-2009 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief Interface for @ref grpBoard.
+ * @ingroup grpBoard
+ */
+#ifndef BOARD_H
+#define BOARD_H (1)
+#include "const.h"
+#include "../MxRadioCfg.h"
+#define DELAY_US(x)  wait_us(x)
+#define DELAY_MS(x)  wait_ms(x)
+
+
+
+#if RADIO_TYPE == RADIO_AT86RF230 || defined(DOXYGEN)
+# include "at86rf230a.h"
+#elif RADIO_TYPE == RADIO_AT86RF230B
+# include "at86rf230b.h"
+#elif RADIO_TYPE == RADIO_AT86RF231
+# include "at86rf231.h"
+#elif RADIO_TYPE == RADIO_AT86RF212
+# include "at86rf212.h"
+#elif RADIO_TYPE == RADIO_AT86RF232
+# include "at86rf232.h"
+#elif RADIO_TYPE == RADIO_AT86RF233
+# include "at86rf233.h"
+
+#else
+# error "RADIO_TYPE is not defined or wrong"
+#endif
+
+//# include "at86rf231.h"
+
+#endif /* #ifndef BOARD_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/const.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/const.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,212 @@
+/* Copyright (c) 2007, 2008, 2009, 2010
+    Marco Arena
+    Axel Wachtler
+
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief General Definitions.
+ *
+ */
+/*====================================================================*/
+#ifndef CONST_H
+#define CONST_H
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @addtogroup grpRadio
+ * @{
+ */
+#if RADIO_TYPE == RADIO_AT86RF230 ||RADIO_TYPE == RADIO_AT86RF230B|| RADIO_TYPE == RADIO_AT86RF231
+#define RSSI_BASE_VAL (-91)
+#elif RADIO_TYPE == RADIO_ATMEGA128RFA1_A || RADIO_TYPE == RADIO_ATMEGA128RFA1_B ||RADIO_TYPE == RADIO_ATMEGA128RFA1_c ||RADIO_TYPE == RADIO_ATMEGA128RFA1_D ||RADIO_TYPE == RADIO_ATMEGA256RFR2_A
+#define RSSI_BASE_VAL (-90)
+#elif RADIO_TYPE == RADIO_AT86RF212
+#define RSSI_BASE_VAL (-97)
+#endif
+
+/*=== radio constants ================================================*/
+#define  RADIO_AT86RF230 (1) /**< Identifier for radio AT86RF230 */
+#define  RADIO_AT86RF230A (RADIO_AT86RF230) /**< Identifier for radio AT86RF230 Rev A */
+#define  RADIO_AT86RF230B (2) /**< Identifier for radio AT86RF230 Rev B */
+#define  RADIO_AT86RF231 (3) /**< Identifier for radio AT86RF231 */
+#define  RADIO_AT86RF212 (4) /**< Identifier for radio AT86RF212 */
+#define  RADIO_ATMEGA128RFA1_A (5) /**< Identifier for radio ATmega128RFA1 Rev. A */
+#define  RADIO_ATMEGA128RFA1_B (6) /**< Identifier for radio ATmega128RFA1 Rev. B */
+#define  RADIO_ATMEGA128RFA1_C (7) /**< Identifier for radio ATmega128RFA1 Rev. C */
+#define  RADIO_ATMEGA128RFA1_D (8) /**< Identifier for radio ATmega128RFA1 Rev. D */
+#define  RADIO_AT86RF232 (9) /**< Identifier for radio AT86RF232 */
+#define  RADIO_AT86RF233 (10) /**< Identifier for radio AT86RF233 */
+
+#define  RADIO_ATMEGA256RFR2 (11) /**< Identifier for radio ATmega128RFR2 */
+#define  RADIO_ATMEGA256RFR2_A (11) /**< Identifier for radio RADIO_ATMEGA256RFR2_A Rev. A */
+#define  RADIO_ATMEGA256RFR2_B (12) /**< Identifier for radio RADIO_ATMEGA256RFR2_A Rev. A */
+#define  RADIO_ATMEGA256RFR2_C (13) /**< Identifier for radio RADIO_ATMEGA256RFR2_A Rev. A */
+
+#define RADIO_BAND_700 (1) /**< 700MHz frequency band (china) */
+#define RADIO_BAND_800 (2) /**< 868MHz frequency band (europe)*/
+#define RADIO_BAND_900 (3) /**< 900MHz frequency band (north america)*/
+#define RADIO_BAND_2400 (4)  /**< 2.4GHz frequency band (international)*/
+
+/*=== modulation schemes =============================================*/
+#define MOD_BPSK_20    (0) /**< PHY modulation BPSK, 20 kbit/s */
+#define MOD_BPSK_40    (1) /**< PHY modulation BPSK, 40 kbit/s */
+#define MOD_OQPSK_100  (2) /**< PHY modulation O-QPSK, 100 kbit/s */
+#define MOD_OQPSK_200  (3) /**< PHY modulation O-QPSK, 200 kbit/s */
+#define MOD_OQPSK_250  (4) /**< PHY modulation O-QPSK, 250 kbit/s */
+#define MOD_OQPSK_400  (5) /**< PHY modulation O-QPSK, 400 kbit/s */
+#define MOD_OQPSK_500  (6) /**< PHY modulation O-QPSK, 500 kbit/s */
+#define MOD_OQPSK_1000 (7) /**< PHY modulation O-QPSK, 1000 kbit/s */
+#define MOD_OQPSK_2000 (8) /**< PHY modulation O-QPSK, 2000 kbit/s */
+
+
+/** @} */
+
+/**
+ * @addtogroup grpHIF
+ * @{
+ */
+
+/*=== HIF type constants =============================================*/
+#define  HIF_NONE     (0)  /**< Identifier for no host interface */
+#define  HIF_UART_0   (10) /**< Identifier for HIF type UART 0 */
+#define  HIF_UART_1   (11) /**< Identifier for HIF type UART 1 */
+#define  HIF_FT245    (20) /**< Identifier for HIF type USB/FT245*/
+#define  HIF_AT90USB  (21) /**< Identifier for HIF type USB/ATmega1287 */
+
+/*=== USB constants ==================================================*/
+/**
+ * uracoli USB Vendor ID
+ *
+ * The pair of the uracoli vendor id, device id are obtained by
+ *
+ *  - http://www.voti.nl/pids/
+ *  - http://www.frank-buss.de/pid.txt
+ */
+#define URACOLI_USB_VID (5824)
+/**
+ * uracoli USB Product ID
+ * see also @ref USB_VID_URACOLI
+ */
+#define URACOLI_USB_PID (2183)
+
+#define URACOLI_USB_BCD_RELEASE (0x100)
+#define URACOLI_USB_VENDOR_NAME  L"URACOLI"
+#define URACOLI_USB_PRODUCT_NAME L"RZUSBSTICK"
+
+/** @} */
+
+/**
+ * @addtogroup grpTrx
+ * @{
+ */
+
+/*=== spi constants ==================================================*/
+#define SPI_RATE_1_2      (4) /**< SPI clock running is 0.5 (1/2) of cpu clock */
+#define SPI_RATE_1_4      (0) /**< SPI clock running is 0.25 (1/4) of cpu clock */
+#define SPI_RATE_1_8      (5) /**< SPI clock running is 0.125 (1/8) of cpu clock */
+#define SPI_RATE_1_16     (1) /**< SPI clock running is 0.0635 (1/16) of cpu clock */
+#define SPI_RATE_1_32     (6) /**< SPI clock running is 0.03125 (1/32)of cpu clock */
+#define SPI_RATE_1_64     (2) /**< SPI clock running is 0.015625 (1/64)of cpu clock */
+#define SPI_RATE_1_128    (3) /**< SPI clock running is 0.0078125 (1/128) of cpuclock */
+
+/** @} */
+
+
+#if defined (DOXYGEN)
+/** macro that forces an enumeration to use 8 bit instead of 16 bit integers. */
+#define SHORTENUM
+#else
+#define SHORTENUM  __attribute__((packed))
+#endif
+
+/**
+ * @addtogroup grpTrx
+ * @{
+ */
+#define FCTL_DATA _BV(0)        /**< data frame fype in frame control field */
+#define FCTL_ACK  _BV(5)        /**< ack request in frame control field */
+#define FCTL_IPAN _BV(6)        /**< intra pan bit in frame control field */
+#define FCTL_DST_SHORT 0x0800   /**< destination short address in frame control field */
+#define FCTL_DST_LONG  0x0c00   /**< destination long address in frame control field */
+#define FCTL_SRC_SHORT 0x8000   /**< source short address in frame control field */
+#define FCTL_SRC_LONG  0xc000   /**< source long address in frame control field */
+
+#define FCTL_SRC_MASK (FCTL_SRC_LONG)
+#define FCTL_DST_MASK (FCTL_DST_LONG)
+#define FCTL_IPAN_MASK (FCTL_IPAN)
+/** @} */
+
+/* === Types ================================================================= */
+
+
+/**
+ * @addtogroup grpTrx
+ * @{
+ */
+
+/** transceiver channel type */
+typedef int8_t  channel_t;
+
+/** transceiver transmit type */
+typedef int8_t  txpwr_t;
+
+/** radio idle state, if true radio idles in state PX_ON
+ *  @todo make it state_t variable, so that idle state can explicitely selected.
+ */
+typedef bool    rxidle_t;
+
+/** transceiver cca mode, 1 : ED, 2: CS, 3: CS & ED */
+typedef uint8_t ccamode_t;
+
+/* ... cca_ed_tresh, clkm, pdt, ... */
+
+/**
+ * Transceiver parameter structure
+ */
+typedef struct
+{
+    /** current channel see sub register @ref SR_CHANNEL*/
+    channel_t chan;
+    /**  TX power index see sub register @ref SR_TX_PWR*/
+    unsigned int txp   : 4;
+    /**  CCA mode see sub register @ref SR_CCA_MODE */
+    unsigned int cca   : 2;
+    /**  ED threshold see sub register @ref SR_CCA_ED_THRES */
+    unsigned int edt   : 4;
+
+    /**  clkm control  see sub register @ref SR_CLKM_CTRL */
+    unsigned int clkm  : 3;
+
+} trx_param_t;
+
+/** @} */
+#endif  /* #ifndef CONST_H */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/radio.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/radio.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,371 @@
+/* Copyright (c) 2007-2009 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief Interface for @ref grpLibRadio.
+ *
+ */
+#ifndef RADIO_H
+#define RADIO_H
+
+/* === Includes ============================================================== */
+#include <stdbool.h>
+#include <stdio.h>
+#include "const.h"
+
+/**
+ * @addtogroup grpRadio
+ * @{
+ */
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+/**
+ * Radio state enumeration
+ */
+
+/** TRX in OFF state. */
+#define  STATE_OFF (0)
+/** Basic mode TX state. */
+#define  STATE_TX (1)
+/** Basic mode RX state. */
+#define STATE_RX (2)
+/** Extended mode TX state (TX_ARET). */
+#define STATE_TXAUTO (3)
+/** Extended mode RX state (RX_AACK). */
+#define STATE_RXAUTO (4)
+/** Sleep state (lowest power consumption). */
+#define STATE_SLEEP (5)
+
+
+/** Radio state type */
+typedef uint8_t radio_state_t;
+
+/**
+ * error codes for tx done event
+ */
+typedef enum
+{
+    TX_OK,			/**< transmission completed successfully */
+    TX_CCA_FAIL,		/**< channel was busy (TX_AUTO only) */
+    TX_NO_ACK,			/**< no ACK received (TX_AUTO only) */
+    TX_FAIL,			/**< unexpected error */
+} radio_tx_done_t;
+
+
+/**
+ * codes for CCA
+ */
+typedef enum SHORTENUM
+{
+#if defined(CCA_BUSY)
+	/** @todo this is workaround for name clash for RFA1 and avr-libc
+	 *   avr/iom128rfa1.h, check if this is OK or if we should change
+	 *   the names of CCA_FREE, ..., etc.
+	 */
+	RADIO_CCA_FREE = CCA_IDLE,
+	RADIO_CCA_BUSY = CCA_BUSY,
+	RADIO_CCA_FAIL = 255,
+#else
+    /** The CCA measurement estimates, that the channel is free. */
+    RADIO_CCA_FREE = 0,
+    /** The CCA measurement estimates, that the channel is busy. */
+    RADIO_CCA_BUSY,
+    /** The CCA measurement was not finished. */
+    RADIO_CCA_FAIL
+#endif
+
+} radio_cca_t;
+
+
+/** Enumeration to identify radio attributes.
+ */
+typedef enum SHORTENUM
+{
+    /** Set the current channel */
+    phyCurrentChannel,
+    /** Currently unused */
+    phyChannelsSupported,
+    /** Set the Tx power */
+    phyTransmitPower,
+    /** Transceiver state to return to after transmission */
+    phyIdleState,
+    /** CCA mode to use in CSMA-CA:
+     * <table>
+     *   <tr><th>value</th><th>CCA mode</th></tr>
+     *   <tr><td>0</td>    <td>carrier sense OR energy above threshold</td></tr>
+     *   <tr><td>1</td>    <td>energy above threshold (default)</td></tr>
+     *   <tr><td>2</td>    <td>carrier sense</td></tr>
+     *   <tr><td>3</td>    <td>carrier sense AND energy above threshold</td></tr>
+     * </table>
+     */
+    phyCCAMode,
+    /** PAN ID to use in STATE_RXAUTO frame filter */
+    phyPanId,
+    /** Short (16-bit) address to use in STATE_RXAUTO frame filter */
+    phyShortAddr,
+    /** Pointer to long (EUI-64) address to use in STATE_RXAUTO frame filter */
+    phyLongAddr,
+
+    /** Datarate */
+    phyDataRate,
+
+    /** PA enable */
+    phyTxPa,
+    /** LNA enable */
+    phyRxLna
+
+} radio_attribute_t;
+
+
+/**
+ * @brief Container for handover of radio parameter values.
+ *
+ * @note
+ * The elements in this union should have max. a size
+ * of 2 byte, all other parameters should be configured with
+ * the void pointer.
+ */
+typedef union radio_param_t
+{
+#if defined __cplusplus
+public:
+    radio_param_t(int8_t c) { channel = c; } /* also used for txpwr_t */
+    //radio_param_t(radio_state_t s) { idle_state = s; }
+    radio_param_t(uint8_t m) { cca_mode = m; } /* also used for data_rate, tx_pa, rx_lna */
+    radio_param_t(uint16_t p) { pan_id = p; } /* also used for short_addr */
+    radio_param_t(uint64_t *la) { long_addr = la; }
+#endif
+    /** Value for current radio channel. (@ref MIN_CHANNEL ... @ref MAX_CHANNEL)*/
+    channel_t channel;
+    /** Value for transmit power in dB.*/
+    txpwr_t   tx_pwr;
+    /** after TX go to idle state */
+    radio_state_t idle_state;
+    /** Value for cca mode. */
+    ccamode_t cca_mode;
+    /** Value for PANID */
+    uint16_t pan_id;
+    /** Value for short address */
+    uint16_t short_addr;
+    /** Pointer to long (64-bit) address */
+    uint64_t *long_addr;
+    /** data rate type */
+    uint8_t data_rate;
+
+    /** TX power amp type */
+    uint8_t tx_pa;
+    /** RX LNA type */
+    uint8_t rx_lna;
+
+} radio_param_t;
+
+
+/**
+ * @brief Error codes.
+ */
+typedef enum SHORTENUM
+{
+	#ifndef SUCCESS
+	/** @todo same like CCA_FREE, include/avr/iom128rfa1.h:3687:#define SUCCESS*/
+    SUCCESS = 0,        /**< OK Code*/
+    #endif
+    STATE_SET_FAILED = 1,   /**< function radio_set_state failed */
+    SET_PARM_FAILED,    /**< function radio_set_param failed */
+    GET_PARM_FAILED,    /**< function radio_get_param failed */
+    GENERAL_ERROR,      /**< something unexpected happened */
+} radio_error_t;
+
+
+/**
+ * @brief Structure for storage of radio parameters.
+ */
+typedef struct
+{
+    uint8_t  channel;      /**< Current radio channel.
+                                (@ref MIN_CHANNEL ... @ref MAX_CHANNEL) */
+    uint8_t  tx_pwr;       /**< Current transmit power. */
+    uint8_t  cca_mode;     /**< Current cca mode. */
+    radio_state_t state;      /**< Current transceiver state. */
+    radio_state_t idle_state; /**< after TX go to idle state */
+    uint8_t  *rxframe;      /**< Pointer for frame data storage. */
+    uint8_t  rxframesz;     /**< Length of the buffer rxframesz */
+    uint8_t tx_pa;
+    uint8_t rx_lna;
+} radio_status_t;
+
+/* === Macros ================================================================ */
+
+/**
+ * Code for invalid RSSI value.
+ */
+#define VOID_RSSI (0xff)
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the channel number to @c x.
+ */
+#  define RP_CHANNEL(x)
+#elif defined __cplusplus
+#  define RP_CHANNEL(x) phyCurrentChannel,radio_param_t((channel_t)x)
+#else
+#  define RP_CHANNEL(x) phyCurrentChannel,(radio_param_t){.channel=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the tx power value to @c x.
+ */
+#  define RP_TXPWR(x)
+#elif defined __cplusplus
+#  define RP_TXPWR(x)   phyTransmitPower,radio_param_t((txpwr_t)x)
+#else
+#  define RP_TXPWR(x)   phyTransmitPower,(radio_param_t){.tx_pwr=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the transceiver's idle state to @c x.
+ */
+#  define RP_IDLESTATE(x)
+#elif defined __cplusplus
+#  define RP_IDLESTATE(x)  phyIdleState,radio_param_t(x)
+#else
+#  define RP_IDLESTATE(x)  phyIdleState,(radio_param_t){.idle_state=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the CCA mode to @c x.
+ */
+#  define RP_CCAMODE(x)
+#elif defined __cplusplus
+#  define RP_CCAMODE(x)  phyCCAMode,radio_param_t((ccamode_t)x)
+#else
+#  define RP_CCAMODE(x) phyCCAMode,(radio_param_t){.cca_mode=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the PAN ID to @c x.
+ */
+#  define RP_PANID(x)
+#elif defined __cplusplus
+#  define RP_PANID(x) phyPanId,radio_param_t((uint16_t)x)
+#else
+#  define RP_PANID(x) phyPanId,(radio_param_t){.pan_id=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the short address to @c x.
+ */
+#  define RP_SHORTADDR(x)
+#elif defined __cplusplus
+#  define RP_SHORTADDR(x) phyShortAddr,radio_param_t((uint16_t)x)
+#else
+#  define RP_SHORTADDR(x) phyShortAddr,(radio_param_t){.short_addr=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the long address pointer to @c x.
+ */
+#  define RP_LONGADDR(x)
+#elif defined __cplusplus
+#  define RP_LONGADDR(x) phyLongAddr,radio_param_t((uint64_t *)x)
+#else
+#  define RP_LONGADDR(x) phyLongAddr,(radio_param_t){.long_addr=x}
+#endif
+
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the data rate to @c x.
+ */
+#  define RP_DATARATE(x)
+#elif defined __cplusplus
+#  define RP_DATARATE(x) phyDataRate,radio_param_t((uint16_t)x)
+#else
+#  define RP_DATARATE(x) phyDataRate,(radio_param_t){.data_rate=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the TX power amplifier enable number to @c x.
+ */
+#  define RP_CHANNEL(x)
+#elif defined __cplusplus
+#  define RP_TX_PA(x) phyTxPa,radio_param_t((tx_pa_t)x)
+#else
+#  define RP_TX_PA(x) phyTxPa,(radio_param_t){.tx_pa=x}
+#endif
+
+#if defined(DOXYGEN)
+/**
+ * Helper macro to construct the arguments for @ref radio_set_param in
+ * order to set the TX power amplifier enable number to @c x.
+ */
+#  define RP_RX_LNA(x)
+#elif defined __cplusplus
+#  define RP_RX_LNA(x) phyRxLna,radio_param_t((rx_lna_t)x)
+#else
+#  define RP_RX_LNA(x) phyRxLna,(radio_param_t){.rx_lna=x}
+#endif
+
+#define CRC_CCITT_UPDATE(crc, data) crc16_update(crc, data)
+
+
+#ifndef RADIO_CFG_EEOFFSET
+/** offset of radio config data in EEPROM */
+#define RADIO_CFG_EEOFFSET (8)
+#endif
+
+#ifndef RADIO_CFG_DATA
+/** a default radio configuration data structure */
+#define RADIO_CFG_DATA {chan: 16, txp: 0, cca: 1, edt: 11, clkm: 0, crc: 0xab12}
+#endif
+
+/** @} */
+
+
+#endif  /* #ifndef RADIO_H */
+/* EOF */

diff -r 000000000000 -r 5f1d66c85ae0 uracolib/transceiver.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/uracolib/transceiver.h	Thu Apr 09 16:42:51 2015 +0800
@@ -0,0 +1,182 @@
+/* Copyright (c) 2007 Axel Wachtler
+   All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+
+   * Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   * Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   * Neither the name of the authors nor the names of its contributors
+     may be used to endorse or promote products derived from this software
+     without specific prior written permission.
+
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+/**
+ * @file
+ * @brief Interface for @ref grpTrx.
+ * @ingroup grpTrx
+ */
+#ifndef TRANSCEIVER_H
+#define TRANSCEIVER_H
+
+/**
+ *  @addtogroup grpTrx
+ *  @{
+ */
+
+/* === Includes ============================================================== */
+#include "board.h"
+
+#include <stdbool.h>
+
+/* === Externals ============================================================= */
+
+/* === Types ================================================================= */
+
+#if defined(DOXYGEN)
+
+    /* this types are defined in at86rfXXX.{h,txt} in order
+       to provide a radio abstraction */
+
+    /** Data Type for Transceiver SRAM address
+     */
+    typedef uint8_t trx_ramaddr_t;
+
+    /** Data Type for Transceiver register value
+     */
+    typedef uint8_t trx_regval_t;
+
+    /** Data Type for Transceiver register address
+     */
+    typedef uint8_t trx_regaddr_t;
+
+#endif
+
+/** Data Type for Transceiver IRQ callback function
+ */
+typedef void (*trx_irq_handler_t)(uint8_t cause);
+
+
+
+/* === Macros ================================================================ */
+/* error codes */
+/** trx function succeeded */
+#define TRX_OK        (0)
+/** trx init function failed (TRX_OFF not reached after reset) */
+#define TRX_INIT_FAIL (1)
+/** trx pll check function failed (PLL_LOCK coult not be observed in PLL_ON) */
+#define TRX_PLL_FAIL  (2)
+
+#define INVALID_PART_NUM (2)  /**< flag for invalid part number */
+#define INVALID_REV_NUM  (1)  /**< flag for invalid revision number */
+
+/* Data Rate macros, generated by python Tools/cmdhash.py  `cat rates.txt` */
+#define BPSK20 (0x52)
+#define BPSK20_STR "BPSK20"
+#define BPSK40 (0x92)
+#define BPSK40_STR "BPSK40"
+#define OQPSK100 (0x90)
+#define OQPSK100_STR "OQPSK100"
+#define OQPSK200 (0x93)
+#define OQPSK200_STR "OQPSK200"
+#define OQPSK250 (0x33)
+#define OQPSK250_STR "OQPSK250"
+#define OQPSK400 (0x95)
+#define OQPSK400_STR "OQPSK400"
+#define OQPSK500 (0x94)
+#define OQPSK500_STR "OQPSK500"
+#define OQPSK1000 (0x34)
+#define OQPSK1000_STR "OQPSK1000"
+#define OQPSK2000 (0x54)
+#define OQPSK2000_STR "OQPSK2000"
+
+#define RATE_NONE (0xFF)
+
+/** Maximum size in bytes of an IEEE 802.15.4 frame */
+#ifndef MAX_FRAME_SIZE
+# define MAX_FRAME_SIZE (127)
+#endif
+
+/* channel handling */
+#define TRX_NEXT_CHANNEL(x) ((channel_t)(x+1) > TRX_MAX_CHANNEL ? TRX_MAX_CHANNEL : x+1)
+#define TRX_PREV_CHANNEL(x) ((channel_t)(x-1) < TRX_MIN_CHANNEL ? TRX_MIN_CHANNEL : x-1)
+#define TRX_NEXT_CHANNEL_WRAP(x) ((channel_t)(x+1) > TRX_MAX_CHANNEL ? TRX_MIN_CHANNEL : x+1 )
+#define TRX_PREV_CHANNEL_WRAP(x) ((channel_t)(x-1) < TRX_MIN_CHANNEL ? TRX_MAX_CHANNEL : x-1 )
+
+
+#if defined (SR_MASK_AMI) || defined(DOXYGEN)
+/** @brief Enable AMI IRQ. */
+# define TRX_IRQ_AMI_EI() trx_bit_write(SR_MASK_AMI, 1);
+/** @brief Disable AMI IRQ. */
+# define TRX_IRQ_AMI_DI() trx_bit_write(SR_MASK_AMI, 0);
+#endif
+
+#if defined (SR_MASK_BAT_LOW) || defined(DOXYGEN)
+/** @brief Enable BAT_LOW IRQ. */
+# define TRX_IRQ_BAT_LOW_EI() trx_bit_write(SR_MASK_BAT_LOW, 1);
+/** @brief Disable BAT_LOW IRQ. */
+# define TRX_IRQ_BAT_LOW_DI() trx_bit_write(SR_MASK_BAT_LOW, 0);
+#endif
+
+#if defined (SR_MASK_CCA_ED_READY) || defined(DOXYGEN)
+/** @brief Enable CCA_ED_READY IRQ. */
+# define TRX_IRQ_CCA_ED_READY_EI() trx_bit_write(SR_MASK_CCA_ED_READY, 1);
+/** @brief Disable CCA_ED_READY IRQ. */
+# define TRX_IRQ_CCA_ED_READY_DI() trx_bit_write(SR_MASK_CCA_ED_READY, 0);
+#endif
+
+#if defined (SR_MASK_PLL_UNLOCK) || defined(DOXYGEN)
+/** @brief Enable PLL_UNLOCK IRQ. */
+# define TRX_IRQ_PLL_UNLOCK_EI() trx_bit_write(SR_MASK_PLL_UNLOCK, 1);
+/** @brief Disable PLL_UNLOCK IRQ. */
+# define TRX_IRQ_PLL_UNLOCK_DI() trx_bit_write(SR_MASK_PLL_UNLOCK, 0);
+#endif
+
+#if defined (SR_MASK_RX_START) || defined(DOXYGEN)
+/** @brief Enable RX_START IRQ. */
+# define TRX_IRQ_RX_START_EI() trx_bit_write(SR_MASK_RX_START, 1);
+/** @brief Disable RX_START IRQ. */
+# define TRX_IRQ_RX_START_DI() trx_bit_write(SR_MASK_RX_START, 0);
+#endif
+
+#if defined (SR_MASK_TRX_IRQ_END) || defined(DOXYGEN)
+/** @brief Enable TRX_IRQ_END IRQ. */
+# define TRX_IRQ_TRX_IRQ_END_EI() trx_bit_write(SR_MASK_TRX_IRQ_END, 1);
+/** @brief Disable TRX_IRQ_END IRQ. */
+# define TRX_IRQ_TRX_IRQ_END_DI() trx_bit_write(SR_MASK_TRX_IRQ_END, 0);
+#endif
+
+#if defined (SR_MASK_TRX_IRQ_START) || defined(DOXYGEN)
+/** @brief Enable TRX_IRQ_START IRQ. */
+# define TRX_IRQ_TRX_IRQ_START_EI() trx_bit_write(SR_MASK_TRX_IRQ_START, 1);
+/** @brief Disable TRX_IRQ_START IRQ. */
+# define TRX_IRQ_TRX_IRQ_START_DI() trx_bit_write(SR_MASK_TRX_IRQ_START, 0);
+#endif
+
+#if defined (SR_MASK_UR) || defined(DOXYGEN)
+/** @brief Enable TX/RX underun IRQ. */
+# define TRX_IRQ_UR_EI() trx_bit_write(SR_MASK_UR, 1);
+/** @brief Disable TX/RX underun IRQ. */
+# define TRX_IRQ_UR_DI() trx_bit_write(SR_MASK_UR, 0);
+#endif
+
+/**
+ *  @}
+ */
+#endif /* TRANSCEIVER_H */