lpc_phy_dp83848.c

00001 /**********************************************************************
00002 * $Id$        lpc_phy_dp83848.c            2011-11-20
00003 *//**
00004 * @file        lpc_phy_dp83848.c
00005 * @brief    DP83848C PHY status and control.
00006 * @version    1.0
00007 * @date        20 Nov. 2011
00008 * @author    NXP MCU SW Application Team
00009 *
00010 * Copyright(C) 2011, NXP Semiconductor
00011 * All rights reserved.
00012 *
00013 ***********************************************************************
00014 * Software that is described herein is for illustrative purposes only
00015 * which provides customers with programming information regarding the
00016 * products. This software is supplied "AS IS" without any warranties.
00017 * NXP Semiconductors assumes no responsibility or liability for the
00018 * use of the software, conveys no license or title under any patent,
00019 * copyright, or mask work right to the product. NXP Semiconductors
00020 * reserves the right to make changes in the software without
00021 * notification. NXP Semiconductors also make no representation or
00022 * warranty that such application will be suitable for the specified
00023 * use without further testing or modification.
00024 **********************************************************************/
00025 
00026 #include "lwip/opt.h"
00027 #include "lwip/err.h"
00028 #include "lwip/tcpip.h"
00029 #include "lwip/snmp.h"
00030 #include "lpc_emac_config.h"
00031 #include "lpc_phy.h"
00032 
00033 /** @defgroup dp83848_phy    PHY status and control for the DP83848.
00034  * @ingroup lwip_phy
00035  *
00036  * Various functions for controlling and monitoring the status of the
00037  * DP83848 PHY. In polled (standalone) systems, the PHY state must be
00038  * monitored as part of the application. In a threaded (RTOS) system,
00039  * the PHY state is monitored by the PHY handler thread. The MAC
00040  * driver will not transmit unless the PHY link is active.
00041  * @{
00042  */
00043 
00044 /** \brief  DP83848 PHY register offsets */
00045 #define DP8_BMCR_REG        0x0  /**< Basic Mode Control Register */
00046 #define DP8_BMSR_REG        0x1  /**< Basic Mode Status Reg */
00047 #define DP8_ANADV_REG       0x4  /**< Auto_Neg Advt Reg  */
00048 #define DP8_ANLPA_REG       0x5  /**< Auto_neg Link Partner Ability Reg */
00049 #define DP8_ANEEXP_REG      0x6  /**< Auto-neg Expansion Reg  */
00050 #define DP8_PHY_STAT_REG    0x10 /**< PHY Status Register  */
00051 #define DP8_PHY_INT_CTL_REG 0x11 /**< PHY Interrupt Control Register */
00052 #define DP8_PHY_RBR_REG     0x17 /**< PHY RMII and Bypass Register  */
00053 #define DP8_PHY_STS_REG     0x19 /**< PHY Status Register  */
00054 
00055 /** \brief DP83848 Control register definitions */
00056 #define DP8_RESET          (1 << 15)  /**< 1= S/W Reset */
00057 #define DP8_LOOPBACK       (1 << 14)  /**< 1=loopback Enabled */
00058 #define DP8_SPEED_SELECT   (1 << 13)  /**< 1=Select 100MBps */
00059 #define DP8_AUTONEG        (1 << 12)  /**< 1=Enable auto-negotiation */
00060 #define DP8_POWER_DOWN     (1 << 11)  /**< 1=Power down PHY */
00061 #define DP8_ISOLATE        (1 << 10)  /**< 1=Isolate PHY */
00062 #define DP8_RESTART_AUTONEG (1 << 9)  /**< 1=Restart auto-negoatiation */
00063 #define DP8_DUPLEX_MODE    (1 << 8)   /**< 1=Full duplex mode */
00064 #define DP8_COLLISION_TEST (1 << 7)   /**< 1=Perform collsion test */
00065 
00066 /** \brief DP83848 Status register definitions */
00067 #define DP8_100BASE_T4     (1 << 15)  /**< T4 mode */
00068 #define DP8_100BASE_TX_FD  (1 << 14)  /**< 100MBps full duplex */
00069 #define DP8_100BASE_TX_HD  (1 << 13)  /**< 100MBps half duplex */
00070 #define DP8_10BASE_T_FD    (1 << 12)  /**< 100Bps full duplex */
00071 #define DP8_10BASE_T_HD    (1 << 11)  /**< 10MBps half duplex */
00072 #define DP8_MF_PREAMB_SUPPR (1 << 6)  /**< Preamble suppress */
00073 #define DP8_AUTONEG_COMP   (1 << 5)   /**< Auto-negotation complete */
00074 #define DP8_RMT_FAULT      (1 << 4)   /**< Fault */
00075 #define DP8_AUTONEG_ABILITY (1 << 3)  /**< Auto-negotation supported */
00076 #define DP8_LINK_STATUS    (1 << 2)   /**< 1=Link active */
00077 #define DP8_JABBER_DETECT  (1 << 1)   /**< Jabber detect */
00078 #define DP8_EXTEND_CAPAB   (1 << 0)   /**< Supports extended capabilities */
00079 
00080 /** \brief DP83848 PHY RBR MII dode definitions */
00081 #define DP8_RBR_RMII_MODE  (1 << 5)   /**< Use RMII mode */
00082 
00083 /** \brief DP83848 PHY status definitions */
00084 #define DP8_REMOTEFAULT    (1 << 6)   /**< Remote fault */
00085 #define DP8_FULLDUPLEX     (1 << 2)   /**< 1=full duplex */
00086 #define DP8_SPEED10MBPS    (1 << 1)   /**< 1=10MBps speed */
00087 #define DP8_VALID_LINK     (1 << 0)   /**< 1=Link active */
00088 
00089 /** \brief DP83848 PHY ID register definitions */
00090 #define DP8_PHYID1_OUI     0x2000     /**< Expected PHY ID1 */
00091 #define DP8_PHYID2_OUI     0x5c90     /**< Expected PHY ID2 */
00092 
00093 /** \brief PHY status structure used to indicate current status of PHY.
00094  */
00095 typedef struct {
00096     u32_t     phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
00097     u32_t     phy_full_duplex:1;  /**< Half/full duplex connection speed flag. */
00098     u32_t     phy_link_active:1;  /**< Phy link active flag. */
00099 } PHY_STATUS_TYPE;
00100 
00101 /** \brief  PHY update flags */
00102 static PHY_STATUS_TYPE physts;
00103 
00104 /** \brief  Last PHY update flags, used for determing if something has changed */
00105 static PHY_STATUS_TYPE olddphysts;
00106 
00107 /** \brief  PHY update counter for state machine */
00108 static s32_t phyustate;
00109 
00110 /** \brief  Update PHY status from passed value
00111  *
00112  *  This function updates the current PHY status based on the
00113  *  passed PHY status word. The PHY status indicate if the link
00114  *  is active, the connection speed, and duplex.
00115  *
00116  *  \param[in]    netif   NETIF structure
00117  *  \param[in]    linksts Status word from PHY
00118  *  \return        1 if the status has changed, otherwise 0
00119  */
00120 static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts)
00121 {
00122     s32_t changed = 0;
00123 
00124     /* Update link active status */
00125     if (linksts & DP8_VALID_LINK)
00126         physts.phy_link_active = 1;
00127     else
00128         physts.phy_link_active = 0;
00129 
00130     /* Full or half duplex */
00131     if (linksts & DP8_FULLDUPLEX)
00132         physts.phy_full_duplex = 1;
00133     else
00134         physts.phy_full_duplex = 0;
00135 
00136     /* Configure 100MBit/10MBit mode. */
00137     if (linksts & DP8_SPEED10MBPS)
00138         physts.phy_speed_100mbs = 0;
00139     else
00140         physts.phy_speed_100mbs = 1;
00141 
00142     if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
00143         changed = 1;
00144         if (physts.phy_speed_100mbs) {
00145             /* 100MBit mode. */
00146             lpc_emac_set_speed(1);
00147 
00148             NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
00149         }
00150         else {
00151             /* 10MBit mode. */
00152             lpc_emac_set_speed(0);
00153 
00154             NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
00155         }
00156 
00157         olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
00158     }
00159 
00160     if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
00161         changed = 1;
00162         if (physts.phy_full_duplex)
00163             lpc_emac_set_duplex(1);
00164         else
00165             lpc_emac_set_duplex(0);
00166 
00167         olddphysts.phy_full_duplex = physts.phy_full_duplex;
00168     }
00169 
00170     if (physts.phy_link_active != olddphysts.phy_link_active) {
00171         changed = 1;
00172 #if NO_SYS == 1
00173         if (physts.phy_link_active)
00174             netif_set_link_up(netif);
00175         else
00176             netif_set_link_down(netif);
00177 #else
00178         if (physts.phy_link_active)
00179             tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
00180                 (void*) netif, 1);
00181          else
00182             tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
00183                 (void*) netif, 1);
00184 #endif
00185 
00186         olddphysts.phy_link_active = physts.phy_link_active;
00187     }
00188 
00189     return changed;
00190 }
00191 
00192 /** \brief  Initialize the DP83848 PHY.
00193  *
00194  *  This function initializes the DP83848 PHY. It will block until
00195  *  complete. This function is called as part of the EMAC driver
00196  *  initialization. Configuration of the PHY at startup is
00197  *  controlled by setting up configuration defines in lpc_phy.h.
00198  *
00199  *  \param[in]     netif   NETIF structure
00200  *  \param[in]     rmii    If set, configures the PHY for RMII mode
00201  *  \return         ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
00202  */
00203 err_t lpc_phy_init(struct netif *netif, int rmii)
00204 {
00205     u32_t tmp;
00206     s32_t i;
00207 
00208     physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
00209     physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
00210     physts.phy_link_active = olddphysts.phy_link_active = 2;
00211     phyustate = 0;
00212 
00213     /* Only first read and write are checked for failure */
00214     /* Put the DP83848C in reset mode and wait for completion */
00215     if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
00216         return ERR_TIMEOUT;
00217     i = 400;
00218     while (i > 0) {
00219         osDelay(1);   /* 1 ms */
00220         if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
00221             return ERR_TIMEOUT;
00222 
00223         if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
00224             i = -1;
00225         else
00226             i--;
00227     }
00228     /* Timeout? */
00229     if (i == 0)
00230         return ERR_TIMEOUT;
00231 
00232     /* Setup link based on configuration options */
00233 #if PHY_USE_AUTONEG==1
00234     tmp = DP8_AUTONEG;
00235 #else
00236     tmp = 0;
00237 #endif
00238 #if PHY_USE_100MBS==1
00239     tmp |= DP8_SPEED_SELECT;
00240 #endif
00241 #if PHY_USE_FULL_DUPLEX==1
00242     tmp |= DP8_DUPLEX_MODE;
00243 #endif
00244     lpc_mii_write(DP8_BMCR_REG, tmp);
00245 
00246     /* Enable RMII mode for PHY */
00247     if (rmii)
00248         lpc_mii_write(DP8_PHY_RBR_REG, DP8_RBR_RMII_MODE);
00249 
00250     /* The link is not set active at this point, but will be detected
00251        later */
00252 
00253     return ERR_OK;
00254 }
00255 
00256 /* Phy status update state machine */
00257 s32_t lpc_phy_sts_sm(struct netif *netif)
00258 {
00259     s32_t changed = 0;
00260 
00261     switch (phyustate) {
00262         default:
00263         case 0:
00264             /* Read BMSR to clear faults */
00265             lpc_mii_read_noblock(DP8_PHY_STAT_REG);
00266             phyustate = 1;
00267             break;
00268 
00269         case 1:
00270             /* Wait for read status state */
00271             if (!lpc_mii_is_busy()) {
00272                 /* Update PHY status */
00273                 changed = lpc_update_phy_sts(netif, lpc_mii_read_data());
00274                 phyustate = 0;
00275             }
00276             break;
00277     }
00278 
00279     return changed;
00280 }
00281 
00282 /**
00283  * @}
00284  */
00285 
00286 /* --------------------------------- End Of File ------------------------------ */