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targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.c@188:60408c49b6d4, 2018-09-20 (annotated)

Committer:
WaleedElmughrabi
Date:
Thu Sep 20 16:11:23 2018 +0000
Revision:
188:60408c49b6d4
Parent:
182:a56a73fd2a6f 
Fork modified for BG96 error

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 161:2cc1468da177 1 /**
<> 161:2cc1468da177 2 ******************************************************************************
<> 161:2cc1468da177 3 * @file stm32f7xx_ll_usart.c
<> 161:2cc1468da177 4 * @author MCD Application Team
<> 161:2cc1468da177 5 * @brief USART LL module driver.
<> 161:2cc1468da177 6 ******************************************************************************
<> 161:2cc1468da177 7 * @attention
<> 161:2cc1468da177 8 *
<> 161:2cc1468da177 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 161:2cc1468da177 10 *
<> 161:2cc1468da177 11 * Redistribution and use in source and binary forms, with or without modification,
<> 161:2cc1468da177 12 * are permitted provided that the following conditions are met:
<> 161:2cc1468da177 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 161:2cc1468da177 14 * this list of conditions and the following disclaimer.
<> 161:2cc1468da177 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 161:2cc1468da177 16 * this list of conditions and the following disclaimer in the documentation
<> 161:2cc1468da177 17 * and/or other materials provided with the distribution.
<> 161:2cc1468da177 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 161:2cc1468da177 19 * may be used to endorse or promote products derived from this software
<> 161:2cc1468da177 20 * without specific prior written permission.
<> 161:2cc1468da177 21 *
<> 161:2cc1468da177 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 161:2cc1468da177 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 161:2cc1468da177 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 161:2cc1468da177 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 161:2cc1468da177 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 161:2cc1468da177 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 161:2cc1468da177 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 161:2cc1468da177 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 161:2cc1468da177 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 161:2cc1468da177 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 161:2cc1468da177 32 *
<> 161:2cc1468da177 33 ******************************************************************************
<> 161:2cc1468da177 34 */
<> 161:2cc1468da177 35 #if defined(USE_FULL_LL_DRIVER)
<> 161:2cc1468da177 36
<> 161:2cc1468da177 37 /* Includes ------------------------------------------------------------------*/
<> 161:2cc1468da177 38 #include "stm32f7xx_ll_usart.h"
<> 161:2cc1468da177 39 #include "stm32f7xx_ll_rcc.h"
<> 161:2cc1468da177 40 #include "stm32f7xx_ll_bus.h"
<> 161:2cc1468da177 41 #ifdef USE_FULL_ASSERT
<> 161:2cc1468da177 42 #include "stm32_assert.h"
<> 161:2cc1468da177 43 #else
<> 161:2cc1468da177 44 #define assert_param(expr) ((void)0U)
<> 161:2cc1468da177 45 #endif
<> 161:2cc1468da177 46
<> 161:2cc1468da177 47 /** @addtogroup STM32F7xx_LL_Driver
<> 161:2cc1468da177 48 * @{
<> 161:2cc1468da177 49 */
<> 161:2cc1468da177 50
<> 161:2cc1468da177 51 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8)
<> 161:2cc1468da177 52
<> 161:2cc1468da177 53 /** @addtogroup USART_LL
<> 161:2cc1468da177 54 * @{
<> 161:2cc1468da177 55 */
<> 161:2cc1468da177 56
<> 161:2cc1468da177 57 /* Private types -------------------------------------------------------------*/
<> 161:2cc1468da177 58 /* Private variables ---------------------------------------------------------*/
<> 161:2cc1468da177 59 /* Private constants ---------------------------------------------------------*/
<> 161:2cc1468da177 60 /** @addtogroup USART_LL_Private_Constants
<> 161:2cc1468da177 61 * @{
<> 161:2cc1468da177 62 */
<> 161:2cc1468da177 63
<> 161:2cc1468da177 64 /**
<> 161:2cc1468da177 65 * @}
<> 161:2cc1468da177 66 */
<> 161:2cc1468da177 67
<> 161:2cc1468da177 68
<> 161:2cc1468da177 69 /* Private macros ------------------------------------------------------------*/
<> 161:2cc1468da177 70 /** @addtogroup USART_LL_Private_Macros
<> 161:2cc1468da177 71 * @{
<> 161:2cc1468da177 72 */
<> 161:2cc1468da177 73
<> 161:2cc1468da177 74 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
<> 161:2cc1468da177 75 * divided by the smallest oversampling used on the USART (i.e. 8) */
<> 161:2cc1468da177 76 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U)
<> 161:2cc1468da177 77
<> 161:2cc1468da177 78 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
AnnaBridge 182:a56a73fd2a6f 79 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
AnnaBridge 182:a56a73fd2a6f 80
AnnaBridge 182:a56a73fd2a6f 81 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
AnnaBridge 182:a56a73fd2a6f 82 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
<> 161:2cc1468da177 83
<> 161:2cc1468da177 84 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
<> 161:2cc1468da177 85 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
<> 161:2cc1468da177 86 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
<> 161:2cc1468da177 87 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
<> 161:2cc1468da177 88
<> 161:2cc1468da177 89 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
<> 161:2cc1468da177 90 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
<> 161:2cc1468da177 91 || ((__VALUE__) == LL_USART_PARITY_ODD))
<> 161:2cc1468da177 92
<> 161:2cc1468da177 93 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
<> 161:2cc1468da177 94 || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
<> 161:2cc1468da177 95 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
<> 161:2cc1468da177 96
<> 161:2cc1468da177 97 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
<> 161:2cc1468da177 98 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
<> 161:2cc1468da177 99
<> 161:2cc1468da177 100 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
<> 161:2cc1468da177 101 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
<> 161:2cc1468da177 102
<> 161:2cc1468da177 103 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
<> 161:2cc1468da177 104 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
<> 161:2cc1468da177 105
<> 161:2cc1468da177 106 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
<> 161:2cc1468da177 107 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
<> 161:2cc1468da177 108
<> 161:2cc1468da177 109 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
<> 161:2cc1468da177 110 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
<> 161:2cc1468da177 111
<> 161:2cc1468da177 112 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
<> 161:2cc1468da177 113 || ((__VALUE__) == LL_USART_STOPBITS_1) \
<> 161:2cc1468da177 114 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
<> 161:2cc1468da177 115 || ((__VALUE__) == LL_USART_STOPBITS_2))
<> 161:2cc1468da177 116
<> 161:2cc1468da177 117 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
<> 161:2cc1468da177 118 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
<> 161:2cc1468da177 119 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
<> 161:2cc1468da177 120 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
<> 161:2cc1468da177 121
<> 161:2cc1468da177 122 /**
<> 161:2cc1468da177 123 * @}
<> 161:2cc1468da177 124 */
<> 161:2cc1468da177 125
<> 161:2cc1468da177 126 /* Private function prototypes -----------------------------------------------*/
<> 161:2cc1468da177 127
<> 161:2cc1468da177 128 /* Exported functions --------------------------------------------------------*/
<> 161:2cc1468da177 129 /** @addtogroup USART_LL_Exported_Functions
<> 161:2cc1468da177 130 * @{
<> 161:2cc1468da177 131 */
<> 161:2cc1468da177 132
<> 161:2cc1468da177 133 /** @addtogroup USART_LL_EF_Init
<> 161:2cc1468da177 134 * @{
<> 161:2cc1468da177 135 */
<> 161:2cc1468da177 136
<> 161:2cc1468da177 137 /**
<> 161:2cc1468da177 138 * @brief De-initialize USART registers (Registers restored to their default values).
<> 161:2cc1468da177 139 * @param USARTx USART Instance
<> 161:2cc1468da177 140 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 141 * - SUCCESS: USART registers are de-initialized
<> 161:2cc1468da177 142 * - ERROR: USART registers are not de-initialized
<> 161:2cc1468da177 143 */
<> 161:2cc1468da177 144 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
<> 161:2cc1468da177 145 {
<> 161:2cc1468da177 146 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 147
<> 161:2cc1468da177 148 /* Check the parameters */
<> 161:2cc1468da177 149 assert_param(IS_UART_INSTANCE(USARTx));
<> 161:2cc1468da177 150
<> 161:2cc1468da177 151 if (USARTx == USART1)
<> 161:2cc1468da177 152 {
<> 161:2cc1468da177 153 /* Force reset of USART clock */
<> 161:2cc1468da177 154 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
<> 161:2cc1468da177 155
<> 161:2cc1468da177 156 /* Release reset of USART clock */
<> 161:2cc1468da177 157 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
<> 161:2cc1468da177 158 }
<> 161:2cc1468da177 159 else if (USARTx == USART2)
<> 161:2cc1468da177 160 {
<> 161:2cc1468da177 161 /* Force reset of USART clock */
<> 161:2cc1468da177 162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
<> 161:2cc1468da177 163
<> 161:2cc1468da177 164 /* Release reset of USART clock */
<> 161:2cc1468da177 165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
<> 161:2cc1468da177 166 }
<> 161:2cc1468da177 167 else if (USARTx == USART3)
<> 161:2cc1468da177 168 {
<> 161:2cc1468da177 169 /* Force reset of USART clock */
<> 161:2cc1468da177 170 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
<> 161:2cc1468da177 171
<> 161:2cc1468da177 172 /* Release reset of USART clock */
<> 161:2cc1468da177 173 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
<> 161:2cc1468da177 174 }
<> 161:2cc1468da177 175 else if (USARTx == USART6)
<> 161:2cc1468da177 176 {
<> 161:2cc1468da177 177 /* Force reset of USART clock */
<> 161:2cc1468da177 178 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
<> 161:2cc1468da177 179
<> 161:2cc1468da177 180 /* Release reset of USART clock */
<> 161:2cc1468da177 181 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
<> 161:2cc1468da177 182 }
<> 161:2cc1468da177 183 else if (USARTx == UART4)
<> 161:2cc1468da177 184 {
<> 161:2cc1468da177 185 /* Force reset of UART clock */
<> 161:2cc1468da177 186 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
<> 161:2cc1468da177 187
<> 161:2cc1468da177 188 /* Release reset of UART clock */
<> 161:2cc1468da177 189 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
<> 161:2cc1468da177 190 }
<> 161:2cc1468da177 191 else if (USARTx == UART5)
<> 161:2cc1468da177 192 {
<> 161:2cc1468da177 193 /* Force reset of UART clock */
<> 161:2cc1468da177 194 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
<> 161:2cc1468da177 195
<> 161:2cc1468da177 196 /* Release reset of UART clock */
<> 161:2cc1468da177 197 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
<> 161:2cc1468da177 198 }
<> 161:2cc1468da177 199 else if (USARTx == UART7)
<> 161:2cc1468da177 200 {
<> 161:2cc1468da177 201 /* Force reset of UART clock */
<> 161:2cc1468da177 202 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
<> 161:2cc1468da177 203
<> 161:2cc1468da177 204 /* Release reset of UART clock */
<> 161:2cc1468da177 205 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
<> 161:2cc1468da177 206 }
<> 161:2cc1468da177 207 else if (USARTx == UART8)
<> 161:2cc1468da177 208 {
<> 161:2cc1468da177 209 /* Force reset of UART clock */
<> 161:2cc1468da177 210 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
<> 161:2cc1468da177 211
<> 161:2cc1468da177 212 /* Release reset of UART clock */
<> 161:2cc1468da177 213 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
<> 161:2cc1468da177 214 }
<> 161:2cc1468da177 215 else
<> 161:2cc1468da177 216 {
<> 161:2cc1468da177 217 status = ERROR;
<> 161:2cc1468da177 218 }
<> 161:2cc1468da177 219
<> 161:2cc1468da177 220 return (status);
<> 161:2cc1468da177 221 }
<> 161:2cc1468da177 222
<> 161:2cc1468da177 223 /**
<> 161:2cc1468da177 224 * @brief Initialize USART registers according to the specified
<> 161:2cc1468da177 225 * parameters in USART_InitStruct.
<> 161:2cc1468da177 226 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 161:2cc1468da177 227 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 161:2cc1468da177 228 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
<> 161:2cc1468da177 229 * @param USARTx USART Instance
AnnaBridge 182:a56a73fd2a6f 230 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
<> 161:2cc1468da177 231 * that contains the configuration information for the specified USART peripheral.
<> 161:2cc1468da177 232 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 233 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
<> 161:2cc1468da177 234 * - ERROR: Problem occurred during USART Registers initialization
<> 161:2cc1468da177 235 */
<> 161:2cc1468da177 236 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
<> 161:2cc1468da177 237 {
<> 161:2cc1468da177 238 ErrorStatus status = ERROR;
<> 161:2cc1468da177 239 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
<> 161:2cc1468da177 240
<> 161:2cc1468da177 241 /* Check the parameters */
<> 161:2cc1468da177 242 assert_param(IS_UART_INSTANCE(USARTx));
<> 161:2cc1468da177 243 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
<> 161:2cc1468da177 244 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
<> 161:2cc1468da177 245 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
<> 161:2cc1468da177 246 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
<> 161:2cc1468da177 247 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
<> 161:2cc1468da177 248 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
<> 161:2cc1468da177 249 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
<> 161:2cc1468da177 250
<> 161:2cc1468da177 251 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 161:2cc1468da177 252 CRx registers */
<> 161:2cc1468da177 253 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 161:2cc1468da177 254 {
<> 161:2cc1468da177 255 /*---------------------------- USART CR1 Configuration ---------------------
<> 161:2cc1468da177 256 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
<> 161:2cc1468da177 257 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
<> 161:2cc1468da177 258 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
<> 161:2cc1468da177 259 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
<> 161:2cc1468da177 260 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
<> 161:2cc1468da177 261 */
<> 161:2cc1468da177 262 MODIFY_REG(USARTx->CR1,
<> 161:2cc1468da177 263 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
<> 161:2cc1468da177 264 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
<> 161:2cc1468da177 265 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
<> 161:2cc1468da177 266 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
<> 161:2cc1468da177 267
<> 161:2cc1468da177 268 /*---------------------------- USART CR2 Configuration ---------------------
<> 161:2cc1468da177 269 * Configure USARTx CR2 (Stop bits) with parameters:
<> 161:2cc1468da177 270 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
<> 161:2cc1468da177 271 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
<> 161:2cc1468da177 272 */
<> 161:2cc1468da177 273 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
<> 161:2cc1468da177 274
<> 161:2cc1468da177 275 /*---------------------------- USART CR3 Configuration ---------------------
<> 161:2cc1468da177 276 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
<> 161:2cc1468da177 277 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
<> 161:2cc1468da177 278 */
<> 161:2cc1468da177 279 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
<> 161:2cc1468da177 280
<> 161:2cc1468da177 281 /*---------------------------- USART BRR Configuration ---------------------
<> 161:2cc1468da177 282 * Retrieve Clock frequency used for USART Peripheral
<> 161:2cc1468da177 283 */
<> 161:2cc1468da177 284 if (USARTx == USART1)
<> 161:2cc1468da177 285 {
<> 161:2cc1468da177 286 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
<> 161:2cc1468da177 287 }
<> 161:2cc1468da177 288 else if (USARTx == USART2)
<> 161:2cc1468da177 289 {
<> 161:2cc1468da177 290 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
<> 161:2cc1468da177 291 }
<> 161:2cc1468da177 292 else if (USARTx == USART3)
<> 161:2cc1468da177 293 {
<> 161:2cc1468da177 294 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
<> 161:2cc1468da177 295 }
<> 161:2cc1468da177 296 else if (USARTx == USART6)
<> 161:2cc1468da177 297 {
<> 161:2cc1468da177 298 periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
<> 161:2cc1468da177 299 }
<> 161:2cc1468da177 300 else if (USARTx == UART4)
<> 161:2cc1468da177 301 {
<> 161:2cc1468da177 302 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
<> 161:2cc1468da177 303 }
<> 161:2cc1468da177 304 else if (USARTx == UART5)
<> 161:2cc1468da177 305 {
<> 161:2cc1468da177 306 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
<> 161:2cc1468da177 307 }
<> 161:2cc1468da177 308 else if (USARTx == UART7)
<> 161:2cc1468da177 309 {
<> 161:2cc1468da177 310 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE);
<> 161:2cc1468da177 311 }
<> 161:2cc1468da177 312 else if (USARTx == UART8)
<> 161:2cc1468da177 313 {
<> 161:2cc1468da177 314 periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE);
<> 161:2cc1468da177 315 }
<> 161:2cc1468da177 316 else
<> 161:2cc1468da177 317 {
<> 161:2cc1468da177 318 /* Nothing to do, as error code is already assigned to ERROR value */
<> 161:2cc1468da177 319 }
<> 161:2cc1468da177 320
<> 161:2cc1468da177 321 /* Configure the USART Baud Rate :
<> 161:2cc1468da177 322 - valid baud rate value (different from 0) is required
<> 161:2cc1468da177 323 - Peripheral clock as returned by RCC service, should be valid (different from 0).
<> 161:2cc1468da177 324 */
<> 161:2cc1468da177 325 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
<> 161:2cc1468da177 326 && (USART_InitStruct->BaudRate != 0U))
<> 161:2cc1468da177 327 {
<> 161:2cc1468da177 328 status = SUCCESS;
<> 161:2cc1468da177 329 LL_USART_SetBaudRate(USARTx,
<> 161:2cc1468da177 330 periphclk,
<> 161:2cc1468da177 331 USART_InitStruct->OverSampling,
<> 161:2cc1468da177 332 USART_InitStruct->BaudRate);
<> 161:2cc1468da177 333
<> 161:2cc1468da177 334 /* Check BRR is greater than or equal to 16d */
AnnaBridge 182:a56a73fd2a6f 335 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
AnnaBridge 182:a56a73fd2a6f 336
AnnaBridge 182:a56a73fd2a6f 337 /* Check BRR is greater than or equal to 16d */
AnnaBridge 182:a56a73fd2a6f 338 assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
<> 161:2cc1468da177 339 }
<> 161:2cc1468da177 340 }
<> 161:2cc1468da177 341 /* Endif (=> USART not in Disabled state => return ERROR) */
<> 161:2cc1468da177 342
<> 161:2cc1468da177 343 return (status);
<> 161:2cc1468da177 344 }
<> 161:2cc1468da177 345
<> 161:2cc1468da177 346 /**
<> 161:2cc1468da177 347 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
AnnaBridge 182:a56a73fd2a6f 348 * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
<> 161:2cc1468da177 349 * whose fields will be set to default values.
<> 161:2cc1468da177 350 * @retval None
<> 161:2cc1468da177 351 */
<> 161:2cc1468da177 352
<> 161:2cc1468da177 353 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
<> 161:2cc1468da177 354 {
<> 161:2cc1468da177 355 /* Set USART_InitStruct fields to default values */
<> 161:2cc1468da177 356 USART_InitStruct->BaudRate = 9600U;
<> 161:2cc1468da177 357 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
<> 161:2cc1468da177 358 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
<> 161:2cc1468da177 359 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
<> 161:2cc1468da177 360 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
<> 161:2cc1468da177 361 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
<> 161:2cc1468da177 362 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
<> 161:2cc1468da177 363 }
<> 161:2cc1468da177 364
<> 161:2cc1468da177 365 /**
<> 161:2cc1468da177 366 * @brief Initialize USART Clock related settings according to the
<> 161:2cc1468da177 367 * specified parameters in the USART_ClockInitStruct.
<> 161:2cc1468da177 368 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
<> 161:2cc1468da177 369 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
<> 161:2cc1468da177 370 * @param USARTx USART Instance
AnnaBridge 182:a56a73fd2a6f 371 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 161:2cc1468da177 372 * that contains the Clock configuration information for the specified USART peripheral.
<> 161:2cc1468da177 373 * @retval An ErrorStatus enumeration value:
<> 161:2cc1468da177 374 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
<> 161:2cc1468da177 375 * - ERROR: Problem occurred during USART Registers initialization
<> 161:2cc1468da177 376 */
<> 161:2cc1468da177 377 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 161:2cc1468da177 378 {
<> 161:2cc1468da177 379 ErrorStatus status = SUCCESS;
<> 161:2cc1468da177 380
<> 161:2cc1468da177 381 /* Check USART Instance and Clock signal output parameters */
<> 161:2cc1468da177 382 assert_param(IS_UART_INSTANCE(USARTx));
<> 161:2cc1468da177 383 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
<> 161:2cc1468da177 384
<> 161:2cc1468da177 385 /* USART needs to be in disabled state, in order to be able to configure some bits in
<> 161:2cc1468da177 386 CRx registers */
<> 161:2cc1468da177 387 if (LL_USART_IsEnabled(USARTx) == 0U)
<> 161:2cc1468da177 388 {
<> 161:2cc1468da177 389 /*---------------------------- USART CR2 Configuration -----------------------*/
<> 161:2cc1468da177 390 /* If Clock signal has to be output */
<> 161:2cc1468da177 391 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
<> 161:2cc1468da177 392 {
<> 161:2cc1468da177 393 /* Deactivate Clock signal delivery :
<> 161:2cc1468da177 394 * - Disable Clock Output: USART_CR2_CLKEN cleared
<> 161:2cc1468da177 395 */
<> 161:2cc1468da177 396 LL_USART_DisableSCLKOutput(USARTx);
<> 161:2cc1468da177 397 }
<> 161:2cc1468da177 398 else
<> 161:2cc1468da177 399 {
<> 161:2cc1468da177 400 /* Ensure USART instance is USART capable */
<> 161:2cc1468da177 401 assert_param(IS_USART_INSTANCE(USARTx));
<> 161:2cc1468da177 402
<> 161:2cc1468da177 403 /* Check clock related parameters */
<> 161:2cc1468da177 404 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
<> 161:2cc1468da177 405 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
<> 161:2cc1468da177 406 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
<> 161:2cc1468da177 407
<> 161:2cc1468da177 408 /*---------------------------- USART CR2 Configuration -----------------------
<> 161:2cc1468da177 409 * Configure USARTx CR2 (Clock signal related bits) with parameters:
<> 161:2cc1468da177 410 * - Enable Clock Output: USART_CR2_CLKEN set
<> 161:2cc1468da177 411 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
<> 161:2cc1468da177 412 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
<> 161:2cc1468da177 413 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
<> 161:2cc1468da177 414 */
<> 161:2cc1468da177 415 MODIFY_REG(USARTx->CR2,
<> 161:2cc1468da177 416 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
<> 161:2cc1468da177 417 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
<> 161:2cc1468da177 418 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
<> 161:2cc1468da177 419 }
<> 161:2cc1468da177 420 }
<> 161:2cc1468da177 421 /* Else (USART not in Disabled state => return ERROR */
<> 161:2cc1468da177 422 else
<> 161:2cc1468da177 423 {
<> 161:2cc1468da177 424 status = ERROR;
<> 161:2cc1468da177 425 }
<> 161:2cc1468da177 426
<> 161:2cc1468da177 427 return (status);
<> 161:2cc1468da177 428 }
<> 161:2cc1468da177 429
<> 161:2cc1468da177 430 /**
<> 161:2cc1468da177 431 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
AnnaBridge 182:a56a73fd2a6f 432 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
<> 161:2cc1468da177 433 * whose fields will be set to default values.
<> 161:2cc1468da177 434 * @retval None
<> 161:2cc1468da177 435 */
<> 161:2cc1468da177 436 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
<> 161:2cc1468da177 437 {
<> 161:2cc1468da177 438 /* Set LL_USART_ClockInitStruct fields with default values */
<> 161:2cc1468da177 439 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
<> 161:2cc1468da177 440 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 161:2cc1468da177 441 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 161:2cc1468da177 442 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
<> 161:2cc1468da177 443 }
<> 161:2cc1468da177 444
<> 161:2cc1468da177 445 /**
<> 161:2cc1468da177 446 * @}
<> 161:2cc1468da177 447 */
<> 161:2cc1468da177 448
<> 161:2cc1468da177 449 /**
<> 161:2cc1468da177 450 * @}
<> 161:2cc1468da177 451 */
<> 161:2cc1468da177 452
<> 161:2cc1468da177 453 /**
<> 161:2cc1468da177 454 * @}
<> 161:2cc1468da177 455 */
<> 161:2cc1468da177 456
<> 161:2cc1468da177 457 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
<> 161:2cc1468da177 458
<> 161:2cc1468da177 459 /**
<> 161:2cc1468da177 460 * @}
<> 161:2cc1468da177 461 */
<> 161:2cc1468da177 462
<> 161:2cc1468da177 463 #endif /* USE_FULL_LL_DRIVER */
<> 161:2cc1468da177 464
<> 161:2cc1468da177 465 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 161:2cc1468da177 466