SilentSensors
/
mbed-dev
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
mbed-dev
by 
mbed official
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_ll_spi.c@188:60408c49b6d4, 2018-09-20 (annotated)
- Committer:
- WaleedElmughrabi
- Date:
- Thu Sep 20 16:11:23 2018 +0000
- Revision:
- 188:60408c49b6d4
- Parent:
- 186:707f6e361f3e
Fork modified for BG96 error
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| <> | 157:ff67d9f36b67 | 1 | /** |
| <> | 157:ff67d9f36b67 | 2 | ****************************************************************************** |
| <> | 157:ff67d9f36b67 | 3 | * @file stm32f3xx_ll_spi.c |
| <> | 157:ff67d9f36b67 | 4 | * @author MCD Application Team |
| <> | 157:ff67d9f36b67 | 5 | * @brief SPI LL module driver. |
| <> | 157:ff67d9f36b67 | 6 | ****************************************************************************** |
| <> | 157:ff67d9f36b67 | 7 | * @attention |
| <> | 157:ff67d9f36b67 | 8 | * |
| <> | 157:ff67d9f36b67 | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| <> | 157:ff67d9f36b67 | 10 | * |
| <> | 157:ff67d9f36b67 | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| <> | 157:ff67d9f36b67 | 12 | * are permitted provided that the following conditions are met: |
| <> | 157:ff67d9f36b67 | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| <> | 157:ff67d9f36b67 | 14 | * this list of conditions and the following disclaimer. |
| <> | 157:ff67d9f36b67 | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| <> | 157:ff67d9f36b67 | 16 | * this list of conditions and the following disclaimer in the documentation |
| <> | 157:ff67d9f36b67 | 17 | * and/or other materials provided with the distribution. |
| <> | 157:ff67d9f36b67 | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| <> | 157:ff67d9f36b67 | 19 | * may be used to endorse or promote products derived from this software |
| <> | 157:ff67d9f36b67 | 20 | * without specific prior written permission. |
| <> | 157:ff67d9f36b67 | 21 | * |
| <> | 157:ff67d9f36b67 | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| <> | 157:ff67d9f36b67 | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| <> | 157:ff67d9f36b67 | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| <> | 157:ff67d9f36b67 | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| <> | 157:ff67d9f36b67 | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| <> | 157:ff67d9f36b67 | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| <> | 157:ff67d9f36b67 | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| <> | 157:ff67d9f36b67 | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| <> | 157:ff67d9f36b67 | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| <> | 157:ff67d9f36b67 | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| <> | 157:ff67d9f36b67 | 32 | * |
| <> | 157:ff67d9f36b67 | 33 | ****************************************************************************** |
| <> | 157:ff67d9f36b67 | 34 | */ |
| <> | 157:ff67d9f36b67 | 35 | #if defined(USE_FULL_LL_DRIVER) |
| <> | 157:ff67d9f36b67 | 36 | |
| <> | 157:ff67d9f36b67 | 37 | /* Includes ------------------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 38 | #include "stm32f3xx_ll_spi.h" |
| <> | 157:ff67d9f36b67 | 39 | #include "stm32f3xx_ll_bus.h" |
| <> | 157:ff67d9f36b67 | 40 | #include "stm32f3xx_ll_rcc.h" |
| <> | 157:ff67d9f36b67 | 41 | |
| <> | 157:ff67d9f36b67 | 42 | #ifdef USE_FULL_ASSERT |
| <> | 157:ff67d9f36b67 | 43 | #include "stm32_assert.h" |
| <> | 157:ff67d9f36b67 | 44 | #else |
| <> | 157:ff67d9f36b67 | 45 | #define assert_param(expr) ((void)0U) |
| <> | 157:ff67d9f36b67 | 46 | #endif |
| <> | 157:ff67d9f36b67 | 47 | |
| <> | 157:ff67d9f36b67 | 48 | /** @addtogroup STM32F3xx_LL_Driver |
| <> | 157:ff67d9f36b67 | 49 | * @{ |
| <> | 157:ff67d9f36b67 | 50 | */ |
| <> | 157:ff67d9f36b67 | 51 | |
| <> | 157:ff67d9f36b67 | 52 | #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) |
| <> | 157:ff67d9f36b67 | 53 | |
| <> | 157:ff67d9f36b67 | 54 | /** @addtogroup SPI_LL |
| <> | 157:ff67d9f36b67 | 55 | * @{ |
| <> | 157:ff67d9f36b67 | 56 | */ |
| <> | 157:ff67d9f36b67 | 57 | |
| <> | 157:ff67d9f36b67 | 58 | /* Private types -------------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 59 | /* Private variables ---------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 60 | |
| <> | 157:ff67d9f36b67 | 61 | /* Private constants ---------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 62 | /** @defgroup SPI_LL_Private_Constants SPI Private Constants |
| <> | 157:ff67d9f36b67 | 63 | * @{ |
| <> | 157:ff67d9f36b67 | 64 | */ |
| <> | 157:ff67d9f36b67 | 65 | /* SPI registers Masks */ |
| <> | 157:ff67d9f36b67 | 66 | #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ |
| <> | 157:ff67d9f36b67 | 67 | SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ |
| <> | 157:ff67d9f36b67 | 68 | SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \ |
| <> | 157:ff67d9f36b67 | 69 | SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ |
| <> | 157:ff67d9f36b67 | 70 | SPI_CR1_BIDIMODE) |
| <> | 157:ff67d9f36b67 | 71 | /** |
| <> | 157:ff67d9f36b67 | 72 | * @} |
| <> | 157:ff67d9f36b67 | 73 | */ |
| <> | 157:ff67d9f36b67 | 74 | |
| <> | 157:ff67d9f36b67 | 75 | /* Private macros ------------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 76 | /** @defgroup SPI_LL_Private_Macros SPI Private Macros |
| <> | 157:ff67d9f36b67 | 77 | * @{ |
| <> | 157:ff67d9f36b67 | 78 | */ |
| <> | 157:ff67d9f36b67 | 79 | #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ |
| <> | 157:ff67d9f36b67 | 80 | || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ |
| <> | 157:ff67d9f36b67 | 81 | || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ |
| <> | 157:ff67d9f36b67 | 82 | || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) |
| <> | 157:ff67d9f36b67 | 83 | |
| <> | 157:ff67d9f36b67 | 84 | #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ |
| <> | 157:ff67d9f36b67 | 85 | || ((__VALUE__) == LL_SPI_MODE_SLAVE)) |
| <> | 157:ff67d9f36b67 | 86 | |
| <> | 157:ff67d9f36b67 | 87 | #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ |
| <> | 157:ff67d9f36b67 | 88 | || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ |
| <> | 157:ff67d9f36b67 | 89 | || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ |
| <> | 157:ff67d9f36b67 | 90 | || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ |
| <> | 157:ff67d9f36b67 | 91 | || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ |
| <> | 157:ff67d9f36b67 | 92 | || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ |
| <> | 157:ff67d9f36b67 | 93 | || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ |
| <> | 157:ff67d9f36b67 | 94 | || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ |
| <> | 157:ff67d9f36b67 | 95 | || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ |
| <> | 157:ff67d9f36b67 | 96 | || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ |
| <> | 157:ff67d9f36b67 | 97 | || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ |
| <> | 157:ff67d9f36b67 | 98 | || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ |
| <> | 157:ff67d9f36b67 | 99 | || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) |
| <> | 157:ff67d9f36b67 | 100 | |
| <> | 157:ff67d9f36b67 | 101 | #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ |
| <> | 157:ff67d9f36b67 | 102 | || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) |
| <> | 157:ff67d9f36b67 | 103 | |
| <> | 157:ff67d9f36b67 | 104 | #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ |
| <> | 157:ff67d9f36b67 | 105 | || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) |
| <> | 157:ff67d9f36b67 | 106 | |
| <> | 157:ff67d9f36b67 | 107 | #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ |
| <> | 157:ff67d9f36b67 | 108 | || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ |
| <> | 157:ff67d9f36b67 | 109 | || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) |
| <> | 157:ff67d9f36b67 | 110 | |
| <> | 157:ff67d9f36b67 | 111 | #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ |
| <> | 157:ff67d9f36b67 | 112 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ |
| <> | 157:ff67d9f36b67 | 113 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ |
| <> | 157:ff67d9f36b67 | 114 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ |
| <> | 157:ff67d9f36b67 | 115 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ |
| <> | 157:ff67d9f36b67 | 116 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ |
| <> | 157:ff67d9f36b67 | 117 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ |
| <> | 157:ff67d9f36b67 | 118 | || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) |
| <> | 157:ff67d9f36b67 | 119 | |
| <> | 157:ff67d9f36b67 | 120 | #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ |
| <> | 157:ff67d9f36b67 | 121 | || ((__VALUE__) == LL_SPI_MSB_FIRST)) |
| <> | 157:ff67d9f36b67 | 122 | |
| <> | 157:ff67d9f36b67 | 123 | #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ |
| <> | 157:ff67d9f36b67 | 124 | || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) |
| <> | 157:ff67d9f36b67 | 125 | |
| <> | 157:ff67d9f36b67 | 126 | #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) |
| <> | 157:ff67d9f36b67 | 127 | |
| <> | 157:ff67d9f36b67 | 128 | /** |
| <> | 157:ff67d9f36b67 | 129 | * @} |
| <> | 157:ff67d9f36b67 | 130 | */ |
| <> | 157:ff67d9f36b67 | 131 | |
| <> | 157:ff67d9f36b67 | 132 | /* Private function prototypes -----------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 133 | |
| <> | 157:ff67d9f36b67 | 134 | /* Exported functions --------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 135 | /** @addtogroup SPI_LL_Exported_Functions |
| <> | 157:ff67d9f36b67 | 136 | * @{ |
| <> | 157:ff67d9f36b67 | 137 | */ |
| <> | 157:ff67d9f36b67 | 138 | |
| <> | 157:ff67d9f36b67 | 139 | /** @addtogroup SPI_LL_EF_Init |
| <> | 157:ff67d9f36b67 | 140 | * @{ |
| <> | 157:ff67d9f36b67 | 141 | */ |
| <> | 157:ff67d9f36b67 | 142 | |
| <> | 157:ff67d9f36b67 | 143 | /** |
| <> | 157:ff67d9f36b67 | 144 | * @brief De-initialize the SPI registers to their default reset values. |
| <> | 157:ff67d9f36b67 | 145 | * @param SPIx SPI Instance |
| <> | 157:ff67d9f36b67 | 146 | * @retval An ErrorStatus enumeration value: |
| <> | 157:ff67d9f36b67 | 147 | * - SUCCESS: SPI registers are de-initialized |
| <> | 157:ff67d9f36b67 | 148 | * - ERROR: SPI registers are not de-initialized |
| <> | 157:ff67d9f36b67 | 149 | */ |
| <> | 157:ff67d9f36b67 | 150 | ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) |
| <> | 157:ff67d9f36b67 | 151 | { |
| <> | 157:ff67d9f36b67 | 152 | ErrorStatus status = ERROR; |
| <> | 157:ff67d9f36b67 | 153 | |
| <> | 157:ff67d9f36b67 | 154 | /* Check the parameters */ |
| <> | 157:ff67d9f36b67 | 155 | assert_param(IS_SPI_ALL_INSTANCE(SPIx)); |
| <> | 157:ff67d9f36b67 | 156 | |
| <> | 157:ff67d9f36b67 | 157 | #if defined(SPI1) |
| <> | 157:ff67d9f36b67 | 158 | if (SPIx == SPI1) |
| <> | 157:ff67d9f36b67 | 159 | { |
| <> | 157:ff67d9f36b67 | 160 | /* Force reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 161 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); |
| <> | 157:ff67d9f36b67 | 162 | |
| <> | 157:ff67d9f36b67 | 163 | /* Release reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 164 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); |
| <> | 157:ff67d9f36b67 | 165 | |
| <> | 157:ff67d9f36b67 | 166 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 167 | } |
| <> | 157:ff67d9f36b67 | 168 | #endif /* SPI1 */ |
| <> | 157:ff67d9f36b67 | 169 | #if defined(SPI2) |
| <> | 157:ff67d9f36b67 | 170 | if (SPIx == SPI2) |
| <> | 157:ff67d9f36b67 | 171 | { |
| <> | 157:ff67d9f36b67 | 172 | /* Force reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 173 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); |
| <> | 157:ff67d9f36b67 | 174 | |
| <> | 157:ff67d9f36b67 | 175 | /* Release reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 176 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); |
| <> | 157:ff67d9f36b67 | 177 | |
| <> | 157:ff67d9f36b67 | 178 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 179 | } |
| <> | 157:ff67d9f36b67 | 180 | #endif /* SPI2 */ |
| <> | 157:ff67d9f36b67 | 181 | #if defined(SPI3) |
| <> | 157:ff67d9f36b67 | 182 | if (SPIx == SPI3) |
| <> | 157:ff67d9f36b67 | 183 | { |
| <> | 157:ff67d9f36b67 | 184 | /* Force reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 185 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); |
| <> | 157:ff67d9f36b67 | 186 | |
| <> | 157:ff67d9f36b67 | 187 | /* Release reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 188 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); |
| <> | 157:ff67d9f36b67 | 189 | |
| <> | 157:ff67d9f36b67 | 190 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 191 | } |
| <> | 157:ff67d9f36b67 | 192 | #endif /* SPI3 */ |
| <> | 157:ff67d9f36b67 | 193 | #if defined(SPI4) |
| <> | 157:ff67d9f36b67 | 194 | if (SPIx == SPI4) |
| <> | 157:ff67d9f36b67 | 195 | { |
| <> | 157:ff67d9f36b67 | 196 | /* Force reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 197 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); |
| <> | 157:ff67d9f36b67 | 198 | |
| <> | 157:ff67d9f36b67 | 199 | /* Release reset of SPI clock */ |
| <> | 157:ff67d9f36b67 | 200 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); |
| <> | 157:ff67d9f36b67 | 201 | |
| <> | 157:ff67d9f36b67 | 202 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 203 | } |
| <> | 157:ff67d9f36b67 | 204 | #endif /* SPI4 */ |
| <> | 157:ff67d9f36b67 | 205 | |
| <> | 157:ff67d9f36b67 | 206 | return status; |
| <> | 157:ff67d9f36b67 | 207 | } |
| <> | 157:ff67d9f36b67 | 208 | |
| <> | 157:ff67d9f36b67 | 209 | /** |
| <> | 157:ff67d9f36b67 | 210 | * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. |
| <> | 157:ff67d9f36b67 | 211 | * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), |
| <> | 157:ff67d9f36b67 | 212 | * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. |
| <> | 157:ff67d9f36b67 | 213 | * @param SPIx SPI Instance |
| <> | 157:ff67d9f36b67 | 214 | * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure |
| <> | 157:ff67d9f36b67 | 215 | * @retval An ErrorStatus enumeration value. (Return always SUCCESS) |
| <> | 157:ff67d9f36b67 | 216 | */ |
| <> | 157:ff67d9f36b67 | 217 | ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) |
| <> | 157:ff67d9f36b67 | 218 | { |
| <> | 157:ff67d9f36b67 | 219 | ErrorStatus status = ERROR; |
| <> | 157:ff67d9f36b67 | 220 | |
| <> | 157:ff67d9f36b67 | 221 | /* Check the SPI Instance SPIx*/ |
| <> | 157:ff67d9f36b67 | 222 | assert_param(IS_SPI_ALL_INSTANCE(SPIx)); |
| <> | 157:ff67d9f36b67 | 223 | |
| <> | 157:ff67d9f36b67 | 224 | /* Check the SPI parameters from SPI_InitStruct*/ |
| <> | 157:ff67d9f36b67 | 225 | assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); |
| <> | 157:ff67d9f36b67 | 226 | assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); |
| <> | 157:ff67d9f36b67 | 227 | assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); |
| <> | 157:ff67d9f36b67 | 228 | assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); |
| <> | 157:ff67d9f36b67 | 229 | assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); |
| <> | 157:ff67d9f36b67 | 230 | assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); |
| <> | 157:ff67d9f36b67 | 231 | assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); |
| <> | 157:ff67d9f36b67 | 232 | assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); |
| <> | 157:ff67d9f36b67 | 233 | assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); |
| <> | 157:ff67d9f36b67 | 234 | |
| <> | 157:ff67d9f36b67 | 235 | if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) |
| <> | 157:ff67d9f36b67 | 236 | { |
| <> | 157:ff67d9f36b67 | 237 | /*---------------------------- SPIx CR1 Configuration ------------------------ |
| <> | 157:ff67d9f36b67 | 238 | * Configure SPIx CR1 with parameters: |
| <> | 157:ff67d9f36b67 | 239 | * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits |
| <> | 157:ff67d9f36b67 | 240 | * - Master/Slave Mode: SPI_CR1_MSTR bit |
| <> | 157:ff67d9f36b67 | 241 | * - ClockPolarity: SPI_CR1_CPOL bit |
| <> | 157:ff67d9f36b67 | 242 | * - ClockPhase: SPI_CR1_CPHA bit |
| <> | 157:ff67d9f36b67 | 243 | * - NSS management: SPI_CR1_SSM bit |
| <> | 157:ff67d9f36b67 | 244 | * - BaudRate prescaler: SPI_CR1_BR[2:0] bits |
| <> | 157:ff67d9f36b67 | 245 | * - BitOrder: SPI_CR1_LSBFIRST bit |
| <> | 157:ff67d9f36b67 | 246 | * - CRCCalculation: SPI_CR1_CRCEN bit |
| <> | 157:ff67d9f36b67 | 247 | */ |
| <> | 157:ff67d9f36b67 | 248 | MODIFY_REG(SPIx->CR1, |
| <> | 157:ff67d9f36b67 | 249 | SPI_CR1_CLEAR_MASK, |
| <> | 157:ff67d9f36b67 | 250 | SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | |
| <> | 157:ff67d9f36b67 | 251 | SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | |
| <> | 157:ff67d9f36b67 | 252 | SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | |
| <> | 157:ff67d9f36b67 | 253 | SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); |
| <> | 157:ff67d9f36b67 | 254 | |
| <> | 157:ff67d9f36b67 | 255 | /*---------------------------- SPIx CR2 Configuration ------------------------ |
| <> | 157:ff67d9f36b67 | 256 | * Configure SPIx CR2 with parameters: |
| <> | 157:ff67d9f36b67 | 257 | * - DataWidth: DS[3:0] bits |
| <> | 157:ff67d9f36b67 | 258 | * - NSS management: SSOE bit |
| <> | 157:ff67d9f36b67 | 259 | */ |
| <> | 157:ff67d9f36b67 | 260 | MODIFY_REG(SPIx->CR2, |
| <> | 157:ff67d9f36b67 | 261 | SPI_CR2_DS | SPI_CR2_SSOE, |
| <> | 157:ff67d9f36b67 | 262 | SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); |
| <> | 157:ff67d9f36b67 | 263 | |
| <> | 157:ff67d9f36b67 | 264 | /*---------------------------- SPIx CRCPR Configuration ---------------------- |
| <> | 157:ff67d9f36b67 | 265 | * Configure SPIx CRCPR with parameters: |
| <> | 157:ff67d9f36b67 | 266 | * - CRCPoly: CRCPOLY[15:0] bits |
| <> | 157:ff67d9f36b67 | 267 | */ |
| <> | 157:ff67d9f36b67 | 268 | if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) |
| <> | 157:ff67d9f36b67 | 269 | { |
| <> | 157:ff67d9f36b67 | 270 | assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); |
| <> | 157:ff67d9f36b67 | 271 | LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); |
| <> | 157:ff67d9f36b67 | 272 | } |
| <> | 157:ff67d9f36b67 | 273 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 274 | } |
| <> | 157:ff67d9f36b67 | 275 | |
| <> | 157:ff67d9f36b67 | 276 | #if defined (SPI_I2S_SUPPORT) |
| <> | 157:ff67d9f36b67 | 277 | /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ |
| <> | 157:ff67d9f36b67 | 278 | CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); |
| <> | 157:ff67d9f36b67 | 279 | #endif /* SPI_I2S_SUPPORT */ |
| <> | 157:ff67d9f36b67 | 280 | return status; |
| <> | 157:ff67d9f36b67 | 281 | } |
| <> | 157:ff67d9f36b67 | 282 | |
| <> | 157:ff67d9f36b67 | 283 | /** |
| <> | 157:ff67d9f36b67 | 284 | * @brief Set each @ref LL_SPI_InitTypeDef field to default value. |
| <> | 157:ff67d9f36b67 | 285 | * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure |
| <> | 157:ff67d9f36b67 | 286 | * whose fields will be set to default values. |
| <> | 157:ff67d9f36b67 | 287 | * @retval None |
| <> | 157:ff67d9f36b67 | 288 | */ |
| <> | 157:ff67d9f36b67 | 289 | void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) |
| <> | 157:ff67d9f36b67 | 290 | { |
| <> | 157:ff67d9f36b67 | 291 | /* Set SPI_InitStruct fields to default values */ |
| <> | 157:ff67d9f36b67 | 292 | SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; |
| <> | 157:ff67d9f36b67 | 293 | SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; |
| <> | 157:ff67d9f36b67 | 294 | SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; |
| <> | 157:ff67d9f36b67 | 295 | SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; |
| <> | 157:ff67d9f36b67 | 296 | SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; |
| <> | 157:ff67d9f36b67 | 297 | SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; |
| <> | 157:ff67d9f36b67 | 298 | SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; |
| <> | 157:ff67d9f36b67 | 299 | SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; |
| <> | 157:ff67d9f36b67 | 300 | SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; |
| <> | 157:ff67d9f36b67 | 301 | SPI_InitStruct->CRCPoly = 7U; |
| <> | 157:ff67d9f36b67 | 302 | } |
| <> | 157:ff67d9f36b67 | 303 | |
| <> | 157:ff67d9f36b67 | 304 | /** |
| <> | 157:ff67d9f36b67 | 305 | * @} |
| <> | 157:ff67d9f36b67 | 306 | */ |
| <> | 157:ff67d9f36b67 | 307 | |
| <> | 157:ff67d9f36b67 | 308 | /** |
| <> | 157:ff67d9f36b67 | 309 | * @} |
| <> | 157:ff67d9f36b67 | 310 | */ |
| <> | 157:ff67d9f36b67 | 311 | |
| <> | 157:ff67d9f36b67 | 312 | /** |
| <> | 157:ff67d9f36b67 | 313 | * @} |
| <> | 157:ff67d9f36b67 | 314 | */ |
| <> | 157:ff67d9f36b67 | 315 | |
| <> | 157:ff67d9f36b67 | 316 | #if defined(SPI_I2S_SUPPORT) |
| <> | 157:ff67d9f36b67 | 317 | /** @addtogroup I2S_LL |
| <> | 157:ff67d9f36b67 | 318 | * @{ |
| <> | 157:ff67d9f36b67 | 319 | */ |
| <> | 157:ff67d9f36b67 | 320 | |
| <> | 157:ff67d9f36b67 | 321 | /* Private types -------------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 322 | /* Private variables ---------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 323 | /* Private constants ---------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 324 | /** @defgroup I2S_LL_Private_Constants I2S Private Constants |
| <> | 157:ff67d9f36b67 | 325 | * @{ |
| <> | 157:ff67d9f36b67 | 326 | */ |
| <> | 157:ff67d9f36b67 | 327 | /* I2S registers Masks */ |
| <> | 157:ff67d9f36b67 | 328 | #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ |
| <> | 157:ff67d9f36b67 | 329 | SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ |
| <> | 157:ff67d9f36b67 | 330 | SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) |
| <> | 157:ff67d9f36b67 | 331 | |
| <> | 157:ff67d9f36b67 | 332 | #define I2S_I2SPR_CLEAR_MASK 0x0002U |
| <> | 157:ff67d9f36b67 | 333 | /** |
| <> | 157:ff67d9f36b67 | 334 | * @} |
| <> | 157:ff67d9f36b67 | 335 | */ |
| <> | 157:ff67d9f36b67 | 336 | /* Private macros ------------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 337 | /** @defgroup I2S_LL_Private_Macros I2S Private Macros |
| <> | 157:ff67d9f36b67 | 338 | * @{ |
| <> | 157:ff67d9f36b67 | 339 | */ |
| <> | 157:ff67d9f36b67 | 340 | |
| <> | 157:ff67d9f36b67 | 341 | #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ |
| <> | 157:ff67d9f36b67 | 342 | || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ |
| <> | 157:ff67d9f36b67 | 343 | || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ |
| <> | 157:ff67d9f36b67 | 344 | || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) |
| <> | 157:ff67d9f36b67 | 345 | |
| <> | 157:ff67d9f36b67 | 346 | #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ |
| <> | 157:ff67d9f36b67 | 347 | || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) |
| <> | 157:ff67d9f36b67 | 348 | |
| <> | 157:ff67d9f36b67 | 349 | #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ |
| <> | 157:ff67d9f36b67 | 350 | || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ |
| <> | 157:ff67d9f36b67 | 351 | || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ |
| <> | 157:ff67d9f36b67 | 352 | || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ |
| <> | 157:ff67d9f36b67 | 353 | || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) |
| <> | 157:ff67d9f36b67 | 354 | |
| <> | 157:ff67d9f36b67 | 355 | #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ |
| <> | 157:ff67d9f36b67 | 356 | || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ |
| <> | 157:ff67d9f36b67 | 357 | || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ |
| <> | 157:ff67d9f36b67 | 358 | || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) |
| <> | 157:ff67d9f36b67 | 359 | |
| <> | 157:ff67d9f36b67 | 360 | #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ |
| <> | 157:ff67d9f36b67 | 361 | || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) |
| <> | 157:ff67d9f36b67 | 362 | |
| <> | 157:ff67d9f36b67 | 363 | #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ |
| <> | 157:ff67d9f36b67 | 364 | && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ |
| <> | 157:ff67d9f36b67 | 365 | || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) |
| <> | 157:ff67d9f36b67 | 366 | |
| <> | 157:ff67d9f36b67 | 367 | #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) |
| <> | 157:ff67d9f36b67 | 368 | |
| <> | 157:ff67d9f36b67 | 369 | #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ |
| <> | 157:ff67d9f36b67 | 370 | || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) |
| <> | 157:ff67d9f36b67 | 371 | /** |
| <> | 157:ff67d9f36b67 | 372 | * @} |
| <> | 157:ff67d9f36b67 | 373 | */ |
| <> | 157:ff67d9f36b67 | 374 | |
| <> | 157:ff67d9f36b67 | 375 | /* Private function prototypes -----------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 376 | |
| <> | 157:ff67d9f36b67 | 377 | /* Exported functions --------------------------------------------------------*/ |
| <> | 157:ff67d9f36b67 | 378 | /** @addtogroup I2S_LL_Exported_Functions |
| <> | 157:ff67d9f36b67 | 379 | * @{ |
| <> | 157:ff67d9f36b67 | 380 | */ |
| <> | 157:ff67d9f36b67 | 381 | |
| <> | 157:ff67d9f36b67 | 382 | /** @addtogroup I2S_LL_EF_Init |
| <> | 157:ff67d9f36b67 | 383 | * @{ |
| <> | 157:ff67d9f36b67 | 384 | */ |
| <> | 157:ff67d9f36b67 | 385 | |
| <> | 157:ff67d9f36b67 | 386 | /** |
| <> | 157:ff67d9f36b67 | 387 | * @brief De-initialize the SPI/I2S registers to their default reset values. |
| <> | 157:ff67d9f36b67 | 388 | * @param SPIx SPI Instance |
| <> | 157:ff67d9f36b67 | 389 | * @retval An ErrorStatus enumeration value: |
| <> | 157:ff67d9f36b67 | 390 | * - SUCCESS: SPI registers are de-initialized |
| <> | 157:ff67d9f36b67 | 391 | * - ERROR: SPI registers are not de-initialized |
| <> | 157:ff67d9f36b67 | 392 | */ |
| <> | 157:ff67d9f36b67 | 393 | ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) |
| <> | 157:ff67d9f36b67 | 394 | { |
| <> | 157:ff67d9f36b67 | 395 | return LL_SPI_DeInit(SPIx); |
| <> | 157:ff67d9f36b67 | 396 | } |
| <> | 157:ff67d9f36b67 | 397 | |
| <> | 157:ff67d9f36b67 | 398 | /** |
| <> | 157:ff67d9f36b67 | 399 | * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. |
| <> | 157:ff67d9f36b67 | 400 | * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), |
| <> | 157:ff67d9f36b67 | 401 | * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. |
| <> | 157:ff67d9f36b67 | 402 | * @param SPIx SPI Instance |
| <> | 157:ff67d9f36b67 | 403 | * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure |
| <> | 157:ff67d9f36b67 | 404 | * @retval An ErrorStatus enumeration value: |
| <> | 157:ff67d9f36b67 | 405 | * - SUCCESS: SPI registers are Initialized |
| <> | 157:ff67d9f36b67 | 406 | * - ERROR: SPI registers are not Initialized |
| <> | 157:ff67d9f36b67 | 407 | */ |
| <> | 157:ff67d9f36b67 | 408 | ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) |
| <> | 157:ff67d9f36b67 | 409 | { |
| <> | 157:ff67d9f36b67 | 410 | uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; |
| <> | 157:ff67d9f36b67 | 411 | uint32_t tmp = 0U; |
| <> | 157:ff67d9f36b67 | 412 | LL_RCC_ClocksTypeDef rcc_clocks; |
| <> | 157:ff67d9f36b67 | 413 | uint32_t sourceclock = 0U; |
| <> | 157:ff67d9f36b67 | 414 | ErrorStatus status = ERROR; |
| <> | 157:ff67d9f36b67 | 415 | |
| <> | 157:ff67d9f36b67 | 416 | /* Check the I2S parameters */ |
| <> | 157:ff67d9f36b67 | 417 | assert_param(IS_I2S_ALL_INSTANCE(SPIx)); |
| <> | 157:ff67d9f36b67 | 418 | assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); |
| <> | 157:ff67d9f36b67 | 419 | assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); |
| <> | 157:ff67d9f36b67 | 420 | assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); |
| <> | 157:ff67d9f36b67 | 421 | assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); |
| <> | 157:ff67d9f36b67 | 422 | assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); |
| <> | 157:ff67d9f36b67 | 423 | assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); |
| <> | 157:ff67d9f36b67 | 424 | |
| <> | 157:ff67d9f36b67 | 425 | if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) |
| <> | 157:ff67d9f36b67 | 426 | { |
| <> | 157:ff67d9f36b67 | 427 | /*---------------------------- SPIx I2SCFGR Configuration -------------------- |
| <> | 157:ff67d9f36b67 | 428 | * Configure SPIx I2SCFGR with parameters: |
| <> | 157:ff67d9f36b67 | 429 | * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit |
| <> | 157:ff67d9f36b67 | 430 | * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits |
| <> | 157:ff67d9f36b67 | 431 | * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits |
| <> | 157:ff67d9f36b67 | 432 | * - ClockPolarity: SPI_I2SCFGR_CKPOL bit |
| <> | 157:ff67d9f36b67 | 433 | */ |
| <> | 157:ff67d9f36b67 | 434 | |
| <> | 157:ff67d9f36b67 | 435 | /* Write to SPIx I2SCFGR */ |
| <> | 157:ff67d9f36b67 | 436 | MODIFY_REG(SPIx->I2SCFGR, |
| <> | 157:ff67d9f36b67 | 437 | I2S_I2SCFGR_CLEAR_MASK, |
| <> | 157:ff67d9f36b67 | 438 | I2S_InitStruct->Mode | I2S_InitStruct->Standard | |
| <> | 157:ff67d9f36b67 | 439 | I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | |
| <> | 157:ff67d9f36b67 | 440 | SPI_I2SCFGR_I2SMOD); |
| <> | 157:ff67d9f36b67 | 441 | |
| <> | 157:ff67d9f36b67 | 442 | /*---------------------------- SPIx I2SPR Configuration ---------------------- |
| <> | 157:ff67d9f36b67 | 443 | * Configure SPIx I2SPR with parameters: |
| <> | 157:ff67d9f36b67 | 444 | * - MCLKOutput: SPI_I2SPR_MCKOE bit |
| <> | 157:ff67d9f36b67 | 445 | * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits |
| <> | 157:ff67d9f36b67 | 446 | */ |
| <> | 157:ff67d9f36b67 | 447 | |
| <> | 157:ff67d9f36b67 | 448 | /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) |
| <> | 157:ff67d9f36b67 | 449 | * else, default values are used: i2sodd = 0U, i2sdiv = 2U. |
| <> | 157:ff67d9f36b67 | 450 | */ |
| <> | 157:ff67d9f36b67 | 451 | if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) |
| <> | 157:ff67d9f36b67 | 452 | { |
| <> | 157:ff67d9f36b67 | 453 | /* Check the frame length (For the Prescaler computing) |
| <> | 157:ff67d9f36b67 | 454 | * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). |
| <> | 157:ff67d9f36b67 | 455 | */ |
| <> | 157:ff67d9f36b67 | 456 | if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) |
| <> | 157:ff67d9f36b67 | 457 | { |
| <> | 157:ff67d9f36b67 | 458 | /* Packet length is 32 bits */ |
| <> | 157:ff67d9f36b67 | 459 | packetlength = 2U; |
| <> | 157:ff67d9f36b67 | 460 | } |
| <> | 157:ff67d9f36b67 | 461 | |
| <> | 157:ff67d9f36b67 | 462 | /* I2S Clock source is System clock: Get System Clock frequency */ |
| <> | 157:ff67d9f36b67 | 463 | LL_RCC_GetSystemClocksFreq(&rcc_clocks); |
| <> | 157:ff67d9f36b67 | 464 | |
| <> | 157:ff67d9f36b67 | 465 | /* Get the source clock value: based on System Clock value */ |
| <> | 157:ff67d9f36b67 | 466 | sourceclock = rcc_clocks.SYSCLK_Frequency; |
| <> | 157:ff67d9f36b67 | 467 | |
| <> | 157:ff67d9f36b67 | 468 | /* Compute the Real divider depending on the MCLK output state with a floating point */ |
| <> | 157:ff67d9f36b67 | 469 | if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) |
| <> | 157:ff67d9f36b67 | 470 | { |
| <> | 157:ff67d9f36b67 | 471 | /* MCLK output is enabled */ |
| <> | 157:ff67d9f36b67 | 472 | tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); |
| <> | 157:ff67d9f36b67 | 473 | } |
| <> | 157:ff67d9f36b67 | 474 | else |
| <> | 157:ff67d9f36b67 | 475 | { |
| <> | 157:ff67d9f36b67 | 476 | /* MCLK output is disabled */ |
| <> | 157:ff67d9f36b67 | 477 | tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); |
| <> | 157:ff67d9f36b67 | 478 | } |
| <> | 157:ff67d9f36b67 | 479 | |
| <> | 157:ff67d9f36b67 | 480 | /* Remove the floating point */ |
| <> | 157:ff67d9f36b67 | 481 | tmp = tmp / 10U; |
| <> | 157:ff67d9f36b67 | 482 | |
| <> | 157:ff67d9f36b67 | 483 | /* Check the parity of the divider */ |
| <> | 157:ff67d9f36b67 | 484 | i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); |
| <> | 157:ff67d9f36b67 | 485 | |
| <> | 157:ff67d9f36b67 | 486 | /* Compute the i2sdiv prescaler */ |
| <> | 157:ff67d9f36b67 | 487 | i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); |
| <> | 157:ff67d9f36b67 | 488 | |
| <> | 157:ff67d9f36b67 | 489 | /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ |
| <> | 157:ff67d9f36b67 | 490 | i2sodd = (uint16_t)(i2sodd << 8U); |
| <> | 157:ff67d9f36b67 | 491 | } |
| <> | 157:ff67d9f36b67 | 492 | |
| <> | 157:ff67d9f36b67 | 493 | /* Test if the divider is 1 or 0 or greater than 0xFF */ |
| <> | 157:ff67d9f36b67 | 494 | if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) |
| <> | 157:ff67d9f36b67 | 495 | { |
| <> | 157:ff67d9f36b67 | 496 | /* Set the default values */ |
| <> | 157:ff67d9f36b67 | 497 | i2sdiv = 2U; |
| <> | 157:ff67d9f36b67 | 498 | i2sodd = 0U; |
| <> | 157:ff67d9f36b67 | 499 | } |
| <> | 157:ff67d9f36b67 | 500 | |
| <> | 157:ff67d9f36b67 | 501 | /* Write to SPIx I2SPR register the computed value */ |
| <> | 157:ff67d9f36b67 | 502 | WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); |
| <> | 157:ff67d9f36b67 | 503 | |
| <> | 157:ff67d9f36b67 | 504 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 505 | } |
| <> | 157:ff67d9f36b67 | 506 | return status; |
| <> | 157:ff67d9f36b67 | 507 | } |
| <> | 157:ff67d9f36b67 | 508 | |
| <> | 157:ff67d9f36b67 | 509 | /** |
| <> | 157:ff67d9f36b67 | 510 | * @brief Set each @ref LL_I2S_InitTypeDef field to default value. |
| <> | 157:ff67d9f36b67 | 511 | * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure |
| <> | 157:ff67d9f36b67 | 512 | * whose fields will be set to default values. |
| <> | 157:ff67d9f36b67 | 513 | * @retval None |
| <> | 157:ff67d9f36b67 | 514 | */ |
| <> | 157:ff67d9f36b67 | 515 | void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) |
| <> | 157:ff67d9f36b67 | 516 | { |
| <> | 157:ff67d9f36b67 | 517 | /*--------------- Reset I2S init structure parameters values -----------------*/ |
| <> | 157:ff67d9f36b67 | 518 | I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; |
| <> | 157:ff67d9f36b67 | 519 | I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; |
| <> | 157:ff67d9f36b67 | 520 | I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; |
| <> | 157:ff67d9f36b67 | 521 | I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; |
| <> | 157:ff67d9f36b67 | 522 | I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; |
| <> | 157:ff67d9f36b67 | 523 | I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; |
| <> | 157:ff67d9f36b67 | 524 | } |
| <> | 157:ff67d9f36b67 | 525 | |
| <> | 157:ff67d9f36b67 | 526 | /** |
| <> | 157:ff67d9f36b67 | 527 | * @brief Set linear and parity prescaler. |
| <> | 157:ff67d9f36b67 | 528 | * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n |
| <> | 157:ff67d9f36b67 | 529 | * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). |
| <> | 157:ff67d9f36b67 | 530 | * @param SPIx SPI Instance |
| <> | 157:ff67d9f36b67 | 531 | * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. |
| <> | 157:ff67d9f36b67 | 532 | * @param PrescalerParity This parameter can be one of the following values: |
| <> | 157:ff67d9f36b67 | 533 | * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN |
| <> | 157:ff67d9f36b67 | 534 | * @arg @ref LL_I2S_PRESCALER_PARITY_ODD |
| <> | 157:ff67d9f36b67 | 535 | * @retval None |
| <> | 157:ff67d9f36b67 | 536 | */ |
| <> | 157:ff67d9f36b67 | 537 | void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) |
| <> | 157:ff67d9f36b67 | 538 | { |
| <> | 157:ff67d9f36b67 | 539 | /* Check the I2S parameters */ |
| <> | 157:ff67d9f36b67 | 540 | assert_param(IS_I2S_ALL_INSTANCE(SPIx)); |
| <> | 157:ff67d9f36b67 | 541 | assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); |
| <> | 157:ff67d9f36b67 | 542 | assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); |
| <> | 157:ff67d9f36b67 | 543 | |
| <> | 157:ff67d9f36b67 | 544 | /* Write to SPIx I2SPR */ |
| <> | 157:ff67d9f36b67 | 545 | MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); |
| <> | 157:ff67d9f36b67 | 546 | } |
| <> | 157:ff67d9f36b67 | 547 | |
| <> | 157:ff67d9f36b67 | 548 | #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) |
| <> | 157:ff67d9f36b67 | 549 | /** |
| <> | 157:ff67d9f36b67 | 550 | * @brief Configures the full duplex mode for the I2Sx peripheral using its extension |
| <> | 157:ff67d9f36b67 | 551 | * I2Sxext according to the specified parameters in the I2S_InitStruct. |
| <> | 157:ff67d9f36b67 | 552 | * @note The structure pointed by I2S_InitStruct parameter should be the same |
| <> | 157:ff67d9f36b67 | 553 | * used for the master I2S peripheral. In this case, if the master is |
| <> | 157:ff67d9f36b67 | 554 | * configured as transmitter, the slave will be receiver and vice versa. |
| <> | 157:ff67d9f36b67 | 555 | * Or you can force a different mode by modifying the field I2S_Mode to the |
| <> | 157:ff67d9f36b67 | 556 | * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration. |
| <> | 157:ff67d9f36b67 | 557 | * @param I2Sxext SPI Instance |
| <> | 157:ff67d9f36b67 | 558 | * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure |
| <> | 157:ff67d9f36b67 | 559 | * @retval An ErrorStatus enumeration value: |
| <> | 157:ff67d9f36b67 | 560 | * - SUCCESS: I2Sxext registers are Initialized |
| <> | 157:ff67d9f36b67 | 561 | * - ERROR: I2Sxext registers are not Initialized |
| <> | 157:ff67d9f36b67 | 562 | */ |
| <> | 157:ff67d9f36b67 | 563 | ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct) |
| <> | 157:ff67d9f36b67 | 564 | { |
| <> | 157:ff67d9f36b67 | 565 | uint16_t mode = 0U; |
| <> | 157:ff67d9f36b67 | 566 | ErrorStatus status = ERROR; |
| <> | 157:ff67d9f36b67 | 567 | |
| <> | 157:ff67d9f36b67 | 568 | /* Check the I2S parameters */ |
| <> | 157:ff67d9f36b67 | 569 | assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext)); |
| <> | 157:ff67d9f36b67 | 570 | assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); |
| <> | 157:ff67d9f36b67 | 571 | assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); |
| <> | 157:ff67d9f36b67 | 572 | assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); |
| <> | 157:ff67d9f36b67 | 573 | assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); |
| <> | 157:ff67d9f36b67 | 574 | |
| <> | 157:ff67d9f36b67 | 575 | if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U) |
| <> | 157:ff67d9f36b67 | 576 | { |
| <> | 157:ff67d9f36b67 | 577 | /*---------------------------- SPIx I2SCFGR Configuration -------------------- |
| <> | 157:ff67d9f36b67 | 578 | * Configure SPIx I2SCFGR with parameters: |
| <> | 157:ff67d9f36b67 | 579 | * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit |
| <> | 157:ff67d9f36b67 | 580 | * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits |
| <> | 157:ff67d9f36b67 | 581 | * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits |
| <> | 157:ff67d9f36b67 | 582 | * - ClockPolarity: SPI_I2SCFGR_CKPOL bit |
| <> | 157:ff67d9f36b67 | 583 | */ |
| <> | 157:ff67d9f36b67 | 584 | |
| <> | 157:ff67d9f36b67 | 585 | /* Reset I2SPR registers */ |
| <> | 157:ff67d9f36b67 | 586 | WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK); |
| <> | 157:ff67d9f36b67 | 587 | |
| <> | 157:ff67d9f36b67 | 588 | /* Get the mode to be configured for the extended I2S */ |
| <> | 157:ff67d9f36b67 | 589 | if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX)) |
| <> | 157:ff67d9f36b67 | 590 | { |
| <> | 157:ff67d9f36b67 | 591 | mode = LL_I2S_MODE_SLAVE_RX; |
| <> | 157:ff67d9f36b67 | 592 | } |
| <> | 157:ff67d9f36b67 | 593 | else |
| <> | 157:ff67d9f36b67 | 594 | { |
| <> | 157:ff67d9f36b67 | 595 | if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX)) |
| <> | 157:ff67d9f36b67 | 596 | { |
| <> | 157:ff67d9f36b67 | 597 | mode = LL_I2S_MODE_SLAVE_TX; |
| <> | 157:ff67d9f36b67 | 598 | } |
| <> | 157:ff67d9f36b67 | 599 | } |
| <> | 157:ff67d9f36b67 | 600 | |
| <> | 157:ff67d9f36b67 | 601 | /* Write to SPIx I2SCFGR */ |
| <> | 157:ff67d9f36b67 | 602 | MODIFY_REG(I2Sxext->I2SCFGR, |
| <> | 157:ff67d9f36b67 | 603 | I2S_I2SCFGR_CLEAR_MASK, |
| <> | 157:ff67d9f36b67 | 604 | I2S_InitStruct->Standard | |
| <> | 157:ff67d9f36b67 | 605 | I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | |
| <> | 157:ff67d9f36b67 | 606 | SPI_I2SCFGR_I2SMOD | mode); |
| <> | 157:ff67d9f36b67 | 607 | |
| <> | 157:ff67d9f36b67 | 608 | status = SUCCESS; |
| <> | 157:ff67d9f36b67 | 609 | } |
| <> | 157:ff67d9f36b67 | 610 | return status; |
| <> | 157:ff67d9f36b67 | 611 | } |
| <> | 157:ff67d9f36b67 | 612 | #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ |
| <> | 157:ff67d9f36b67 | 613 | |
| <> | 157:ff67d9f36b67 | 614 | /** |
| <> | 157:ff67d9f36b67 | 615 | * @} |
| <> | 157:ff67d9f36b67 | 616 | */ |
| <> | 157:ff67d9f36b67 | 617 | |
| <> | 157:ff67d9f36b67 | 618 | /** |
| <> | 157:ff67d9f36b67 | 619 | * @} |
| <> | 157:ff67d9f36b67 | 620 | */ |
| <> | 157:ff67d9f36b67 | 621 | |
| <> | 157:ff67d9f36b67 | 622 | /** |
| <> | 157:ff67d9f36b67 | 623 | * @} |
| <> | 157:ff67d9f36b67 | 624 | */ |
| <> | 157:ff67d9f36b67 | 625 | #endif /* SPI_I2S_SUPPORT */ |
| <> | 157:ff67d9f36b67 | 626 | |
| <> | 157:ff67d9f36b67 | 627 | #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */ |
| <> | 157:ff67d9f36b67 | 628 | |
| <> | 157:ff67d9f36b67 | 629 | /** |
| <> | 157:ff67d9f36b67 | 630 | * @} |
| <> | 157:ff67d9f36b67 | 631 | */ |
| <> | 157:ff67d9f36b67 | 632 | |
| <> | 157:ff67d9f36b67 | 633 | #endif /* USE_FULL_LL_DRIVER */ |
| <> | 157:ff67d9f36b67 | 634 | |
| <> | 157:ff67d9f36b67 | 635 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |