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targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_usart.h@188:60408c49b6d4, 2018-09-20 (annotated)

Committer:
WaleedElmughrabi
Date:
Thu Sep 20 16:11:23 2018 +0000
Revision:
188:60408c49b6d4
Parent:
186:707f6e361f3e 
Fork modified for BG96 error

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_usart.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of USART HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F3xx_HAL_USART_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F3xx_HAL_USART_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 45 #include "stm32f3xx_hal_def.h"
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 48 * @{
<> 144:ef7eb2e8f9f7 49 */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup USART
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 /** @defgroup USART_Exported_Types USART Exported Types
<> 144:ef7eb2e8f9f7 57 * @{
<> 144:ef7eb2e8f9f7 58 */
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 /**
<> 144:ef7eb2e8f9f7 61 * @brief USART Init Structure definition
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 typedef struct
<> 144:ef7eb2e8f9f7 64 {
<> 144:ef7eb2e8f9f7 65 uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
<> 144:ef7eb2e8f9f7 66 The baud rate is computed using the following formula:
<> 144:ef7eb2e8f9f7 67 Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<> 144:ef7eb2e8f9f7 70 This parameter can be a value of @ref USARTEx_Word_Length. */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<> 144:ef7eb2e8f9f7 73 This parameter can be a value of @ref USART_Stop_Bits. */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t Parity; /*!< Specifies the parity mode.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref USART_Parity
<> 144:ef7eb2e8f9f7 77 @note When parity is enabled, the computed parity is inserted
<> 144:ef7eb2e8f9f7 78 at the MSB position of the transmitted data (9th bit when
<> 144:ef7eb2e8f9f7 79 the word length is set to 9 data bits; 8th bit when the
<> 144:ef7eb2e8f9f7 80 word length is set to 8 data bits). */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref USART_Mode. */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref USART_Clock_Polarity. */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref USART_Clock_Phase. */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
<> 144:ef7eb2e8f9f7 92 data bit (MSB) has to be output on the SCLK pin in synchronous mode.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref USART_Last_Bit. */
<> 144:ef7eb2e8f9f7 94 }USART_InitTypeDef;
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /**
<> 144:ef7eb2e8f9f7 97 * @brief HAL USART State structures definition
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 typedef enum
<> 144:ef7eb2e8f9f7 100 {
<> 157:ff67d9f36b67 101 HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
<> 157:ff67d9f36b67 102 HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 157:ff67d9f36b67 103 HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
<> 157:ff67d9f36b67 104 HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
<> 157:ff67d9f36b67 105 HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
<> 157:ff67d9f36b67 106 HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
<> 157:ff67d9f36b67 107 HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
<> 157:ff67d9f36b67 108 HAL_USART_STATE_ERROR = 0x04U /*!< Error */
<> 144:ef7eb2e8f9f7 109 }HAL_USART_StateTypeDef;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @brief USART clock sources definitions
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114 typedef enum
<> 144:ef7eb2e8f9f7 115 {
<> 157:ff67d9f36b67 116 USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
<> 157:ff67d9f36b67 117 USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
<> 157:ff67d9f36b67 118 USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
<> 157:ff67d9f36b67 119 USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
<> 157:ff67d9f36b67 120 USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
<> 157:ff67d9f36b67 121 USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
<> 144:ef7eb2e8f9f7 122 }USART_ClockSourceTypeDef;
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /**
<> 144:ef7eb2e8f9f7 126 * @brief USART handle Structure definition
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 typedef struct
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 USART_TypeDef *Instance; /*!< USART registers base address */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 USART_InitTypeDef Init; /*!< USART communication parameters */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 uint16_t TxXferSize; /*!< USART Tx Transfer size */
<> 144:ef7eb2e8f9f7 137
<> 157:ff67d9f36b67 138 __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 uint16_t RxXferSize; /*!< USART Rx Transfer size */
<> 144:ef7eb2e8f9f7 143
<> 157:ff67d9f36b67 144 __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 uint16_t Mask; /*!< USART Rx RDR register mask */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 151
<> 157:ff67d9f36b67 152 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 153
<> 157:ff67d9f36b67 154 __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
<> 144:ef7eb2e8f9f7 155
<> 157:ff67d9f36b67 156 __IO uint32_t ErrorCode; /*!< USART Error code */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 }USART_HandleTypeDef;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /**
<> 144:ef7eb2e8f9f7 161 * @}
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /** @defgroup USART_Exported_Constants USART Exported Constants
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 /** @defgroup USART_Error USART Error
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 157:ff67d9f36b67 172 #define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
<> 157:ff67d9f36b67 173 #define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
<> 157:ff67d9f36b67 174 #define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
<> 157:ff67d9f36b67 175 #define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */
<> 157:ff67d9f36b67 176 #define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
<> 157:ff67d9f36b67 177 #define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 178 /**
<> 144:ef7eb2e8f9f7 179 * @}
<> 157:ff67d9f36b67 180 */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
<> 144:ef7eb2e8f9f7 183 * @{
<> 144:ef7eb2e8f9f7 184 */
<> 157:ff67d9f36b67 185 #define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
<> 157:ff67d9f36b67 186 #define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
<> 157:ff67d9f36b67 187 #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
<> 157:ff67d9f36b67 188 #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @}
<> 157:ff67d9f36b67 191 */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /** @defgroup USART_Parity USART Parity
<> 144:ef7eb2e8f9f7 194 * @{
<> 144:ef7eb2e8f9f7 195 */
<> 157:ff67d9f36b67 196 #define USART_PARITY_NONE (0x00000000U) /*!< No parity */
<> 144:ef7eb2e8f9f7 197 #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
<> 144:ef7eb2e8f9f7 198 #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @}
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup USART_Mode USART Mode
<> 144:ef7eb2e8f9f7 204 * @{
<> 144:ef7eb2e8f9f7 205 */
<> 157:ff67d9f36b67 206 #define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
<> 144:ef7eb2e8f9f7 207 #define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
<> 144:ef7eb2e8f9f7 208 #define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @}
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup USART_Clock USART Clock
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 157:ff67d9f36b67 216 #define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */
<> 144:ef7eb2e8f9f7 217 #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /** @defgroup USART_Clock_Polarity USART Clock Polarity
<> 144:ef7eb2e8f9f7 223 * @{
<> 144:ef7eb2e8f9f7 224 */
<> 157:ff67d9f36b67 225 #define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */
<> 157:ff67d9f36b67 226 #define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup USART_Clock_Phase USART Clock Phase
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
<> 157:ff67d9f36b67 234 #define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */
<> 144:ef7eb2e8f9f7 235 #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup USART_Last_Bit USART Last Bit
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 157:ff67d9f36b67 243 #define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
<> 144:ef7eb2e8f9f7 244 #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /** @defgroup USART_Request_Parameters USART Request Parameters
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 #define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 253 #define USART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @}
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** @defgroup USART_Flags USART Flags
<> 144:ef7eb2e8f9f7 259 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 260 * - 0xXXXX : Flag mask in the ISR register
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
<> 157:ff67d9f36b67 263 #define USART_FLAG_REACK (0x00400000U) /*!< USART receive enable acknowledge flag */
<> 157:ff67d9f36b67 264 #define USART_FLAG_TEACK (0x00200000U) /*!< USART transmit enable acknowledge flag */
<> 157:ff67d9f36b67 265 #define USART_FLAG_BUSY (0x00010000U) /*!< USART busy flag */
<> 157:ff67d9f36b67 266 #define USART_FLAG_CTS (0x00000400U) /*!< USART clear to send flag */
<> 157:ff67d9f36b67 267 #define USART_FLAG_CTSIF (0x00000200U) /*!< USART clear to send interrupt flag */
<> 157:ff67d9f36b67 268 #define USART_FLAG_LBDF (0x00000100U) /*!< USART LIN break detection flag */
<> 157:ff67d9f36b67 269 #define USART_FLAG_TXE (0x00000080U) /*!< USART transmit data register empty */
<> 157:ff67d9f36b67 270 #define USART_FLAG_TC (0x00000040U) /*!< USART transmission complete */
<> 157:ff67d9f36b67 271 #define USART_FLAG_RXNE (0x00000020U) /*!< USART read data register not empty */
<> 157:ff67d9f36b67 272 #define USART_FLAG_IDLE (0x00000010U) /*!< USART idle flag */
<> 157:ff67d9f36b67 273 #define USART_FLAG_ORE (0x00000008U) /*!< USART overrun error */
<> 157:ff67d9f36b67 274 #define USART_FLAG_NE (0x00000004U) /*!< USART noise error */
<> 157:ff67d9f36b67 275 #define USART_FLAG_FE (0x00000002U) /*!< USART frame error */
<> 157:ff67d9f36b67 276 #define USART_FLAG_PE (0x00000001U) /*!< USART parity error */
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @}
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
<> 144:ef7eb2e8f9f7 282 * Elements values convention: 0000ZZZZ0XXYYYYYb
<> 144:ef7eb2e8f9f7 283 * - YYYYY : Interrupt source position in the XX register (5bits)
<> 144:ef7eb2e8f9f7 284 * - XX : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 285 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 286 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 287 * - 11: CR3 register
<> 144:ef7eb2e8f9f7 288 * - ZZZZ : Flag position in the ISR register(4bits)
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 157:ff67d9f36b67 292 #define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */
<> 157:ff67d9f36b67 293 #define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */
<> 157:ff67d9f36b67 294 #define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */
<> 157:ff67d9f36b67 295 #define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */
<> 157:ff67d9f36b67 296 #define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */
<> 157:ff67d9f36b67 297 #define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */
<> 157:ff67d9f36b67 298 #define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */
<> 157:ff67d9f36b67 299 #define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */
<> 157:ff67d9f36b67 300 #define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */
<> 144:ef7eb2e8f9f7 301 /**
<> 144:ef7eb2e8f9f7 302 * @}
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308 #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
<> 144:ef7eb2e8f9f7 309 #define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
<> 144:ef7eb2e8f9f7 310 #define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
<> 144:ef7eb2e8f9f7 311 #define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
<> 144:ef7eb2e8f9f7 312 #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
<> 144:ef7eb2e8f9f7 313 #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
<> 144:ef7eb2e8f9f7 314 #define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
<> 144:ef7eb2e8f9f7 315 /**
<> 144:ef7eb2e8f9f7 316 * @}
<> 144:ef7eb2e8f9f7 317 */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
<> 144:ef7eb2e8f9f7 320 * @{
<> 144:ef7eb2e8f9f7 321 */
<> 157:ff67d9f36b67 322 #define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
<> 144:ef7eb2e8f9f7 323 /**
<> 144:ef7eb2e8f9f7 324 * @}
<> 144:ef7eb2e8f9f7 325 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 /**
<> 144:ef7eb2e8f9f7 328 * @}
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 332 /** @defgroup USART_Exported_Macros USART Exported Macros
<> 144:ef7eb2e8f9f7 333 * @{
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /** @brief Reset USART handle state.
Anna Bridge 186:707f6e361f3e 337 * @param __HANDLE__ USART handle.
<> 144:ef7eb2e8f9f7 338 * @retval None
<> 144:ef7eb2e8f9f7 339 */
<> 144:ef7eb2e8f9f7 340 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /** @brief Flush the USART Data registers.
Anna Bridge 186:707f6e361f3e 343 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 344 * @retval None
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346 #define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 347 do{ \
<> 144:ef7eb2e8f9f7 348 SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 349 SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
<> 157:ff67d9f36b67 350 } while(0U)
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /** @brief Check whether the specified USART flag is set or not.
Anna Bridge 186:707f6e361f3e 353 * @param __HANDLE__ specifies the USART Handle
Anna Bridge 186:707f6e361f3e 354 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 355 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 356 * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
<> 157:ff67d9f36b67 357 * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
<> 157:ff67d9f36b67 358 * @arg @ref USART_FLAG_BUSY Busy flag
<> 157:ff67d9f36b67 359 * @arg @ref USART_FLAG_CTS CTS Change flag
<> 157:ff67d9f36b67 360 * @arg @ref USART_FLAG_TXE Transmit data register empty flag
<> 157:ff67d9f36b67 361 * @arg @ref USART_FLAG_TC Transmission Complete flag
<> 157:ff67d9f36b67 362 * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
<> 157:ff67d9f36b67 363 * @arg @ref USART_FLAG_IDLE Idle Line detection flag
<> 157:ff67d9f36b67 364 * @arg @ref USART_FLAG_ORE OverRun Error flag
<> 157:ff67d9f36b67 365 * @arg @ref USART_FLAG_NE Noise Error flag
<> 157:ff67d9f36b67 366 * @arg @ref USART_FLAG_FE Framing Error flag
<> 157:ff67d9f36b67 367 * @arg @ref USART_FLAG_PE Parity Error flag
<> 144:ef7eb2e8f9f7 368 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /** @brief Clear the specified USART pending flag.
Anna Bridge 186:707f6e361f3e 373 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 374 * @param __FLAG__ specifies the flag to check.
<> 144:ef7eb2e8f9f7 375 * This parameter can be any combination of the following values:
<> 157:ff67d9f36b67 376 * @arg @ref USART_CLEAR_PEF
<> 157:ff67d9f36b67 377 * @arg @ref USART_CLEAR_FEF
<> 157:ff67d9f36b67 378 * @arg @ref USART_CLEAR_NEF
<> 157:ff67d9f36b67 379 * @arg @ref USART_CLEAR_OREF
<> 157:ff67d9f36b67 380 * @arg @ref USART_CLEAR_IDLEF
<> 157:ff67d9f36b67 381 * @arg @ref USART_CLEAR_TCF
<> 157:ff67d9f36b67 382 * @arg @ref USART_CLEAR_CTSF
<> 144:ef7eb2e8f9f7 383 * @retval None
<> 144:ef7eb2e8f9f7 384 */
<> 144:ef7eb2e8f9f7 385 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /** @brief Clear the USART PE pending flag.
Anna Bridge 186:707f6e361f3e 388 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 389 * @retval None
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /** @brief Clear the USART FE pending flag.
Anna Bridge 186:707f6e361f3e 394 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 395 * @retval None
<> 144:ef7eb2e8f9f7 396 */
<> 144:ef7eb2e8f9f7 397 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /** @brief Clear the USART NE pending flag.
Anna Bridge 186:707f6e361f3e 400 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 401 * @retval None
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 /** @brief Clear the USART ORE pending flag.
Anna Bridge 186:707f6e361f3e 406 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 407 * @retval None
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /** @brief Clear the USART IDLE pending flag.
Anna Bridge 186:707f6e361f3e 412 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 413 * @retval None
<> 144:ef7eb2e8f9f7 414 */
<> 144:ef7eb2e8f9f7 415 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /** @brief Enable the specified USART interrupt.
Anna Bridge 186:707f6e361f3e 418 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 419 * @param __INTERRUPT__ specifies the USART interrupt source to enable.
<> 144:ef7eb2e8f9f7 420 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 421 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
<> 157:ff67d9f36b67 422 * @arg @ref USART_IT_TC Transmission complete interrupt
<> 157:ff67d9f36b67 423 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
<> 157:ff67d9f36b67 424 * @arg @ref USART_IT_IDLE Idle line detection interrupt
<> 157:ff67d9f36b67 425 * @arg @ref USART_IT_PE Parity Error interrupt
<> 157:ff67d9f36b67 426 * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 427 * @retval None
<> 144:ef7eb2e8f9f7 428 */
<> 157:ff67d9f36b67 429 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
<> 157:ff67d9f36b67 430 ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
<> 144:ef7eb2e8f9f7 431 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @brief Disable the specified USART interrupt.
Anna Bridge 186:707f6e361f3e 434 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 435 * @param __INTERRUPT__ specifies the USART interrupt source to disable.
<> 144:ef7eb2e8f9f7 436 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 437 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
<> 157:ff67d9f36b67 438 * @arg @ref USART_IT_TC Transmission complete interrupt
<> 157:ff67d9f36b67 439 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
<> 157:ff67d9f36b67 440 * @arg @ref USART_IT_IDLE Idle line detection interrupt
<> 157:ff67d9f36b67 441 * @arg @ref USART_IT_PE Parity Error interrupt
<> 157:ff67d9f36b67 442 * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
<> 144:ef7eb2e8f9f7 443 * @retval None
<> 144:ef7eb2e8f9f7 444 */
<> 157:ff67d9f36b67 445 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFFU) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
<> 157:ff67d9f36b67 446 ((((__INTERRUPT__) & 0xFFU) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
<> 144:ef7eb2e8f9f7 447 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /** @brief Check whether the specified USART interrupt has occurred or not.
Anna Bridge 186:707f6e361f3e 451 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 452 * @param __IT__ specifies the USART interrupt source to check.
<> 144:ef7eb2e8f9f7 453 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 454 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
<> 157:ff67d9f36b67 455 * @arg @ref USART_IT_TC Transmission complete interrupt
<> 157:ff67d9f36b67 456 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
<> 157:ff67d9f36b67 457 * @arg @ref USART_IT_IDLE Idle line detection interrupt
<> 157:ff67d9f36b67 458 * @arg @ref USART_IT_ORE OverRun Error interrupt
<> 157:ff67d9f36b67 459 * @arg @ref USART_IT_NE Noise Error interrupt
<> 157:ff67d9f36b67 460 * @arg @ref USART_IT_FE Framing Error interrupt
<> 157:ff67d9f36b67 461 * @arg @ref USART_IT_PE Parity Error interrupt
<> 144:ef7eb2e8f9f7 462 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 463 */
<> 157:ff67d9f36b67 464 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /** @brief Check whether the specified USART interrupt source is enabled or not.
Anna Bridge 186:707f6e361f3e 467 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 468 * @param __IT__ specifies the USART interrupt source to check.
<> 144:ef7eb2e8f9f7 469 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 470 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
<> 157:ff67d9f36b67 471 * @arg @ref USART_IT_TC Transmission complete interrupt
<> 157:ff67d9f36b67 472 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
<> 157:ff67d9f36b67 473 * @arg @ref USART_IT_IDLE Idle line detection interrupt
<> 157:ff67d9f36b67 474 * @arg @ref USART_IT_ORE OverRun Error interrupt
<> 157:ff67d9f36b67 475 * @arg @ref USART_IT_NE Noise Error interrupt
<> 157:ff67d9f36b67 476 * @arg @ref USART_IT_FE Framing Error interrupt
<> 157:ff67d9f36b67 477 * @arg @ref USART_IT_PE Parity Error interrupt
<> 144:ef7eb2e8f9f7 478 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 479 */
<> 157:ff67d9f36b67 480 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
<> 157:ff67d9f36b67 481 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
<> 144:ef7eb2e8f9f7 482 (((uint16_t)(__IT__)) & USART_IT_MASK)))
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
Anna Bridge 186:707f6e361f3e 486 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 487 * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
<> 144:ef7eb2e8f9f7 488 * to clear the corresponding interrupt.
<> 144:ef7eb2e8f9f7 489 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 490 * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
<> 157:ff67d9f36b67 491 * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
<> 157:ff67d9f36b67 492 * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
<> 157:ff67d9f36b67 493 * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
<> 157:ff67d9f36b67 494 * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
<> 157:ff67d9f36b67 495 * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
<> 157:ff67d9f36b67 496 * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
<> 144:ef7eb2e8f9f7 497 * @retval None
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /** @brief Set a specific USART request flag.
Anna Bridge 186:707f6e361f3e 502 * @param __HANDLE__ specifies the USART Handle.
Anna Bridge 186:707f6e361f3e 503 * @param __REQ__ specifies the request flag to set.
<> 144:ef7eb2e8f9f7 504 * This parameter can be one of the following values:
<> 157:ff67d9f36b67 505 * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
<> 157:ff67d9f36b67 506 * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
<> 144:ef7eb2e8f9f7 507 *
<> 144:ef7eb2e8f9f7 508 * @retval None
<> 144:ef7eb2e8f9f7 509 */
<> 144:ef7eb2e8f9f7 510 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /** @brief Enable the USART one bit sample method.
Anna Bridge 186:707f6e361f3e 513 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 514 * @retval None
<> 157:ff67d9f36b67 515 */
<> 144:ef7eb2e8f9f7 516 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /** @brief Disable the USART one bit sample method.
Anna Bridge 186:707f6e361f3e 519 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 520 * @retval None
<> 157:ff67d9f36b67 521 */
<> 144:ef7eb2e8f9f7 522 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /** @brief Enable USART.
Anna Bridge 186:707f6e361f3e 525 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 526 * @retval None
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528 #define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /** @brief Disable USART.
Anna Bridge 186:707f6e361f3e 531 * @param __HANDLE__ specifies the USART Handle.
<> 144:ef7eb2e8f9f7 532 * @retval None
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534 #define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /**
<> 144:ef7eb2e8f9f7 537 * @}
<> 144:ef7eb2e8f9f7 538 */
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Private macros --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 541 /** @defgroup USART_Private_Macros USART Private Macros
<> 144:ef7eb2e8f9f7 542 * @{
<> 144:ef7eb2e8f9f7 543 */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /** @brief Check USART Baud rate.
Anna Bridge 186:707f6e361f3e 546 * @param __BAUDRATE__ Baudrate specified by the user.
<> 144:ef7eb2e8f9f7 547 * The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
<> 157:ff67d9f36b67 548 * divided by the smallest oversampling used on the USART (i.e. 8).
<> 144:ef7eb2e8f9f7 549 * @retval Test result (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 550 */
<> 157:ff67d9f36b67 551 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9000001U)
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /**
<> 144:ef7eb2e8f9f7 554 * @brief Ensure that USART frame number of stop bits is valid.
Anna Bridge 186:707f6e361f3e 555 * @param __STOPBITS__ USART frame number of stop bits.
<> 144:ef7eb2e8f9f7 556 * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
<> 144:ef7eb2e8f9f7 559 ((__STOPBITS__) == USART_STOPBITS_1) || \
<> 144:ef7eb2e8f9f7 560 ((__STOPBITS__) == USART_STOPBITS_1_5) || \
<> 144:ef7eb2e8f9f7 561 ((__STOPBITS__) == USART_STOPBITS_2))
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @brief Ensure that USART frame parity is valid.
Anna Bridge 186:707f6e361f3e 565 * @param __PARITY__ USART frame parity.
<> 144:ef7eb2e8f9f7 566 * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
<> 144:ef7eb2e8f9f7 567 */
<> 144:ef7eb2e8f9f7 568 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
<> 144:ef7eb2e8f9f7 569 ((__PARITY__) == USART_PARITY_EVEN) || \
<> 144:ef7eb2e8f9f7 570 ((__PARITY__) == USART_PARITY_ODD))
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /**
<> 144:ef7eb2e8f9f7 573 * @brief Ensure that USART communication mode is valid.
Anna Bridge 186:707f6e361f3e 574 * @param __MODE__ USART communication mode.
<> 144:ef7eb2e8f9f7 575 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 576 */
<> 157:ff67d9f36b67 577 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @brief Ensure that USART clock state is valid.
Anna Bridge 186:707f6e361f3e 581 * @param __CLOCK__ USART clock state.
<> 144:ef7eb2e8f9f7 582 * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
<> 144:ef7eb2e8f9f7 583 */
<> 144:ef7eb2e8f9f7 584 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
<> 144:ef7eb2e8f9f7 585 ((__CLOCK__) == USART_CLOCK_ENABLE))
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /**
<> 144:ef7eb2e8f9f7 588 * @brief Ensure that USART frame polarity is valid.
Anna Bridge 186:707f6e361f3e 589 * @param __CPOL__ USART frame polarity.
<> 144:ef7eb2e8f9f7 590 * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /**
<> 144:ef7eb2e8f9f7 595 * @brief Ensure that USART frame phase is valid.
Anna Bridge 186:707f6e361f3e 596 * @param __CPHA__ USART frame phase.
<> 144:ef7eb2e8f9f7 597 * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 600
<> 144:ef7eb2e8f9f7 601 /**
<> 144:ef7eb2e8f9f7 602 * @brief Ensure that USART frame last bit clock pulse setting is valid.
Anna Bridge 186:707f6e361f3e 603 * @param __LASTBIT__ USART frame last bit clock pulse setting.
<> 144:ef7eb2e8f9f7 604 * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
<> 144:ef7eb2e8f9f7 607 ((__LASTBIT__) == USART_LASTBIT_ENABLE))
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609 /**
<> 144:ef7eb2e8f9f7 610 * @brief Ensure that USART request parameter is valid.
Anna Bridge 186:707f6e361f3e 611 * @param __PARAM__ USART request parameter.
<> 144:ef7eb2e8f9f7 612 * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614 #define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
<> 144:ef7eb2e8f9f7 615 ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 616
<> 144:ef7eb2e8f9f7 617 /**
<> 144:ef7eb2e8f9f7 618 * @}
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620
<> 157:ff67d9f36b67 621 /* Include USART HAL Extended module */
<> 144:ef7eb2e8f9f7 622 #include "stm32f3xx_hal_usart_ex.h"
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 625 /** @addtogroup USART_Exported_Functions USART Exported Functions
<> 144:ef7eb2e8f9f7 626 * @{
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628
<> 144:ef7eb2e8f9f7 629 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 630 * @{
<> 144:ef7eb2e8f9f7 631 */
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 634 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 635 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 636 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 637 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * @}
<> 144:ef7eb2e8f9f7 641 */
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 644 * @{
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 648 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 649 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 650 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 651 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 652 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 653 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 654 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 655 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 656 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 657 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 658 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 659 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
<> 157:ff67d9f36b67 660 /* Transfer Abort functions */
<> 157:ff67d9f36b67 661 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
<> 157:ff67d9f36b67 662 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
<> 157:ff67d9f36b67 663
<> 144:ef7eb2e8f9f7 664 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 665 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 666 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 667 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 668 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 669 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 670 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
<> 157:ff67d9f36b67 671 void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @}
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Peripheral Control functions ***********************************************/
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 680 * @{
<> 144:ef7eb2e8f9f7 681 */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 684 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 685 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @}
<> 144:ef7eb2e8f9f7 689 */
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /**
<> 144:ef7eb2e8f9f7 692 * @}
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @}
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /**
<> 144:ef7eb2e8f9f7 700 * @}
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705 #endif
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #endif /* __STM32F3xx_HAL_USART_H */
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 710