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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi_ex.c@184:08ed48f1de7f, 2018-04-19 (annotated)

Committer:
AnnaBridge
Date:
Thu Apr 19 17:12:19 2018 +0100
Revision:
184:08ed48f1de7f
Parent:
149:156823d33999 
mbed-dev library. Release version 161

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_spi_ex.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief Extended SPI HAL module driver.
AnnaBridge 184:08ed48f1de7f 6 * This file provides firmware functions to manage the following
AnnaBridge 184:08ed48f1de7f 7 * SPI peripheral extended functionalities :
AnnaBridge 184:08ed48f1de7f 8 * + IO operation functions
AnnaBridge 184:08ed48f1de7f 9 *
<> 149:156823d33999 10 ******************************************************************************
<> 149:156823d33999 11 * @attention
<> 149:156823d33999 12 *
AnnaBridge 184:08ed48f1de7f 13 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 14 *
<> 149:156823d33999 15 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 16 * are permitted provided that the following conditions are met:
<> 149:156823d33999 17 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 18 * this list of conditions and the following disclaimer.
<> 149:156823d33999 19 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 20 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 21 * and/or other materials provided with the distribution.
<> 149:156823d33999 22 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 23 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 24 * without specific prior written permission.
<> 149:156823d33999 25 *
<> 149:156823d33999 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 34 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 36 *
<> 149:156823d33999 37 ******************************************************************************
<> 149:156823d33999 38 */
<> 149:156823d33999 39
<> 149:156823d33999 40 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 41 #include "stm32l1xx_hal.h"
<> 149:156823d33999 42
<> 149:156823d33999 43 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 44 * @{
<> 149:156823d33999 45 */
<> 149:156823d33999 46
<> 149:156823d33999 47 /** @addtogroup SPI
<> 149:156823d33999 48 * @{
<> 149:156823d33999 49 */
<> 149:156823d33999 50 #ifdef HAL_SPI_MODULE_ENABLED
<> 149:156823d33999 51
<> 149:156823d33999 52 /* Private typedef -----------------------------------------------------------*/
AnnaBridge 184:08ed48f1de7f 53 /* Private defines -----------------------------------------------------------*/
AnnaBridge 184:08ed48f1de7f 54 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 55 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 56 /* Private function prototypes -----------------------------------------------*/
AnnaBridge 184:08ed48f1de7f 57 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 58
<> 149:156823d33999 59 /** @addtogroup SPI_Exported_Functions
<> 149:156823d33999 60 * @{
<> 149:156823d33999 61 */
<> 149:156823d33999 62
<> 149:156823d33999 63 /** @addtogroup SPI_Exported_Functions_Group1
<> 149:156823d33999 64 *
<> 149:156823d33999 65 * @{
<> 149:156823d33999 66 */
<> 149:156823d33999 67
<> 149:156823d33999 68 /**
AnnaBridge 184:08ed48f1de7f 69 * @brief Initializes the SPI according to the specified parameters
<> 149:156823d33999 70 * in the SPI_InitTypeDef and create the associated handle.
<> 149:156823d33999 71 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
AnnaBridge 184:08ed48f1de7f 72 * the configuration information for SPI module.
<> 149:156823d33999 73 * @retval HAL status
<> 149:156823d33999 74 */
<> 149:156823d33999 75 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
<> 149:156823d33999 76 {
<> 149:156823d33999 77 /* Check the SPI handle allocation */
AnnaBridge 184:08ed48f1de7f 78 if (hspi == NULL)
<> 149:156823d33999 79 {
<> 149:156823d33999 80 return HAL_ERROR;
<> 149:156823d33999 81 }
<> 149:156823d33999 82
<> 149:156823d33999 83 /* Check the parameters */
<> 149:156823d33999 84 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
<> 149:156823d33999 85 assert_param(IS_SPI_MODE(hspi->Init.Mode));
<> 149:156823d33999 86 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
<> 149:156823d33999 87 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
<> 149:156823d33999 88 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
<> 149:156823d33999 89 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
<> 149:156823d33999 90 assert_param(IS_SPI_NSS(hspi->Init.NSS));
<> 149:156823d33999 91 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
<> 149:156823d33999 92 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
<> 149:156823d33999 93 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
<> 149:156823d33999 94 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
<> 149:156823d33999 95 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
<> 149:156823d33999 96
AnnaBridge 184:08ed48f1de7f 97 if (hspi->State == HAL_SPI_STATE_RESET)
<> 149:156823d33999 98 {
<> 149:156823d33999 99 /* Allocate lock resource and initialize it */
<> 149:156823d33999 100 hspi->Lock = HAL_UNLOCKED;
<> 149:156823d33999 101
<> 149:156823d33999 102 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
<> 149:156823d33999 103 HAL_SPI_MspInit(hspi);
<> 149:156823d33999 104 }
AnnaBridge 184:08ed48f1de7f 105
<> 149:156823d33999 106 hspi->State = HAL_SPI_STATE_BUSY;
<> 149:156823d33999 107
<> 149:156823d33999 108 /* Disble the selected SPI peripheral */
<> 149:156823d33999 109 __HAL_SPI_DISABLE(hspi);
<> 149:156823d33999 110
<> 149:156823d33999 111 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
<> 149:156823d33999 112 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
<> 149:156823d33999 113 Communication speed, First bit and CRC calculation state */
<> 149:156823d33999 114 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
<> 149:156823d33999 115 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
<> 149:156823d33999 116 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
<> 149:156823d33999 117
<> 149:156823d33999 118 /* Configure : NSS management */
AnnaBridge 184:08ed48f1de7f 119 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode);
<> 149:156823d33999 120
<> 149:156823d33999 121 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
<> 149:156823d33999 122 /* Configure : CRC Polynomial */
<> 149:156823d33999 123 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
<> 149:156823d33999 124
<> 149:156823d33999 125 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
<> 149:156823d33999 126 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
<> 149:156823d33999 127 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
<> 149:156823d33999 128 #endif
<> 149:156823d33999 129
<> 149:156823d33999 130 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
<> 149:156823d33999 131 hspi->State = HAL_SPI_STATE_READY;
AnnaBridge 184:08ed48f1de7f 132
<> 149:156823d33999 133 return HAL_OK;
<> 149:156823d33999 134 }
<> 149:156823d33999 135
<> 149:156823d33999 136 /**
<> 149:156823d33999 137 * @}
<> 149:156823d33999 138 */
<> 149:156823d33999 139
<> 149:156823d33999 140 /**
<> 149:156823d33999 141 * @}
<> 149:156823d33999 142 */
<> 149:156823d33999 143
<> 149:156823d33999 144 #endif /* HAL_SPI_MODULE_ENABLED */
AnnaBridge 184:08ed48f1de7f 145
<> 149:156823d33999 146 /**
<> 149:156823d33999 147 * @}
<> 149:156823d33999 148 */
<> 149:156823d33999 149
<> 149:156823d33999 150 /**
<> 149:156823d33999 151 * @}
<> 149:156823d33999 152 */
<> 149:156823d33999 153
<> 149:156823d33999 154 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/