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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_hash.c@167:e84263d55307, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:46:44 2017 +0100
Revision:
167:e84263d55307
Parent:
149:156823d33999
Child:
187:0387e8f68319
This updates the lib to the mbed lib v 145

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_hash.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 167:e84263d55307 5 * @version V1.2.1
AnnaBridge 167:e84263d55307 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief HASH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the HASH peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + HASH/HMAC Processing functions by algorithm using polling mode
<> 144:ef7eb2e8f9f7 12 * + HASH/HMAC functions by algorithm using interrupt mode
<> 144:ef7eb2e8f9f7 13 * + HASH/HMAC functions by algorithm using DMA mode
<> 144:ef7eb2e8f9f7 14 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 @verbatim
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 19 ==============================================================================
<> 144:ef7eb2e8f9f7 20 [..]
<> 144:ef7eb2e8f9f7 21 The HASH HAL driver can be used as follows:
<> 144:ef7eb2e8f9f7 22 (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit():
<> 144:ef7eb2e8f9f7 23 (##) Enable the HASH interface clock using __HAL_RCC_HASH_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 24 (##) In case of using processing APIs based on interrupts (e.g. HAL_HMAC_SHA1_Start_IT())
<> 144:ef7eb2e8f9f7 25 (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 26 (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 27 (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler()
<> 144:ef7eb2e8f9f7 28 (##) In case of using DMA to control data transfer (e.g. HAL_HMAC_SHA1_Start_DMA())
<> 144:ef7eb2e8f9f7 29 (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 30 (+++) Configure and enable one DMA stream one for managing data transfer from
<> 144:ef7eb2e8f9f7 31 memory to peripheral (input stream). Managing data transfer from
<> 144:ef7eb2e8f9f7 32 peripheral to memory can be performed only using CPU
<> 144:ef7eb2e8f9f7 33 (+++) Associate the initialized DMA handle to the HASH DMA handle
<> 144:ef7eb2e8f9f7 34 using __HAL_LINKDMA()
<> 144:ef7eb2e8f9f7 35 (+++) Configure the priority and enable the NVIC for the transfer complete
<> 144:ef7eb2e8f9f7 36 interrupt on the DMA Stream using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 37 (#)Initialize the HASH HAL using HAL_HASH_Init(). This function configures mainly:
<> 144:ef7eb2e8f9f7 38 (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit.
<> 144:ef7eb2e8f9f7 39 (##) For HMAC, the encryption key.
<> 144:ef7eb2e8f9f7 40 (##) For HMAC, the key size used for encryption.
<> 144:ef7eb2e8f9f7 41 (#)Three processing functions are available:
<> 144:ef7eb2e8f9f7 42 (##) Polling mode: processing APIs are blocking functions
<> 144:ef7eb2e8f9f7 43 i.e. they process the data and wait till the digest computation is finished
<> 144:ef7eb2e8f9f7 44 e.g. HAL_HASH_SHA1_Start()
<> 144:ef7eb2e8f9f7 45 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
<> 144:ef7eb2e8f9f7 46 i.e. they process the data under interrupt
<> 144:ef7eb2e8f9f7 47 e.g. HAL_HASH_SHA1_Start_IT()
<> 144:ef7eb2e8f9f7 48 (##) DMA mode: processing APIs are not blocking functions and the CPU is
<> 144:ef7eb2e8f9f7 49 not used for data transfer i.e. the data transfer is ensured by DMA
<> 144:ef7eb2e8f9f7 50 e.g. HAL_HASH_SHA1_Start_DMA()
<> 144:ef7eb2e8f9f7 51 (#)When the processing function is called at first time after HAL_HASH_Init()
<> 144:ef7eb2e8f9f7 52 the HASH peripheral is initialized and processes the buffer in input.
<> 144:ef7eb2e8f9f7 53 After that, the digest computation is started.
<> 144:ef7eb2e8f9f7 54 When processing multi-buffer use the accumulate function to write the
<> 144:ef7eb2e8f9f7 55 data in the peripheral without starting the digest computation. In last
<> 144:ef7eb2e8f9f7 56 buffer use the start function to input the last buffer ans start the digest
<> 144:ef7eb2e8f9f7 57 computation.
<> 144:ef7eb2e8f9f7 58 (##) e.g. HAL_HASH_SHA1_Accumulate() : write 1st data buffer in the peripheral without starting the digest computation
<> 144:ef7eb2e8f9f7 59 (##) write (n-1)th data buffer in the peripheral without starting the digest computation
<> 144:ef7eb2e8f9f7 60 (##) HAL_HASH_SHA1_Start() : write (n)th data buffer in the peripheral and start the digest computation
<> 144:ef7eb2e8f9f7 61 (#)In HMAC mode, there is no Accumulate API. Only Start API is available.
<> 144:ef7eb2e8f9f7 62 (#)In case of using DMA, call the DMA start processing e.g. HAL_HASH_SHA1_Start_DMA().
<> 144:ef7eb2e8f9f7 63 After that, call the finish function in order to get the digest value
<> 144:ef7eb2e8f9f7 64 e.g. HAL_HASH_SHA1_Finish()
<> 144:ef7eb2e8f9f7 65 (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 @endverbatim
<> 144:ef7eb2e8f9f7 68 ******************************************************************************
<> 144:ef7eb2e8f9f7 69 * @attention
<> 144:ef7eb2e8f9f7 70 *
AnnaBridge 167:e84263d55307 71 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 74 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 75 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 76 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 78 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 79 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 81 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 82 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 83 *
<> 144:ef7eb2e8f9f7 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 ******************************************************************************
<> 144:ef7eb2e8f9f7 96 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup HASH HASH
<> 144:ef7eb2e8f9f7 106 * @brief HASH HAL module driver.
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #ifdef HAL_HASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #if defined(STM32F215xx) || defined(STM32F217xx)
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 118 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 119 /** @defgroup HASH_Private_Functions HASH Private Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 123 static void HASH_DMAError(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 124 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size);
<> 144:ef7eb2e8f9f7 125 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size);
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /** @addtogroup HASH_Private_Functions
<> 144:ef7eb2e8f9f7 132 * @{
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @brief DMA HASH Input Data complete callback.
<> 144:ef7eb2e8f9f7 137 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 138 * @retval None
<> 144:ef7eb2e8f9f7 139 */
<> 144:ef7eb2e8f9f7 140 static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 141 {
<> 144:ef7eb2e8f9f7 142 HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 143 uint32_t inputaddr = 0U;
<> 144:ef7eb2e8f9f7 144 uint32_t buffersize = 0U;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 if((HASH->CR & HASH_CR_MODE) != HASH_CR_MODE)
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /* Disable the DMA transfer */
<> 144:ef7eb2e8f9f7 149 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 152 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 155 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 156 }
<> 144:ef7eb2e8f9f7 157 else
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 /* Increment Interrupt counter */
<> 144:ef7eb2e8f9f7 160 hhash->HashInCount++;
<> 144:ef7eb2e8f9f7 161 /* Disable the DMA transfer before starting the next transfer */
<> 144:ef7eb2e8f9f7 162 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 if(hhash->HashInCount <= 2U)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 /* In case HashInCount = 1, set the DMA to transfer data to HASH DIN register */
<> 144:ef7eb2e8f9f7 167 if(hhash->HashInCount == 1U)
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 170 buffersize = hhash->HashBuffSize;
<> 144:ef7eb2e8f9f7 171 }
<> 144:ef7eb2e8f9f7 172 /* In case HashInCount = 2, set the DMA to transfer key to HASH DIN register */
<> 144:ef7eb2e8f9f7 173 else if(hhash->HashInCount == 2U)
<> 144:ef7eb2e8f9f7 174 {
<> 144:ef7eb2e8f9f7 175 inputaddr = (uint32_t)hhash->Init.pKey;
<> 144:ef7eb2e8f9f7 176 buffersize = hhash->Init.KeySize;
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 179 MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * (buffersize % 4U));
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /* Set the HASH DMA transfer complete */
<> 144:ef7eb2e8f9f7 182 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 185 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (buffersize%4U ? (buffersize+3U)/4U:buffersize/4U));
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 188 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 else
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 /* Disable the DMA transfer */
<> 144:ef7eb2e8f9f7 193 HASH->CR &= (uint32_t)(~HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Reset the InCount */
<> 144:ef7eb2e8f9f7 196 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 199 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 202 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 }
<> 144:ef7eb2e8f9f7 205 }
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /**
<> 144:ef7eb2e8f9f7 208 * @brief DMA HASH communication error callback.
<> 144:ef7eb2e8f9f7 209 * @param hdma: DMA handle
<> 144:ef7eb2e8f9f7 210 * @retval None
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212 static void HASH_DMAError(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 215 hhash->State= HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 216 HAL_HASH_ErrorCallback(hhash);
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @brief Writes the input buffer in data register.
<> 144:ef7eb2e8f9f7 221 * @param pInBuffer: Pointer to input buffer
<> 144:ef7eb2e8f9f7 222 * @param Size: The size of input buffer
<> 144:ef7eb2e8f9f7 223 * @retval None
<> 144:ef7eb2e8f9f7 224 */
<> 144:ef7eb2e8f9f7 225 static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 226 {
<> 144:ef7eb2e8f9f7 227 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 228 uint32_t inputaddr = (uint32_t) pInBuffer;
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U)
<> 144:ef7eb2e8f9f7 231 {
<> 144:ef7eb2e8f9f7 232 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 233 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 }
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @brief Provides the message digest result.
<> 144:ef7eb2e8f9f7 239 * @param pMsgDigest: Pointer to the message digest
<> 144:ef7eb2e8f9f7 240 * @param Size: The size of the message digest in bytes
<> 144:ef7eb2e8f9f7 241 * @retval None
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 uint32_t msgdigest = (uint32_t)pMsgDigest;
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 switch(Size)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 case 16U:
<> 144:ef7eb2e8f9f7 250 /* Read the message digest */
<> 144:ef7eb2e8f9f7 251 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 252 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 253 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 254 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 255 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 256 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 257 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 258 break;
<> 144:ef7eb2e8f9f7 259 case 20U:
<> 144:ef7eb2e8f9f7 260 /* Read the message digest */
<> 144:ef7eb2e8f9f7 261 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 262 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 263 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 264 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 265 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 266 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 267 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 268 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 269 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 270 break;
<> 144:ef7eb2e8f9f7 271 case 28U:
<> 144:ef7eb2e8f9f7 272 /* Read the message digest */
<> 144:ef7eb2e8f9f7 273 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 274 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 275 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 276 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 277 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 278 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 279 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 280 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 281 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 282 break;
<> 144:ef7eb2e8f9f7 283 case 32U:
<> 144:ef7eb2e8f9f7 284 /* Read the message digest */
<> 144:ef7eb2e8f9f7 285 *(uint32_t*)(msgdigest) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 286 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 287 *(uint32_t*)(msgdigest) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 288 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 289 *(uint32_t*)(msgdigest) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 290 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 291 *(uint32_t*)(msgdigest) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 292 msgdigest+=4U;
<> 144:ef7eb2e8f9f7 293 *(uint32_t*)(msgdigest) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 294 break;
<> 144:ef7eb2e8f9f7 295 default:
<> 144:ef7eb2e8f9f7 296 break;
<> 144:ef7eb2e8f9f7 297 }
<> 144:ef7eb2e8f9f7 298 }
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 305 /** @addtogroup HASH_Exported_Functions
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 311 * @brief Initialization and Configuration functions.
<> 144:ef7eb2e8f9f7 312 *
<> 144:ef7eb2e8f9f7 313 @verbatim
<> 144:ef7eb2e8f9f7 314 ===============================================================================
<> 144:ef7eb2e8f9f7 315 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 316 ===============================================================================
<> 144:ef7eb2e8f9f7 317 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 318 (+) Initialize the HASH according to the specified parameters
<> 144:ef7eb2e8f9f7 319 in the HASH_InitTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 320 (+) DeInitialize the HASH peripheral.
<> 144:ef7eb2e8f9f7 321 (+) Initialize the HASH MSP.
<> 144:ef7eb2e8f9f7 322 (+) DeInitialize HASH MSP.
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 @endverbatim
<> 144:ef7eb2e8f9f7 325 * @{
<> 144:ef7eb2e8f9f7 326 */
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @brief Initializes the HASH according to the specified parameters in the
<> 144:ef7eb2e8f9f7 330 HASH_HandleTypeDef and creates the associated handle.
<> 144:ef7eb2e8f9f7 331 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 332 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 333 * @retval HAL status
<> 144:ef7eb2e8f9f7 334 */
<> 144:ef7eb2e8f9f7 335 HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 336 {
<> 144:ef7eb2e8f9f7 337 /* Check the hash handle allocation */
<> 144:ef7eb2e8f9f7 338 if(hhash == NULL)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Check the parameters */
<> 144:ef7eb2e8f9f7 344 assert_param(IS_HASH_DATATYPE(hhash->Init.DataType));
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 if(hhash->State == HAL_HASH_STATE_RESET)
<> 144:ef7eb2e8f9f7 347 {
<> 144:ef7eb2e8f9f7 348 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 349 hhash->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 350 /* Init the low level hardware */
<> 144:ef7eb2e8f9f7 351 HAL_HASH_MspInit(hhash);
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 355 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /* Reset HashInCount, HashBuffSize and HashITCounter */
<> 144:ef7eb2e8f9f7 358 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 359 hhash->HashBuffSize = 0U;
<> 144:ef7eb2e8f9f7 360 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Set the data type */
<> 144:ef7eb2e8f9f7 363 HASH->CR |= (uint32_t) (hhash->Init.DataType);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 366 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Set the default HASH phase */
<> 144:ef7eb2e8f9f7 369 hhash->Phase = HAL_HASH_PHASE_READY;
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Return function status */
<> 144:ef7eb2e8f9f7 372 return HAL_OK;
<> 144:ef7eb2e8f9f7 373 }
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /**
<> 144:ef7eb2e8f9f7 376 * @brief DeInitializes the HASH peripheral.
<> 144:ef7eb2e8f9f7 377 * @note This API must be called before starting a new processing.
<> 144:ef7eb2e8f9f7 378 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 379 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 380 * @retval HAL status
<> 144:ef7eb2e8f9f7 381 */
<> 144:ef7eb2e8f9f7 382 HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 383 {
<> 144:ef7eb2e8f9f7 384 /* Check the HASH handle allocation */
<> 144:ef7eb2e8f9f7 385 if(hhash == NULL)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 391 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Set the default HASH phase */
<> 144:ef7eb2e8f9f7 394 hhash->Phase = HAL_HASH_PHASE_READY;
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Reset HashInCount, HashBuffSize and HashITCounter */
<> 144:ef7eb2e8f9f7 397 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 398 hhash->HashBuffSize = 0U;
<> 144:ef7eb2e8f9f7 399 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 /* DeInit the low level hardware */
<> 144:ef7eb2e8f9f7 402 HAL_HASH_MspDeInit(hhash);
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 405 hhash->State = HAL_HASH_STATE_RESET;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Release Lock */
<> 144:ef7eb2e8f9f7 408 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Return function status */
<> 144:ef7eb2e8f9f7 411 return HAL_OK;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @brief Initializes the HASH MSP.
<> 144:ef7eb2e8f9f7 416 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 417 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 418 * @retval None
<> 144:ef7eb2e8f9f7 419 */
<> 144:ef7eb2e8f9f7 420 __weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 423 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 424 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 425 the HAL_HASH_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief DeInitializes HASH MSP.
<> 144:ef7eb2e8f9f7 431 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 432 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 433 * @retval None
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 438 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 439 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 440 the HAL_HASH_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 441 */
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /**
<> 144:ef7eb2e8f9f7 445 * @brief Input data transfer complete callback.
<> 144:ef7eb2e8f9f7 446 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 447 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 448 * @retval None
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 __weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 453 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 454 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 455 the HAL_HASH_InCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /**
<> 144:ef7eb2e8f9f7 460 * @brief Data transfer Error callback.
<> 144:ef7eb2e8f9f7 461 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 462 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 463 * @retval None
<> 144:ef7eb2e8f9f7 464 */
<> 144:ef7eb2e8f9f7 465 __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 468 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 469 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 470 the HAL_HASH_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 /**
<> 144:ef7eb2e8f9f7 475 * @brief Digest computation complete callback. It is used only with interrupt.
<> 144:ef7eb2e8f9f7 476 * @note This callback is not relevant with DMA.
<> 144:ef7eb2e8f9f7 477 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 478 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 479 * @retval None
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481 __weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 484 UNUSED(hhash);
<> 144:ef7eb2e8f9f7 485 /* NOTE: This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 486 the HAL_HASH_DgstCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /**
<> 144:ef7eb2e8f9f7 491 * @}
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions using polling mode
<> 144:ef7eb2e8f9f7 495 * @brief processing functions using polling mode
<> 144:ef7eb2e8f9f7 496 *
<> 144:ef7eb2e8f9f7 497 @verbatim
<> 144:ef7eb2e8f9f7 498 ===============================================================================
<> 144:ef7eb2e8f9f7 499 ##### HASH processing using polling mode functions#####
<> 144:ef7eb2e8f9f7 500 ===============================================================================
<> 144:ef7eb2e8f9f7 501 [..] This section provides functions allowing to calculate in polling mode
<> 144:ef7eb2e8f9f7 502 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 503 (+) MD5
<> 144:ef7eb2e8f9f7 504 (+) SHA1
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 @endverbatim
<> 144:ef7eb2e8f9f7 507 * @{
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /**
<> 144:ef7eb2e8f9f7 511 * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 512 The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 513 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 514 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 515 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 516 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 517 * If the Size is multiple of 64 bytes, appending the input buffer is possible.
<> 144:ef7eb2e8f9f7 518 * If the Size is not multiple of 64 bytes, the padding is managed by hardware
<> 144:ef7eb2e8f9f7 519 * and appending the input buffer is no more possible.
<> 144:ef7eb2e8f9f7 520 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 521 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 522 * @retval HAL status
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 /* Process Locked */
<> 144:ef7eb2e8f9f7 529 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 532 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 535 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 536 {
<> 144:ef7eb2e8f9f7 537 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 538 the message digest of a new message */
<> 144:ef7eb2e8f9f7 539 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /* Set the phase */
<> 144:ef7eb2e8f9f7 543 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 546 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 549 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 552 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Get tick */
<> 144:ef7eb2e8f9f7 555 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 560 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 563 {
<> 144:ef7eb2e8f9f7 564 /* Change state */
<> 144:ef7eb2e8f9f7 565 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 568 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Read the message digest */
<> 144:ef7eb2e8f9f7 576 HASH_GetDigest(pOutBuffer, 16U);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 579 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 582 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Return function status */
<> 144:ef7eb2e8f9f7 585 return HAL_OK;
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 /**
<> 144:ef7eb2e8f9f7 589 * @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
<> 144:ef7eb2e8f9f7 590 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 591 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 592 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 593 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 594 * If the Size is multiple of 64 bytes, appending the input buffer is possible.
<> 144:ef7eb2e8f9f7 595 * If the Size is not multiple of 64 bytes, the padding is managed by hardware
<> 144:ef7eb2e8f9f7 596 * and appending the input buffer is no more possible.
<> 144:ef7eb2e8f9f7 597 * @retval HAL status
<> 144:ef7eb2e8f9f7 598 */
<> 144:ef7eb2e8f9f7 599 HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Process Locked */
<> 144:ef7eb2e8f9f7 602 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 605 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 608 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 611 the message digest of a new message */
<> 144:ef7eb2e8f9f7 612 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Set the phase */
<> 144:ef7eb2e8f9f7 616 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 619 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 622 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 625 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 628 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 /* Return function status */
<> 144:ef7eb2e8f9f7 631 return HAL_OK;
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /**
<> 144:ef7eb2e8f9f7 635 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 636 The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 637 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 638 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 639 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 640 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 641 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 642 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 643 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 644 * @retval HAL status
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 647 {
<> 144:ef7eb2e8f9f7 648 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 /* Process Locked */
<> 144:ef7eb2e8f9f7 651 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 654 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 657 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 658 {
<> 144:ef7eb2e8f9f7 659 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 660 the message digest of a new message */
<> 144:ef7eb2e8f9f7 661 HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 /* Set the phase */
<> 144:ef7eb2e8f9f7 665 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 668 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 671 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 674 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 675
<> 144:ef7eb2e8f9f7 676 /* Get tick */
<> 144:ef7eb2e8f9f7 677 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 682 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 685 {
<> 144:ef7eb2e8f9f7 686 /* Change state */
<> 144:ef7eb2e8f9f7 687 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 690 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Read the message digest */
<> 144:ef7eb2e8f9f7 698 HASH_GetDigest(pOutBuffer, 20U);
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 701 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 704 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* Return function status */
<> 144:ef7eb2e8f9f7 707 return HAL_OK;
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 712 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 713 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 714 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 715 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 716 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 717 * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
<> 144:ef7eb2e8f9f7 718 * @retval HAL status
<> 144:ef7eb2e8f9f7 719 */
<> 144:ef7eb2e8f9f7 720 HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 /* Check the parameters */
<> 144:ef7eb2e8f9f7 723 assert_param(IS_HASH_SHA1_BUFFER_SIZE(Size));
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Process Locked */
<> 144:ef7eb2e8f9f7 726 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 729 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 732 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 735 the message digest of a new message */
<> 144:ef7eb2e8f9f7 736 HASH->CR |= HASH_ALGOSELECTION_SHA1 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 737 }
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Set the phase */
<> 144:ef7eb2e8f9f7 740 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 743 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 746 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 749 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 752 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /* Return function status */
<> 144:ef7eb2e8f9f7 755 return HAL_OK;
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /**
<> 144:ef7eb2e8f9f7 759 * @}
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions using interrupt mode
<> 144:ef7eb2e8f9f7 763 * @brief processing functions using interrupt mode.
<> 144:ef7eb2e8f9f7 764 *
<> 144:ef7eb2e8f9f7 765 @verbatim
<> 144:ef7eb2e8f9f7 766 ===============================================================================
<> 144:ef7eb2e8f9f7 767 ##### HASH processing using interrupt mode functions #####
<> 144:ef7eb2e8f9f7 768 ===============================================================================
<> 144:ef7eb2e8f9f7 769 [..] This section provides functions allowing to calculate in interrupt mode
<> 144:ef7eb2e8f9f7 770 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 771 (+) MD5
<> 144:ef7eb2e8f9f7 772 (+) SHA1
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 @endverbatim
<> 144:ef7eb2e8f9f7 775 * @{
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /**
<> 144:ef7eb2e8f9f7 779 * @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 780 * The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 781 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 782 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 783 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 784 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 785 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 786 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 787 * @retval HAL status
<> 144:ef7eb2e8f9f7 788 */
<> 144:ef7eb2e8f9f7 789 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 uint32_t inputaddr;
<> 144:ef7eb2e8f9f7 792 uint32_t outputaddr;
<> 144:ef7eb2e8f9f7 793 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 794 uint32_t inputcounter;
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Process Locked */
<> 144:ef7eb2e8f9f7 797 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 if(hhash->State == HAL_HASH_STATE_READY)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 802 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 hhash->HashInCount = Size;
<> 144:ef7eb2e8f9f7 805 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 806 hhash->pHashOutBuffPtr = pOutBuffer;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 809 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 /* Select the SHA1 mode */
<> 144:ef7eb2e8f9f7 812 HASH->CR |= HASH_ALGOSELECTION_MD5;
<> 144:ef7eb2e8f9f7 813 /* Reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 814 the message digest of a new message */
<> 144:ef7eb2e8f9f7 815 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 /* Reset interrupt counter */
<> 144:ef7eb2e8f9f7 818 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 819
<> 144:ef7eb2e8f9f7 820 /* Set the phase */
<> 144:ef7eb2e8f9f7 821 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 824 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 827 HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 /* Return function status */
<> 144:ef7eb2e8f9f7 830 return HAL_OK;
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
<> 144:ef7eb2e8f9f7 835 /* Read the Output block from the Output FIFO */
<> 144:ef7eb2e8f9f7 836 *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 837 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 838 *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 839 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 840 *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 841 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 842 *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 if(hhash->HashInCount == 0U)
<> 144:ef7eb2e8f9f7 845 {
<> 144:ef7eb2e8f9f7 846 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 847 HASH->IMR = 0U;
<> 144:ef7eb2e8f9f7 848 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 849 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 850 /* Call digest computation complete callback */
<> 144:ef7eb2e8f9f7 851 HAL_HASH_DgstCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 854 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Return function status */
<> 144:ef7eb2e8f9f7 857 return HAL_OK;
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 863 {
<> 144:ef7eb2e8f9f7 864 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 865 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 866 for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
<> 144:ef7eb2e8f9f7 867 {
<> 144:ef7eb2e8f9f7 868 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 869 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 870 }
<> 144:ef7eb2e8f9f7 871 if(hhash->HashITCounter == 0U)
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 878 hhash->HashInCount -= 68U;
<> 144:ef7eb2e8f9f7 879 hhash->pHashInBuffPtr+= 68U;
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881 else
<> 144:ef7eb2e8f9f7 882 {
<> 144:ef7eb2e8f9f7 883 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 884 hhash->pHashInBuffPtr+= hhash->HashInCount;
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886 /* Set Interrupt counter */
<> 144:ef7eb2e8f9f7 887 hhash->HashITCounter = 1U;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889 else
<> 144:ef7eb2e8f9f7 890 {
<> 144:ef7eb2e8f9f7 891 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 892 hhash->HashInCount -= 64U;
<> 144:ef7eb2e8f9f7 893 hhash->pHashInBuffPtr+= 64U;
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895 }
<> 144:ef7eb2e8f9f7 896 else
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 /* Get the buffer address */
<> 144:ef7eb2e8f9f7 899 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 900 /* Get the buffer counter */
<> 144:ef7eb2e8f9f7 901 inputcounter = hhash->HashInCount;
<> 144:ef7eb2e8f9f7 902 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 903 HASH->IMR &= ~(HASH_IT_DINI);
<> 144:ef7eb2e8f9f7 904 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 905 __HAL_HASH_SET_NBVALIDBITS(inputcounter);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 if((inputcounter > 4U) && (inputcounter%4U))
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 inputcounter = (inputcounter+4U-inputcounter%4U);
<> 144:ef7eb2e8f9f7 910 }
<> 144:ef7eb2e8f9f7 911 else if ((inputcounter < 4U) && (inputcounter != 0U))
<> 144:ef7eb2e8f9f7 912 {
<> 144:ef7eb2e8f9f7 913 inputcounter = 4U;
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 916 for(buffercounter = 0U; buffercounter < inputcounter/4U; buffercounter++)
<> 144:ef7eb2e8f9f7 917 {
<> 144:ef7eb2e8f9f7 918 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 919 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 920 }
<> 144:ef7eb2e8f9f7 921 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 922 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 923 /* Reset buffer counter */
<> 144:ef7eb2e8f9f7 924 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 925 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 926 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 931 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /* Return function status */
<> 144:ef7eb2e8f9f7 934 return HAL_OK;
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
<> 144:ef7eb2e8f9f7 939 * The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 940 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 941 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 942 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 943 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 944 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 945 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 946 * @retval HAL status
<> 144:ef7eb2e8f9f7 947 */
<> 144:ef7eb2e8f9f7 948 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
<> 144:ef7eb2e8f9f7 949 {
<> 144:ef7eb2e8f9f7 950 uint32_t inputaddr;
<> 144:ef7eb2e8f9f7 951 uint32_t outputaddr;
<> 144:ef7eb2e8f9f7 952 uint32_t buffercounter;
<> 144:ef7eb2e8f9f7 953 uint32_t inputcounter;
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /* Process Locked */
<> 144:ef7eb2e8f9f7 956 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 if(hhash->State == HAL_HASH_STATE_READY)
<> 144:ef7eb2e8f9f7 959 {
<> 144:ef7eb2e8f9f7 960 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 961 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 hhash->HashInCount = Size;
<> 144:ef7eb2e8f9f7 964 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 965 hhash->pHashOutBuffPtr = pOutBuffer;
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 968 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 969 {
<> 144:ef7eb2e8f9f7 970 /* Select the SHA1 mode */
<> 144:ef7eb2e8f9f7 971 HASH->CR |= HASH_ALGOSELECTION_SHA1;
<> 144:ef7eb2e8f9f7 972 /* Reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 973 the message digest of a new message */
<> 144:ef7eb2e8f9f7 974 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 975 }
<> 144:ef7eb2e8f9f7 976 /* Reset interrupt counter */
<> 144:ef7eb2e8f9f7 977 hhash->HashITCounter = 0U;
<> 144:ef7eb2e8f9f7 978
<> 144:ef7eb2e8f9f7 979 /* Set the phase */
<> 144:ef7eb2e8f9f7 980 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 981
<> 144:ef7eb2e8f9f7 982 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 983 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /* Enable Interrupts */
<> 144:ef7eb2e8f9f7 986 HASH->IMR = (HASH_IT_DINI | HASH_IT_DCI);
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 /* Return function status */
<> 144:ef7eb2e8f9f7 989 return HAL_OK;
<> 144:ef7eb2e8f9f7 990 }
<> 144:ef7eb2e8f9f7 991 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 outputaddr = (uint32_t)hhash->pHashOutBuffPtr;
<> 144:ef7eb2e8f9f7 994 /* Read the Output block from the Output FIFO */
<> 144:ef7eb2e8f9f7 995 *(uint32_t*)(outputaddr) = __REV(HASH->HR[0U]);
<> 144:ef7eb2e8f9f7 996 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 997 *(uint32_t*)(outputaddr) = __REV(HASH->HR[1U]);
<> 144:ef7eb2e8f9f7 998 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 999 *(uint32_t*)(outputaddr) = __REV(HASH->HR[2U]);
<> 144:ef7eb2e8f9f7 1000 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 1001 *(uint32_t*)(outputaddr) = __REV(HASH->HR[3U]);
<> 144:ef7eb2e8f9f7 1002 outputaddr+=4U;
<> 144:ef7eb2e8f9f7 1003 *(uint32_t*)(outputaddr) = __REV(HASH->HR[4U]);
<> 144:ef7eb2e8f9f7 1004 if(hhash->HashInCount == 0U)
<> 144:ef7eb2e8f9f7 1005 {
<> 144:ef7eb2e8f9f7 1006 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 1007 HASH->IMR = 0U;
<> 144:ef7eb2e8f9f7 1008 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1009 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1010 /* Call digest computation complete callback */
<> 144:ef7eb2e8f9f7 1011 HAL_HASH_DgstCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1014 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1015
<> 144:ef7eb2e8f9f7 1016 /* Return function status */
<> 144:ef7eb2e8f9f7 1017 return HAL_OK;
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020 if(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
<> 144:ef7eb2e8f9f7 1021 {
<> 144:ef7eb2e8f9f7 1022 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 1025 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 1026 for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U)
<> 144:ef7eb2e8f9f7 1027 {
<> 144:ef7eb2e8f9f7 1028 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1029 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 1030 }
<> 144:ef7eb2e8f9f7 1031 if(hhash->HashITCounter == 0U)
<> 144:ef7eb2e8f9f7 1032 {
<> 144:ef7eb2e8f9f7 1033 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1034 if(hhash->HashInCount >= 68U)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 1037 hhash->HashInCount -= 68U;
<> 144:ef7eb2e8f9f7 1038 hhash->pHashInBuffPtr+= 68U;
<> 144:ef7eb2e8f9f7 1039 }
<> 144:ef7eb2e8f9f7 1040 else
<> 144:ef7eb2e8f9f7 1041 {
<> 144:ef7eb2e8f9f7 1042 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1043 hhash->pHashInBuffPtr+= hhash->HashInCount;
<> 144:ef7eb2e8f9f7 1044 }
<> 144:ef7eb2e8f9f7 1045 /* Set Interrupt counter */
<> 144:ef7eb2e8f9f7 1046 hhash->HashITCounter = 1U;
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048 else
<> 144:ef7eb2e8f9f7 1049 {
<> 144:ef7eb2e8f9f7 1050 /* Decrement buffer counter */
<> 144:ef7eb2e8f9f7 1051 hhash->HashInCount -= 64U;
<> 144:ef7eb2e8f9f7 1052 hhash->pHashInBuffPtr+= 64U;
<> 144:ef7eb2e8f9f7 1053 }
<> 144:ef7eb2e8f9f7 1054 }
<> 144:ef7eb2e8f9f7 1055 else
<> 144:ef7eb2e8f9f7 1056 {
<> 144:ef7eb2e8f9f7 1057 /* Get the buffer address */
<> 144:ef7eb2e8f9f7 1058 inputaddr = (uint32_t)hhash->pHashInBuffPtr;
<> 144:ef7eb2e8f9f7 1059 /* Get the buffer counter */
<> 144:ef7eb2e8f9f7 1060 inputcounter = hhash->HashInCount;
<> 144:ef7eb2e8f9f7 1061 /* Disable Interrupts */
<> 144:ef7eb2e8f9f7 1062 HASH->IMR &= ~(HASH_IT_DINI);
<> 144:ef7eb2e8f9f7 1063 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1064 __HAL_HASH_SET_NBVALIDBITS(inputcounter);
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 if((inputcounter > 4U) && (inputcounter%4U))
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 inputcounter = (inputcounter+4U-inputcounter%4U);
<> 144:ef7eb2e8f9f7 1069 }
<> 144:ef7eb2e8f9f7 1070 else if ((inputcounter < 4U) && (inputcounter != 0U))
<> 144:ef7eb2e8f9f7 1071 {
<> 144:ef7eb2e8f9f7 1072 inputcounter = 4U;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074 /* Write the Input block in the Data IN register */
<> 144:ef7eb2e8f9f7 1075 for(buffercounter = 0U; buffercounter < inputcounter/4; buffercounter++)
<> 144:ef7eb2e8f9f7 1076 {
<> 144:ef7eb2e8f9f7 1077 HASH->DIN = *(uint32_t*)inputaddr;
<> 144:ef7eb2e8f9f7 1078 inputaddr+=4U;
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1081 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1082 /* Reset buffer counter */
<> 144:ef7eb2e8f9f7 1083 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1084 /* Call Input data transfer complete callback */
<> 144:ef7eb2e8f9f7 1085 HAL_HASH_InCpltCallback(hhash);
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 }
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1090 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Return function status */
<> 144:ef7eb2e8f9f7 1093 return HAL_OK;
<> 144:ef7eb2e8f9f7 1094 }
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /**
<> 144:ef7eb2e8f9f7 1097 * @brief This function handles HASH interrupt request.
<> 144:ef7eb2e8f9f7 1098 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1099 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1100 * @retval None
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 switch(HASH->CR & HASH_CR_ALGO)
<> 144:ef7eb2e8f9f7 1105 {
<> 144:ef7eb2e8f9f7 1106 case HASH_ALGOSELECTION_MD5:
<> 144:ef7eb2e8f9f7 1107 HAL_HASH_MD5_Start_IT(hhash, NULL, 0U, NULL);
<> 144:ef7eb2e8f9f7 1108 break;
<> 144:ef7eb2e8f9f7 1109
<> 144:ef7eb2e8f9f7 1110 case HASH_ALGOSELECTION_SHA1:
<> 144:ef7eb2e8f9f7 1111 HAL_HASH_SHA1_Start_IT(hhash, NULL, 0U, NULL);
<> 144:ef7eb2e8f9f7 1112 break;
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 default:
<> 144:ef7eb2e8f9f7 1115 break;
<> 144:ef7eb2e8f9f7 1116 }
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 /**
<> 144:ef7eb2e8f9f7 1120 * @}
<> 144:ef7eb2e8f9f7 1121 */
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions using DMA mode
<> 144:ef7eb2e8f9f7 1124 * @brief processing functions using DMA mode.
<> 144:ef7eb2e8f9f7 1125 *
<> 144:ef7eb2e8f9f7 1126 @verbatim
<> 144:ef7eb2e8f9f7 1127 ===============================================================================
<> 144:ef7eb2e8f9f7 1128 ##### HASH processing using DMA mode functions #####
<> 144:ef7eb2e8f9f7 1129 ===============================================================================
<> 144:ef7eb2e8f9f7 1130 [..] This section provides functions allowing to calculate in DMA mode
<> 144:ef7eb2e8f9f7 1131 the hash value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1132 (+) MD5
<> 144:ef7eb2e8f9f7 1133 (+) SHA1
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 @endverbatim
<> 144:ef7eb2e8f9f7 1136 * @{
<> 144:ef7eb2e8f9f7 1137 */
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /**
<> 144:ef7eb2e8f9f7 1140 * @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
<> 144:ef7eb2e8f9f7 1141 control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
<> 144:ef7eb2e8f9f7 1142 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1143 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1144 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1145 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1146 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1147 * @retval HAL status
<> 144:ef7eb2e8f9f7 1148 */
<> 144:ef7eb2e8f9f7 1149 HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 uint32_t inputaddr = (uint32_t)pInBuffer;
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 /* Process Locked */
<> 144:ef7eb2e8f9f7 1154 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1157 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1158
<> 144:ef7eb2e8f9f7 1159 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1160 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1161 {
<> 144:ef7eb2e8f9f7 1162 /* Select the MD5 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 1163 the message digest of a new message */
<> 144:ef7eb2e8f9f7 1164 HASH->CR |= HASH_ALGOSELECTION_MD5 | HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 1165 }
<> 144:ef7eb2e8f9f7 1166
<> 144:ef7eb2e8f9f7 1167 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1168 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Set the phase */
<> 144:ef7eb2e8f9f7 1171 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1174 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1175 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1176 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Enable the DMA In DMA Stream */
<> 144:ef7eb2e8f9f7 1179 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1182 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1185 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Return function status */
<> 144:ef7eb2e8f9f7 1188 return HAL_OK;
<> 144:ef7eb2e8f9f7 1189 }
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /**
<> 144:ef7eb2e8f9f7 1192 * @brief Returns the computed digest in MD5 mode
<> 144:ef7eb2e8f9f7 1193 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1194 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1195 * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
<> 144:ef7eb2e8f9f7 1196 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1197 * @retval HAL status
<> 144:ef7eb2e8f9f7 1198 */
<> 144:ef7eb2e8f9f7 1199 HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1200 {
<> 144:ef7eb2e8f9f7 1201 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 /* Process Locked */
<> 144:ef7eb2e8f9f7 1204 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1207 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /* Get tick */
<> 144:ef7eb2e8f9f7 1210 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1213 {
<> 144:ef7eb2e8f9f7 1214 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1215 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1216 {
<> 144:ef7eb2e8f9f7 1217 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1218 {
<> 144:ef7eb2e8f9f7 1219 /* Change state */
<> 144:ef7eb2e8f9f7 1220 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1221
<> 144:ef7eb2e8f9f7 1222 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1223 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1224
<> 144:ef7eb2e8f9f7 1225 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227 }
<> 144:ef7eb2e8f9f7 1228 }
<> 144:ef7eb2e8f9f7 1229
<> 144:ef7eb2e8f9f7 1230 /* Read the message digest */
AnnaBridge 167:e84263d55307 1231 HASH_GetDigest(pOutBuffer, 16);
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1234 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1235
<> 144:ef7eb2e8f9f7 1236 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1237 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /* Return function status */
<> 144:ef7eb2e8f9f7 1240 return HAL_OK;
<> 144:ef7eb2e8f9f7 1241 }
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /**
<> 144:ef7eb2e8f9f7 1244 * @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
<> 144:ef7eb2e8f9f7 1245 control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
<> 144:ef7eb2e8f9f7 1246 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1247 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1248 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1249 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1250 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1251 * @retval HAL status
<> 144:ef7eb2e8f9f7 1252 */
<> 144:ef7eb2e8f9f7 1253 HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1254 {
<> 144:ef7eb2e8f9f7 1255 uint32_t inputaddr = (uint32_t)pInBuffer;
<> 144:ef7eb2e8f9f7 1256
<> 144:ef7eb2e8f9f7 1257 /* Process Locked */
<> 144:ef7eb2e8f9f7 1258 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1259
<> 144:ef7eb2e8f9f7 1260 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1261 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1264 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1265 {
<> 144:ef7eb2e8f9f7 1266 /* Select the SHA1 mode and reset the HASH processor core, so that the HASH will be ready to compute
<> 144:ef7eb2e8f9f7 1267 the message digest of a new message */
<> 144:ef7eb2e8f9f7 1268 HASH->CR |= HASH_ALGOSELECTION_SHA1;
<> 144:ef7eb2e8f9f7 1269 HASH->CR |= HASH_CR_INIT;
<> 144:ef7eb2e8f9f7 1270 }
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1273 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* Set the phase */
<> 144:ef7eb2e8f9f7 1276 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1279 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1280 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1281 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /* Enable the DMA In DMA Stream */
AnnaBridge 167:e84263d55307 1284 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (Size%4U ? (Size+3U)/4U:Size/4U));
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1287 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1290 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* Return function status */
<> 144:ef7eb2e8f9f7 1293 return HAL_OK;
<> 144:ef7eb2e8f9f7 1294 }
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /**
<> 144:ef7eb2e8f9f7 1297 * @brief Returns the computed digest in SHA1 mode.
<> 144:ef7eb2e8f9f7 1298 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1299 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1300 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1301 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1302 * @retval HAL status
<> 144:ef7eb2e8f9f7 1303 */
<> 144:ef7eb2e8f9f7 1304 HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1305 {
<> 144:ef7eb2e8f9f7 1306 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /* Process Locked */
<> 144:ef7eb2e8f9f7 1309 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1310
<> 144:ef7eb2e8f9f7 1311 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1312 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /* Get tick */
<> 144:ef7eb2e8f9f7 1315 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1316 while(HAL_IS_BIT_CLR(HASH->SR, HASH_FLAG_DCIS))
<> 144:ef7eb2e8f9f7 1317 {
<> 144:ef7eb2e8f9f7 1318 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1319 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1320 {
<> 144:ef7eb2e8f9f7 1321 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1322 {
<> 144:ef7eb2e8f9f7 1323 /* Change state */
<> 144:ef7eb2e8f9f7 1324 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1327 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1328
<> 144:ef7eb2e8f9f7 1329 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1330 }
<> 144:ef7eb2e8f9f7 1331 }
<> 144:ef7eb2e8f9f7 1332 }
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1335 HASH_GetDigest(pOutBuffer, 20U);
<> 144:ef7eb2e8f9f7 1336
<> 144:ef7eb2e8f9f7 1337 /* Change HASH peripheral state */
<> 144:ef7eb2e8f9f7 1338 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1339
<> 144:ef7eb2e8f9f7 1340 /* Process UnLock */
<> 144:ef7eb2e8f9f7 1341 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /* Return function status */
<> 144:ef7eb2e8f9f7 1344 return HAL_OK;
<> 144:ef7eb2e8f9f7 1345 }
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /**
<> 144:ef7eb2e8f9f7 1349 * @}
<> 144:ef7eb2e8f9f7 1350 */
<> 144:ef7eb2e8f9f7 1351
<> 144:ef7eb2e8f9f7 1352 /** @defgroup HASH_Exported_Functions_Group5 HASH-MAC (HMAC) processing functions using polling mode
<> 144:ef7eb2e8f9f7 1353 * @brief HMAC processing functions using polling mode .
<> 144:ef7eb2e8f9f7 1354 *
<> 144:ef7eb2e8f9f7 1355 @verbatim
<> 144:ef7eb2e8f9f7 1356 ===============================================================================
<> 144:ef7eb2e8f9f7 1357 ##### HMAC processing using polling mode functions #####
<> 144:ef7eb2e8f9f7 1358 ===============================================================================
<> 144:ef7eb2e8f9f7 1359 [..] This section provides functions allowing to calculate in polling mode
<> 144:ef7eb2e8f9f7 1360 the HMAC value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1361 (+) MD5
<> 144:ef7eb2e8f9f7 1362 (+) SHA1
<> 144:ef7eb2e8f9f7 1363
<> 144:ef7eb2e8f9f7 1364 @endverbatim
<> 144:ef7eb2e8f9f7 1365 * @{
<> 144:ef7eb2e8f9f7 1366 */
<> 144:ef7eb2e8f9f7 1367
<> 144:ef7eb2e8f9f7 1368 /**
<> 144:ef7eb2e8f9f7 1369 * @brief Initializes the HASH peripheral in HMAC MD5 mode
<> 144:ef7eb2e8f9f7 1370 * then processes pInBuffer. The digest is available in pOutBuffer
<> 144:ef7eb2e8f9f7 1371 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1372 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1373 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1374 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1375 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1376 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1377 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1378 * @retval HAL status
<> 144:ef7eb2e8f9f7 1379 */
<> 144:ef7eb2e8f9f7 1380 HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1381 {
<> 144:ef7eb2e8f9f7 1382 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1383
<> 144:ef7eb2e8f9f7 1384 /* Process Locked */
<> 144:ef7eb2e8f9f7 1385 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1388 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1391 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1392 {
<> 144:ef7eb2e8f9f7 1393 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1394 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1395 {
<> 144:ef7eb2e8f9f7 1396 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1397 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1398 }
<> 144:ef7eb2e8f9f7 1399 else
<> 144:ef7eb2e8f9f7 1400 {
<> 144:ef7eb2e8f9f7 1401 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1402 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1403 }
<> 144:ef7eb2e8f9f7 1404 }
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 /* Set the phase */
<> 144:ef7eb2e8f9f7 1407 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1408
<> 144:ef7eb2e8f9f7 1409 /************************** STEP 1 ******************************************/
<> 144:ef7eb2e8f9f7 1410 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1411 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1414 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1417 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1418
<> 144:ef7eb2e8f9f7 1419 /* Get tick */
<> 144:ef7eb2e8f9f7 1420 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1423 {
<> 144:ef7eb2e8f9f7 1424 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1425 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1426 {
<> 144:ef7eb2e8f9f7 1427 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1428 {
<> 144:ef7eb2e8f9f7 1429 /* Change state */
<> 144:ef7eb2e8f9f7 1430 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1431
<> 144:ef7eb2e8f9f7 1432 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1433 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1434
<> 144:ef7eb2e8f9f7 1435 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1436 }
<> 144:ef7eb2e8f9f7 1437 }
<> 144:ef7eb2e8f9f7 1438 }
<> 144:ef7eb2e8f9f7 1439 /************************** STEP 2 ******************************************/
<> 144:ef7eb2e8f9f7 1440 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1441 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1442
<> 144:ef7eb2e8f9f7 1443 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1444 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1447 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 /* Get tick */
<> 144:ef7eb2e8f9f7 1450 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1453 {
<> 144:ef7eb2e8f9f7 1454 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1455 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1456 {
<> 144:ef7eb2e8f9f7 1457 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1458 {
<> 144:ef7eb2e8f9f7 1459 /* Change state */
<> 144:ef7eb2e8f9f7 1460 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1461
<> 144:ef7eb2e8f9f7 1462 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1463 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1466 }
<> 144:ef7eb2e8f9f7 1467 }
<> 144:ef7eb2e8f9f7 1468 }
<> 144:ef7eb2e8f9f7 1469 /************************** STEP 3 ******************************************/
<> 144:ef7eb2e8f9f7 1470 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1471 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1472
<> 144:ef7eb2e8f9f7 1473 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1474 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1477 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /* Get tick */
<> 144:ef7eb2e8f9f7 1480 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1483 {
<> 144:ef7eb2e8f9f7 1484 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1485 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1486 {
<> 144:ef7eb2e8f9f7 1487 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1488 {
<> 144:ef7eb2e8f9f7 1489 /* Change state */
<> 144:ef7eb2e8f9f7 1490 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1491
<> 144:ef7eb2e8f9f7 1492 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1493 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1496 }
<> 144:ef7eb2e8f9f7 1497 }
<> 144:ef7eb2e8f9f7 1498 }
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /* Read the message digest */
<> 144:ef7eb2e8f9f7 1501 HASH_GetDigest(pOutBuffer, 16U);
<> 144:ef7eb2e8f9f7 1502
<> 144:ef7eb2e8f9f7 1503 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1504 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1507 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1508
<> 144:ef7eb2e8f9f7 1509 /* Return function status */
<> 144:ef7eb2e8f9f7 1510 return HAL_OK;
<> 144:ef7eb2e8f9f7 1511 }
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /**
<> 144:ef7eb2e8f9f7 1514 * @brief Initializes the HASH peripheral in HMAC SHA1 mode
<> 144:ef7eb2e8f9f7 1515 * then processes pInBuffer. The digest is available in pOutBuffer.
<> 144:ef7eb2e8f9f7 1516 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1517 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1518 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1519 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1520 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1521 * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
<> 144:ef7eb2e8f9f7 1522 * @param Timeout: Timeout value
<> 144:ef7eb2e8f9f7 1523 * @retval HAL status
<> 144:ef7eb2e8f9f7 1524 */
<> 144:ef7eb2e8f9f7 1525 HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1526 {
<> 144:ef7eb2e8f9f7 1527 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /* Process Locked */
<> 144:ef7eb2e8f9f7 1530 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1531
<> 144:ef7eb2e8f9f7 1532 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1533 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1536 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1537 {
<> 144:ef7eb2e8f9f7 1538 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1539 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1540 {
<> 144:ef7eb2e8f9f7 1541 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1542 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1543 }
<> 144:ef7eb2e8f9f7 1544 else
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1547 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1548 }
<> 144:ef7eb2e8f9f7 1549 }
<> 144:ef7eb2e8f9f7 1550
<> 144:ef7eb2e8f9f7 1551 /* Set the phase */
<> 144:ef7eb2e8f9f7 1552 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1553
<> 144:ef7eb2e8f9f7 1554 /************************** STEP 1 ******************************************/
<> 144:ef7eb2e8f9f7 1555 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1556 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1559 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1562 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 /* Get tick */
<> 144:ef7eb2e8f9f7 1565 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1568 {
<> 144:ef7eb2e8f9f7 1569 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1570 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1571 {
<> 144:ef7eb2e8f9f7 1572 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1573 {
<> 144:ef7eb2e8f9f7 1574 /* Change state */
<> 144:ef7eb2e8f9f7 1575 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1578 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1581 }
<> 144:ef7eb2e8f9f7 1582 }
<> 144:ef7eb2e8f9f7 1583 }
<> 144:ef7eb2e8f9f7 1584 /************************** STEP 2 ******************************************/
<> 144:ef7eb2e8f9f7 1585 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1586 __HAL_HASH_SET_NBVALIDBITS(Size);
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1589 HASH_WriteData(pInBuffer, Size);
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1592 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /* Get tick */
<> 144:ef7eb2e8f9f7 1595 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1598 {
<> 144:ef7eb2e8f9f7 1599 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1600 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1601 {
<> 144:ef7eb2e8f9f7 1602 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1603 {
<> 144:ef7eb2e8f9f7 1604 /* Change state */
<> 144:ef7eb2e8f9f7 1605 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1608 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1611 }
<> 144:ef7eb2e8f9f7 1612 }
<> 144:ef7eb2e8f9f7 1613 }
<> 144:ef7eb2e8f9f7 1614 /************************** STEP 3 ******************************************/
<> 144:ef7eb2e8f9f7 1615 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1616 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 /* Write input buffer in data register */
<> 144:ef7eb2e8f9f7 1619 HASH_WriteData(hhash->Init.pKey, hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /* Start the digest calculation */
<> 144:ef7eb2e8f9f7 1622 __HAL_HASH_START_DIGEST();
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /* Get tick */
<> 144:ef7eb2e8f9f7 1625 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 while(HAL_IS_BIT_SET(HASH->SR, HASH_FLAG_BUSY))
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1630 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1631 {
<> 144:ef7eb2e8f9f7 1632 if((HAL_GetTick() - tickstart ) > Timeout)
<> 144:ef7eb2e8f9f7 1633 {
<> 144:ef7eb2e8f9f7 1634 /* Change state */
<> 144:ef7eb2e8f9f7 1635 hhash->State = HAL_HASH_STATE_TIMEOUT;
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1638 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1639
<> 144:ef7eb2e8f9f7 1640 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1641 }
<> 144:ef7eb2e8f9f7 1642 }
<> 144:ef7eb2e8f9f7 1643 }
<> 144:ef7eb2e8f9f7 1644 /* Read the message digest */
AnnaBridge 167:e84263d55307 1645 HASH_GetDigest(pOutBuffer, 20);
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1648 hhash->State = HAL_HASH_STATE_READY;
<> 144:ef7eb2e8f9f7 1649
<> 144:ef7eb2e8f9f7 1650 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1651 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 /* Return function status */
<> 144:ef7eb2e8f9f7 1654 return HAL_OK;
<> 144:ef7eb2e8f9f7 1655 }
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /**
<> 144:ef7eb2e8f9f7 1658 * @}
<> 144:ef7eb2e8f9f7 1659 */
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 /** @defgroup HASH_Exported_Functions_Group6 HASH-MAC (HMAC) processing functions using DMA mode
<> 144:ef7eb2e8f9f7 1662 * @brief HMAC processing functions using DMA mode .
<> 144:ef7eb2e8f9f7 1663 *
<> 144:ef7eb2e8f9f7 1664 @verbatim
<> 144:ef7eb2e8f9f7 1665 ===============================================================================
<> 144:ef7eb2e8f9f7 1666 ##### HMAC processing using DMA mode functions #####
<> 144:ef7eb2e8f9f7 1667 ===============================================================================
<> 144:ef7eb2e8f9f7 1668 [..] This section provides functions allowing to calculate in DMA mode
<> 144:ef7eb2e8f9f7 1669 the HMAC value using one of the following algorithms:
<> 144:ef7eb2e8f9f7 1670 (+) MD5
<> 144:ef7eb2e8f9f7 1671 (+) SHA1
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 @endverbatim
<> 144:ef7eb2e8f9f7 1674 * @{
<> 144:ef7eb2e8f9f7 1675 */
<> 144:ef7eb2e8f9f7 1676
<> 144:ef7eb2e8f9f7 1677 /**
<> 144:ef7eb2e8f9f7 1678 * @brief Initializes the HASH peripheral in HMAC MD5 mode
<> 144:ef7eb2e8f9f7 1679 * then enables DMA to control data transfer.
<> 144:ef7eb2e8f9f7 1680 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1681 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1682 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1683 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1684 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1685 * @retval HAL status
<> 144:ef7eb2e8f9f7 1686 */
<> 144:ef7eb2e8f9f7 1687 HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1688 {
<> 144:ef7eb2e8f9f7 1689 uint32_t inputaddr = 0U;
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 /* Process Locked */
<> 144:ef7eb2e8f9f7 1692 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1695 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1696
<> 144:ef7eb2e8f9f7 1697 /* Save buffer pointer and size in handle */
<> 144:ef7eb2e8f9f7 1698 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 1699 hhash->HashBuffSize = Size;
<> 144:ef7eb2e8f9f7 1700 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1703 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1704 {
<> 144:ef7eb2e8f9f7 1705 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1706 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1707 {
<> 144:ef7eb2e8f9f7 1708 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1709 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1710 }
<> 144:ef7eb2e8f9f7 1711 else
<> 144:ef7eb2e8f9f7 1712 {
<> 144:ef7eb2e8f9f7 1713 /* Select the HMAC MD5 mode */
<> 144:ef7eb2e8f9f7 1714 HASH->CR |= (HASH_ALGOSELECTION_MD5 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1715 }
<> 144:ef7eb2e8f9f7 1716 }
<> 144:ef7eb2e8f9f7 1717
<> 144:ef7eb2e8f9f7 1718 /* Set the phase */
<> 144:ef7eb2e8f9f7 1719 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1722 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 /* Get the key address */
<> 144:ef7eb2e8f9f7 1725 inputaddr = (uint32_t)(hhash->Init.pKey);
<> 144:ef7eb2e8f9f7 1726
<> 144:ef7eb2e8f9f7 1727 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1728 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1729 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1730 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 /* Enable the DMA In DMA Stream */
AnnaBridge 167:e84263d55307 1733 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
<> 144:ef7eb2e8f9f7 1734 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1735 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1736
<> 144:ef7eb2e8f9f7 1737 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1738 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1739
<> 144:ef7eb2e8f9f7 1740 /* Return function status */
<> 144:ef7eb2e8f9f7 1741 return HAL_OK;
<> 144:ef7eb2e8f9f7 1742 }
<> 144:ef7eb2e8f9f7 1743
<> 144:ef7eb2e8f9f7 1744 /**
<> 144:ef7eb2e8f9f7 1745 * @brief Initializes the HASH peripheral in HMAC SHA1 mode
<> 144:ef7eb2e8f9f7 1746 * then enables DMA to control data transfer.
<> 144:ef7eb2e8f9f7 1747 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1748 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1749 * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
<> 144:ef7eb2e8f9f7 1750 * @param Size: Length of the input buffer in bytes.
<> 144:ef7eb2e8f9f7 1751 * If the Size is not multiple of 64 bytes, the padding is managed by hardware.
<> 144:ef7eb2e8f9f7 1752 * @retval HAL status
<> 144:ef7eb2e8f9f7 1753 */
<> 144:ef7eb2e8f9f7 1754 HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size)
<> 144:ef7eb2e8f9f7 1755 {
<> 144:ef7eb2e8f9f7 1756 uint32_t inputaddr = 0U;
<> 144:ef7eb2e8f9f7 1757
<> 144:ef7eb2e8f9f7 1758 /* Process Locked */
<> 144:ef7eb2e8f9f7 1759 __HAL_LOCK(hhash);
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /* Change the HASH state */
<> 144:ef7eb2e8f9f7 1762 hhash->State = HAL_HASH_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1763
<> 144:ef7eb2e8f9f7 1764 /* Save buffer pointer and size in handle */
<> 144:ef7eb2e8f9f7 1765 hhash->pHashInBuffPtr = pInBuffer;
<> 144:ef7eb2e8f9f7 1766 hhash->HashBuffSize = Size;
<> 144:ef7eb2e8f9f7 1767 hhash->HashInCount = 0U;
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 /* Check if initialization phase has already been performed */
<> 144:ef7eb2e8f9f7 1770 if(hhash->Phase == HAL_HASH_PHASE_READY)
<> 144:ef7eb2e8f9f7 1771 {
<> 144:ef7eb2e8f9f7 1772 /* Check if key size is greater than 64 bytes */
<> 144:ef7eb2e8f9f7 1773 if(hhash->Init.KeySize > 64U)
<> 144:ef7eb2e8f9f7 1774 {
<> 144:ef7eb2e8f9f7 1775 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1776 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1777 }
<> 144:ef7eb2e8f9f7 1778 else
<> 144:ef7eb2e8f9f7 1779 {
<> 144:ef7eb2e8f9f7 1780 /* Select the HMAC SHA1 mode */
<> 144:ef7eb2e8f9f7 1781 HASH->CR |= (HASH_ALGOSELECTION_SHA1 | HASH_ALGOMODE_HMAC | HASH_CR_INIT);
<> 144:ef7eb2e8f9f7 1782 }
<> 144:ef7eb2e8f9f7 1783 }
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /* Set the phase */
<> 144:ef7eb2e8f9f7 1786 hhash->Phase = HAL_HASH_PHASE_PROCESS;
<> 144:ef7eb2e8f9f7 1787
<> 144:ef7eb2e8f9f7 1788 /* Configure the number of valid bits in last word of the message */
<> 144:ef7eb2e8f9f7 1789 __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize);
<> 144:ef7eb2e8f9f7 1790
<> 144:ef7eb2e8f9f7 1791 /* Get the key address */
<> 144:ef7eb2e8f9f7 1792 inputaddr = (uint32_t)(hhash->Init.pKey);
<> 144:ef7eb2e8f9f7 1793
<> 144:ef7eb2e8f9f7 1794 /* Set the HASH DMA transfer complete callback */
<> 144:ef7eb2e8f9f7 1795 hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
<> 144:ef7eb2e8f9f7 1796 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1797 hhash->hdmain->XferErrorCallback = HASH_DMAError;
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /* Enable the DMA In DMA Stream */
AnnaBridge 167:e84263d55307 1800 HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (hhash->Init.KeySize%4U ? (hhash->Init.KeySize+3U)/4U:hhash->Init.KeySize/4U));
<> 144:ef7eb2e8f9f7 1801 /* Enable DMA requests */
<> 144:ef7eb2e8f9f7 1802 HASH->CR |= (HASH_CR_DMAE);
<> 144:ef7eb2e8f9f7 1803
<> 144:ef7eb2e8f9f7 1804 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 1805 __HAL_UNLOCK(hhash);
<> 144:ef7eb2e8f9f7 1806
<> 144:ef7eb2e8f9f7 1807 /* Return function status */
<> 144:ef7eb2e8f9f7 1808 return HAL_OK;
<> 144:ef7eb2e8f9f7 1809 }
<> 144:ef7eb2e8f9f7 1810
<> 144:ef7eb2e8f9f7 1811 /**
<> 144:ef7eb2e8f9f7 1812 * @}
<> 144:ef7eb2e8f9f7 1813 */
<> 144:ef7eb2e8f9f7 1814
<> 144:ef7eb2e8f9f7 1815 /** @defgroup HASH_Exported_Functions_Group7 Peripheral State functions
<> 144:ef7eb2e8f9f7 1816 * @brief Peripheral State functions.
<> 144:ef7eb2e8f9f7 1817 *
<> 144:ef7eb2e8f9f7 1818 @verbatim
<> 144:ef7eb2e8f9f7 1819 ===============================================================================
<> 144:ef7eb2e8f9f7 1820 ##### Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1821 ===============================================================================
<> 144:ef7eb2e8f9f7 1822 [..]
<> 144:ef7eb2e8f9f7 1823 This subsection permits to get in run-time the status of the peripheral.
<> 144:ef7eb2e8f9f7 1824
<> 144:ef7eb2e8f9f7 1825 @endverbatim
<> 144:ef7eb2e8f9f7 1826 * @{
<> 144:ef7eb2e8f9f7 1827 */
<> 144:ef7eb2e8f9f7 1828
<> 144:ef7eb2e8f9f7 1829 /**
<> 144:ef7eb2e8f9f7 1830 * @brief return the HASH state
<> 144:ef7eb2e8f9f7 1831 * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1832 * the configuration information for HASH module
<> 144:ef7eb2e8f9f7 1833 * @retval HAL state
<> 144:ef7eb2e8f9f7 1834 */
<> 144:ef7eb2e8f9f7 1835 HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
<> 144:ef7eb2e8f9f7 1836 {
<> 144:ef7eb2e8f9f7 1837 return hhash->State;
<> 144:ef7eb2e8f9f7 1838 }
<> 144:ef7eb2e8f9f7 1839
<> 144:ef7eb2e8f9f7 1840 /**
<> 144:ef7eb2e8f9f7 1841 * @}
<> 144:ef7eb2e8f9f7 1842 */
<> 144:ef7eb2e8f9f7 1843
<> 144:ef7eb2e8f9f7 1844 /**
<> 144:ef7eb2e8f9f7 1845 * @}
<> 144:ef7eb2e8f9f7 1846 */
<> 144:ef7eb2e8f9f7 1847 #endif /* STM32F215xx || STM32F217xx */
<> 144:ef7eb2e8f9f7 1848 #endif /* HAL_HASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1849 /**
<> 144:ef7eb2e8f9f7 1850 * @}
<> 144:ef7eb2e8f9f7 1851 */
<> 144:ef7eb2e8f9f7 1852
<> 144:ef7eb2e8f9f7 1853 /**
<> 144:ef7eb2e8f9f7 1854 * @}
<> 144:ef7eb2e8f9f7 1855 */
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/