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Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F3/i2c_device.h@188:60408c49b6d4, 2018-09-20 (annotated)

Committer:
WaleedElmughrabi
Date:
Thu Sep 20 16:11:23 2018 +0000
Revision:
188:60408c49b6d4
Parent:
156:95d6b41a828b 
Fork modified for BG96 error

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /* mbed Microcontroller Library
<> 153:fa9ff456f731 2 *******************************************************************************
<> 153:fa9ff456f731 3 * Copyright (c) 2015, STMicroelectronics
<> 153:fa9ff456f731 4 * All rights reserved.
<> 153:fa9ff456f731 5 *
<> 153:fa9ff456f731 6 * Redistribution and use in source and binary forms, with or without
<> 153:fa9ff456f731 7 * modification, are permitted provided that the following conditions are met:
<> 153:fa9ff456f731 8 *
<> 153:fa9ff456f731 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 153:fa9ff456f731 10 * this list of conditions and the following disclaimer.
<> 153:fa9ff456f731 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 153:fa9ff456f731 12 * this list of conditions and the following disclaimer in the documentation
<> 153:fa9ff456f731 13 * and/or other materials provided with the distribution.
<> 153:fa9ff456f731 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 153:fa9ff456f731 15 * may be used to endorse or promote products derived from this software
<> 153:fa9ff456f731 16 * without specific prior written permission.
<> 153:fa9ff456f731 17 *
<> 153:fa9ff456f731 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 153:fa9ff456f731 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 153:fa9ff456f731 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 153:fa9ff456f731 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 153:fa9ff456f731 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 153:fa9ff456f731 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 153:fa9ff456f731 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 153:fa9ff456f731 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 153:fa9ff456f731 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 153:fa9ff456f731 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 153:fa9ff456f731 28 *******************************************************************************
<> 153:fa9ff456f731 29 */
<> 153:fa9ff456f731 30 #ifndef MBED_I2C_DEVICE_H
<> 153:fa9ff456f731 31 #define MBED_I2C_DEVICE_H
<> 153:fa9ff456f731 32
<> 153:fa9ff456f731 33 #include "cmsis.h"
<> 153:fa9ff456f731 34
<> 153:fa9ff456f731 35 #ifdef __cplusplus
<> 153:fa9ff456f731 36 extern "C" {
<> 153:fa9ff456f731 37 #endif
<> 153:fa9ff456f731 38
<> 153:fa9ff456f731 39 #ifdef DEVICE_I2C
<> 153:fa9ff456f731 40
<> 153:fa9ff456f731 41 #define I2C_IP_VERSION_V2
<> 153:fa9ff456f731 42
<> 153:fa9ff456f731 43 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI)
<> 153:fa9ff456f731 44
<> 153:fa9ff456f731 45 /* Family specifc settings for clock source */
<> 153:fa9ff456f731 46 #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 47 #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 48 #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK
<> 153:fa9ff456f731 49
<> 153:fa9ff456f731 50 /* Provide the suitable timing depending on requested frequencie */
<> 156:95d6b41a828b 51 static inline uint32_t get_i2c_timing(int hz)
<> 153:fa9ff456f731 52 {
<> 153:fa9ff456f731 53 uint32_t tim = 0;
<> 153:fa9ff456f731 54 /*
<> 153:fa9ff456f731 55 Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235)
<> 153:fa9ff456f731 56 * Standard mode (up to 100 kHz)
<> 153:fa9ff456f731 57 * Fast Mode (up to 400 kHz)
<> 153:fa9ff456f731 58 * Fast Mode Plus (up to 1 MHz)
<> 153:fa9ff456f731 59 Below values obtained with:
<> 153:fa9ff456f731 60 - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE)
<> 153:fa9ff456f731 61 - Analog filter delay = ON
<> 153:fa9ff456f731 62 - Digital filter coefficient = 0
<> 153:fa9ff456f731 63 */
<> 153:fa9ff456f731 64 if (SystemCoreClock == 64000000) {
<> 153:fa9ff456f731 65 switch (hz) {
<> 153:fa9ff456f731 66 case 100000:
<> 153:fa9ff456f731 67 tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns
<> 153:fa9ff456f731 68 break;
<> 153:fa9ff456f731 69 case 400000:
<> 153:fa9ff456f731 70 tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns
<> 153:fa9ff456f731 71 break;
<> 153:fa9ff456f731 72 case 1000000:
<> 153:fa9ff456f731 73 tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
<> 153:fa9ff456f731 74 break;
<> 153:fa9ff456f731 75 default:
<> 153:fa9ff456f731 76 break;
<> 153:fa9ff456f731 77 }
<> 153:fa9ff456f731 78 } else if (SystemCoreClock == 72000000) {
<> 153:fa9ff456f731 79 switch (hz) {
<> 153:fa9ff456f731 80 case 100000:
<> 153:fa9ff456f731 81 tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns
<> 153:fa9ff456f731 82 break;
<> 153:fa9ff456f731 83 case 400000:
<> 153:fa9ff456f731 84 tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns
<> 153:fa9ff456f731 85 break;
<> 153:fa9ff456f731 86 case 1000000:
<> 153:fa9ff456f731 87 tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns
<> 153:fa9ff456f731 88 break;
<> 153:fa9ff456f731 89 default:
<> 153:fa9ff456f731 90 break;
<> 153:fa9ff456f731 91 }
<> 153:fa9ff456f731 92 }
<> 153:fa9ff456f731 93 return tim;
<> 153:fa9ff456f731 94 }
<> 153:fa9ff456f731 95
<> 153:fa9ff456f731 96 #ifdef __cplusplus
<> 153:fa9ff456f731 97 }
<> 153:fa9ff456f731 98 #endif
<> 153:fa9ff456f731 99
<> 153:fa9ff456f731 100 #endif // DEVICE_I2C
<> 153:fa9ff456f731 101
<> 153:fa9ff456f731 102 #endif