SilentSensors / mbed-dev

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_NUC472/device/system_NUC472_442.c@188:60408c49b6d4, 2018-09-20 (annotated)

Committer:
WaleedElmughrabi
Date:
Thu Sep 20 16:11:23 2018 +0000
Revision:
188:60408c49b6d4
Parent:
160:d5399cc887bb 
Fork modified for BG96 error

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************//**
<> 149:156823d33999 2 * @file system_NUC472_442.c
<> 149:156823d33999 3 * @version V1.00
<> 149:156823d33999 4 * $Revision: 15 $
<> 149:156823d33999 5 * $Date: 14/05/29 1:13p $
<> 149:156823d33999 6 * @brief NUC472/NUC442 system clock init code and assert handler
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *****************************************************************************/
<> 149:156823d33999 11
<> 149:156823d33999 12 #include "NUC472_442.h"
<> 149:156823d33999 13 //#include "rtc.h"
<> 149:156823d33999 14
<> 149:156823d33999 15 /*----------------------------------------------------------------------------
<> 149:156823d33999 16 Clock Variable definitions
<> 149:156823d33999 17 *----------------------------------------------------------------------------*/
<> 149:156823d33999 18 uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock)*/
<> 149:156823d33999 19 uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
<> 149:156823d33999 20 uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0, __LIRC, 0, 0, 0, __HIRC}; /*!< System clock source table */
<> 149:156823d33999 21
<> 160:d5399cc887bb 22 #if defined TARGET_NU_XRAM_SUPPORTED
<> 149:156823d33999 23 static void nu_ebi_init(void);
<> 149:156823d33999 24 #endif
<> 149:156823d33999 25
<> 149:156823d33999 26 /*----------------------------------------------------------------------------
<> 149:156823d33999 27 Clock functions
<> 149:156823d33999 28 *----------------------------------------------------------------------------*/
<> 149:156823d33999 29 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
<> 149:156823d33999 30 {
<> 149:156823d33999 31 uint32_t u32Freq, u32ClkSrc;
<> 149:156823d33999 32 uint32_t u32HclkDiv;
<> 149:156823d33999 33
<> 149:156823d33999 34 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
<> 149:156823d33999 35
<> 149:156823d33999 36 if(u32ClkSrc != CLK_CLKSEL0_HCLKSEL_PLL) {
<> 149:156823d33999 37 /* Use the clock sources directly */
<> 149:156823d33999 38 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
<> 149:156823d33999 39 } else {
<> 149:156823d33999 40 /* Use PLL clock */
<> 149:156823d33999 41 u32Freq = CLK_GetPLLClockFreq();
<> 149:156823d33999 42 }
<> 149:156823d33999 43
<> 149:156823d33999 44 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1;
<> 149:156823d33999 45
<> 149:156823d33999 46 /* Update System Core Clock */
<> 149:156823d33999 47 SystemCoreClock = u32Freq/u32HclkDiv;
<> 149:156823d33999 48
<> 149:156823d33999 49 CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
<> 149:156823d33999 50 }
<> 149:156823d33999 51
<> 149:156823d33999 52 /**
<> 149:156823d33999 53 * Initialize the system
<> 149:156823d33999 54 *
<> 149:156823d33999 55 * @return none
<> 149:156823d33999 56 *
<> 149:156823d33999 57 * @brief Setup the microcontroller system.
<> 149:156823d33999 58 */
<> 149:156823d33999 59 void SystemInit (void)
<> 149:156823d33999 60 {
<> 149:156823d33999 61 //uint32_t u32RTC_EN_Flag = 0;
<> 149:156823d33999 62
<> 149:156823d33999 63 /* FPU settings ------------------------------------------------------------*/
<> 149:156823d33999 64 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
<> 149:156823d33999 65 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
<> 149:156823d33999 66 (3UL << 11*2) ); /* set CP11 Full Access */
<> 149:156823d33999 67 #endif
<> 149:156823d33999 68
<> 149:156823d33999 69 /* The code snippet below is for old-version chip and has potential risk, e.g. program reboots and hangs in it with the call to NVIC_SystemReset(). Remove it for new-version chip. */
<> 149:156823d33999 70 #if 0
<> 149:156823d33999 71 /* ------------------ Release Tamper pin ---------------------------------*/
<> 149:156823d33999 72 /* Waiting for 10kHz clock ready */
<> 149:156823d33999 73 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
<> 149:156823d33999 74
<> 149:156823d33999 75 u32RTC_EN_Flag = ((CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk) >> CLK_APBCLK0_RTCCKEN_Pos);
<> 149:156823d33999 76
<> 149:156823d33999 77 if(!u32RTC_EN_Flag) {
<> 149:156823d33999 78 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Enable
<> 149:156823d33999 79 }
<> 149:156823d33999 80
<> 149:156823d33999 81 RTC->INIT = RTC_INIT_KEY;
<> 149:156823d33999 82 while(RTC->INIT != 0x1);
<> 149:156823d33999 83
<> 149:156823d33999 84 if(!(RTC->TAMPCTL & RTC_TAMPCTL_TIEN_Msk)) {
<> 149:156823d33999 85 RTC->RWEN = RTC_WRITE_KEY;
<> 149:156823d33999 86 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
<> 149:156823d33999 87
<> 149:156823d33999 88 RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk;
<> 149:156823d33999 89
<> 149:156823d33999 90 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
<> 149:156823d33999 91
<> 149:156823d33999 92 RTC->RWEN = RTC_WRITE_KEY;
<> 149:156823d33999 93 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
<> 149:156823d33999 94
<> 149:156823d33999 95 RTC->SPR[23] = RTC->SPR[23];
<> 149:156823d33999 96 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
<> 149:156823d33999 97
<> 149:156823d33999 98 RTC->RWEN = RTC_WRITE_KEY;
<> 149:156823d33999 99 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
<> 149:156823d33999 100
<> 149:156823d33999 101 RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk;
<> 149:156823d33999 102 while(!(RTC->SPRCTL & RTC_SPRCTL_SPRRWRDY_Msk));
<> 149:156823d33999 103
<> 149:156823d33999 104 RTC->RWEN = RTC_WRITE_KEY;
<> 149:156823d33999 105 while(!(RTC->RWEN & RTC_RWEN_RWENF_Msk));
<> 149:156823d33999 106
<> 149:156823d33999 107 RTC->INTSTS = RTC_INTSTS_TICKIF_Msk;
<> 149:156823d33999 108 }
<> 149:156823d33999 109
<> 149:156823d33999 110 if(!u32RTC_EN_Flag) {
<> 149:156823d33999 111 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; // RTC Clock Disable
<> 149:156823d33999 112 }
<> 149:156823d33999 113 /*------------------------------------------------------------------------*/
<> 149:156823d33999 114 #endif
<> 149:156823d33999 115
<> 160:d5399cc887bb 116 #if defined TARGET_NU_XRAM_SUPPORTED
<> 149:156823d33999 117 // NOTE: C-runtime not initialized yet. Ensure no static memory (global variable) are accessed in this function.
<> 149:156823d33999 118 nu_ebi_init();
<> 149:156823d33999 119 #endif
<> 149:156823d33999 120 }
<> 149:156823d33999 121
<> 160:d5399cc887bb 122 #if defined TARGET_NU_XRAM_SUPPORTED
<> 149:156823d33999 123 void nu_ebi_init(void)
<> 149:156823d33999 124 {
<> 149:156823d33999 125 /* Enable IP clock */
<> 149:156823d33999 126 CLK_EnableModuleClock(EBI_MODULE);
<> 149:156823d33999 127
<> 149:156823d33999 128 /* Configure EBI multi-function pins */
<> 149:156823d33999 129 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA10MFP_Msk) ) | SYS_GPA_MFPH_PA10MFP_EBI_A20; /* A20. = PA10 */
<> 149:156823d33999 130 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA9MFP_Msk) ) | SYS_GPA_MFPH_PA9MFP_EBI_A19; /* A19. = PA9 */
<> 149:156823d33999 131 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA8MFP_Msk) ) | SYS_GPA_MFPH_PA8MFP_EBI_A18; /* A18. = PA8 */
<> 149:156823d33999 132 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA7MFP_Msk) ) | SYS_GPA_MFPL_PA7MFP_EBI_A17; /* A17. = PA7 */
<> 149:156823d33999 133 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA6MFP_Msk) ) | SYS_GPA_MFPL_PA6MFP_EBI_A16; /* A16. = PA6 */
<> 149:156823d33999 134 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB13MFP_Msk) ) | SYS_GPB_MFPH_PB13MFP_EBI_AD15; /* AD15 = PB13 */
<> 149:156823d33999 135
<> 149:156823d33999 136 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB12MFP_Msk) ) | SYS_GPB_MFPH_PB12MFP_EBI_AD14; /* AD14 = PB12 */
<> 149:156823d33999 137 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB11MFP_Msk) ) | SYS_GPB_MFPH_PB11MFP_EBI_AD13; /* AD13 = PB11 */
<> 149:156823d33999 138 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB10MFP_Msk) ) | SYS_GPB_MFPH_PB10MFP_EBI_AD12; /* AD12 = PB10 */
<> 149:156823d33999 139 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB9MFP_Msk) ) | SYS_GPB_MFPH_PB9MFP_EBI_AD11; /* AD11 = PB9 */
<> 149:156823d33999 140 SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SYS_GPB_MFPH_PB8MFP_Msk) ) | SYS_GPB_MFPH_PB8MFP_EBI_AD10; /* AD10 = PB8 */
<> 149:156823d33999 141
<> 149:156823d33999 142 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB7MFP_Msk) ) | SYS_GPB_MFPL_PB7MFP_EBI_AD9; /* AD9 = PB7 */
<> 149:156823d33999 143 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB6MFP_Msk) ) | SYS_GPB_MFPL_PB6MFP_EBI_AD8; /* AD8 = PB6 */
<> 149:156823d33999 144 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB5MFP_Msk) ) | SYS_GPB_MFPL_PB5MFP_EBI_AD7; /* AD7 = PB5 */
<> 149:156823d33999 145 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB4MFP_Msk) ) | SYS_GPB_MFPL_PB4MFP_EBI_AD6; /* AD6 = PB4 */
<> 149:156823d33999 146 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB3MFP_Msk) ) | SYS_GPB_MFPL_PB3MFP_EBI_AD5; /* AD5 = PB3 */
<> 149:156823d33999 147 SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SYS_GPB_MFPL_PB2MFP_Msk) ) | SYS_GPB_MFPL_PB2MFP_EBI_AD4; /* AD4 = PB2 */
<> 149:156823d33999 148
<> 149:156823d33999 149 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA14MFP_Msk) ) | SYS_GPA_MFPH_PA14MFP_EBI_AD3; /* AD3. = PA14 */
<> 149:156823d33999 150 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA13MFP_Msk) ) | SYS_GPA_MFPH_PA13MFP_EBI_AD2; /* AD2. = PA13 */
<> 149:156823d33999 151 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA12MFP_Msk) ) | SYS_GPA_MFPH_PA12MFP_EBI_AD1; /* AD1. = PA12 */
<> 149:156823d33999 152 SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SYS_GPA_MFPH_PA11MFP_Msk) ) | SYS_GPA_MFPH_PA11MFP_EBI_AD0; /* AD0. = PA11 */
<> 149:156823d33999 153
<> 149:156823d33999 154 SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE6MFP_Msk) ) | SYS_GPE_MFPL_PE6MFP_EBI_nWR; /* PE.6 = nWR */
<> 149:156823d33999 155 SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SYS_GPE_MFPL_PE7MFP_Msk) ) | SYS_GPE_MFPL_PE7MFP_EBI_nRD; /* PE.7 = nRD */
<> 149:156823d33999 156 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE8MFP_Msk) ) | SYS_GPE_MFPH_PE8MFP_EBI_ALE; /* PE.8 = ALE */
<> 149:156823d33999 157 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE9MFP_Msk) ) | SYS_GPE_MFPH_PE9MFP_EBI_nWRH; /* PE.9 = WRH */
<> 149:156823d33999 158 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE10MFP_Msk) ) | SYS_GPE_MFPH_PE10MFP_EBI_nWRL; /* PE.10 = WRL */
<> 149:156823d33999 159
<> 149:156823d33999 160 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE11MFP_Msk) ) | SYS_GPE_MFPH_PE11MFP_EBI_nCS0; /* PE.11 = nCS0 */
<> 149:156823d33999 161 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE12MFP_Msk) ) | SYS_GPE_MFPH_PE12MFP_EBI_nCS1; /* PE.12 = nCS1 */
<> 149:156823d33999 162 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE13MFP_Msk) ) | SYS_GPE_MFPH_PE13MFP_EBI_nCS2; /* PE.13 = nCS2 */
<> 149:156823d33999 163 SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SYS_GPE_MFPH_PE14MFP_Msk) ) | SYS_GPE_MFPH_PE14MFP_EBI_nCS3; /* PE.14 = nCS3 */
<> 149:156823d33999 164
<> 149:156823d33999 165 const uint32_t u32Timing = 0x21C;
<> 149:156823d33999 166
<> 149:156823d33999 167 /* Open EBI interface */
<> 149:156823d33999 168 EBI_Open(EBI_BANK0, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
<> 149:156823d33999 169 EBI_Open(EBI_BANK1, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
<> 149:156823d33999 170 EBI_Open(EBI_BANK2, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
<> 149:156823d33999 171 EBI_Open(EBI_BANK3, EBI_BUSWIDTH_16BIT, EBI_TIMING_FAST, EBI_SEPARATEMODE_DISABLE, EBI_CS_ACTIVE_LOW);
<> 149:156823d33999 172
<> 149:156823d33999 173 /* Configure EBI timing */
<> 149:156823d33999 174 EBI_SetBusTiming(EBI_BANK0, u32Timing, EBI_MCLKDIV_2);
<> 149:156823d33999 175 EBI_SetBusTiming(EBI_BANK1, u32Timing, EBI_MCLKDIV_2);
<> 149:156823d33999 176 EBI_SetBusTiming(EBI_BANK2, u32Timing, EBI_MCLKDIV_2);
<> 149:156823d33999 177 EBI_SetBusTiming(EBI_BANK3, u32Timing, EBI_MCLKDIV_2);
<> 149:156823d33999 178 }
<> 149:156823d33999 179 #endif
<> 149:156823d33999 180 /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/