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targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/bpwm_reg.h@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
mbed-dev library. Release version 163

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 187:0387e8f68319 1 /**************************************************************************//**
AnnaBridge 187:0387e8f68319 2 * @file bpwm_reg.h
AnnaBridge 187:0387e8f68319 3 * @version V1.00
AnnaBridge 187:0387e8f68319 4 * @brief BPWM register definition header file
AnnaBridge 187:0387e8f68319 5 *
AnnaBridge 187:0387e8f68319 6 * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 187:0387e8f68319 7 *****************************************************************************/
AnnaBridge 187:0387e8f68319 8 #ifndef __BPWM_REG_H__
AnnaBridge 187:0387e8f68319 9 #define __BPWM_REG_H__
AnnaBridge 187:0387e8f68319 10
AnnaBridge 187:0387e8f68319 11
AnnaBridge 187:0387e8f68319 12 /*---------------------- Basic Pulse Width Modulation Controller -------------------------*/
AnnaBridge 187:0387e8f68319 13 /**
AnnaBridge 187:0387e8f68319 14 @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM)
AnnaBridge 187:0387e8f68319 15 Memory Mapped Structure for BPWM Controller
AnnaBridge 187:0387e8f68319 16 @{ */
AnnaBridge 187:0387e8f68319 17
AnnaBridge 187:0387e8f68319 18 typedef struct
AnnaBridge 187:0387e8f68319 19 {
AnnaBridge 187:0387e8f68319 20 /**
AnnaBridge 187:0387e8f68319 21 * @var BCAPDAT_T::RCAPDAT
AnnaBridge 187:0387e8f68319 22 * Offset: 0x20C BPWM Rising Capture Data Register 0~5
AnnaBridge 187:0387e8f68319 23 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 24 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 25 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 26 * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only)
AnnaBridge 187:0387e8f68319 27 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 28 * @var BCAPDAT_T::FCAPDAT
AnnaBridge 187:0387e8f68319 29 * Offset: 0x210 BPWM Falling Capture Data Register 0~5
AnnaBridge 187:0387e8f68319 30 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 31 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 32 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 33 * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only)
AnnaBridge 187:0387e8f68319 34 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 35 */
AnnaBridge 187:0387e8f68319 36 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */
AnnaBridge 187:0387e8f68319 37 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */
AnnaBridge 187:0387e8f68319 38 } BCAPDAT_T;
AnnaBridge 187:0387e8f68319 39
AnnaBridge 187:0387e8f68319 40
AnnaBridge 187:0387e8f68319 41 typedef struct
AnnaBridge 187:0387e8f68319 42 {
AnnaBridge 187:0387e8f68319 43 /**
AnnaBridge 187:0387e8f68319 44 * @var BPWM_T::CTL0
AnnaBridge 187:0387e8f68319 45 * Offset: 0x00 BPWM Control Register 0
AnnaBridge 187:0387e8f68319 46 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 47 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 48 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 49 * |[0] |CTRLD0 |Center Re-load
AnnaBridge 187:0387e8f68319 50 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 51 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 52 * | | |CMPDAT will load to CMPBUF at the center point of a period
AnnaBridge 187:0387e8f68319 53 * |[1] |CTRLD1 |Center Re-load
AnnaBridge 187:0387e8f68319 54 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 55 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 56 * | | |CMPDAT will load to CMPBUF at the center point of a period
AnnaBridge 187:0387e8f68319 57 * |[2] |CTRLD2 |Center Re-load
AnnaBridge 187:0387e8f68319 58 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 59 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 60 * | | |CMPDAT will load to CMPBUF at the center point of a period
AnnaBridge 187:0387e8f68319 61 * |[3] |CTRLD3 |Center Re-load
AnnaBridge 187:0387e8f68319 62 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 63 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 64 * | | |CMPDAT will load to CMPBUF at the center point of a period
AnnaBridge 187:0387e8f68319 65 * |[4] |CTRLD4 |Center Re-load
AnnaBridge 187:0387e8f68319 66 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 67 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 68 * | | |CMPDAT will load to CMPBUF at the center point of a period
AnnaBridge 187:0387e8f68319 69 * |[5] |CTRLD5 |Center Re-load
AnnaBridge 187:0387e8f68319 70 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 71 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 72 * | | |CMPDAT will load to CMPBUF at the center point of a period
AnnaBridge 187:0387e8f68319 73 * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S)
AnnaBridge 187:0387e8f68319 74 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 75 * | | |0 = PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 76 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 187:0387e8f68319 77 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 187:0387e8f68319 78 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 187:0387e8f68319 79 * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S)
AnnaBridge 187:0387e8f68319 80 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 81 * | | |0 = PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 82 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 187:0387e8f68319 83 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 187:0387e8f68319 84 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 187:0387e8f68319 85 * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S)
AnnaBridge 187:0387e8f68319 86 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 87 * | | |0 = PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 88 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 187:0387e8f68319 89 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 187:0387e8f68319 90 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 187:0387e8f68319 91 * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S)
AnnaBridge 187:0387e8f68319 92 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 93 * | | |0 = PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 94 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 187:0387e8f68319 95 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 187:0387e8f68319 96 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 187:0387e8f68319 97 * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S)
AnnaBridge 187:0387e8f68319 98 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 99 * | | |0 = PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 100 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 187:0387e8f68319 101 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 187:0387e8f68319 102 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 187:0387e8f68319 103 * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S)
AnnaBridge 187:0387e8f68319 104 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 105 * | | |0 = PERIOD will load to PBUF at the end point of each period
AnnaBridge 187:0387e8f68319 106 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
AnnaBridge 187:0387e8f68319 107 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
AnnaBridge 187:0387e8f68319 108 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid.
AnnaBridge 187:0387e8f68319 109 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect)
AnnaBridge 187:0387e8f68319 110 * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode.
AnnaBridge 187:0387e8f68319 111 * | | |0 = ICE debug mode counter halt Disable.
AnnaBridge 187:0387e8f68319 112 * | | |1 = ICE debug mode counter halt Enable.
AnnaBridge 187:0387e8f68319 113 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 187:0387e8f68319 114 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect)
AnnaBridge 187:0387e8f68319 115 * | | |0 = ICE debug mode acknowledgement effects BPWM output.
AnnaBridge 187:0387e8f68319 116 * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged.
AnnaBridge 187:0387e8f68319 117 * | | |1 = ICE debug mode acknowledgement Disabled.
AnnaBridge 187:0387e8f68319 118 * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not.
AnnaBridge 187:0387e8f68319 119 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register.
AnnaBridge 187:0387e8f68319 120 * @var BPWM_T::CTL1
AnnaBridge 187:0387e8f68319 121 * Offset: 0x04 BPWM Control Register 1
AnnaBridge 187:0387e8f68319 122 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 123 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 124 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 125 * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0
AnnaBridge 187:0387e8f68319 126 * | | |Each bit n controls corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 127 * | | |00 = Up counter type (supports in capture mode).
AnnaBridge 187:0387e8f68319 128 * | | |01 = Down count type (supports in capture mode).
AnnaBridge 187:0387e8f68319 129 * | | |10 = Up-down counter type.
AnnaBridge 187:0387e8f68319 130 * | | |11 = Reserved.
AnnaBridge 187:0387e8f68319 131 * @var BPWM_T::CLKSRC
AnnaBridge 187:0387e8f68319 132 * Offset: 0x10 BPWM Clock Source Register
AnnaBridge 187:0387e8f68319 133 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 134 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 135 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 136 * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select
AnnaBridge 187:0387e8f68319 137 * | | |000 = BPWMx_CLK, x denotes 0 or 1.
AnnaBridge 187:0387e8f68319 138 * | | |001 = TIMER0 overflow.
AnnaBridge 187:0387e8f68319 139 * | | |010 = TIMER1 overflow.
AnnaBridge 187:0387e8f68319 140 * | | |011 = TIMER2 overflow.
AnnaBridge 187:0387e8f68319 141 * | | |100 = TIMER3 overflow.
AnnaBridge 187:0387e8f68319 142 * | | |Others = Reserved.
AnnaBridge 187:0387e8f68319 143 * @var BPWM_T::CLKPSC
AnnaBridge 187:0387e8f68319 144 * Offset: 0x14 BPWM Clock Prescale Register
AnnaBridge 187:0387e8f68319 145 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 146 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 147 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 148 * |[11:0] |CLKPSC |BPWM Counter Clock Prescale
AnnaBridge 187:0387e8f68319 149 * | | |The clock of BPWM counter is decided by clock prescaler
AnnaBridge 187:0387e8f68319 150 * | | |Each BPWM pair share one BPWM counter clock prescaler
AnnaBridge 187:0387e8f68319 151 * | | |The clock of BPWM counter is divided by (CLKPSC+ 1)
AnnaBridge 187:0387e8f68319 152 * @var BPWM_T::CNTEN
AnnaBridge 187:0387e8f68319 153 * Offset: 0x20 BPWM Counter Enable Register
AnnaBridge 187:0387e8f68319 154 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 155 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 156 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 157 * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit
AnnaBridge 187:0387e8f68319 158 * | | |0 = BPWM Counter and clock prescaler stop running.
AnnaBridge 187:0387e8f68319 159 * | | |1 = BPWM Counter and clock prescaler start running.
AnnaBridge 187:0387e8f68319 160 * @var BPWM_T::CNTCLR
AnnaBridge 187:0387e8f68319 161 * Offset: 0x24 BPWM Clear Counter Register
AnnaBridge 187:0387e8f68319 162 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 163 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 164 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 165 * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0
AnnaBridge 187:0387e8f68319 166 * | | |It is automatically cleared by hardware.
AnnaBridge 187:0387e8f68319 167 * | | |0 = No effect.
AnnaBridge 187:0387e8f68319 168 * | | |1 = Clear 16-bit BPWM counter to 0000H.
AnnaBridge 187:0387e8f68319 169 * @var BPWM_T::PERIOD
AnnaBridge 187:0387e8f68319 170 * Offset: 0x30 BPWM Period Register
AnnaBridge 187:0387e8f68319 171 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 172 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 173 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 174 * |[15:0] |PERIOD |BPWM Period Register
AnnaBridge 187:0387e8f68319 175 * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0.
AnnaBridge 187:0387e8f68319 176 * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD.
AnnaBridge 187:0387e8f68319 177 * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period.
AnnaBridge 187:0387e8f68319 178 * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
AnnaBridge 187:0387e8f68319 179 * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period.
AnnaBridge 187:0387e8f68319 180 * @var BPWM_T::CMPDAT[6]
AnnaBridge 187:0387e8f68319 181 * Offset: 0x50 BPWM Comparator Register 0~5
AnnaBridge 187:0387e8f68319 182 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 183 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 184 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 185 * |[15:0] |CMPDAT |BPWM Comparator Register
AnnaBridge 187:0387e8f68319 186 * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC.
AnnaBridge 187:0387e8f68319 187 * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point.
AnnaBridge 187:0387e8f68319 188 * @var BPWM_T::CNT
AnnaBridge 187:0387e8f68319 189 * Offset: 0x90 BPWM Counter Register
AnnaBridge 187:0387e8f68319 190 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 191 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 192 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 193 * |[15:0] |CNT |BPWM Data Register (Read Only)
AnnaBridge 187:0387e8f68319 194 * | | |User can monitor CNTR to know the current value in 16-bit period counter.
AnnaBridge 187:0387e8f68319 195 * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only)
AnnaBridge 187:0387e8f68319 196 * | | |0 = Counter is Down count.
AnnaBridge 187:0387e8f68319 197 * | | |1 = Counter is UP count.
AnnaBridge 187:0387e8f68319 198 * @var BPWM_T::WGCTL0
AnnaBridge 187:0387e8f68319 199 * Offset: 0xB0 BPWM Generation Register 0
AnnaBridge 187:0387e8f68319 200 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 201 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 202 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 203 * |[1:0] |ZPCTL0 |BPWM Zero Point Control
AnnaBridge 187:0387e8f68319 204 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 205 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 206 * | | |01 = BPWM zero point output Low.
AnnaBridge 187:0387e8f68319 207 * | | |10 = BPWM zero point output High.
AnnaBridge 187:0387e8f68319 208 * | | |11 = BPWM zero point output Toggle.
AnnaBridge 187:0387e8f68319 209 * | | |BPWM can control output level when BPWM counter count to zero.
AnnaBridge 187:0387e8f68319 210 * |[3:2] |ZPCTL1 |BPWM Zero Point Control
AnnaBridge 187:0387e8f68319 211 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 212 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 213 * | | |01 = BPWM zero point output Low.
AnnaBridge 187:0387e8f68319 214 * | | |10 = BPWM zero point output High.
AnnaBridge 187:0387e8f68319 215 * | | |11 = BPWM zero point output Toggle.
AnnaBridge 187:0387e8f68319 216 * | | |BPWM can control output level when BPWM counter count to zero.
AnnaBridge 187:0387e8f68319 217 * |[5:4] |ZPCTL2 |BPWM Zero Point Control
AnnaBridge 187:0387e8f68319 218 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 219 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 220 * | | |01 = BPWM zero point output Low.
AnnaBridge 187:0387e8f68319 221 * | | |10 = BPWM zero point output High.
AnnaBridge 187:0387e8f68319 222 * | | |11 = BPWM zero point output Toggle.
AnnaBridge 187:0387e8f68319 223 * | | |BPWM can control output level when BPWM counter count to zero.
AnnaBridge 187:0387e8f68319 224 * |[7:6] |ZPCTL3 |BPWM Zero Point Control
AnnaBridge 187:0387e8f68319 225 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 226 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 227 * | | |01 = BPWM zero point output Low.
AnnaBridge 187:0387e8f68319 228 * | | |10 = BPWM zero point output High.
AnnaBridge 187:0387e8f68319 229 * | | |11 = BPWM zero point output Toggle.
AnnaBridge 187:0387e8f68319 230 * | | |BPWM can control output level when BPWM counter count to zero.
AnnaBridge 187:0387e8f68319 231 * |[9:8] |ZPCTL4 |BPWM Zero Point Control
AnnaBridge 187:0387e8f68319 232 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 233 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 234 * | | |01 = BPWM zero point output Low.
AnnaBridge 187:0387e8f68319 235 * | | |10 = BPWM zero point output High.
AnnaBridge 187:0387e8f68319 236 * | | |11 = BPWM zero point output Toggle.
AnnaBridge 187:0387e8f68319 237 * | | |BPWM can control output level when BPWM counter count to zero.
AnnaBridge 187:0387e8f68319 238 * |[11:10] |ZPCTL5 |BPWM Zero Point Control
AnnaBridge 187:0387e8f68319 239 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 240 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 241 * | | |01 = BPWM zero point output Low.
AnnaBridge 187:0387e8f68319 242 * | | |10 = BPWM zero point output High.
AnnaBridge 187:0387e8f68319 243 * | | |11 = BPWM zero point output Toggle.
AnnaBridge 187:0387e8f68319 244 * | | |BPWM can control output level when BPWM counter count to zero.
AnnaBridge 187:0387e8f68319 245 * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control
AnnaBridge 187:0387e8f68319 246 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 247 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 248 * | | |01 = BPWM period (center) point output Low.
AnnaBridge 187:0387e8f68319 249 * | | |10 = BPWM period (center) point output High.
AnnaBridge 187:0387e8f68319 250 * | | |11 = BPWM period (center) point output Toggle.
AnnaBridge 187:0387e8f68319 251 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
AnnaBridge 187:0387e8f68319 252 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
AnnaBridge 187:0387e8f68319 253 * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control
AnnaBridge 187:0387e8f68319 254 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 255 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 256 * | | |01 = BPWM period (center) point output Low.
AnnaBridge 187:0387e8f68319 257 * | | |10 = BPWM period (center) point output High.
AnnaBridge 187:0387e8f68319 258 * | | |11 = BPWM period (center) point output Toggle.
AnnaBridge 187:0387e8f68319 259 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
AnnaBridge 187:0387e8f68319 260 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
AnnaBridge 187:0387e8f68319 261 * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control
AnnaBridge 187:0387e8f68319 262 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 263 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 264 * | | |01 = BPWM period (center) point output Low.
AnnaBridge 187:0387e8f68319 265 * | | |10 = BPWM period (center) point output High.
AnnaBridge 187:0387e8f68319 266 * | | |11 = BPWM period (center) point output Toggle.
AnnaBridge 187:0387e8f68319 267 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
AnnaBridge 187:0387e8f68319 268 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
AnnaBridge 187:0387e8f68319 269 * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control
AnnaBridge 187:0387e8f68319 270 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 271 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 272 * | | |01 = BPWM period (center) point output Low.
AnnaBridge 187:0387e8f68319 273 * | | |10 = BPWM period (center) point output High.
AnnaBridge 187:0387e8f68319 274 * | | |11 = BPWM period (center) point output Toggle.
AnnaBridge 187:0387e8f68319 275 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
AnnaBridge 187:0387e8f68319 276 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
AnnaBridge 187:0387e8f68319 277 * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control
AnnaBridge 187:0387e8f68319 278 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 279 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 280 * | | |01 = BPWM period (center) point output Low.
AnnaBridge 187:0387e8f68319 281 * | | |10 = BPWM period (center) point output High.
AnnaBridge 187:0387e8f68319 282 * | | |11 = BPWM period (center) point output Toggle.
AnnaBridge 187:0387e8f68319 283 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
AnnaBridge 187:0387e8f68319 284 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
AnnaBridge 187:0387e8f68319 285 * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control
AnnaBridge 187:0387e8f68319 286 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 287 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 288 * | | |01 = BPWM period (center) point output Low.
AnnaBridge 187:0387e8f68319 289 * | | |10 = BPWM period (center) point output High.
AnnaBridge 187:0387e8f68319 290 * | | |11 = BPWM period (center) point output Toggle.
AnnaBridge 187:0387e8f68319 291 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1).
AnnaBridge 187:0387e8f68319 292 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type.
AnnaBridge 187:0387e8f68319 293 * @var BPWM_T::WGCTL1
AnnaBridge 187:0387e8f68319 294 * Offset: 0xB4 BPWM Generation Register 1
AnnaBridge 187:0387e8f68319 295 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 296 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 297 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 298 * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control
AnnaBridge 187:0387e8f68319 299 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 300 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 301 * | | |01 = BPWM compare up point output Low.
AnnaBridge 187:0387e8f68319 302 * | | |10 = BPWM compare up point output High.
AnnaBridge 187:0387e8f68319 303 * | | |11 = BPWM compare up point output Toggle.
AnnaBridge 187:0387e8f68319 304 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
AnnaBridge 187:0387e8f68319 305 * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control
AnnaBridge 187:0387e8f68319 306 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 307 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 308 * | | |01 = BPWM compare up point output Low.
AnnaBridge 187:0387e8f68319 309 * | | |10 = BPWM compare up point output High.
AnnaBridge 187:0387e8f68319 310 * | | |11 = BPWM compare up point output Toggle.
AnnaBridge 187:0387e8f68319 311 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
AnnaBridge 187:0387e8f68319 312 * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control
AnnaBridge 187:0387e8f68319 313 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 314 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 315 * | | |01 = BPWM compare up point output Low.
AnnaBridge 187:0387e8f68319 316 * | | |10 = BPWM compare up point output High.
AnnaBridge 187:0387e8f68319 317 * | | |11 = BPWM compare up point output Toggle.
AnnaBridge 187:0387e8f68319 318 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
AnnaBridge 187:0387e8f68319 319 * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control
AnnaBridge 187:0387e8f68319 320 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 321 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 322 * | | |01 = BPWM compare up point output Low.
AnnaBridge 187:0387e8f68319 323 * | | |10 = BPWM compare up point output High.
AnnaBridge 187:0387e8f68319 324 * | | |11 = BPWM compare up point output Toggle.
AnnaBridge 187:0387e8f68319 325 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
AnnaBridge 187:0387e8f68319 326 * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control
AnnaBridge 187:0387e8f68319 327 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 328 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 329 * | | |01 = BPWM compare up point output Low.
AnnaBridge 187:0387e8f68319 330 * | | |10 = BPWM compare up point output High.
AnnaBridge 187:0387e8f68319 331 * | | |11 = BPWM compare up point output Toggle.
AnnaBridge 187:0387e8f68319 332 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
AnnaBridge 187:0387e8f68319 333 * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control
AnnaBridge 187:0387e8f68319 334 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 335 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 336 * | | |01 = BPWM compare up point output Low.
AnnaBridge 187:0387e8f68319 337 * | | |10 = BPWM compare up point output High.
AnnaBridge 187:0387e8f68319 338 * | | |11 = BPWM compare up point output Toggle.
AnnaBridge 187:0387e8f68319 339 * | | |BPWM can control output level when BPWM counter up count to CMPDAT.
AnnaBridge 187:0387e8f68319 340 * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control
AnnaBridge 187:0387e8f68319 341 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 342 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 343 * | | |01 = BPWM compare down point output Low.
AnnaBridge 187:0387e8f68319 344 * | | |10 = BPWM compare down point output High.
AnnaBridge 187:0387e8f68319 345 * | | |11 = BPWM compare down point output Toggle.
AnnaBridge 187:0387e8f68319 346 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
AnnaBridge 187:0387e8f68319 347 * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control
AnnaBridge 187:0387e8f68319 348 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 349 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 350 * | | |01 = BPWM compare down point output Low.
AnnaBridge 187:0387e8f68319 351 * | | |10 = BPWM compare down point output High.
AnnaBridge 187:0387e8f68319 352 * | | |11 = BPWM compare down point output Toggle.
AnnaBridge 187:0387e8f68319 353 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
AnnaBridge 187:0387e8f68319 354 * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control
AnnaBridge 187:0387e8f68319 355 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 356 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 357 * | | |01 = BPWM compare down point output Low.
AnnaBridge 187:0387e8f68319 358 * | | |10 = BPWM compare down point output High.
AnnaBridge 187:0387e8f68319 359 * | | |11 = BPWM compare down point output Toggle.
AnnaBridge 187:0387e8f68319 360 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
AnnaBridge 187:0387e8f68319 361 * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control
AnnaBridge 187:0387e8f68319 362 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 363 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 364 * | | |01 = BPWM compare down point output Low.
AnnaBridge 187:0387e8f68319 365 * | | |10 = BPWM compare down point output High.
AnnaBridge 187:0387e8f68319 366 * | | |11 = BPWM compare down point output Toggle.
AnnaBridge 187:0387e8f68319 367 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
AnnaBridge 187:0387e8f68319 368 * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control
AnnaBridge 187:0387e8f68319 369 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 370 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 371 * | | |01 = BPWM compare down point output Low.
AnnaBridge 187:0387e8f68319 372 * | | |10 = BPWM compare down point output High.
AnnaBridge 187:0387e8f68319 373 * | | |11 = BPWM compare down point output Toggle.
AnnaBridge 187:0387e8f68319 374 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
AnnaBridge 187:0387e8f68319 375 * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control
AnnaBridge 187:0387e8f68319 376 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 377 * | | |00 = Do nothing.
AnnaBridge 187:0387e8f68319 378 * | | |01 = BPWM compare down point output Low.
AnnaBridge 187:0387e8f68319 379 * | | |10 = BPWM compare down point output High.
AnnaBridge 187:0387e8f68319 380 * | | |11 = BPWM compare down point output Toggle.
AnnaBridge 187:0387e8f68319 381 * | | |BPWM can control output level when BPWM counter down count to CMPDAT.
AnnaBridge 187:0387e8f68319 382 * @var BPWM_T::MSKEN
AnnaBridge 187:0387e8f68319 383 * Offset: 0xB8 BPWM Mask Enable Register
AnnaBridge 187:0387e8f68319 384 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 385 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 386 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 387 * |[0] |MSKEN0 |BPWM Mask Enable Bits
AnnaBridge 187:0387e8f68319 388 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 389 * | | |The BPWM output signal will be masked when this bit is enabled
AnnaBridge 187:0387e8f68319 390 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
AnnaBridge 187:0387e8f68319 391 * | | |0 = BPWM output signal is non-masked.
AnnaBridge 187:0387e8f68319 392 * | | |1 = BPWM output signal is masked and output MSKDATn data.
AnnaBridge 187:0387e8f68319 393 * |[1] |MSKEN1 |BPWM Mask Enable Bits
AnnaBridge 187:0387e8f68319 394 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 395 * | | |The BPWM output signal will be masked when this bit is enabled
AnnaBridge 187:0387e8f68319 396 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
AnnaBridge 187:0387e8f68319 397 * | | |0 = BPWM output signal is non-masked.
AnnaBridge 187:0387e8f68319 398 * | | |1 = BPWM output signal is masked and output MSKDATn data.
AnnaBridge 187:0387e8f68319 399 * |[2] |MSKEN2 |BPWM Mask Enable Bits
AnnaBridge 187:0387e8f68319 400 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 401 * | | |The BPWM output signal will be masked when this bit is enabled
AnnaBridge 187:0387e8f68319 402 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
AnnaBridge 187:0387e8f68319 403 * | | |0 = BPWM output signal is non-masked.
AnnaBridge 187:0387e8f68319 404 * | | |1 = BPWM output signal is masked and output MSKDATn data.
AnnaBridge 187:0387e8f68319 405 * |[3] |MSKEN3 |BPWM Mask Enable Bits
AnnaBridge 187:0387e8f68319 406 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 407 * | | |The BPWM output signal will be masked when this bit is enabled
AnnaBridge 187:0387e8f68319 408 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
AnnaBridge 187:0387e8f68319 409 * | | |0 = BPWM output signal is non-masked.
AnnaBridge 187:0387e8f68319 410 * | | |1 = BPWM output signal is masked and output MSKDATn data.
AnnaBridge 187:0387e8f68319 411 * |[4] |MSKEN4 |BPWM Mask Enable Bits
AnnaBridge 187:0387e8f68319 412 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 413 * | | |The BPWM output signal will be masked when this bit is enabled
AnnaBridge 187:0387e8f68319 414 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
AnnaBridge 187:0387e8f68319 415 * | | |0 = BPWM output signal is non-masked.
AnnaBridge 187:0387e8f68319 416 * | | |1 = BPWM output signal is masked and output MSKDATn data.
AnnaBridge 187:0387e8f68319 417 * |[5] |MSKEN5 |BPWM Mask Enable Bits
AnnaBridge 187:0387e8f68319 418 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 419 * | | |The BPWM output signal will be masked when this bit is enabled
AnnaBridge 187:0387e8f68319 420 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data.
AnnaBridge 187:0387e8f68319 421 * | | |0 = BPWM output signal is non-masked.
AnnaBridge 187:0387e8f68319 422 * | | |1 = BPWM output signal is masked and output MSKDATn data.
AnnaBridge 187:0387e8f68319 423 * @var BPWM_T::MSK
AnnaBridge 187:0387e8f68319 424 * Offset: 0xBC BPWM Mask Data Register
AnnaBridge 187:0387e8f68319 425 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 426 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 427 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 428 * |[0] |MSKDAT0 |BPWM Mask Data Bit
AnnaBridge 187:0387e8f68319 429 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
AnnaBridge 187:0387e8f68319 430 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 431 * | | |0 = Output logic low to BPWMn.
AnnaBridge 187:0387e8f68319 432 * | | |1 = Output logic high to BPWMn.
AnnaBridge 187:0387e8f68319 433 * |[1] |MSKDAT1 |BPWM Mask Data Bit
AnnaBridge 187:0387e8f68319 434 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
AnnaBridge 187:0387e8f68319 435 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 436 * | | |0 = Output logic low to BPWMn.
AnnaBridge 187:0387e8f68319 437 * | | |1 = Output logic high to BPWMn.
AnnaBridge 187:0387e8f68319 438 * |[2] |MSKDAT2 |BPWM Mask Data Bit
AnnaBridge 187:0387e8f68319 439 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
AnnaBridge 187:0387e8f68319 440 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 441 * | | |0 = Output logic low to BPWMn.
AnnaBridge 187:0387e8f68319 442 * | | |1 = Output logic high to BPWMn.
AnnaBridge 187:0387e8f68319 443 * |[3] |MSKDAT3 |BPWM Mask Data Bit
AnnaBridge 187:0387e8f68319 444 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
AnnaBridge 187:0387e8f68319 445 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 446 * | | |0 = Output logic low to BPWMn.
AnnaBridge 187:0387e8f68319 447 * | | |1 = Output logic high to BPWMn.
AnnaBridge 187:0387e8f68319 448 * |[4] |MSKDAT4 |BPWM Mask Data Bit
AnnaBridge 187:0387e8f68319 449 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
AnnaBridge 187:0387e8f68319 450 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 451 * | | |0 = Output logic low to BPWMn.
AnnaBridge 187:0387e8f68319 452 * | | |1 = Output logic high to BPWMn.
AnnaBridge 187:0387e8f68319 453 * |[5] |MSKDAT5 |BPWM Mask Data Bit
AnnaBridge 187:0387e8f68319 454 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled
AnnaBridge 187:0387e8f68319 455 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 456 * | | |0 = Output logic low to BPWMn.
AnnaBridge 187:0387e8f68319 457 * | | |1 = Output logic high to BPWMn.
AnnaBridge 187:0387e8f68319 458 * @var BPWM_T::POLCTL
AnnaBridge 187:0387e8f68319 459 * Offset: 0xD4 BPWM Pin Polar Inverse Register
AnnaBridge 187:0387e8f68319 460 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 461 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 462 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 463 * |[0] |PINV0 |BPWM PIN Polar Inverse Control
AnnaBridge 187:0387e8f68319 464 * | | |The register controls polarity state of BPWM output
AnnaBridge 187:0387e8f68319 465 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 466 * | | |0 = BPWM output polar inverse Disabled.
AnnaBridge 187:0387e8f68319 467 * | | |1 = BPWM output polar inverse Enabled.
AnnaBridge 187:0387e8f68319 468 * |[1] |PINV1 |BPWM PIN Polar Inverse Control
AnnaBridge 187:0387e8f68319 469 * | | |The register controls polarity state of BPWM output
AnnaBridge 187:0387e8f68319 470 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 471 * | | |0 = BPWM output polar inverse Disabled.
AnnaBridge 187:0387e8f68319 472 * | | |1 = BPWM output polar inverse Enabled.
AnnaBridge 187:0387e8f68319 473 * |[2] |PINV2 |BPWM PIN Polar Inverse Control
AnnaBridge 187:0387e8f68319 474 * | | |The register controls polarity state of BPWM output
AnnaBridge 187:0387e8f68319 475 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 476 * | | |0 = BPWM output polar inverse Disabled.
AnnaBridge 187:0387e8f68319 477 * | | |1 = BPWM output polar inverse Enabled.
AnnaBridge 187:0387e8f68319 478 * |[3] |PINV3 |BPWM PIN Polar Inverse Control
AnnaBridge 187:0387e8f68319 479 * | | |The register controls polarity state of BPWM output
AnnaBridge 187:0387e8f68319 480 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 481 * | | |0 = BPWM output polar inverse Disabled.
AnnaBridge 187:0387e8f68319 482 * | | |1 = BPWM output polar inverse Enabled.
AnnaBridge 187:0387e8f68319 483 * |[4] |PINV4 |BPWM PIN Polar Inverse Control
AnnaBridge 187:0387e8f68319 484 * | | |The register controls polarity state of BPWM output
AnnaBridge 187:0387e8f68319 485 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 486 * | | |0 = BPWM output polar inverse Disabled.
AnnaBridge 187:0387e8f68319 487 * | | |1 = BPWM output polar inverse Enabled.
AnnaBridge 187:0387e8f68319 488 * |[5] |PINV5 |BPWM PIN Polar Inverse Control
AnnaBridge 187:0387e8f68319 489 * | | |The register controls polarity state of BPWM output
AnnaBridge 187:0387e8f68319 490 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 491 * | | |0 = BPWM output polar inverse Disabled.
AnnaBridge 187:0387e8f68319 492 * | | |1 = BPWM output polar inverse Enabled.
AnnaBridge 187:0387e8f68319 493 * @var BPWM_T::POEN
AnnaBridge 187:0387e8f68319 494 * Offset: 0xD8 BPWM Output Enable Register
AnnaBridge 187:0387e8f68319 495 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 496 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 497 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 498 * |[0] |POEN0 |BPWM Pin Output Enable Bits
AnnaBridge 187:0387e8f68319 499 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 500 * | | |0 = BPWM pin at tri-state.
AnnaBridge 187:0387e8f68319 501 * | | |1 = BPWM pin in output mode.
AnnaBridge 187:0387e8f68319 502 * |[1] |POEN1 |BPWM Pin Output Enable Bits
AnnaBridge 187:0387e8f68319 503 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 504 * | | |0 = BPWM pin at tri-state.
AnnaBridge 187:0387e8f68319 505 * | | |1 = BPWM pin in output mode.
AnnaBridge 187:0387e8f68319 506 * |[2] |POEN2 |BPWM Pin Output Enable Bits
AnnaBridge 187:0387e8f68319 507 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 508 * | | |0 = BPWM pin at tri-state.
AnnaBridge 187:0387e8f68319 509 * | | |1 = BPWM pin in output mode.
AnnaBridge 187:0387e8f68319 510 * |[3] |POEN3 |BPWM Pin Output Enable Bits
AnnaBridge 187:0387e8f68319 511 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 512 * | | |0 = BPWM pin at tri-state.
AnnaBridge 187:0387e8f68319 513 * | | |1 = BPWM pin in output mode.
AnnaBridge 187:0387e8f68319 514 * |[4] |POEN4 |BPWM Pin Output Enable Bits
AnnaBridge 187:0387e8f68319 515 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 516 * | | |0 = BPWM pin at tri-state.
AnnaBridge 187:0387e8f68319 517 * | | |1 = BPWM pin in output mode.
AnnaBridge 187:0387e8f68319 518 * |[5] |POEN5 |BPWM Pin Output Enable Bits
AnnaBridge 187:0387e8f68319 519 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 520 * | | |0 = BPWM pin at tri-state.
AnnaBridge 187:0387e8f68319 521 * | | |1 = BPWM pin in output mode.
AnnaBridge 187:0387e8f68319 522 * @var BPWM_T::INTEN
AnnaBridge 187:0387e8f68319 523 * Offset: 0xE0 BPWM Interrupt Enable Register
AnnaBridge 187:0387e8f68319 524 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 525 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 526 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 527 * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit
AnnaBridge 187:0387e8f68319 528 * | | |0 = Zero point interrupt Disabled.
AnnaBridge 187:0387e8f68319 529 * | | |1 = Zero point interrupt Enabled.
AnnaBridge 187:0387e8f68319 530 * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit
AnnaBridge 187:0387e8f68319 531 * | | |0 = Period point interrupt Disabled.
AnnaBridge 187:0387e8f68319 532 * | | |1 = Period point interrupt Enabled.
AnnaBridge 187:0387e8f68319 533 * | | |Note: When up-down counter type period point means center point.
AnnaBridge 187:0387e8f68319 534 * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 535 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 536 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 187:0387e8f68319 537 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 187:0387e8f68319 538 * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 539 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 540 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 187:0387e8f68319 541 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 187:0387e8f68319 542 * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 543 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 544 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 187:0387e8f68319 545 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 187:0387e8f68319 546 * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 547 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 548 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 187:0387e8f68319 549 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 187:0387e8f68319 550 * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 551 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 552 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 187:0387e8f68319 553 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 187:0387e8f68319 554 * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 555 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 556 * | | |0 = Compare up count interrupt Disabled.
AnnaBridge 187:0387e8f68319 557 * | | |1 = Compare up count interrupt Enabled.
AnnaBridge 187:0387e8f68319 558 * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 559 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 560 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 187:0387e8f68319 561 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 187:0387e8f68319 562 * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 563 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 564 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 187:0387e8f68319 565 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 187:0387e8f68319 566 * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 567 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 568 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 187:0387e8f68319 569 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 187:0387e8f68319 570 * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 571 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 572 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 187:0387e8f68319 573 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 187:0387e8f68319 574 * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 575 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 576 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 187:0387e8f68319 577 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 187:0387e8f68319 578 * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 579 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 580 * | | |0 = Compare down count interrupt Disabled.
AnnaBridge 187:0387e8f68319 581 * | | |1 = Compare down count interrupt Enabled.
AnnaBridge 187:0387e8f68319 582 * @var BPWM_T::INTSTS
AnnaBridge 187:0387e8f68319 583 * Offset: 0xE8 BPWM Interrupt Flag Register
AnnaBridge 187:0387e8f68319 584 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 585 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 586 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 587 * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0
AnnaBridge 187:0387e8f68319 588 * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero.
AnnaBridge 187:0387e8f68319 589 * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0
AnnaBridge 187:0387e8f68319 590 * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero.
AnnaBridge 187:0387e8f68319 591 * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag
AnnaBridge 187:0387e8f68319 592 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
AnnaBridge 187:0387e8f68319 593 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 594 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 187:0387e8f68319 595 * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag
AnnaBridge 187:0387e8f68319 596 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
AnnaBridge 187:0387e8f68319 597 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 598 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 187:0387e8f68319 599 * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag
AnnaBridge 187:0387e8f68319 600 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
AnnaBridge 187:0387e8f68319 601 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 602 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 187:0387e8f68319 603 * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag
AnnaBridge 187:0387e8f68319 604 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
AnnaBridge 187:0387e8f68319 605 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 606 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 187:0387e8f68319 607 * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag
AnnaBridge 187:0387e8f68319 608 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
AnnaBridge 187:0387e8f68319 609 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 610 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 187:0387e8f68319 611 * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag
AnnaBridge 187:0387e8f68319 612 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it
AnnaBridge 187:0387e8f68319 613 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 614 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
AnnaBridge 187:0387e8f68319 615 * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag
AnnaBridge 187:0387e8f68319 616 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 617 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 187:0387e8f68319 618 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 187:0387e8f68319 619 * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag
AnnaBridge 187:0387e8f68319 620 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 621 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 187:0387e8f68319 622 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 187:0387e8f68319 623 * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag
AnnaBridge 187:0387e8f68319 624 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 625 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 187:0387e8f68319 626 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 187:0387e8f68319 627 * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag
AnnaBridge 187:0387e8f68319 628 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 629 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 187:0387e8f68319 630 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 187:0387e8f68319 631 * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag
AnnaBridge 187:0387e8f68319 632 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 633 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 187:0387e8f68319 634 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 187:0387e8f68319 635 * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag
AnnaBridge 187:0387e8f68319 636 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 637 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it.
AnnaBridge 187:0387e8f68319 638 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
AnnaBridge 187:0387e8f68319 639 * @var BPWM_T::EADCTS0
AnnaBridge 187:0387e8f68319 640 * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0
AnnaBridge 187:0387e8f68319 641 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 642 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 643 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 644 * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select
AnnaBridge 187:0387e8f68319 645 * | | |0000 = BPWM_CH0 zero point.
AnnaBridge 187:0387e8f68319 646 * | | |0001 = BPWM_CH0 period point.
AnnaBridge 187:0387e8f68319 647 * | | |0010 = BPWM_CH0 zero or period point.
AnnaBridge 187:0387e8f68319 648 * | | |0011 = BPWM_CH0 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 649 * | | |0100 = BPWM_CH0 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 650 * | | |0101 = Reserved.
AnnaBridge 187:0387e8f68319 651 * | | |0110 = Reserved.
AnnaBridge 187:0387e8f68319 652 * | | |0111 = Reserved.
AnnaBridge 187:0387e8f68319 653 * | | |1000 = BPWM_CH1 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 654 * | | |1001 = BPWM_CH1 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 655 * | | |Others reserved
AnnaBridge 187:0387e8f68319 656 * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit
AnnaBridge 187:0387e8f68319 657 * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select
AnnaBridge 187:0387e8f68319 658 * | | |0000 = BPWM_CH0 zero point.
AnnaBridge 187:0387e8f68319 659 * | | |0001 = BPWM_CH0 period point.
AnnaBridge 187:0387e8f68319 660 * | | |0010 = BPWM_CH0 zero or period point.
AnnaBridge 187:0387e8f68319 661 * | | |0011 = BPWM_CH0 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 662 * | | |0100 = BPWM_CH0 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 663 * | | |0101 = Reserved.
AnnaBridge 187:0387e8f68319 664 * | | |0110 = Reserved.
AnnaBridge 187:0387e8f68319 665 * | | |0111 = Reserved.
AnnaBridge 187:0387e8f68319 666 * | | |1000 = BPWM_CH1 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 667 * | | |1001 = BPWM_CH1 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 668 * | | |Others reserved
AnnaBridge 187:0387e8f68319 669 * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit
AnnaBridge 187:0387e8f68319 670 * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select
AnnaBridge 187:0387e8f68319 671 * | | |0000 = BPWM_CH2 zero point.
AnnaBridge 187:0387e8f68319 672 * | | |0001 = BPWM_CH2 period point.
AnnaBridge 187:0387e8f68319 673 * | | |0010 = BPWM_CH2 zero or period point.
AnnaBridge 187:0387e8f68319 674 * | | |0011 = BPWM_CH2 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 675 * | | |0100 = BPWM_CH2 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 676 * | | |0101 = Reserved.
AnnaBridge 187:0387e8f68319 677 * | | |0110 = Reserved.
AnnaBridge 187:0387e8f68319 678 * | | |0111 = Reserved.
AnnaBridge 187:0387e8f68319 679 * | | |1000 = BPWM_CH3 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 680 * | | |1001 = BPWM_CH3 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 681 * | | |Others reserved
AnnaBridge 187:0387e8f68319 682 * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit
AnnaBridge 187:0387e8f68319 683 * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select
AnnaBridge 187:0387e8f68319 684 * | | |0000 = BPWM_CH2 zero point.
AnnaBridge 187:0387e8f68319 685 * | | |0001 = BPWM_CH2 period point.
AnnaBridge 187:0387e8f68319 686 * | | |0010 = BPWM_CH2 zero or period point.
AnnaBridge 187:0387e8f68319 687 * | | |0011 = BPWM_CH2 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 688 * | | |0100 = BPWM_CH2 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 689 * | | |0101 = Reserved.
AnnaBridge 187:0387e8f68319 690 * | | |0110 = Reserved.
AnnaBridge 187:0387e8f68319 691 * | | |0111 = Reserved.
AnnaBridge 187:0387e8f68319 692 * | | |1000 = BPWM_CH3 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 693 * | | |1001 = BPWM_CH3 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 694 * | | |Others reserved.
AnnaBridge 187:0387e8f68319 695 * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit
AnnaBridge 187:0387e8f68319 696 * @var BPWM_T::EADCTS1
AnnaBridge 187:0387e8f68319 697 * Offset: 0xFC BPWM Trigger EADC Source Select Register 1
AnnaBridge 187:0387e8f68319 698 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 699 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 700 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 701 * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select
AnnaBridge 187:0387e8f68319 702 * | | |0000 = BPWM_CH4 zero point.
AnnaBridge 187:0387e8f68319 703 * | | |0001 = BPWM_CH4 period point.
AnnaBridge 187:0387e8f68319 704 * | | |0010 = BPWM_CH4 zero or period point.
AnnaBridge 187:0387e8f68319 705 * | | |0011 = BPWM_CH4 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 706 * | | |0100 = BPWM_CH4 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 707 * | | |0101 = Reserved.
AnnaBridge 187:0387e8f68319 708 * | | |0110 = Reserved.
AnnaBridge 187:0387e8f68319 709 * | | |0111 = Reserved.
AnnaBridge 187:0387e8f68319 710 * | | |1000 = BPWM_CH5 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 711 * | | |1001 = BPWM_CH5 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 712 * | | |Others reserved
AnnaBridge 187:0387e8f68319 713 * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit
AnnaBridge 187:0387e8f68319 714 * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select
AnnaBridge 187:0387e8f68319 715 * | | |0000 = BPWM_CH4 zero point.
AnnaBridge 187:0387e8f68319 716 * | | |0001 = BPWM_CH4 period point.
AnnaBridge 187:0387e8f68319 717 * | | |0010 = BPWM_CH4 zero or period point.
AnnaBridge 187:0387e8f68319 718 * | | |0011 = BPWM_CH4 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 719 * | | |0100 = BPWM_CH4 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 720 * | | |0101 = Reserved.
AnnaBridge 187:0387e8f68319 721 * | | |0110 = Reserved.
AnnaBridge 187:0387e8f68319 722 * | | |0111 = Reserved.
AnnaBridge 187:0387e8f68319 723 * | | |1000 = BPWM_CH5 up-count CMPDAT point.
AnnaBridge 187:0387e8f68319 724 * | | |1001 = BPWM_CH5 down-count CMPDAT point.
AnnaBridge 187:0387e8f68319 725 * | | |Others reserved
AnnaBridge 187:0387e8f68319 726 * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit
AnnaBridge 187:0387e8f68319 727 * @var BPWM_T::SSCTL
AnnaBridge 187:0387e8f68319 728 * Offset: 0x110 BPWM Synchronous Start Control Register
AnnaBridge 187:0387e8f68319 729 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 730 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 731 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 732 * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit
AnnaBridge 187:0387e8f68319 733 * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN).
AnnaBridge 187:0387e8f68319 734 * | | |0 = BPWM synchronous start function Disabled.
AnnaBridge 187:0387e8f68319 735 * | | |1 = BPWM synchronous start function Enabled.
AnnaBridge 187:0387e8f68319 736 * |[9:8] |SSRC |BPWM Synchronous Start Source Select
AnnaBridge 187:0387e8f68319 737 * | | |00 = Synchronous start source come from PWM0.
AnnaBridge 187:0387e8f68319 738 * | | |01 = Synchronous start source come from PWM1.
AnnaBridge 187:0387e8f68319 739 * | | |10 = Synchronous start source come from BPWM0.
AnnaBridge 187:0387e8f68319 740 * | | |11 = Synchronous start source come from BPWM1.
AnnaBridge 187:0387e8f68319 741 * @var BPWM_T::SSTRG
AnnaBridge 187:0387e8f68319 742 * Offset: 0x114 BPWM Synchronous Start Trigger Register
AnnaBridge 187:0387e8f68319 743 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 744 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 745 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 746 * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only)
AnnaBridge 187:0387e8f68319 747 * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time.
AnnaBridge 187:0387e8f68319 748 * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled.
AnnaBridge 187:0387e8f68319 749 * @var BPWM_T::STATUS
AnnaBridge 187:0387e8f68319 750 * Offset: 0x120 BPWM Status Register
AnnaBridge 187:0387e8f68319 751 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 752 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 753 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 754 * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status
AnnaBridge 187:0387e8f68319 755 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF.
AnnaBridge 187:0387e8f68319 756 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 757 * |[16] |EADCTRG0 |EADC Start of Conversion Status
AnnaBridge 187:0387e8f68319 758 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 759 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 187:0387e8f68319 760 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 761 * |[17] |EADCTRG1 |EADC Start of Conversion Status
AnnaBridge 187:0387e8f68319 762 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 763 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 187:0387e8f68319 764 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 765 * |[18] |EADCTRG2 |EADC Start of Conversion Status
AnnaBridge 187:0387e8f68319 766 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 767 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 187:0387e8f68319 768 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 769 * |[19] |EADCTRG3 |EADC Start of Conversion Status
AnnaBridge 187:0387e8f68319 770 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 771 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 187:0387e8f68319 772 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 773 * |[20] |EADCTRG4 |EADC Start of Conversion Status
AnnaBridge 187:0387e8f68319 774 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 775 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 187:0387e8f68319 776 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 777 * |[21] |EADCTRG5 |EADC Start of Conversion Status
AnnaBridge 187:0387e8f68319 778 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 779 * | | |0 = Indicates no EADC start of conversion trigger event has occurred.
AnnaBridge 187:0387e8f68319 780 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.
AnnaBridge 187:0387e8f68319 781 * @var BPWM_T::CAPINEN
AnnaBridge 187:0387e8f68319 782 * Offset: 0x200 BPWM Capture Input Enable Register
AnnaBridge 187:0387e8f68319 783 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 784 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 785 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 786 * |[0] |CAPINEN0 |Capture Input Enable Bits
AnnaBridge 187:0387e8f68319 787 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 788 * | | |0 = BPWM Channel capture input path Disabled
AnnaBridge 187:0387e8f68319 789 * | | |The input of BPWM channel capture function is always regarded as 0.
AnnaBridge 187:0387e8f68319 790 * | | |1 = BPWM Channel capture input path Enabled
AnnaBridge 187:0387e8f68319 791 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
AnnaBridge 187:0387e8f68319 792 * |[1] |CAPINEN1 |Capture Input Enable Bits
AnnaBridge 187:0387e8f68319 793 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 794 * | | |0 = BPWM Channel capture input path Disabled
AnnaBridge 187:0387e8f68319 795 * | | |The input of BPWM channel capture function is always regarded as 0.
AnnaBridge 187:0387e8f68319 796 * | | |1 = BPWM Channel capture input path Enabled
AnnaBridge 187:0387e8f68319 797 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
AnnaBridge 187:0387e8f68319 798 * |[2] |CAPINEN2 |Capture Input Enable Bits
AnnaBridge 187:0387e8f68319 799 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 800 * | | |0 = BPWM Channel capture input path Disabled
AnnaBridge 187:0387e8f68319 801 * | | |The input of BPWM channel capture function is always regarded as 0.
AnnaBridge 187:0387e8f68319 802 * | | |1 = BPWM Channel capture input path Enabled
AnnaBridge 187:0387e8f68319 803 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
AnnaBridge 187:0387e8f68319 804 * |[3] |CAPINEN3 |Capture Input Enable Bits
AnnaBridge 187:0387e8f68319 805 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 806 * | | |0 = BPWM Channel capture input path Disabled
AnnaBridge 187:0387e8f68319 807 * | | |The input of BPWM channel capture function is always regarded as 0.
AnnaBridge 187:0387e8f68319 808 * | | |1 = BPWM Channel capture input path Enabled
AnnaBridge 187:0387e8f68319 809 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
AnnaBridge 187:0387e8f68319 810 * |[4] |CAPINEN4 |Capture Input Enable Bits
AnnaBridge 187:0387e8f68319 811 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 812 * | | |0 = BPWM Channel capture input path Disabled
AnnaBridge 187:0387e8f68319 813 * | | |The input of BPWM channel capture function is always regarded as 0.
AnnaBridge 187:0387e8f68319 814 * | | |1 = BPWM Channel capture input path Enabled
AnnaBridge 187:0387e8f68319 815 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
AnnaBridge 187:0387e8f68319 816 * |[5] |CAPINEN5 |Capture Input Enable Bits
AnnaBridge 187:0387e8f68319 817 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 818 * | | |0 = BPWM Channel capture input path Disabled
AnnaBridge 187:0387e8f68319 819 * | | |The input of BPWM channel capture function is always regarded as 0.
AnnaBridge 187:0387e8f68319 820 * | | |1 = BPWM Channel capture input path Enabled
AnnaBridge 187:0387e8f68319 821 * | | |The input of BPWM channel capture function comes from correlative multifunction pin.
AnnaBridge 187:0387e8f68319 822 * @var BPWM_T::CAPCTL
AnnaBridge 187:0387e8f68319 823 * Offset: 0x204 BPWM Capture Control Register
AnnaBridge 187:0387e8f68319 824 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 825 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 826 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 827 * |[0] |CAPEN0 |Capture Function Enable Bits
AnnaBridge 187:0387e8f68319 828 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 829 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 187:0387e8f68319 830 * | | |1 = Capture function Enabled
AnnaBridge 187:0387e8f68319 831 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 187:0387e8f68319 832 * |[1] |CAPEN1 |Capture Function Enable Bits
AnnaBridge 187:0387e8f68319 833 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 834 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 187:0387e8f68319 835 * | | |1 = Capture function Enabled
AnnaBridge 187:0387e8f68319 836 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 187:0387e8f68319 837 * |[2] |CAPEN2 |Capture Function Enable Bits
AnnaBridge 187:0387e8f68319 838 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 839 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 187:0387e8f68319 840 * | | |1 = Capture function Enabled
AnnaBridge 187:0387e8f68319 841 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 187:0387e8f68319 842 * |[3] |CAPEN3 |Capture Function Enable Bits
AnnaBridge 187:0387e8f68319 843 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 844 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 187:0387e8f68319 845 * | | |1 = Capture function Enabled
AnnaBridge 187:0387e8f68319 846 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 187:0387e8f68319 847 * |[4] |CAPEN4 |Capture Function Enable Bits
AnnaBridge 187:0387e8f68319 848 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 849 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 187:0387e8f68319 850 * | | |1 = Capture function Enabled
AnnaBridge 187:0387e8f68319 851 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 187:0387e8f68319 852 * |[5] |CAPEN5 |Capture Function Enable Bits
AnnaBridge 187:0387e8f68319 853 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 854 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
AnnaBridge 187:0387e8f68319 855 * | | |1 = Capture function Enabled
AnnaBridge 187:0387e8f68319 856 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
AnnaBridge 187:0387e8f68319 857 * |[8] |CAPINV0 |Capture Inverter Enable Bits
AnnaBridge 187:0387e8f68319 858 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 859 * | | |0 = Capture source inverter Disabled.
AnnaBridge 187:0387e8f68319 860 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 187:0387e8f68319 861 * |[9] |CAPINV1 |Capture Inverter Enable Bits
AnnaBridge 187:0387e8f68319 862 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 863 * | | |0 = Capture source inverter Disabled.
AnnaBridge 187:0387e8f68319 864 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 187:0387e8f68319 865 * |[10] |CAPINV2 |Capture Inverter Enable Bits
AnnaBridge 187:0387e8f68319 866 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 867 * | | |0 = Capture source inverter Disabled.
AnnaBridge 187:0387e8f68319 868 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 187:0387e8f68319 869 * |[11] |CAPINV3 |Capture Inverter Enable Bits
AnnaBridge 187:0387e8f68319 870 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 871 * | | |0 = Capture source inverter Disabled.
AnnaBridge 187:0387e8f68319 872 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 187:0387e8f68319 873 * |[12] |CAPINV4 |Capture Inverter Enable Bits
AnnaBridge 187:0387e8f68319 874 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 875 * | | |0 = Capture source inverter Disabled.
AnnaBridge 187:0387e8f68319 876 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 187:0387e8f68319 877 * |[13] |CAPINV5 |Capture Inverter Enable Bits
AnnaBridge 187:0387e8f68319 878 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 879 * | | |0 = Capture source inverter Disabled.
AnnaBridge 187:0387e8f68319 880 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
AnnaBridge 187:0387e8f68319 881 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 882 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 883 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 884 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 885 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 886 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 887 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 888 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 889 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 890 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 891 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 892 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 893 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 894 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 895 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 896 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 897 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 898 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 899 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 900 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 901 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 902 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 903 * | | |0 = Rising capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 904 * | | |1 = Rising capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 905 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 906 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 907 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 908 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 909 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 910 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 911 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 912 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 913 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 914 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 915 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 916 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 917 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 918 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 919 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 920 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 921 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 922 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 923 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 924 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 925 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits
AnnaBridge 187:0387e8f68319 926 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 927 * | | |0 = Falling capture reload counter Disabled.
AnnaBridge 187:0387e8f68319 928 * | | |1 = Falling capture reload counter Enabled.
AnnaBridge 187:0387e8f68319 929 * @var BPWM_T::CAPSTS
AnnaBridge 187:0387e8f68319 930 * Offset: 0x208 BPWM Capture Status Register
AnnaBridge 187:0387e8f68319 931 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 932 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 933 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 934 * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 935 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
AnnaBridge 187:0387e8f68319 936 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 937 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
AnnaBridge 187:0387e8f68319 938 * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 939 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
AnnaBridge 187:0387e8f68319 940 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 941 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
AnnaBridge 187:0387e8f68319 942 * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 943 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
AnnaBridge 187:0387e8f68319 944 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 945 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
AnnaBridge 187:0387e8f68319 946 * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 947 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
AnnaBridge 187:0387e8f68319 948 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 949 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
AnnaBridge 187:0387e8f68319 950 * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 951 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
AnnaBridge 187:0387e8f68319 952 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 953 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
AnnaBridge 187:0387e8f68319 954 * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 955 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1
AnnaBridge 187:0387e8f68319 956 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 957 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF.
AnnaBridge 187:0387e8f68319 958 * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 959 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
AnnaBridge 187:0387e8f68319 960 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 961 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
AnnaBridge 187:0387e8f68319 962 * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 963 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
AnnaBridge 187:0387e8f68319 964 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 965 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
AnnaBridge 187:0387e8f68319 966 * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 967 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
AnnaBridge 187:0387e8f68319 968 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 969 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
AnnaBridge 187:0387e8f68319 970 * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 971 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
AnnaBridge 187:0387e8f68319 972 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 973 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
AnnaBridge 187:0387e8f68319 974 * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 975 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
AnnaBridge 187:0387e8f68319 976 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 977 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
AnnaBridge 187:0387e8f68319 978 * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only)
AnnaBridge 187:0387e8f68319 979 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
AnnaBridge 187:0387e8f68319 980 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 981 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
AnnaBridge 187:0387e8f68319 982 * @var BPWM_T::RCAPDAT0
AnnaBridge 187:0387e8f68319 983 * Offset: 0x20C BPWM Rising Capture Data Register 0
AnnaBridge 187:0387e8f68319 984 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 985 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 986 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 987 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 988 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 989 * @var BPWM_T::FCAPDAT0
AnnaBridge 187:0387e8f68319 990 * Offset: 0x210 BPWM Falling Capture Data Register 0
AnnaBridge 187:0387e8f68319 991 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 992 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 993 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 994 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 995 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 996 * @var BPWM_T::RCAPDAT1
AnnaBridge 187:0387e8f68319 997 * Offset: 0x214 BPWM Rising Capture Data Register 1
AnnaBridge 187:0387e8f68319 998 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 999 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1000 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1001 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1002 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1003 * @var BPWM_T::FCAPDAT1
AnnaBridge 187:0387e8f68319 1004 * Offset: 0x218 BPWM Falling Capture Data Register 1
AnnaBridge 187:0387e8f68319 1005 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1006 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1007 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1008 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1009 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1010 * @var BPWM_T::RCAPDAT2
AnnaBridge 187:0387e8f68319 1011 * Offset: 0x21C BPWM Rising Capture Data Register 2
AnnaBridge 187:0387e8f68319 1012 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1013 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1014 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1015 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1016 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1017 * @var BPWM_T::FCAPDAT2
AnnaBridge 187:0387e8f68319 1018 * Offset: 0x220 BPWM Falling Capture Data Register 2
AnnaBridge 187:0387e8f68319 1019 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1020 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1021 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1022 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1023 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1024 * @var BPWM_T::RCAPDAT3
AnnaBridge 187:0387e8f68319 1025 * Offset: 0x224 BPWM Rising Capture Data Register 3
AnnaBridge 187:0387e8f68319 1026 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1027 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1028 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1029 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1030 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1031 * @var BPWM_T::FCAPDAT3
AnnaBridge 187:0387e8f68319 1032 * Offset: 0x228 BPWM Falling Capture Data Register 3
AnnaBridge 187:0387e8f68319 1033 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1034 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1035 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1036 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1037 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1038 * @var BPWM_T::RCAPDAT4
AnnaBridge 187:0387e8f68319 1039 * Offset: 0x22C BPWM Rising Capture Data Register 4
AnnaBridge 187:0387e8f68319 1040 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1041 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1042 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1043 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1044 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1045 * @var BPWM_T::FCAPDAT4
AnnaBridge 187:0387e8f68319 1046 * Offset: 0x230 BPWM Falling Capture Data Register 4
AnnaBridge 187:0387e8f68319 1047 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1048 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1049 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1050 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1051 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1052 * @var BPWM_T::RCAPDAT5
AnnaBridge 187:0387e8f68319 1053 * Offset: 0x234 BPWM Rising Capture Data Register 5
AnnaBridge 187:0387e8f68319 1054 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1055 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1056 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1057 * |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1058 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1059 * @var BPWM_T::FCAPDAT5
AnnaBridge 187:0387e8f68319 1060 * Offset: 0x238 BPWM Falling Capture Data Register 5
AnnaBridge 187:0387e8f68319 1061 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1062 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1063 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1064 * |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
AnnaBridge 187:0387e8f68319 1065 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
AnnaBridge 187:0387e8f68319 1066 * @var BPWM_T::CAPIEN
AnnaBridge 187:0387e8f68319 1067 * Offset: 0x250 BPWM Capture Interrupt Enable Register
AnnaBridge 187:0387e8f68319 1068 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1069 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1070 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1071 * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 1072 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1073 * | | |0 = Capture rising edge latch interrupt Disabled.
AnnaBridge 187:0387e8f68319 1074 * | | |1 = Capture rising edge latch interrupt Enabled.
AnnaBridge 187:0387e8f68319 1075 * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits
AnnaBridge 187:0387e8f68319 1076 * | | |Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1077 * | | |0 = Capture falling edge latch interrupt Disabled.
AnnaBridge 187:0387e8f68319 1078 * | | |1 = Capture falling edge latch interrupt Enabled.
AnnaBridge 187:0387e8f68319 1079 * @var BPWM_T::CAPIF
AnnaBridge 187:0387e8f68319 1080 * Offset: 0x254 BPWM Capture Interrupt Flag Register
AnnaBridge 187:0387e8f68319 1081 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1082 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1083 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1084 * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1085 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1086 * | | |0 = No capture rising latch condition happened.
AnnaBridge 187:0387e8f68319 1087 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1088 * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1089 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1090 * | | |0 = No capture rising latch condition happened.
AnnaBridge 187:0387e8f68319 1091 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1092 * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1093 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1094 * | | |0 = No capture rising latch condition happened.
AnnaBridge 187:0387e8f68319 1095 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1096 * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1097 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1098 * | | |0 = No capture rising latch condition happened.
AnnaBridge 187:0387e8f68319 1099 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1100 * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1101 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1102 * | | |0 = No capture rising latch condition happened.
AnnaBridge 187:0387e8f68319 1103 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1104 * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1105 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1106 * | | |0 = No capture rising latch condition happened.
AnnaBridge 187:0387e8f68319 1107 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1108 * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1109 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1110 * | | |0 = No capture falling latch condition happened.
AnnaBridge 187:0387e8f68319 1111 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1112 * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1113 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1114 * | | |0 = No capture falling latch condition happened.
AnnaBridge 187:0387e8f68319 1115 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1116 * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1117 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1118 * | | |0 = No capture falling latch condition happened.
AnnaBridge 187:0387e8f68319 1119 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1120 * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1121 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1122 * | | |0 = No capture falling latch condition happened.
AnnaBridge 187:0387e8f68319 1123 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1124 * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1125 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1126 * | | |0 = No capture falling latch condition happened.
AnnaBridge 187:0387e8f68319 1127 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1128 * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag
AnnaBridge 187:0387e8f68319 1129 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n.
AnnaBridge 187:0387e8f68319 1130 * | | |0 = No capture falling latch condition happened.
AnnaBridge 187:0387e8f68319 1131 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
AnnaBridge 187:0387e8f68319 1132 * @var BPWM_T::PBUF
AnnaBridge 187:0387e8f68319 1133 * Offset: 0x304 BPWM PERIOD Buffer
AnnaBridge 187:0387e8f68319 1134 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1135 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1136 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1137 * |[15:0] |PBUF |BPWM Period Buffer (Read Only)
AnnaBridge 187:0387e8f68319 1138 * | | |Used as PERIOD active register.
AnnaBridge 187:0387e8f68319 1139 * @var BPWM_T::CMPBUF[6]
AnnaBridge 187:0387e8f68319 1140 * Offset: 0x31C BPWM CMPDAT 0~5 Buffer
AnnaBridge 187:0387e8f68319 1141 * ---------------------------------------------------------------------------------------------------
AnnaBridge 187:0387e8f68319 1142 * |Bits |Field |Descriptions
AnnaBridge 187:0387e8f68319 1143 * | :----: | :----: | :---- |
AnnaBridge 187:0387e8f68319 1144 * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only)
AnnaBridge 187:0387e8f68319 1145 * | | |Used as CMP active register.
AnnaBridge 187:0387e8f68319 1146 */
AnnaBridge 187:0387e8f68319 1147 __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */
AnnaBridge 187:0387e8f68319 1148 __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */
AnnaBridge 187:0387e8f68319 1149 __I uint32_t RESERVED0[2];
AnnaBridge 187:0387e8f68319 1150 __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */
AnnaBridge 187:0387e8f68319 1151 __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */
AnnaBridge 187:0387e8f68319 1152 __I uint32_t RESERVED1[2];
AnnaBridge 187:0387e8f68319 1153 __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */
AnnaBridge 187:0387e8f68319 1154 __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */
AnnaBridge 187:0387e8f68319 1155 __I uint32_t RESERVED2[2];
AnnaBridge 187:0387e8f68319 1156 __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */
AnnaBridge 187:0387e8f68319 1157 __I uint32_t RESERVED3[7];
AnnaBridge 187:0387e8f68319 1158 __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] BPWM Comparator Register 0~5 */
AnnaBridge 187:0387e8f68319 1159 __I uint32_t RESERVED4[10];
AnnaBridge 187:0387e8f68319 1160 __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */
AnnaBridge 187:0387e8f68319 1161 __I uint32_t RESERVED5[7];
AnnaBridge 187:0387e8f68319 1162 __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */
AnnaBridge 187:0387e8f68319 1163 __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */
AnnaBridge 187:0387e8f68319 1164 __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */
AnnaBridge 187:0387e8f68319 1165 __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */
AnnaBridge 187:0387e8f68319 1166 __I uint32_t RESERVED6[5];
AnnaBridge 187:0387e8f68319 1167 __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */
AnnaBridge 187:0387e8f68319 1168 __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */
AnnaBridge 187:0387e8f68319 1169 __I uint32_t RESERVED7[1];
AnnaBridge 187:0387e8f68319 1170 __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */
AnnaBridge 187:0387e8f68319 1171 __I uint32_t RESERVED8[1];
AnnaBridge 187:0387e8f68319 1172 __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */
AnnaBridge 187:0387e8f68319 1173 __I uint32_t RESERVED9[3];
AnnaBridge 187:0387e8f68319 1174 __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */
AnnaBridge 187:0387e8f68319 1175 __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */
AnnaBridge 187:0387e8f68319 1176 __I uint32_t RESERVED10[4];
AnnaBridge 187:0387e8f68319 1177 __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */
AnnaBridge 187:0387e8f68319 1178 __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */
AnnaBridge 187:0387e8f68319 1179 __I uint32_t RESERVED11[2];
AnnaBridge 187:0387e8f68319 1180 __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */
AnnaBridge 187:0387e8f68319 1181 __I uint32_t RESERVED12[55];
AnnaBridge 187:0387e8f68319 1182 __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */
AnnaBridge 187:0387e8f68319 1183 __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */
AnnaBridge 187:0387e8f68319 1184 __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */
AnnaBridge 187:0387e8f68319 1185 BCAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5 */
AnnaBridge 187:0387e8f68319 1186 __I uint32_t RESERVED13[5];
AnnaBridge 187:0387e8f68319 1187 __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */
AnnaBridge 187:0387e8f68319 1188 __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */
AnnaBridge 187:0387e8f68319 1189 __I uint32_t RESERVED14[43];
AnnaBridge 187:0387e8f68319 1190 __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */
AnnaBridge 187:0387e8f68319 1191 __I uint32_t RESERVED15[5];
AnnaBridge 187:0387e8f68319 1192 __I uint32_t CMPBUF[6]; /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer */
AnnaBridge 187:0387e8f68319 1193
AnnaBridge 187:0387e8f68319 1194 } BPWM_T;
AnnaBridge 187:0387e8f68319 1195
AnnaBridge 187:0387e8f68319 1196 /**
AnnaBridge 187:0387e8f68319 1197 @addtogroup BPWM_CONST BPWM Bit Field Definition
AnnaBridge 187:0387e8f68319 1198 Constant Definitions for BPWM Controller
AnnaBridge 187:0387e8f68319 1199 @{ */
AnnaBridge 187:0387e8f68319 1200
AnnaBridge 187:0387e8f68319 1201 #define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */
AnnaBridge 187:0387e8f68319 1202 #define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */
AnnaBridge 187:0387e8f68319 1203
AnnaBridge 187:0387e8f68319 1204 #define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */
AnnaBridge 187:0387e8f68319 1205 #define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */
AnnaBridge 187:0387e8f68319 1206
AnnaBridge 187:0387e8f68319 1207 #define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */
AnnaBridge 187:0387e8f68319 1208 #define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */
AnnaBridge 187:0387e8f68319 1209
AnnaBridge 187:0387e8f68319 1210 #define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */
AnnaBridge 187:0387e8f68319 1211 #define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */
AnnaBridge 187:0387e8f68319 1212
AnnaBridge 187:0387e8f68319 1213 #define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */
AnnaBridge 187:0387e8f68319 1214 #define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */
AnnaBridge 187:0387e8f68319 1215
AnnaBridge 187:0387e8f68319 1216 #define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */
AnnaBridge 187:0387e8f68319 1217 #define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */
AnnaBridge 187:0387e8f68319 1218
AnnaBridge 187:0387e8f68319 1219 #define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */
AnnaBridge 187:0387e8f68319 1220 #define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */
AnnaBridge 187:0387e8f68319 1221
AnnaBridge 187:0387e8f68319 1222 #define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */
AnnaBridge 187:0387e8f68319 1223 #define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */
AnnaBridge 187:0387e8f68319 1224
AnnaBridge 187:0387e8f68319 1225 #define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */
AnnaBridge 187:0387e8f68319 1226 #define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */
AnnaBridge 187:0387e8f68319 1227
AnnaBridge 187:0387e8f68319 1228 #define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */
AnnaBridge 187:0387e8f68319 1229 #define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */
AnnaBridge 187:0387e8f68319 1230
AnnaBridge 187:0387e8f68319 1231 #define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */
AnnaBridge 187:0387e8f68319 1232 #define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */
AnnaBridge 187:0387e8f68319 1233
AnnaBridge 187:0387e8f68319 1234 #define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */
AnnaBridge 187:0387e8f68319 1235 #define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */
AnnaBridge 187:0387e8f68319 1236
AnnaBridge 187:0387e8f68319 1237 #define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */
AnnaBridge 187:0387e8f68319 1238 #define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */
AnnaBridge 187:0387e8f68319 1239
AnnaBridge 187:0387e8f68319 1240 #define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */
AnnaBridge 187:0387e8f68319 1241 #define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */
AnnaBridge 187:0387e8f68319 1242
AnnaBridge 187:0387e8f68319 1243 #define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */
AnnaBridge 187:0387e8f68319 1244 #define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */
AnnaBridge 187:0387e8f68319 1245
AnnaBridge 187:0387e8f68319 1246 #define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */
AnnaBridge 187:0387e8f68319 1247 #define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */
AnnaBridge 187:0387e8f68319 1248
AnnaBridge 187:0387e8f68319 1249 #define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */
AnnaBridge 187:0387e8f68319 1250 #define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */
AnnaBridge 187:0387e8f68319 1251
AnnaBridge 187:0387e8f68319 1252 #define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */
AnnaBridge 187:0387e8f68319 1253 #define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */
AnnaBridge 187:0387e8f68319 1254
AnnaBridge 187:0387e8f68319 1255 #define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */
AnnaBridge 187:0387e8f68319 1256 #define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */
AnnaBridge 187:0387e8f68319 1257
AnnaBridge 187:0387e8f68319 1258 #define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */
AnnaBridge 187:0387e8f68319 1259 #define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */
AnnaBridge 187:0387e8f68319 1260
AnnaBridge 187:0387e8f68319 1261 #define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */
AnnaBridge 187:0387e8f68319 1262 #define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */
AnnaBridge 187:0387e8f68319 1263
AnnaBridge 187:0387e8f68319 1264 #define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */
AnnaBridge 187:0387e8f68319 1265 #define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */
AnnaBridge 187:0387e8f68319 1266
AnnaBridge 187:0387e8f68319 1267 #define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */
AnnaBridge 187:0387e8f68319 1268 #define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */
AnnaBridge 187:0387e8f68319 1269
AnnaBridge 187:0387e8f68319 1270 #define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */
AnnaBridge 187:0387e8f68319 1271 #define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */
AnnaBridge 187:0387e8f68319 1272
AnnaBridge 187:0387e8f68319 1273 #define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */
AnnaBridge 187:0387e8f68319 1274 #define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */
AnnaBridge 187:0387e8f68319 1275
AnnaBridge 187:0387e8f68319 1276 #define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */
AnnaBridge 187:0387e8f68319 1277 #define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */
AnnaBridge 187:0387e8f68319 1278
AnnaBridge 187:0387e8f68319 1279 #define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */
AnnaBridge 187:0387e8f68319 1280 #define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */
AnnaBridge 187:0387e8f68319 1281
AnnaBridge 187:0387e8f68319 1282 #define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */
AnnaBridge 187:0387e8f68319 1283 #define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */
AnnaBridge 187:0387e8f68319 1284
AnnaBridge 187:0387e8f68319 1285 #define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */
AnnaBridge 187:0387e8f68319 1286 #define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */
AnnaBridge 187:0387e8f68319 1287
AnnaBridge 187:0387e8f68319 1288 #define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */
AnnaBridge 187:0387e8f68319 1289 #define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */
AnnaBridge 187:0387e8f68319 1290
AnnaBridge 187:0387e8f68319 1291 #define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */
AnnaBridge 187:0387e8f68319 1292 #define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */
AnnaBridge 187:0387e8f68319 1293
AnnaBridge 187:0387e8f68319 1294 #define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */
AnnaBridge 187:0387e8f68319 1295 #define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */
AnnaBridge 187:0387e8f68319 1296
AnnaBridge 187:0387e8f68319 1297 #define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */
AnnaBridge 187:0387e8f68319 1298 #define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */
AnnaBridge 187:0387e8f68319 1299
AnnaBridge 187:0387e8f68319 1300 #define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */
AnnaBridge 187:0387e8f68319 1301 #define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */
AnnaBridge 187:0387e8f68319 1302
AnnaBridge 187:0387e8f68319 1303 #define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */
AnnaBridge 187:0387e8f68319 1304 #define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */
AnnaBridge 187:0387e8f68319 1305
AnnaBridge 187:0387e8f68319 1306 #define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */
AnnaBridge 187:0387e8f68319 1307 #define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */
AnnaBridge 187:0387e8f68319 1308
AnnaBridge 187:0387e8f68319 1309 #define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */
AnnaBridge 187:0387e8f68319 1310 #define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */
AnnaBridge 187:0387e8f68319 1311
AnnaBridge 187:0387e8f68319 1312 #define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */
AnnaBridge 187:0387e8f68319 1313 #define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */
AnnaBridge 187:0387e8f68319 1314
AnnaBridge 187:0387e8f68319 1315 #define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */
AnnaBridge 187:0387e8f68319 1316 #define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */
AnnaBridge 187:0387e8f68319 1317
AnnaBridge 187:0387e8f68319 1318 #define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */
AnnaBridge 187:0387e8f68319 1319 #define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */
AnnaBridge 187:0387e8f68319 1320
AnnaBridge 187:0387e8f68319 1321 #define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */
AnnaBridge 187:0387e8f68319 1322 #define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */
AnnaBridge 187:0387e8f68319 1323
AnnaBridge 187:0387e8f68319 1324 #define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */
AnnaBridge 187:0387e8f68319 1325 #define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */
AnnaBridge 187:0387e8f68319 1326
AnnaBridge 187:0387e8f68319 1327 #define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */
AnnaBridge 187:0387e8f68319 1328 #define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */
AnnaBridge 187:0387e8f68319 1329
AnnaBridge 187:0387e8f68319 1330 #define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */
AnnaBridge 187:0387e8f68319 1331 #define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */
AnnaBridge 187:0387e8f68319 1332
AnnaBridge 187:0387e8f68319 1333 #define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */
AnnaBridge 187:0387e8f68319 1334 #define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */
AnnaBridge 187:0387e8f68319 1335
AnnaBridge 187:0387e8f68319 1336 #define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */
AnnaBridge 187:0387e8f68319 1337 #define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */
AnnaBridge 187:0387e8f68319 1338
AnnaBridge 187:0387e8f68319 1339 #define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */
AnnaBridge 187:0387e8f68319 1340 #define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */
AnnaBridge 187:0387e8f68319 1341
AnnaBridge 187:0387e8f68319 1342 #define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */
AnnaBridge 187:0387e8f68319 1343 #define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */
AnnaBridge 187:0387e8f68319 1344
AnnaBridge 187:0387e8f68319 1345 #define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */
AnnaBridge 187:0387e8f68319 1346 #define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */
AnnaBridge 187:0387e8f68319 1347
AnnaBridge 187:0387e8f68319 1348 #define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */
AnnaBridge 187:0387e8f68319 1349 #define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */
AnnaBridge 187:0387e8f68319 1350
AnnaBridge 187:0387e8f68319 1351 #define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */
AnnaBridge 187:0387e8f68319 1352 #define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */
AnnaBridge 187:0387e8f68319 1353
AnnaBridge 187:0387e8f68319 1354 #define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */
AnnaBridge 187:0387e8f68319 1355 #define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */
AnnaBridge 187:0387e8f68319 1356
AnnaBridge 187:0387e8f68319 1357 #define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */
AnnaBridge 187:0387e8f68319 1358 #define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */
AnnaBridge 187:0387e8f68319 1359
AnnaBridge 187:0387e8f68319 1360 #define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */
AnnaBridge 187:0387e8f68319 1361 #define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */
AnnaBridge 187:0387e8f68319 1362
AnnaBridge 187:0387e8f68319 1363 #define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */
AnnaBridge 187:0387e8f68319 1364 #define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */
AnnaBridge 187:0387e8f68319 1365
AnnaBridge 187:0387e8f68319 1366 #define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */
AnnaBridge 187:0387e8f68319 1367 #define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */
AnnaBridge 187:0387e8f68319 1368
AnnaBridge 187:0387e8f68319 1369 #define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */
AnnaBridge 187:0387e8f68319 1370 #define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */
AnnaBridge 187:0387e8f68319 1371
AnnaBridge 187:0387e8f68319 1372 #define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */
AnnaBridge 187:0387e8f68319 1373 #define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */
AnnaBridge 187:0387e8f68319 1374
AnnaBridge 187:0387e8f68319 1375 #define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */
AnnaBridge 187:0387e8f68319 1376 #define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */
AnnaBridge 187:0387e8f68319 1377
AnnaBridge 187:0387e8f68319 1378 #define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */
AnnaBridge 187:0387e8f68319 1379 #define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */
AnnaBridge 187:0387e8f68319 1380
AnnaBridge 187:0387e8f68319 1381 #define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */
AnnaBridge 187:0387e8f68319 1382 #define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */
AnnaBridge 187:0387e8f68319 1383
AnnaBridge 187:0387e8f68319 1384 #define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */
AnnaBridge 187:0387e8f68319 1385 #define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */
AnnaBridge 187:0387e8f68319 1386
AnnaBridge 187:0387e8f68319 1387 #define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */
AnnaBridge 187:0387e8f68319 1388 #define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */
AnnaBridge 187:0387e8f68319 1389
AnnaBridge 187:0387e8f68319 1390 #define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */
AnnaBridge 187:0387e8f68319 1391 #define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */
AnnaBridge 187:0387e8f68319 1392
AnnaBridge 187:0387e8f68319 1393 #define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */
AnnaBridge 187:0387e8f68319 1394 #define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */
AnnaBridge 187:0387e8f68319 1395
AnnaBridge 187:0387e8f68319 1396 #define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */
AnnaBridge 187:0387e8f68319 1397 #define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */
AnnaBridge 187:0387e8f68319 1398
AnnaBridge 187:0387e8f68319 1399 #define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */
AnnaBridge 187:0387e8f68319 1400 #define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */
AnnaBridge 187:0387e8f68319 1401
AnnaBridge 187:0387e8f68319 1402 #define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */
AnnaBridge 187:0387e8f68319 1403 #define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */
AnnaBridge 187:0387e8f68319 1404
AnnaBridge 187:0387e8f68319 1405 #define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */
AnnaBridge 187:0387e8f68319 1406 #define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */
AnnaBridge 187:0387e8f68319 1407
AnnaBridge 187:0387e8f68319 1408 #define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */
AnnaBridge 187:0387e8f68319 1409 #define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */
AnnaBridge 187:0387e8f68319 1410
AnnaBridge 187:0387e8f68319 1411 #define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */
AnnaBridge 187:0387e8f68319 1412 #define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */
AnnaBridge 187:0387e8f68319 1413
AnnaBridge 187:0387e8f68319 1414 #define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */
AnnaBridge 187:0387e8f68319 1415 #define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */
AnnaBridge 187:0387e8f68319 1416
AnnaBridge 187:0387e8f68319 1417 #define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */
AnnaBridge 187:0387e8f68319 1418 #define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */
AnnaBridge 187:0387e8f68319 1419
AnnaBridge 187:0387e8f68319 1420 #define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */
AnnaBridge 187:0387e8f68319 1421 #define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */
AnnaBridge 187:0387e8f68319 1422
AnnaBridge 187:0387e8f68319 1423 #define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */
AnnaBridge 187:0387e8f68319 1424 #define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */
AnnaBridge 187:0387e8f68319 1425
AnnaBridge 187:0387e8f68319 1426 #define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */
AnnaBridge 187:0387e8f68319 1427 #define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */
AnnaBridge 187:0387e8f68319 1428
AnnaBridge 187:0387e8f68319 1429 #define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */
AnnaBridge 187:0387e8f68319 1430 #define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */
AnnaBridge 187:0387e8f68319 1431
AnnaBridge 187:0387e8f68319 1432 #define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */
AnnaBridge 187:0387e8f68319 1433 #define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */
AnnaBridge 187:0387e8f68319 1434
AnnaBridge 187:0387e8f68319 1435 #define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */
AnnaBridge 187:0387e8f68319 1436 #define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */
AnnaBridge 187:0387e8f68319 1437
AnnaBridge 187:0387e8f68319 1438 #define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */
AnnaBridge 187:0387e8f68319 1439 #define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */
AnnaBridge 187:0387e8f68319 1440
AnnaBridge 187:0387e8f68319 1441 #define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */
AnnaBridge 187:0387e8f68319 1442 #define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */
AnnaBridge 187:0387e8f68319 1443
AnnaBridge 187:0387e8f68319 1444 #define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */
AnnaBridge 187:0387e8f68319 1445 #define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */
AnnaBridge 187:0387e8f68319 1446
AnnaBridge 187:0387e8f68319 1447 #define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */
AnnaBridge 187:0387e8f68319 1448 #define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */
AnnaBridge 187:0387e8f68319 1449
AnnaBridge 187:0387e8f68319 1450 #define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */
AnnaBridge 187:0387e8f68319 1451 #define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */
AnnaBridge 187:0387e8f68319 1452
AnnaBridge 187:0387e8f68319 1453 #define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */
AnnaBridge 187:0387e8f68319 1454 #define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */
AnnaBridge 187:0387e8f68319 1455
AnnaBridge 187:0387e8f68319 1456 #define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */
AnnaBridge 187:0387e8f68319 1457 #define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */
AnnaBridge 187:0387e8f68319 1458
AnnaBridge 187:0387e8f68319 1459 #define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */
AnnaBridge 187:0387e8f68319 1460 #define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */
AnnaBridge 187:0387e8f68319 1461
AnnaBridge 187:0387e8f68319 1462 #define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */
AnnaBridge 187:0387e8f68319 1463 #define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */
AnnaBridge 187:0387e8f68319 1464
AnnaBridge 187:0387e8f68319 1465 #define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */
AnnaBridge 187:0387e8f68319 1466 #define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */
AnnaBridge 187:0387e8f68319 1467
AnnaBridge 187:0387e8f68319 1468 #define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */
AnnaBridge 187:0387e8f68319 1469 #define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */
AnnaBridge 187:0387e8f68319 1470
AnnaBridge 187:0387e8f68319 1471 #define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */
AnnaBridge 187:0387e8f68319 1472 #define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */
AnnaBridge 187:0387e8f68319 1473
AnnaBridge 187:0387e8f68319 1474 #define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */
AnnaBridge 187:0387e8f68319 1475 #define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */
AnnaBridge 187:0387e8f68319 1476
AnnaBridge 187:0387e8f68319 1477 #define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */
AnnaBridge 187:0387e8f68319 1478 #define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */
AnnaBridge 187:0387e8f68319 1479
AnnaBridge 187:0387e8f68319 1480 #define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */
AnnaBridge 187:0387e8f68319 1481 #define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */
AnnaBridge 187:0387e8f68319 1482
AnnaBridge 187:0387e8f68319 1483 #define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */
AnnaBridge 187:0387e8f68319 1484 #define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */
AnnaBridge 187:0387e8f68319 1485
AnnaBridge 187:0387e8f68319 1486 #define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */
AnnaBridge 187:0387e8f68319 1487 #define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */
AnnaBridge 187:0387e8f68319 1488
AnnaBridge 187:0387e8f68319 1489 #define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */
AnnaBridge 187:0387e8f68319 1490 #define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */
AnnaBridge 187:0387e8f68319 1491
AnnaBridge 187:0387e8f68319 1492 #define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */
AnnaBridge 187:0387e8f68319 1493 #define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */
AnnaBridge 187:0387e8f68319 1494
AnnaBridge 187:0387e8f68319 1495 #define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */
AnnaBridge 187:0387e8f68319 1496 #define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */
AnnaBridge 187:0387e8f68319 1497
AnnaBridge 187:0387e8f68319 1498 #define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */
AnnaBridge 187:0387e8f68319 1499 #define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */
AnnaBridge 187:0387e8f68319 1500
AnnaBridge 187:0387e8f68319 1501 #define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */
AnnaBridge 187:0387e8f68319 1502 #define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */
AnnaBridge 187:0387e8f68319 1503
AnnaBridge 187:0387e8f68319 1504 #define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */
AnnaBridge 187:0387e8f68319 1505 #define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */
AnnaBridge 187:0387e8f68319 1506
AnnaBridge 187:0387e8f68319 1507 #define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */
AnnaBridge 187:0387e8f68319 1508 #define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */
AnnaBridge 187:0387e8f68319 1509
AnnaBridge 187:0387e8f68319 1510 #define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */
AnnaBridge 187:0387e8f68319 1511 #define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */
AnnaBridge 187:0387e8f68319 1512
AnnaBridge 187:0387e8f68319 1513 #define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */
AnnaBridge 187:0387e8f68319 1514 #define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */
AnnaBridge 187:0387e8f68319 1515
AnnaBridge 187:0387e8f68319 1516 #define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */
AnnaBridge 187:0387e8f68319 1517 #define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */
AnnaBridge 187:0387e8f68319 1518
AnnaBridge 187:0387e8f68319 1519 #define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */
AnnaBridge 187:0387e8f68319 1520 #define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */
AnnaBridge 187:0387e8f68319 1521
AnnaBridge 187:0387e8f68319 1522 #define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */
AnnaBridge 187:0387e8f68319 1523 #define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */
AnnaBridge 187:0387e8f68319 1524
AnnaBridge 187:0387e8f68319 1525 #define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */
AnnaBridge 187:0387e8f68319 1526 #define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */
AnnaBridge 187:0387e8f68319 1527
AnnaBridge 187:0387e8f68319 1528 #define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */
AnnaBridge 187:0387e8f68319 1529 #define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */
AnnaBridge 187:0387e8f68319 1530
AnnaBridge 187:0387e8f68319 1531 #define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */
AnnaBridge 187:0387e8f68319 1532 #define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */
AnnaBridge 187:0387e8f68319 1533
AnnaBridge 187:0387e8f68319 1534 #define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */
AnnaBridge 187:0387e8f68319 1535 #define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */
AnnaBridge 187:0387e8f68319 1536
AnnaBridge 187:0387e8f68319 1537 #define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */
AnnaBridge 187:0387e8f68319 1538 #define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */
AnnaBridge 187:0387e8f68319 1539
AnnaBridge 187:0387e8f68319 1540 #define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */
AnnaBridge 187:0387e8f68319 1541 #define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */
AnnaBridge 187:0387e8f68319 1542
AnnaBridge 187:0387e8f68319 1543 #define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */
AnnaBridge 187:0387e8f68319 1544 #define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */
AnnaBridge 187:0387e8f68319 1545
AnnaBridge 187:0387e8f68319 1546 #define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */
AnnaBridge 187:0387e8f68319 1547 #define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */
AnnaBridge 187:0387e8f68319 1548
AnnaBridge 187:0387e8f68319 1549 #define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */
AnnaBridge 187:0387e8f68319 1550 #define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */
AnnaBridge 187:0387e8f68319 1551
AnnaBridge 187:0387e8f68319 1552 #define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */
AnnaBridge 187:0387e8f68319 1553 #define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */
AnnaBridge 187:0387e8f68319 1554
AnnaBridge 187:0387e8f68319 1555 #define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */
AnnaBridge 187:0387e8f68319 1556 #define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */
AnnaBridge 187:0387e8f68319 1557
AnnaBridge 187:0387e8f68319 1558 #define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */
AnnaBridge 187:0387e8f68319 1559 #define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */
AnnaBridge 187:0387e8f68319 1560
AnnaBridge 187:0387e8f68319 1561 #define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */
AnnaBridge 187:0387e8f68319 1562 #define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */
AnnaBridge 187:0387e8f68319 1563
AnnaBridge 187:0387e8f68319 1564 #define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */
AnnaBridge 187:0387e8f68319 1565 #define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */
AnnaBridge 187:0387e8f68319 1566
AnnaBridge 187:0387e8f68319 1567 #define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */
AnnaBridge 187:0387e8f68319 1568 #define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */
AnnaBridge 187:0387e8f68319 1569
AnnaBridge 187:0387e8f68319 1570 #define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */
AnnaBridge 187:0387e8f68319 1571 #define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */
AnnaBridge 187:0387e8f68319 1572
AnnaBridge 187:0387e8f68319 1573 #define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */
AnnaBridge 187:0387e8f68319 1574 #define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */
AnnaBridge 187:0387e8f68319 1575
AnnaBridge 187:0387e8f68319 1576 #define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */
AnnaBridge 187:0387e8f68319 1577 #define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */
AnnaBridge 187:0387e8f68319 1578
AnnaBridge 187:0387e8f68319 1579 #define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */
AnnaBridge 187:0387e8f68319 1580 #define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */
AnnaBridge 187:0387e8f68319 1581
AnnaBridge 187:0387e8f68319 1582 #define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */
AnnaBridge 187:0387e8f68319 1583 #define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */
AnnaBridge 187:0387e8f68319 1584
AnnaBridge 187:0387e8f68319 1585 #define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */
AnnaBridge 187:0387e8f68319 1586 #define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */
AnnaBridge 187:0387e8f68319 1587
AnnaBridge 187:0387e8f68319 1588 #define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */
AnnaBridge 187:0387e8f68319 1589 #define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */
AnnaBridge 187:0387e8f68319 1590
AnnaBridge 187:0387e8f68319 1591 #define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */
AnnaBridge 187:0387e8f68319 1592 #define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */
AnnaBridge 187:0387e8f68319 1593
AnnaBridge 187:0387e8f68319 1594 #define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */
AnnaBridge 187:0387e8f68319 1595 #define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */
AnnaBridge 187:0387e8f68319 1596
AnnaBridge 187:0387e8f68319 1597 #define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */
AnnaBridge 187:0387e8f68319 1598 #define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */
AnnaBridge 187:0387e8f68319 1599
AnnaBridge 187:0387e8f68319 1600 #define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */
AnnaBridge 187:0387e8f68319 1601 #define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */
AnnaBridge 187:0387e8f68319 1602
AnnaBridge 187:0387e8f68319 1603 #define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */
AnnaBridge 187:0387e8f68319 1604 #define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */
AnnaBridge 187:0387e8f68319 1605
AnnaBridge 187:0387e8f68319 1606 #define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */
AnnaBridge 187:0387e8f68319 1607 #define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */
AnnaBridge 187:0387e8f68319 1608
AnnaBridge 187:0387e8f68319 1609 #define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */
AnnaBridge 187:0387e8f68319 1610 #define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */
AnnaBridge 187:0387e8f68319 1611
AnnaBridge 187:0387e8f68319 1612 #define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */
AnnaBridge 187:0387e8f68319 1613 #define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */
AnnaBridge 187:0387e8f68319 1614
AnnaBridge 187:0387e8f68319 1615 #define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */
AnnaBridge 187:0387e8f68319 1616 #define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */
AnnaBridge 187:0387e8f68319 1617
AnnaBridge 187:0387e8f68319 1618 #define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */
AnnaBridge 187:0387e8f68319 1619 #define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */
AnnaBridge 187:0387e8f68319 1620
AnnaBridge 187:0387e8f68319 1621 #define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */
AnnaBridge 187:0387e8f68319 1622 #define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */
AnnaBridge 187:0387e8f68319 1623
AnnaBridge 187:0387e8f68319 1624 #define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */
AnnaBridge 187:0387e8f68319 1625 #define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */
AnnaBridge 187:0387e8f68319 1626
AnnaBridge 187:0387e8f68319 1627 #define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */
AnnaBridge 187:0387e8f68319 1628 #define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */
AnnaBridge 187:0387e8f68319 1629
AnnaBridge 187:0387e8f68319 1630 #define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */
AnnaBridge 187:0387e8f68319 1631 #define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */
AnnaBridge 187:0387e8f68319 1632
AnnaBridge 187:0387e8f68319 1633 #define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */
AnnaBridge 187:0387e8f68319 1634 #define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */
AnnaBridge 187:0387e8f68319 1635
AnnaBridge 187:0387e8f68319 1636 #define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */
AnnaBridge 187:0387e8f68319 1637 #define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */
AnnaBridge 187:0387e8f68319 1638
AnnaBridge 187:0387e8f68319 1639 #define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */
AnnaBridge 187:0387e8f68319 1640 #define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */
AnnaBridge 187:0387e8f68319 1641
AnnaBridge 187:0387e8f68319 1642 #define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */
AnnaBridge 187:0387e8f68319 1643 #define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */
AnnaBridge 187:0387e8f68319 1644
AnnaBridge 187:0387e8f68319 1645 #define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */
AnnaBridge 187:0387e8f68319 1646 #define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */
AnnaBridge 187:0387e8f68319 1647
AnnaBridge 187:0387e8f68319 1648 #define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */
AnnaBridge 187:0387e8f68319 1649 #define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */
AnnaBridge 187:0387e8f68319 1650
AnnaBridge 187:0387e8f68319 1651 #define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */
AnnaBridge 187:0387e8f68319 1652 #define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */
AnnaBridge 187:0387e8f68319 1653
AnnaBridge 187:0387e8f68319 1654 #define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */
AnnaBridge 187:0387e8f68319 1655 #define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */
AnnaBridge 187:0387e8f68319 1656
AnnaBridge 187:0387e8f68319 1657 #define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */
AnnaBridge 187:0387e8f68319 1658 #define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */
AnnaBridge 187:0387e8f68319 1659
AnnaBridge 187:0387e8f68319 1660 #define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */
AnnaBridge 187:0387e8f68319 1661 #define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */
AnnaBridge 187:0387e8f68319 1662
AnnaBridge 187:0387e8f68319 1663 #define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */
AnnaBridge 187:0387e8f68319 1664 #define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */
AnnaBridge 187:0387e8f68319 1665
AnnaBridge 187:0387e8f68319 1666 #define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */
AnnaBridge 187:0387e8f68319 1667 #define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */
AnnaBridge 187:0387e8f68319 1668
AnnaBridge 187:0387e8f68319 1669 #define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */
AnnaBridge 187:0387e8f68319 1670 #define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */
AnnaBridge 187:0387e8f68319 1671
AnnaBridge 187:0387e8f68319 1672 #define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */
AnnaBridge 187:0387e8f68319 1673 #define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */
AnnaBridge 187:0387e8f68319 1674
AnnaBridge 187:0387e8f68319 1675 #define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */
AnnaBridge 187:0387e8f68319 1676 #define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */
AnnaBridge 187:0387e8f68319 1677
AnnaBridge 187:0387e8f68319 1678 #define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */
AnnaBridge 187:0387e8f68319 1679 #define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */
AnnaBridge 187:0387e8f68319 1680
AnnaBridge 187:0387e8f68319 1681 #define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */
AnnaBridge 187:0387e8f68319 1682 #define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */
AnnaBridge 187:0387e8f68319 1683
AnnaBridge 187:0387e8f68319 1684 #define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */
AnnaBridge 187:0387e8f68319 1685 #define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */
AnnaBridge 187:0387e8f68319 1686
AnnaBridge 187:0387e8f68319 1687 #define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */
AnnaBridge 187:0387e8f68319 1688 #define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */
AnnaBridge 187:0387e8f68319 1689
AnnaBridge 187:0387e8f68319 1690 #define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */
AnnaBridge 187:0387e8f68319 1691 #define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */
AnnaBridge 187:0387e8f68319 1692
AnnaBridge 187:0387e8f68319 1693 #define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */
AnnaBridge 187:0387e8f68319 1694 #define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */
AnnaBridge 187:0387e8f68319 1695
AnnaBridge 187:0387e8f68319 1696 #define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */
AnnaBridge 187:0387e8f68319 1697 #define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */
AnnaBridge 187:0387e8f68319 1698
AnnaBridge 187:0387e8f68319 1699 #define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */
AnnaBridge 187:0387e8f68319 1700 #define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */
AnnaBridge 187:0387e8f68319 1701
AnnaBridge 187:0387e8f68319 1702 #define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */
AnnaBridge 187:0387e8f68319 1703 #define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */
AnnaBridge 187:0387e8f68319 1704
AnnaBridge 187:0387e8f68319 1705 #define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */
AnnaBridge 187:0387e8f68319 1706 #define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */
AnnaBridge 187:0387e8f68319 1707
AnnaBridge 187:0387e8f68319 1708 #define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */
AnnaBridge 187:0387e8f68319 1709 #define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */
AnnaBridge 187:0387e8f68319 1710
AnnaBridge 187:0387e8f68319 1711 #define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */
AnnaBridge 187:0387e8f68319 1712 #define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */
AnnaBridge 187:0387e8f68319 1713
AnnaBridge 187:0387e8f68319 1714 #define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */
AnnaBridge 187:0387e8f68319 1715 #define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */
AnnaBridge 187:0387e8f68319 1716
AnnaBridge 187:0387e8f68319 1717 #define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */
AnnaBridge 187:0387e8f68319 1718 #define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */
AnnaBridge 187:0387e8f68319 1719
AnnaBridge 187:0387e8f68319 1720 #define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */
AnnaBridge 187:0387e8f68319 1721 #define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */
AnnaBridge 187:0387e8f68319 1722
AnnaBridge 187:0387e8f68319 1723 #define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */
AnnaBridge 187:0387e8f68319 1724 #define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */
AnnaBridge 187:0387e8f68319 1725
AnnaBridge 187:0387e8f68319 1726 #define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */
AnnaBridge 187:0387e8f68319 1727 #define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */
AnnaBridge 187:0387e8f68319 1728
AnnaBridge 187:0387e8f68319 1729 #define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */
AnnaBridge 187:0387e8f68319 1730 #define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */
AnnaBridge 187:0387e8f68319 1731
AnnaBridge 187:0387e8f68319 1732 #define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */
AnnaBridge 187:0387e8f68319 1733 #define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */
AnnaBridge 187:0387e8f68319 1734
AnnaBridge 187:0387e8f68319 1735 #define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */
AnnaBridge 187:0387e8f68319 1736 #define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */
AnnaBridge 187:0387e8f68319 1737
AnnaBridge 187:0387e8f68319 1738 #define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */
AnnaBridge 187:0387e8f68319 1739 #define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */
AnnaBridge 187:0387e8f68319 1740
AnnaBridge 187:0387e8f68319 1741 #define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */
AnnaBridge 187:0387e8f68319 1742 #define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */
AnnaBridge 187:0387e8f68319 1743
AnnaBridge 187:0387e8f68319 1744 #define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */
AnnaBridge 187:0387e8f68319 1745 #define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */
AnnaBridge 187:0387e8f68319 1746
AnnaBridge 187:0387e8f68319 1747 #define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */
AnnaBridge 187:0387e8f68319 1748 #define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */
AnnaBridge 187:0387e8f68319 1749
AnnaBridge 187:0387e8f68319 1750 #define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */
AnnaBridge 187:0387e8f68319 1751 #define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */
AnnaBridge 187:0387e8f68319 1752
AnnaBridge 187:0387e8f68319 1753 #define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */
AnnaBridge 187:0387e8f68319 1754 #define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */
AnnaBridge 187:0387e8f68319 1755
AnnaBridge 187:0387e8f68319 1756 #define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */
AnnaBridge 187:0387e8f68319 1757 #define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */
AnnaBridge 187:0387e8f68319 1758
AnnaBridge 187:0387e8f68319 1759 #define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */
AnnaBridge 187:0387e8f68319 1760 #define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */
AnnaBridge 187:0387e8f68319 1761
AnnaBridge 187:0387e8f68319 1762 #define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */
AnnaBridge 187:0387e8f68319 1763 #define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */
AnnaBridge 187:0387e8f68319 1764
AnnaBridge 187:0387e8f68319 1765 #define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */
AnnaBridge 187:0387e8f68319 1766 #define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1767
AnnaBridge 187:0387e8f68319 1768 #define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */
AnnaBridge 187:0387e8f68319 1769 #define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1770
AnnaBridge 187:0387e8f68319 1771 #define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */
AnnaBridge 187:0387e8f68319 1772 #define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1773
AnnaBridge 187:0387e8f68319 1774 #define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */
AnnaBridge 187:0387e8f68319 1775 #define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1776
AnnaBridge 187:0387e8f68319 1777 #define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */
AnnaBridge 187:0387e8f68319 1778 #define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1779
AnnaBridge 187:0387e8f68319 1780 #define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */
AnnaBridge 187:0387e8f68319 1781 #define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1782
AnnaBridge 187:0387e8f68319 1783 #define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */
AnnaBridge 187:0387e8f68319 1784 #define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1785
AnnaBridge 187:0387e8f68319 1786 #define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */
AnnaBridge 187:0387e8f68319 1787 #define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1788
AnnaBridge 187:0387e8f68319 1789 #define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */
AnnaBridge 187:0387e8f68319 1790 #define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1791
AnnaBridge 187:0387e8f68319 1792 #define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */
AnnaBridge 187:0387e8f68319 1793 #define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1794
AnnaBridge 187:0387e8f68319 1795 #define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */
AnnaBridge 187:0387e8f68319 1796 #define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1797
AnnaBridge 187:0387e8f68319 1798 #define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */
AnnaBridge 187:0387e8f68319 1799 #define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */
AnnaBridge 187:0387e8f68319 1800
AnnaBridge 187:0387e8f68319 1801 #define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */
AnnaBridge 187:0387e8f68319 1802 #define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */
AnnaBridge 187:0387e8f68319 1803
AnnaBridge 187:0387e8f68319 1804 #define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */
AnnaBridge 187:0387e8f68319 1805 #define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */
AnnaBridge 187:0387e8f68319 1806
AnnaBridge 187:0387e8f68319 1807 #define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */
AnnaBridge 187:0387e8f68319 1808 #define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */
AnnaBridge 187:0387e8f68319 1809
AnnaBridge 187:0387e8f68319 1810 #define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */
AnnaBridge 187:0387e8f68319 1811 #define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */
AnnaBridge 187:0387e8f68319 1812
AnnaBridge 187:0387e8f68319 1813 #define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */
AnnaBridge 187:0387e8f68319 1814 #define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */
AnnaBridge 187:0387e8f68319 1815
AnnaBridge 187:0387e8f68319 1816 #define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */
AnnaBridge 187:0387e8f68319 1817 #define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */
AnnaBridge 187:0387e8f68319 1818
AnnaBridge 187:0387e8f68319 1819 #define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */
AnnaBridge 187:0387e8f68319 1820 #define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */
AnnaBridge 187:0387e8f68319 1821
AnnaBridge 187:0387e8f68319 1822 #define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */
AnnaBridge 187:0387e8f68319 1823 #define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */
AnnaBridge 187:0387e8f68319 1824
AnnaBridge 187:0387e8f68319 1825 #define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */
AnnaBridge 187:0387e8f68319 1826 #define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */
AnnaBridge 187:0387e8f68319 1827
AnnaBridge 187:0387e8f68319 1828 #define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */
AnnaBridge 187:0387e8f68319 1829 #define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */
AnnaBridge 187:0387e8f68319 1830
AnnaBridge 187:0387e8f68319 1831 #define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */
AnnaBridge 187:0387e8f68319 1832 #define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */
AnnaBridge 187:0387e8f68319 1833
AnnaBridge 187:0387e8f68319 1834 #define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */
AnnaBridge 187:0387e8f68319 1835 #define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */
AnnaBridge 187:0387e8f68319 1836
AnnaBridge 187:0387e8f68319 1837 #define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */
AnnaBridge 187:0387e8f68319 1838 #define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */
AnnaBridge 187:0387e8f68319 1839
AnnaBridge 187:0387e8f68319 1840 #define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */
AnnaBridge 187:0387e8f68319 1841 #define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */
AnnaBridge 187:0387e8f68319 1842
AnnaBridge 187:0387e8f68319 1843 #define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */
AnnaBridge 187:0387e8f68319 1844 #define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */
AnnaBridge 187:0387e8f68319 1845
AnnaBridge 187:0387e8f68319 1846 #define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */
AnnaBridge 187:0387e8f68319 1847 #define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */
AnnaBridge 187:0387e8f68319 1848
AnnaBridge 187:0387e8f68319 1849 #define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */
AnnaBridge 187:0387e8f68319 1850 #define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */
AnnaBridge 187:0387e8f68319 1851
AnnaBridge 187:0387e8f68319 1852 #define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */
AnnaBridge 187:0387e8f68319 1853 #define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */
AnnaBridge 187:0387e8f68319 1854
AnnaBridge 187:0387e8f68319 1855 #define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */
AnnaBridge 187:0387e8f68319 1856 #define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */
AnnaBridge 187:0387e8f68319 1857
AnnaBridge 187:0387e8f68319 1858 #define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */
AnnaBridge 187:0387e8f68319 1859 #define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */
AnnaBridge 187:0387e8f68319 1860
AnnaBridge 187:0387e8f68319 1861 #define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */
AnnaBridge 187:0387e8f68319 1862 #define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */
AnnaBridge 187:0387e8f68319 1863
AnnaBridge 187:0387e8f68319 1864 #define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */
AnnaBridge 187:0387e8f68319 1865 #define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */
AnnaBridge 187:0387e8f68319 1866
AnnaBridge 187:0387e8f68319 1867 #define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */
AnnaBridge 187:0387e8f68319 1868 #define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */
AnnaBridge 187:0387e8f68319 1869
AnnaBridge 187:0387e8f68319 1870 /**@}*/ /* BPWM_CONST */
AnnaBridge 187:0387e8f68319 1871 /**@}*/ /* end of BPWM register group */
AnnaBridge 187:0387e8f68319 1872
AnnaBridge 187:0387e8f68319 1873
AnnaBridge 187:0387e8f68319 1874 #endif /* __BPWM_REG_H__ */