SilentSensors / mbed-dev

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Fork of mbed-dev by mbed official

cmsis/TARGET_CORTEX_M/mpu_armv8.h@180:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
180:96ed750bd169
Child:
186:707f6e361f3e
mbed-dev libray. Release version 158

Who changed what in which revision?

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Anna Bridge 180:96ed750bd169 1 /******************************************************************************
Anna Bridge 180:96ed750bd169 2 * @file mpu_armv8.h
Anna Bridge 180:96ed750bd169 3 * @brief CMSIS MPU API for ARMv8 MPU
Anna Bridge 180:96ed750bd169 4 * @version V5.0.3
Anna Bridge 180:96ed750bd169 5 * @date 09. August 2017
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 180:96ed750bd169 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #ifndef ARM_MPU_ARMV8_H
Anna Bridge 180:96ed750bd169 26 #define ARM_MPU_ARMV8_H
Anna Bridge 180:96ed750bd169 27
Anna Bridge 180:96ed750bd169 28 /** \brief Attribute for device memory (outer only) */
Anna Bridge 180:96ed750bd169 29 #define ARM_MPU_ATTR_DEVICE ( 0U )
Anna Bridge 180:96ed750bd169 30
Anna Bridge 180:96ed750bd169 31 /** \brief Attribute for non-cacheable, normal memory */
Anna Bridge 180:96ed750bd169 32 #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
Anna Bridge 180:96ed750bd169 33
Anna Bridge 180:96ed750bd169 34 /** \brief Attribute for normal memory (outer and inner)
Anna Bridge 180:96ed750bd169 35 * \param NT Non-Transient: Set to 1 for non-transient data.
Anna Bridge 180:96ed750bd169 36 * \param WB Write-Back: Set to 1 to use write-back update policy.
Anna Bridge 180:96ed750bd169 37 * \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
Anna Bridge 180:96ed750bd169 38 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
Anna Bridge 180:96ed750bd169 39 */
Anna Bridge 180:96ed750bd169 40 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
Anna Bridge 180:96ed750bd169 41 (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
Anna Bridge 180:96ed750bd169 42
Anna Bridge 180:96ed750bd169 43 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
Anna Bridge 180:96ed750bd169 44 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
Anna Bridge 180:96ed750bd169 45
Anna Bridge 180:96ed750bd169 46 /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
Anna Bridge 180:96ed750bd169 47 #define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
Anna Bridge 180:96ed750bd169 48
Anna Bridge 180:96ed750bd169 49 /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
Anna Bridge 180:96ed750bd169 50 #define ARM_MPU_ATTR_DEVICE_nGRE (2U)
Anna Bridge 180:96ed750bd169 51
Anna Bridge 180:96ed750bd169 52 /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
Anna Bridge 180:96ed750bd169 53 #define ARM_MPU_ATTR_DEVICE_GRE (3U)
Anna Bridge 180:96ed750bd169 54
Anna Bridge 180:96ed750bd169 55 /** \brief Memory Attribute
Anna Bridge 180:96ed750bd169 56 * \param O Outer memory attributes
Anna Bridge 180:96ed750bd169 57 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
Anna Bridge 180:96ed750bd169 58 */
Anna Bridge 180:96ed750bd169 59 #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
Anna Bridge 180:96ed750bd169 60
Anna Bridge 180:96ed750bd169 61 /** \brief Normal memory non-shareable */
Anna Bridge 180:96ed750bd169 62 #define ARM_MPU_SH_NON (0U)
Anna Bridge 180:96ed750bd169 63
Anna Bridge 180:96ed750bd169 64 /** \brief Normal memory outer shareable */
Anna Bridge 180:96ed750bd169 65 #define ARM_MPU_SH_OUTER (2U)
Anna Bridge 180:96ed750bd169 66
Anna Bridge 180:96ed750bd169 67 /** \brief Normal memory inner shareable */
Anna Bridge 180:96ed750bd169 68 #define ARM_MPU_SH_INNER (3U)
Anna Bridge 180:96ed750bd169 69
Anna Bridge 180:96ed750bd169 70 /** \brief Memory access permissions
Anna Bridge 180:96ed750bd169 71 * \param RO Read-Only: Set to 1 for read-only memory.
Anna Bridge 180:96ed750bd169 72 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
Anna Bridge 180:96ed750bd169 73 */
Anna Bridge 180:96ed750bd169 74 #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
Anna Bridge 180:96ed750bd169 75
Anna Bridge 180:96ed750bd169 76 /** \brief Region Base Address Register value
Anna Bridge 180:96ed750bd169 77 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
Anna Bridge 180:96ed750bd169 78 * \param SH Defines the Shareability domain for this memory region.
Anna Bridge 180:96ed750bd169 79 * \param RO Read-Only: Set to 1 for a read-only memory region.
Anna Bridge 180:96ed750bd169 80 * \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
Anna Bridge 180:96ed750bd169 81 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
Anna Bridge 180:96ed750bd169 82 */
Anna Bridge 180:96ed750bd169 83 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
Anna Bridge 180:96ed750bd169 84 ((BASE & MPU_RBAR_BASE_Pos) | \
Anna Bridge 180:96ed750bd169 85 ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
Anna Bridge 180:96ed750bd169 86 ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
Anna Bridge 180:96ed750bd169 87 ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
Anna Bridge 180:96ed750bd169 88
Anna Bridge 180:96ed750bd169 89 /** \brief Region Limit Address Register value
Anna Bridge 180:96ed750bd169 90 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
Anna Bridge 180:96ed750bd169 91 * \param IDX The attribute index to be associated with this memory region.
Anna Bridge 180:96ed750bd169 92 */
Anna Bridge 180:96ed750bd169 93 #define ARM_MPU_RLAR(LIMIT, IDX) \
Anna Bridge 180:96ed750bd169 94 ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
Anna Bridge 180:96ed750bd169 95 ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
Anna Bridge 180:96ed750bd169 96 (MPU_RLAR_EN_Msk))
Anna Bridge 180:96ed750bd169 97
Anna Bridge 180:96ed750bd169 98 /**
Anna Bridge 180:96ed750bd169 99 * Struct for a single MPU Region
Anna Bridge 180:96ed750bd169 100 */
Anna Bridge 180:96ed750bd169 101 typedef struct _ARM_MPU_Region_t {
Anna Bridge 180:96ed750bd169 102 uint32_t RBAR; /*!< Region Base Address Register value */
Anna Bridge 180:96ed750bd169 103 uint32_t RLAR; /*!< Region Limit Address Register value */
Anna Bridge 180:96ed750bd169 104 } ARM_MPU_Region_t;
Anna Bridge 180:96ed750bd169 105
Anna Bridge 180:96ed750bd169 106 /** Enable the MPU.
Anna Bridge 180:96ed750bd169 107 * \param MPU_Control Default access permissions for unconfigured regions.
Anna Bridge 180:96ed750bd169 108 */
Anna Bridge 180:96ed750bd169 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Anna Bridge 180:96ed750bd169 110 {
Anna Bridge 180:96ed750bd169 111 __DSB();
Anna Bridge 180:96ed750bd169 112 __ISB();
Anna Bridge 180:96ed750bd169 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 116 #endif
Anna Bridge 180:96ed750bd169 117 }
Anna Bridge 180:96ed750bd169 118
Anna Bridge 180:96ed750bd169 119 /** Disable the MPU.
Anna Bridge 180:96ed750bd169 120 */
Anna Bridge 180:96ed750bd169 121 __STATIC_INLINE void ARM_MPU_Disable(void)
Anna Bridge 180:96ed750bd169 122 {
Anna Bridge 180:96ed750bd169 123 __DSB();
Anna Bridge 180:96ed750bd169 124 __ISB();
Anna Bridge 180:96ed750bd169 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 127 #endif
Anna Bridge 180:96ed750bd169 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 129 }
Anna Bridge 180:96ed750bd169 130
Anna Bridge 180:96ed750bd169 131 #ifdef MPU_NS
Anna Bridge 180:96ed750bd169 132 /** Enable the Non-secure MPU.
Anna Bridge 180:96ed750bd169 133 * \param MPU_Control Default access permissions for unconfigured regions.
Anna Bridge 180:96ed750bd169 134 */
Anna Bridge 180:96ed750bd169 135 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
Anna Bridge 180:96ed750bd169 136 {
Anna Bridge 180:96ed750bd169 137 __DSB();
Anna Bridge 180:96ed750bd169 138 __ISB();
Anna Bridge 180:96ed750bd169 139 MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 140 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 141 SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 142 #endif
Anna Bridge 180:96ed750bd169 143 }
Anna Bridge 180:96ed750bd169 144
Anna Bridge 180:96ed750bd169 145 /** Disable the Non-secure MPU.
Anna Bridge 180:96ed750bd169 146 */
Anna Bridge 180:96ed750bd169 147 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
Anna Bridge 180:96ed750bd169 148 {
Anna Bridge 180:96ed750bd169 149 __DSB();
Anna Bridge 180:96ed750bd169 150 __ISB();
Anna Bridge 180:96ed750bd169 151 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 152 SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 153 #endif
Anna Bridge 180:96ed750bd169 154 MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 155 }
Anna Bridge 180:96ed750bd169 156 #endif
Anna Bridge 180:96ed750bd169 157
Anna Bridge 180:96ed750bd169 158 /** Set the memory attribute encoding to the given MPU.
Anna Bridge 180:96ed750bd169 159 * \param mpu Pointer to the MPU to be configured.
Anna Bridge 180:96ed750bd169 160 * \param idx The attribute index to be set [0-7]
Anna Bridge 180:96ed750bd169 161 * \param attr The attribute value to be set.
Anna Bridge 180:96ed750bd169 162 */
Anna Bridge 180:96ed750bd169 163 __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
Anna Bridge 180:96ed750bd169 164 {
Anna Bridge 180:96ed750bd169 165 const uint8_t reg = idx / 4U;
Anna Bridge 180:96ed750bd169 166 const uint32_t pos = ((idx % 4U) * 8U);
Anna Bridge 180:96ed750bd169 167 const uint32_t mask = 0xFFU << pos;
Anna Bridge 180:96ed750bd169 168
Anna Bridge 180:96ed750bd169 169 if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) {
Anna Bridge 180:96ed750bd169 170 return; // invalid index
Anna Bridge 180:96ed750bd169 171 }
Anna Bridge 180:96ed750bd169 172
Anna Bridge 180:96ed750bd169 173 MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask));
Anna Bridge 180:96ed750bd169 174 }
Anna Bridge 180:96ed750bd169 175
Anna Bridge 180:96ed750bd169 176 /** Set the memory attribute encoding.
Anna Bridge 180:96ed750bd169 177 * \param idx The attribute index to be set [0-7]
Anna Bridge 180:96ed750bd169 178 * \param attr The attribute value to be set.
Anna Bridge 180:96ed750bd169 179 */
Anna Bridge 180:96ed750bd169 180 __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
Anna Bridge 180:96ed750bd169 181 {
Anna Bridge 180:96ed750bd169 182 ARM_MPU_SetMemAttrEx(MPU, idx, attr);
Anna Bridge 180:96ed750bd169 183 }
Anna Bridge 180:96ed750bd169 184
Anna Bridge 180:96ed750bd169 185 #ifdef MPU_NS
Anna Bridge 180:96ed750bd169 186 /** Set the memory attribute encoding to the Non-secure MPU.
Anna Bridge 180:96ed750bd169 187 * \param idx The attribute index to be set [0-7]
Anna Bridge 180:96ed750bd169 188 * \param attr The attribute value to be set.
Anna Bridge 180:96ed750bd169 189 */
Anna Bridge 180:96ed750bd169 190 __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
Anna Bridge 180:96ed750bd169 191 {
Anna Bridge 180:96ed750bd169 192 ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
Anna Bridge 180:96ed750bd169 193 }
Anna Bridge 180:96ed750bd169 194 #endif
Anna Bridge 180:96ed750bd169 195
Anna Bridge 180:96ed750bd169 196 /** Clear and disable the given MPU region of the given MPU.
Anna Bridge 180:96ed750bd169 197 * \param mpu Pointer to MPU to be used.
Anna Bridge 180:96ed750bd169 198 * \param rnr Region number to be cleared.
Anna Bridge 180:96ed750bd169 199 */
Anna Bridge 180:96ed750bd169 200 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
Anna Bridge 180:96ed750bd169 201 {
Anna Bridge 180:96ed750bd169 202 MPU->RNR = rnr;
Anna Bridge 180:96ed750bd169 203 MPU->RLAR = 0U;
Anna Bridge 180:96ed750bd169 204 }
Anna Bridge 180:96ed750bd169 205
Anna Bridge 180:96ed750bd169 206 /** Clear and disable the given MPU region.
Anna Bridge 180:96ed750bd169 207 * \param rnr Region number to be cleared.
Anna Bridge 180:96ed750bd169 208 */
Anna Bridge 180:96ed750bd169 209 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Anna Bridge 180:96ed750bd169 210 {
Anna Bridge 180:96ed750bd169 211 ARM_MPU_ClrRegionEx(MPU, rnr);
Anna Bridge 180:96ed750bd169 212 }
Anna Bridge 180:96ed750bd169 213
Anna Bridge 180:96ed750bd169 214 #ifdef MPU_NS
Anna Bridge 180:96ed750bd169 215 /** Clear and disable the given Non-secure MPU region.
Anna Bridge 180:96ed750bd169 216 * \param rnr Region number to be cleared.
Anna Bridge 180:96ed750bd169 217 */
Anna Bridge 180:96ed750bd169 218 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
Anna Bridge 180:96ed750bd169 219 {
Anna Bridge 180:96ed750bd169 220 ARM_MPU_ClrRegionEx(MPU_NS, rnr);
Anna Bridge 180:96ed750bd169 221 }
Anna Bridge 180:96ed750bd169 222 #endif
Anna Bridge 180:96ed750bd169 223
Anna Bridge 180:96ed750bd169 224 /** Configure the given MPU region of the given MPU.
Anna Bridge 180:96ed750bd169 225 * \param mpu Pointer to MPU to be used.
Anna Bridge 180:96ed750bd169 226 * \param rnr Region number to be configured.
Anna Bridge 180:96ed750bd169 227 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 228 * \param rlar Value for RLAR register.
Anna Bridge 180:96ed750bd169 229 */
Anna Bridge 180:96ed750bd169 230 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
Anna Bridge 180:96ed750bd169 231 {
Anna Bridge 180:96ed750bd169 232 MPU->RNR = rnr;
Anna Bridge 180:96ed750bd169 233 MPU->RBAR = rbar;
Anna Bridge 180:96ed750bd169 234 MPU->RLAR = rlar;
Anna Bridge 180:96ed750bd169 235 }
Anna Bridge 180:96ed750bd169 236
Anna Bridge 180:96ed750bd169 237 /** Configure the given MPU region.
Anna Bridge 180:96ed750bd169 238 * \param rnr Region number to be configured.
Anna Bridge 180:96ed750bd169 239 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 240 * \param rlar Value for RLAR register.
Anna Bridge 180:96ed750bd169 241 */
Anna Bridge 180:96ed750bd169 242 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Anna Bridge 180:96ed750bd169 243 {
Anna Bridge 180:96ed750bd169 244 ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
Anna Bridge 180:96ed750bd169 245 }
Anna Bridge 180:96ed750bd169 246
Anna Bridge 180:96ed750bd169 247 #ifdef MPU_NS
Anna Bridge 180:96ed750bd169 248 /** Configure the given Non-secure MPU region.
Anna Bridge 180:96ed750bd169 249 * \param rnr Region number to be configured.
Anna Bridge 180:96ed750bd169 250 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 251 * \param rlar Value for RLAR register.
Anna Bridge 180:96ed750bd169 252 */
Anna Bridge 180:96ed750bd169 253 __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
Anna Bridge 180:96ed750bd169 254 {
Anna Bridge 180:96ed750bd169 255 ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
Anna Bridge 180:96ed750bd169 256 }
Anna Bridge 180:96ed750bd169 257 #endif
Anna Bridge 180:96ed750bd169 258
Anna Bridge 180:96ed750bd169 259 /** Memcopy with strictly ordered memory access, e.g. for register targets.
Anna Bridge 180:96ed750bd169 260 * \param dst Destination data is copied to.
Anna Bridge 180:96ed750bd169 261 * \param src Source data is copied from.
Anna Bridge 180:96ed750bd169 262 * \param len Amount of data words to be copied.
Anna Bridge 180:96ed750bd169 263 */
Anna Bridge 180:96ed750bd169 264 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
Anna Bridge 180:96ed750bd169 265 {
Anna Bridge 180:96ed750bd169 266 uint32_t i;
Anna Bridge 180:96ed750bd169 267 for (i = 0U; i < len; ++i)
Anna Bridge 180:96ed750bd169 268 {
Anna Bridge 180:96ed750bd169 269 dst[i] = src[i];
Anna Bridge 180:96ed750bd169 270 }
Anna Bridge 180:96ed750bd169 271 }
Anna Bridge 180:96ed750bd169 272
Anna Bridge 180:96ed750bd169 273 /** Load the given number of MPU regions from a table to the given MPU.
Anna Bridge 180:96ed750bd169 274 * \param mpu Pointer to the MPU registers to be used.
Anna Bridge 180:96ed750bd169 275 * \param rnr First region number to be configured.
Anna Bridge 180:96ed750bd169 276 * \param table Pointer to the MPU configuration table.
Anna Bridge 180:96ed750bd169 277 * \param cnt Amount of regions to be configured.
Anna Bridge 180:96ed750bd169 278 */
Anna Bridge 180:96ed750bd169 279 __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 180:96ed750bd169 280 {
Anna Bridge 180:96ed750bd169 281 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Anna Bridge 180:96ed750bd169 282 if (cnt == 1U) {
Anna Bridge 180:96ed750bd169 283 mpu->RNR = rnr;
Anna Bridge 180:96ed750bd169 284 orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
Anna Bridge 180:96ed750bd169 285 } else {
Anna Bridge 180:96ed750bd169 286 uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
Anna Bridge 180:96ed750bd169 287 uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
Anna Bridge 180:96ed750bd169 288
Anna Bridge 180:96ed750bd169 289 mpu->RNR = rnrBase;
Anna Bridge 180:96ed750bd169 290 if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
Anna Bridge 180:96ed750bd169 291 uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
Anna Bridge 180:96ed750bd169 292 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
Anna Bridge 180:96ed750bd169 293 ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c);
Anna Bridge 180:96ed750bd169 294 } else {
Anna Bridge 180:96ed750bd169 295 orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
Anna Bridge 180:96ed750bd169 296 }
Anna Bridge 180:96ed750bd169 297 }
Anna Bridge 180:96ed750bd169 298 }
Anna Bridge 180:96ed750bd169 299
Anna Bridge 180:96ed750bd169 300 /** Load the given number of MPU regions from a table.
Anna Bridge 180:96ed750bd169 301 * \param rnr First region number to be configured.
Anna Bridge 180:96ed750bd169 302 * \param table Pointer to the MPU configuration table.
Anna Bridge 180:96ed750bd169 303 * \param cnt Amount of regions to be configured.
Anna Bridge 180:96ed750bd169 304 */
Anna Bridge 180:96ed750bd169 305 __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 180:96ed750bd169 306 {
Anna Bridge 180:96ed750bd169 307 ARM_MPU_LoadEx(MPU, rnr, table, cnt);
Anna Bridge 180:96ed750bd169 308 }
Anna Bridge 180:96ed750bd169 309
Anna Bridge 180:96ed750bd169 310 #ifdef MPU_NS
Anna Bridge 180:96ed750bd169 311 /** Load the given number of MPU regions from a table to the Non-secure MPU.
Anna Bridge 180:96ed750bd169 312 * \param rnr First region number to be configured.
Anna Bridge 180:96ed750bd169 313 * \param table Pointer to the MPU configuration table.
Anna Bridge 180:96ed750bd169 314 * \param cnt Amount of regions to be configured.
Anna Bridge 180:96ed750bd169 315 */
Anna Bridge 180:96ed750bd169 316 __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 180:96ed750bd169 317 {
Anna Bridge 180:96ed750bd169 318 ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
Anna Bridge 180:96ed750bd169 319 }
Anna Bridge 180:96ed750bd169 320 #endif
Anna Bridge 180:96ed750bd169 321
Anna Bridge 180:96ed750bd169 322 #endif
Anna Bridge 180:96ed750bd169 323