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cmsis/TARGET_CORTEX_M/mpu_armv7.h@180:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
180:96ed750bd169
Child:
186:707f6e361f3e
mbed-dev libray. Release version 158

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Anna Bridge 180:96ed750bd169 1 /******************************************************************************
Anna Bridge 180:96ed750bd169 2 * @file mpu_armv7.h
Anna Bridge 180:96ed750bd169 3 * @brief CMSIS MPU API for ARMv7 MPU
Anna Bridge 180:96ed750bd169 4 * @version V5.0.3
Anna Bridge 180:96ed750bd169 5 * @date 09. August 2017
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 180:96ed750bd169 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #ifndef ARM_MPU_ARMV7_H
Anna Bridge 180:96ed750bd169 26 #define ARM_MPU_ARMV7_H
Anna Bridge 180:96ed750bd169 27
Anna Bridge 180:96ed750bd169 28 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
Anna Bridge 180:96ed750bd169 29 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
Anna Bridge 180:96ed750bd169 30 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
Anna Bridge 180:96ed750bd169 31 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
Anna Bridge 180:96ed750bd169 32 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
Anna Bridge 180:96ed750bd169 33 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
Anna Bridge 180:96ed750bd169 34 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
Anna Bridge 180:96ed750bd169 35 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
Anna Bridge 180:96ed750bd169 36 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
Anna Bridge 180:96ed750bd169 37 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
Anna Bridge 180:96ed750bd169 38 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
Anna Bridge 180:96ed750bd169 39 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
Anna Bridge 180:96ed750bd169 40 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
Anna Bridge 180:96ed750bd169 41 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
Anna Bridge 180:96ed750bd169 42 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
Anna Bridge 180:96ed750bd169 43 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
Anna Bridge 180:96ed750bd169 44 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
Anna Bridge 180:96ed750bd169 45 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
Anna Bridge 180:96ed750bd169 46 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
Anna Bridge 180:96ed750bd169 47 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
Anna Bridge 180:96ed750bd169 48 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
Anna Bridge 180:96ed750bd169 49 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
Anna Bridge 180:96ed750bd169 50 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
Anna Bridge 180:96ed750bd169 51 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
Anna Bridge 180:96ed750bd169 52 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
Anna Bridge 180:96ed750bd169 53 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
Anna Bridge 180:96ed750bd169 54 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
Anna Bridge 180:96ed750bd169 55 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
Anna Bridge 180:96ed750bd169 56
Anna Bridge 180:96ed750bd169 57 #define ARM_MPU_AP_NONE 0U
Anna Bridge 180:96ed750bd169 58 #define ARM_MPU_AP_PRIV 1U
Anna Bridge 180:96ed750bd169 59 #define ARM_MPU_AP_URO 2U
Anna Bridge 180:96ed750bd169 60 #define ARM_MPU_AP_FULL 3U
Anna Bridge 180:96ed750bd169 61 #define ARM_MPU_AP_PRO 5U
Anna Bridge 180:96ed750bd169 62 #define ARM_MPU_AP_RO 6U
Anna Bridge 180:96ed750bd169 63
Anna Bridge 180:96ed750bd169 64 /** MPU Region Base Address Register Value
Anna Bridge 180:96ed750bd169 65 *
Anna Bridge 180:96ed750bd169 66 * \param Region The region to be configured, number 0 to 15.
Anna Bridge 180:96ed750bd169 67 * \param BaseAddress The base address for the region.
Anna Bridge 180:96ed750bd169 68 */
Anna Bridge 180:96ed750bd169 69 #define ARM_MPU_RBAR(Region, BaseAddress) \
Anna Bridge 180:96ed750bd169 70 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
Anna Bridge 180:96ed750bd169 71 ((Region) & MPU_RBAR_REGION_Msk) | \
Anna Bridge 180:96ed750bd169 72 (MPU_RBAR_VALID_Msk))
Anna Bridge 180:96ed750bd169 73
Anna Bridge 180:96ed750bd169 74 /**
Anna Bridge 180:96ed750bd169 75 * MPU Region Attribut and Size Register Value
Anna Bridge 180:96ed750bd169 76 *
Anna Bridge 180:96ed750bd169 77 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
Anna Bridge 180:96ed750bd169 78 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
Anna Bridge 180:96ed750bd169 79 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
Anna Bridge 180:96ed750bd169 80 * \param IsShareable Region is shareable between multiple bus masters.
Anna Bridge 180:96ed750bd169 81 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
Anna Bridge 180:96ed750bd169 82 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
Anna Bridge 180:96ed750bd169 83 * \param SubRegionDisable Sub-region disable field.
Anna Bridge 180:96ed750bd169 84 * \param Size Region size of the region to be configured, for example 4K, 8K.
Anna Bridge 180:96ed750bd169 85 */
Anna Bridge 180:96ed750bd169 86 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
Anna Bridge 180:96ed750bd169 87 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
Anna Bridge 180:96ed750bd169 88 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
Anna Bridge 180:96ed750bd169 89 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
Anna Bridge 180:96ed750bd169 90 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
Anna Bridge 180:96ed750bd169 91 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
Anna Bridge 180:96ed750bd169 92 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
Anna Bridge 180:96ed750bd169 93 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
Anna Bridge 180:96ed750bd169 94 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
Anna Bridge 180:96ed750bd169 95 (MPU_RASR_ENABLE_Msk))
Anna Bridge 180:96ed750bd169 96
Anna Bridge 180:96ed750bd169 97
Anna Bridge 180:96ed750bd169 98 /**
Anna Bridge 180:96ed750bd169 99 * Struct for a single MPU Region
Anna Bridge 180:96ed750bd169 100 */
Anna Bridge 180:96ed750bd169 101 typedef struct _ARM_MPU_Region_t {
Anna Bridge 180:96ed750bd169 102 uint32_t RBAR; //!< The region base address register value (RBAR)
Anna Bridge 180:96ed750bd169 103 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
Anna Bridge 180:96ed750bd169 104 } ARM_MPU_Region_t;
Anna Bridge 180:96ed750bd169 105
Anna Bridge 180:96ed750bd169 106 /** Enable the MPU.
Anna Bridge 180:96ed750bd169 107 * \param MPU_Control Default access permissions for unconfigured regions.
Anna Bridge 180:96ed750bd169 108 */
Anna Bridge 180:96ed750bd169 109 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Anna Bridge 180:96ed750bd169 110 {
Anna Bridge 180:96ed750bd169 111 __DSB();
Anna Bridge 180:96ed750bd169 112 __ISB();
Anna Bridge 180:96ed750bd169 113 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 114 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 115 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 116 #endif
Anna Bridge 180:96ed750bd169 117 }
Anna Bridge 180:96ed750bd169 118
Anna Bridge 180:96ed750bd169 119 /** Disable the MPU.
Anna Bridge 180:96ed750bd169 120 */
Anna Bridge 180:96ed750bd169 121 __STATIC_INLINE void ARM_MPU_Disable(void)
Anna Bridge 180:96ed750bd169 122 {
Anna Bridge 180:96ed750bd169 123 __DSB();
Anna Bridge 180:96ed750bd169 124 __ISB();
Anna Bridge 180:96ed750bd169 125 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 126 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 127 #endif
Anna Bridge 180:96ed750bd169 128 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 129 }
Anna Bridge 180:96ed750bd169 130
Anna Bridge 180:96ed750bd169 131 /** Clear and disable the given MPU region.
Anna Bridge 180:96ed750bd169 132 * \param rnr Region number to be cleared.
Anna Bridge 180:96ed750bd169 133 */
Anna Bridge 180:96ed750bd169 134 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Anna Bridge 180:96ed750bd169 135 {
Anna Bridge 180:96ed750bd169 136 MPU->RNR = rnr;
Anna Bridge 180:96ed750bd169 137 MPU->RASR = 0U;
Anna Bridge 180:96ed750bd169 138 }
Anna Bridge 180:96ed750bd169 139
Anna Bridge 180:96ed750bd169 140 /** Configure an MPU region.
Anna Bridge 180:96ed750bd169 141 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 142 * \param rsar Value for RSAR register.
Anna Bridge 180:96ed750bd169 143 */
Anna Bridge 180:96ed750bd169 144 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
Anna Bridge 180:96ed750bd169 145 {
Anna Bridge 180:96ed750bd169 146 MPU->RBAR = rbar;
Anna Bridge 180:96ed750bd169 147 MPU->RASR = rasr;
Anna Bridge 180:96ed750bd169 148 }
Anna Bridge 180:96ed750bd169 149
Anna Bridge 180:96ed750bd169 150 /** Configure the given MPU region.
Anna Bridge 180:96ed750bd169 151 * \param rnr Region number to be configured.
Anna Bridge 180:96ed750bd169 152 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 153 * \param rsar Value for RSAR register.
Anna Bridge 180:96ed750bd169 154 */
Anna Bridge 180:96ed750bd169 155 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
Anna Bridge 180:96ed750bd169 156 {
Anna Bridge 180:96ed750bd169 157 MPU->RNR = rnr;
Anna Bridge 180:96ed750bd169 158 MPU->RBAR = rbar;
Anna Bridge 180:96ed750bd169 159 MPU->RASR = rasr;
Anna Bridge 180:96ed750bd169 160 }
Anna Bridge 180:96ed750bd169 161
Anna Bridge 180:96ed750bd169 162 /** Memcopy with strictly ordered memory access, e.g. for register targets.
Anna Bridge 180:96ed750bd169 163 * \param dst Destination data is copied to.
Anna Bridge 180:96ed750bd169 164 * \param src Source data is copied from.
Anna Bridge 180:96ed750bd169 165 * \param len Amount of data words to be copied.
Anna Bridge 180:96ed750bd169 166 */
Anna Bridge 180:96ed750bd169 167 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
Anna Bridge 180:96ed750bd169 168 {
Anna Bridge 180:96ed750bd169 169 uint32_t i;
Anna Bridge 180:96ed750bd169 170 for (i = 0U; i < len; ++i)
Anna Bridge 180:96ed750bd169 171 {
Anna Bridge 180:96ed750bd169 172 dst[i] = src[i];
Anna Bridge 180:96ed750bd169 173 }
Anna Bridge 180:96ed750bd169 174 }
Anna Bridge 180:96ed750bd169 175
Anna Bridge 180:96ed750bd169 176 /** Load the given number of MPU regions from a table.
Anna Bridge 180:96ed750bd169 177 * \param table Pointer to the MPU configuration table.
Anna Bridge 180:96ed750bd169 178 * \param cnt Amount of regions to be configured.
Anna Bridge 180:96ed750bd169 179 */
Anna Bridge 180:96ed750bd169 180 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 180:96ed750bd169 181 {
Anna Bridge 180:96ed750bd169 182 static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Anna Bridge 180:96ed750bd169 183 if (cnt > MPU_TYPE_RALIASES) {
Anna Bridge 180:96ed750bd169 184 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
Anna Bridge 180:96ed750bd169 185 ARM_MPU_Load(table+MPU_TYPE_RALIASES, cnt-MPU_TYPE_RALIASES);
Anna Bridge 180:96ed750bd169 186 } else {
Anna Bridge 180:96ed750bd169 187 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
Anna Bridge 180:96ed750bd169 188 }
Anna Bridge 180:96ed750bd169 189 }
Anna Bridge 180:96ed750bd169 190
Anna Bridge 180:96ed750bd169 191 #endif