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lwip-eth/arch/TARGET_NXP/lpc17xx_emac.h@0:d7bd7384a37c, 2016-12-07 (annotated)

Committer:
grzemich
Date:
Wed Dec 07 23:47:50 2016 +0000
Revision:
0:d7bd7384a37c
dgd

Who changed what in which revision?

UserRevisionLine numberNew contents of line
grzemich 0:d7bd7384a37c 1 /**********************************************************************
grzemich 0:d7bd7384a37c 2 * $Id$ lpc17xx_emac.h 2010-05-21
grzemich 0:d7bd7384a37c 3 *//**
grzemich 0:d7bd7384a37c 4 * @file lpc17xx_emac.h
grzemich 0:d7bd7384a37c 5 * @brief Contains all macro definitions and function prototypes
grzemich 0:d7bd7384a37c 6 * support for Ethernet MAC firmware library on LPC17xx
grzemich 0:d7bd7384a37c 7 * @version 2.0
grzemich 0:d7bd7384a37c 8 * @date 21. May. 2010
grzemich 0:d7bd7384a37c 9 * @author NXP MCU SW Application Team
grzemich 0:d7bd7384a37c 10 *
grzemich 0:d7bd7384a37c 11 * Copyright(C) 2010, NXP Semiconductor
grzemich 0:d7bd7384a37c 12 * All rights reserved.
grzemich 0:d7bd7384a37c 13 *
grzemich 0:d7bd7384a37c 14 ***********************************************************************
grzemich 0:d7bd7384a37c 15 * Software that is described herein is for illustrative purposes only
grzemich 0:d7bd7384a37c 16 * which provides customers with programming information regarding the
grzemich 0:d7bd7384a37c 17 * products. This software is supplied "AS IS" without any warranties.
grzemich 0:d7bd7384a37c 18 * NXP Semiconductors assumes no responsibility or liability for the
grzemich 0:d7bd7384a37c 19 * use of the software, conveys no license or title under any patent,
grzemich 0:d7bd7384a37c 20 * copyright, or mask work right to the product. NXP Semiconductors
grzemich 0:d7bd7384a37c 21 * reserves the right to make changes in the software without
grzemich 0:d7bd7384a37c 22 * notification. NXP Semiconductors also make no representation or
grzemich 0:d7bd7384a37c 23 * warranty that such application will be suitable for the specified
grzemich 0:d7bd7384a37c 24 * use without further testing or modification.
grzemich 0:d7bd7384a37c 25 **********************************************************************/
grzemich 0:d7bd7384a37c 26
grzemich 0:d7bd7384a37c 27 /* Peripheral group ----------------------------------------------------------- */
grzemich 0:d7bd7384a37c 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
grzemich 0:d7bd7384a37c 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
grzemich 0:d7bd7384a37c 30 * @{
grzemich 0:d7bd7384a37c 31 */
grzemich 0:d7bd7384a37c 32
grzemich 0:d7bd7384a37c 33 #ifndef LPC17XX_EMAC_H_
grzemich 0:d7bd7384a37c 34 #define LPC17XX_EMAC_H_
grzemich 0:d7bd7384a37c 35
grzemich 0:d7bd7384a37c 36 /* Includes ------------------------------------------------------------------- */
grzemich 0:d7bd7384a37c 37 #include "cmsis.h"
grzemich 0:d7bd7384a37c 38
grzemich 0:d7bd7384a37c 39 #ifdef __cplusplus
grzemich 0:d7bd7384a37c 40 extern "C"
grzemich 0:d7bd7384a37c 41 {
grzemich 0:d7bd7384a37c 42 #endif
grzemich 0:d7bd7384a37c 43
grzemich 0:d7bd7384a37c 44 #define MCB_LPC_1768
grzemich 0:d7bd7384a37c 45 //#define IAR_LPC_1768
grzemich 0:d7bd7384a37c 46
grzemich 0:d7bd7384a37c 47 /* Public Macros -------------------------------------------------------------- */
grzemich 0:d7bd7384a37c 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
grzemich 0:d7bd7384a37c 49 * @{
grzemich 0:d7bd7384a37c 50 */
grzemich 0:d7bd7384a37c 51
grzemich 0:d7bd7384a37c 52
grzemich 0:d7bd7384a37c 53 /* EMAC PHY status type definitions */
grzemich 0:d7bd7384a37c 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
grzemich 0:d7bd7384a37c 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
grzemich 0:d7bd7384a37c 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
grzemich 0:d7bd7384a37c 57
grzemich 0:d7bd7384a37c 58 /* EMAC PHY device Speed definitions */
grzemich 0:d7bd7384a37c 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
grzemich 0:d7bd7384a37c 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
grzemich 0:d7bd7384a37c 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
grzemich 0:d7bd7384a37c 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
grzemich 0:d7bd7384a37c 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
grzemich 0:d7bd7384a37c 64
grzemich 0:d7bd7384a37c 65 /**
grzemich 0:d7bd7384a37c 66 * @}
grzemich 0:d7bd7384a37c 67 */
grzemich 0:d7bd7384a37c 68 /* Private Macros ------------------------------------------------------------- */
grzemich 0:d7bd7384a37c 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
grzemich 0:d7bd7384a37c 70 * @{
grzemich 0:d7bd7384a37c 71 */
grzemich 0:d7bd7384a37c 72
grzemich 0:d7bd7384a37c 73
grzemich 0:d7bd7384a37c 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
grzemich 0:d7bd7384a37c 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
grzemich 0:d7bd7384a37c 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
grzemich 0:d7bd7384a37c 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
grzemich 0:d7bd7384a37c 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
grzemich 0:d7bd7384a37c 79
grzemich 0:d7bd7384a37c 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
grzemich 0:d7bd7384a37c 81 /*********************************************************************//**
grzemich 0:d7bd7384a37c 82 * Macro defines for MAC Configuration Register 1
grzemich 0:d7bd7384a37c 83 **********************************************************************/
grzemich 0:d7bd7384a37c 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
grzemich 0:d7bd7384a37c 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
grzemich 0:d7bd7384a37c 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
grzemich 0:d7bd7384a37c 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
grzemich 0:d7bd7384a37c 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
grzemich 0:d7bd7384a37c 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
grzemich 0:d7bd7384a37c 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
grzemich 0:d7bd7384a37c 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
grzemich 0:d7bd7384a37c 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
grzemich 0:d7bd7384a37c 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
grzemich 0:d7bd7384a37c 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
grzemich 0:d7bd7384a37c 95
grzemich 0:d7bd7384a37c 96 /*********************************************************************//**
grzemich 0:d7bd7384a37c 97 * Macro defines for MAC Configuration Register 2
grzemich 0:d7bd7384a37c 98 **********************************************************************/
grzemich 0:d7bd7384a37c 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
grzemich 0:d7bd7384a37c 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
grzemich 0:d7bd7384a37c 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
grzemich 0:d7bd7384a37c 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
grzemich 0:d7bd7384a37c 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
grzemich 0:d7bd7384a37c 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
grzemich 0:d7bd7384a37c 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
grzemich 0:d7bd7384a37c 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
grzemich 0:d7bd7384a37c 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
grzemich 0:d7bd7384a37c 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
grzemich 0:d7bd7384a37c 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
grzemich 0:d7bd7384a37c 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
grzemich 0:d7bd7384a37c 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
grzemich 0:d7bd7384a37c 112
grzemich 0:d7bd7384a37c 113 /*********************************************************************//**
grzemich 0:d7bd7384a37c 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
grzemich 0:d7bd7384a37c 115 **********************************************************************/
grzemich 0:d7bd7384a37c 116 /** Programmable field representing the nibble time offset of the minimum possible period
grzemich 0:d7bd7384a37c 117 * between the end of any transmitted packet to the beginning of the next */
grzemich 0:d7bd7384a37c 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
grzemich 0:d7bd7384a37c 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
grzemich 0:d7bd7384a37c 120 * offset of the minimum possible period between the end of any transmitted packet to the
grzemich 0:d7bd7384a37c 121 * beginning of the next */
grzemich 0:d7bd7384a37c 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
grzemich 0:d7bd7384a37c 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
grzemich 0:d7bd7384a37c 124 * offset of the minimum possible period between the end of any transmitted packet to the
grzemich 0:d7bd7384a37c 125 * beginning of the next */
grzemich 0:d7bd7384a37c 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
grzemich 0:d7bd7384a37c 127
grzemich 0:d7bd7384a37c 128 /*********************************************************************//**
grzemich 0:d7bd7384a37c 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
grzemich 0:d7bd7384a37c 130 **********************************************************************/
grzemich 0:d7bd7384a37c 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
grzemich 0:d7bd7384a37c 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
grzemich 0:d7bd7384a37c 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
grzemich 0:d7bd7384a37c 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
grzemich 0:d7bd7384a37c 135 /** Programmable field representing the optional carrierSense window referenced in
grzemich 0:d7bd7384a37c 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
grzemich 0:d7bd7384a37c 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
grzemich 0:d7bd7384a37c 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
grzemich 0:d7bd7384a37c 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
grzemich 0:d7bd7384a37c 140
grzemich 0:d7bd7384a37c 141 /*********************************************************************//**
grzemich 0:d7bd7384a37c 142 * Macro defines for Collision Window/Retry Register
grzemich 0:d7bd7384a37c 143 **********************************************************************/
grzemich 0:d7bd7384a37c 144 /** Programmable field specifying the number of retransmission attempts following a collision before
grzemich 0:d7bd7384a37c 145 * aborting the packet due to excessive collisions */
grzemich 0:d7bd7384a37c 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
grzemich 0:d7bd7384a37c 147 /** Programmable field representing the slot time or collision window during which collisions occur
grzemich 0:d7bd7384a37c 148 * in properly configured networks */
grzemich 0:d7bd7384a37c 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
grzemich 0:d7bd7384a37c 150 /** Default value for Collision Window / Retry register */
grzemich 0:d7bd7384a37c 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
grzemich 0:d7bd7384a37c 152
grzemich 0:d7bd7384a37c 153 /*********************************************************************//**
grzemich 0:d7bd7384a37c 154 * Macro defines for Maximum Frame Register
grzemich 0:d7bd7384a37c 155 **********************************************************************/
grzemich 0:d7bd7384a37c 156 /** Represents a maximum receive frame of 1536 octets */
grzemich 0:d7bd7384a37c 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
grzemich 0:d7bd7384a37c 158
grzemich 0:d7bd7384a37c 159 /*********************************************************************//**
grzemich 0:d7bd7384a37c 160 * Macro defines for PHY Support Register
grzemich 0:d7bd7384a37c 161 **********************************************************************/
grzemich 0:d7bd7384a37c 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
grzemich 0:d7bd7384a37c 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
grzemich 0:d7bd7384a37c 164
grzemich 0:d7bd7384a37c 165 /*********************************************************************//**
grzemich 0:d7bd7384a37c 166 * Macro defines for Test Register
grzemich 0:d7bd7384a37c 167 **********************************************************************/
grzemich 0:d7bd7384a37c 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
grzemich 0:d7bd7384a37c 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
grzemich 0:d7bd7384a37c 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
grzemich 0:d7bd7384a37c 171
grzemich 0:d7bd7384a37c 172 /*********************************************************************//**
grzemich 0:d7bd7384a37c 173 * Macro defines for MII Management Configuration Register
grzemich 0:d7bd7384a37c 174 **********************************************************************/
grzemich 0:d7bd7384a37c 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
grzemich 0:d7bd7384a37c 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
grzemich 0:d7bd7384a37c 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
grzemich 0:d7bd7384a37c 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
grzemich 0:d7bd7384a37c 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
grzemich 0:d7bd7384a37c 180
grzemich 0:d7bd7384a37c 181 /*********************************************************************//**
grzemich 0:d7bd7384a37c 182 * Macro defines for MII Management Command Register
grzemich 0:d7bd7384a37c 183 **********************************************************************/
grzemich 0:d7bd7384a37c 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
grzemich 0:d7bd7384a37c 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
grzemich 0:d7bd7384a37c 186
grzemich 0:d7bd7384a37c 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
grzemich 0:d7bd7384a37c 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
grzemich 0:d7bd7384a37c 189
grzemich 0:d7bd7384a37c 190 /*********************************************************************//**
grzemich 0:d7bd7384a37c 191 * Macro defines for MII Management Address Register
grzemich 0:d7bd7384a37c 192 **********************************************************************/
grzemich 0:d7bd7384a37c 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
grzemich 0:d7bd7384a37c 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
grzemich 0:d7bd7384a37c 195
grzemich 0:d7bd7384a37c 196 /*********************************************************************//**
grzemich 0:d7bd7384a37c 197 * Macro defines for MII Management Write Data Register
grzemich 0:d7bd7384a37c 198 **********************************************************************/
grzemich 0:d7bd7384a37c 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
grzemich 0:d7bd7384a37c 200
grzemich 0:d7bd7384a37c 201 /*********************************************************************//**
grzemich 0:d7bd7384a37c 202 * Macro defines for MII Management Read Data Register
grzemich 0:d7bd7384a37c 203 **********************************************************************/
grzemich 0:d7bd7384a37c 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
grzemich 0:d7bd7384a37c 205
grzemich 0:d7bd7384a37c 206 /*********************************************************************//**
grzemich 0:d7bd7384a37c 207 * Macro defines for MII Management Indicators Register
grzemich 0:d7bd7384a37c 208 **********************************************************************/
grzemich 0:d7bd7384a37c 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
grzemich 0:d7bd7384a37c 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
grzemich 0:d7bd7384a37c 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
grzemich 0:d7bd7384a37c 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
grzemich 0:d7bd7384a37c 213
grzemich 0:d7bd7384a37c 214 /* Station Address 0 Register */
grzemich 0:d7bd7384a37c 215 /* Station Address 1 Register */
grzemich 0:d7bd7384a37c 216 /* Station Address 2 Register */
grzemich 0:d7bd7384a37c 217
grzemich 0:d7bd7384a37c 218
grzemich 0:d7bd7384a37c 219 /* Control register definitions --------------------------------------------------------------------------- */
grzemich 0:d7bd7384a37c 220 /*********************************************************************//**
grzemich 0:d7bd7384a37c 221 * Macro defines for Command Register
grzemich 0:d7bd7384a37c 222 **********************************************************************/
grzemich 0:d7bd7384a37c 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
grzemich 0:d7bd7384a37c 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
grzemich 0:d7bd7384a37c 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
grzemich 0:d7bd7384a37c 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
grzemich 0:d7bd7384a37c 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
grzemich 0:d7bd7384a37c 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
grzemich 0:d7bd7384a37c 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
grzemich 0:d7bd7384a37c 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
grzemich 0:d7bd7384a37c 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
grzemich 0:d7bd7384a37c 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
grzemich 0:d7bd7384a37c 233
grzemich 0:d7bd7384a37c 234 /*********************************************************************//**
grzemich 0:d7bd7384a37c 235 * Macro defines for Status Register
grzemich 0:d7bd7384a37c 236 **********************************************************************/
grzemich 0:d7bd7384a37c 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
grzemich 0:d7bd7384a37c 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
grzemich 0:d7bd7384a37c 239
grzemich 0:d7bd7384a37c 240 /*********************************************************************//**
grzemich 0:d7bd7384a37c 241 * Macro defines for Transmit Status Vector 0 Register
grzemich 0:d7bd7384a37c 242 **********************************************************************/
grzemich 0:d7bd7384a37c 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
grzemich 0:d7bd7384a37c 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
grzemich 0:d7bd7384a37c 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
grzemich 0:d7bd7384a37c 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
grzemich 0:d7bd7384a37c 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
grzemich 0:d7bd7384a37c 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
grzemich 0:d7bd7384a37c 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
grzemich 0:d7bd7384a37c 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
grzemich 0:d7bd7384a37c 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
grzemich 0:d7bd7384a37c 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
grzemich 0:d7bd7384a37c 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
grzemich 0:d7bd7384a37c 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
grzemich 0:d7bd7384a37c 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
grzemich 0:d7bd7384a37c 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
grzemich 0:d7bd7384a37c 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
grzemich 0:d7bd7384a37c 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
grzemich 0:d7bd7384a37c 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
grzemich 0:d7bd7384a37c 260
grzemich 0:d7bd7384a37c 261 /*********************************************************************//**
grzemich 0:d7bd7384a37c 262 * Macro defines for Transmit Status Vector 1 Register
grzemich 0:d7bd7384a37c 263 **********************************************************************/
grzemich 0:d7bd7384a37c 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
grzemich 0:d7bd7384a37c 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
grzemich 0:d7bd7384a37c 266
grzemich 0:d7bd7384a37c 267 /*********************************************************************//**
grzemich 0:d7bd7384a37c 268 * Macro defines for Receive Status Vector Register
grzemich 0:d7bd7384a37c 269 **********************************************************************/
grzemich 0:d7bd7384a37c 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
grzemich 0:d7bd7384a37c 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
grzemich 0:d7bd7384a37c 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
grzemich 0:d7bd7384a37c 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
grzemich 0:d7bd7384a37c 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
grzemich 0:d7bd7384a37c 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
grzemich 0:d7bd7384a37c 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
grzemich 0:d7bd7384a37c 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
grzemich 0:d7bd7384a37c 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
grzemich 0:d7bd7384a37c 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
grzemich 0:d7bd7384a37c 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
grzemich 0:d7bd7384a37c 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
grzemich 0:d7bd7384a37c 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
grzemich 0:d7bd7384a37c 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
grzemich 0:d7bd7384a37c 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
grzemich 0:d7bd7384a37c 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
grzemich 0:d7bd7384a37c 286
grzemich 0:d7bd7384a37c 287 /*********************************************************************//**
grzemich 0:d7bd7384a37c 288 * Macro defines for Flow Control Counter Register
grzemich 0:d7bd7384a37c 289 **********************************************************************/
grzemich 0:d7bd7384a37c 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
grzemich 0:d7bd7384a37c 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
grzemich 0:d7bd7384a37c 292
grzemich 0:d7bd7384a37c 293 /*********************************************************************//**
grzemich 0:d7bd7384a37c 294 * Macro defines for Flow Control Status Register
grzemich 0:d7bd7384a37c 295 **********************************************************************/
grzemich 0:d7bd7384a37c 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
grzemich 0:d7bd7384a37c 297
grzemich 0:d7bd7384a37c 298
grzemich 0:d7bd7384a37c 299 /* Receive filter register definitions -------------------------------------------------------- */
grzemich 0:d7bd7384a37c 300 /*********************************************************************//**
grzemich 0:d7bd7384a37c 301 * Macro defines for Receive Filter Control Register
grzemich 0:d7bd7384a37c 302 **********************************************************************/
grzemich 0:d7bd7384a37c 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
grzemich 0:d7bd7384a37c 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
grzemich 0:d7bd7384a37c 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
grzemich 0:d7bd7384a37c 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
grzemich 0:d7bd7384a37c 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
grzemich 0:d7bd7384a37c 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
grzemich 0:d7bd7384a37c 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
grzemich 0:d7bd7384a37c 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
grzemich 0:d7bd7384a37c 311
grzemich 0:d7bd7384a37c 312 /*********************************************************************//**
grzemich 0:d7bd7384a37c 313 * Macro defines for Receive Filter WoL Status/Clear Registers
grzemich 0:d7bd7384a37c 314 **********************************************************************/
grzemich 0:d7bd7384a37c 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
grzemich 0:d7bd7384a37c 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
grzemich 0:d7bd7384a37c 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
grzemich 0:d7bd7384a37c 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
grzemich 0:d7bd7384a37c 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
grzemich 0:d7bd7384a37c 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
grzemich 0:d7bd7384a37c 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
grzemich 0:d7bd7384a37c 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
grzemich 0:d7bd7384a37c 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
grzemich 0:d7bd7384a37c 324
grzemich 0:d7bd7384a37c 325
grzemich 0:d7bd7384a37c 326 /* Module control register definitions ---------------------------------------------------- */
grzemich 0:d7bd7384a37c 327 /*********************************************************************//**
grzemich 0:d7bd7384a37c 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
grzemich 0:d7bd7384a37c 329 **********************************************************************/
grzemich 0:d7bd7384a37c 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
grzemich 0:d7bd7384a37c 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
grzemich 0:d7bd7384a37c 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
grzemich 0:d7bd7384a37c 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
grzemich 0:d7bd7384a37c 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
grzemich 0:d7bd7384a37c 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
grzemich 0:d7bd7384a37c 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
grzemich 0:d7bd7384a37c 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
grzemich 0:d7bd7384a37c 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
grzemich 0:d7bd7384a37c 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
grzemich 0:d7bd7384a37c 340
grzemich 0:d7bd7384a37c 341 /*********************************************************************//**
grzemich 0:d7bd7384a37c 342 * Macro defines for Power Down Register
grzemich 0:d7bd7384a37c 343 **********************************************************************/
grzemich 0:d7bd7384a37c 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
grzemich 0:d7bd7384a37c 345
grzemich 0:d7bd7384a37c 346 /* Descriptor and status formats ---------------------------------------------------- */
grzemich 0:d7bd7384a37c 347 /*********************************************************************//**
grzemich 0:d7bd7384a37c 348 * Macro defines for RX Descriptor Control Word
grzemich 0:d7bd7384a37c 349 **********************************************************************/
grzemich 0:d7bd7384a37c 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
grzemich 0:d7bd7384a37c 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
grzemich 0:d7bd7384a37c 352
grzemich 0:d7bd7384a37c 353 /*********************************************************************//**
grzemich 0:d7bd7384a37c 354 * Macro defines for RX Status Hash CRC Word
grzemich 0:d7bd7384a37c 355 **********************************************************************/
grzemich 0:d7bd7384a37c 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
grzemich 0:d7bd7384a37c 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
grzemich 0:d7bd7384a37c 358
grzemich 0:d7bd7384a37c 359 /*********************************************************************//**
grzemich 0:d7bd7384a37c 360 * Macro defines for RX Status Information Word
grzemich 0:d7bd7384a37c 361 **********************************************************************/
grzemich 0:d7bd7384a37c 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
grzemich 0:d7bd7384a37c 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
grzemich 0:d7bd7384a37c 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
grzemich 0:d7bd7384a37c 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
grzemich 0:d7bd7384a37c 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
grzemich 0:d7bd7384a37c 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
grzemich 0:d7bd7384a37c 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
grzemich 0:d7bd7384a37c 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
grzemich 0:d7bd7384a37c 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
grzemich 0:d7bd7384a37c 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
grzemich 0:d7bd7384a37c 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
grzemich 0:d7bd7384a37c 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
grzemich 0:d7bd7384a37c 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
grzemich 0:d7bd7384a37c 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
grzemich 0:d7bd7384a37c 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
grzemich 0:d7bd7384a37c 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
grzemich 0:d7bd7384a37c 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
grzemich 0:d7bd7384a37c 379
grzemich 0:d7bd7384a37c 380 /*********************************************************************//**
grzemich 0:d7bd7384a37c 381 * Macro defines for TX Descriptor Control Word
grzemich 0:d7bd7384a37c 382 **********************************************************************/
grzemich 0:d7bd7384a37c 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
grzemich 0:d7bd7384a37c 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
grzemich 0:d7bd7384a37c 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
grzemich 0:d7bd7384a37c 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
grzemich 0:d7bd7384a37c 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
grzemich 0:d7bd7384a37c 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
grzemich 0:d7bd7384a37c 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
grzemich 0:d7bd7384a37c 390
grzemich 0:d7bd7384a37c 391 /*********************************************************************//**
grzemich 0:d7bd7384a37c 392 * Macro defines for TX Status Information Word
grzemich 0:d7bd7384a37c 393 **********************************************************************/
grzemich 0:d7bd7384a37c 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
grzemich 0:d7bd7384a37c 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
grzemich 0:d7bd7384a37c 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
grzemich 0:d7bd7384a37c 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
grzemich 0:d7bd7384a37c 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
grzemich 0:d7bd7384a37c 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
grzemich 0:d7bd7384a37c 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
grzemich 0:d7bd7384a37c 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
grzemich 0:d7bd7384a37c 402
grzemich 0:d7bd7384a37c 403 #ifdef MCB_LPC_1768
grzemich 0:d7bd7384a37c 404 /* DP83848C PHY definition ------------------------------------------------------------ */
grzemich 0:d7bd7384a37c 405
grzemich 0:d7bd7384a37c 406 /** PHY device reset time out definition */
grzemich 0:d7bd7384a37c 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
grzemich 0:d7bd7384a37c 408
grzemich 0:d7bd7384a37c 409 /* ENET Device Revision ID */
grzemich 0:d7bd7384a37c 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
grzemich 0:d7bd7384a37c 411
grzemich 0:d7bd7384a37c 412 /*********************************************************************//**
grzemich 0:d7bd7384a37c 413 * Macro defines for DP83848C PHY Registers
grzemich 0:d7bd7384a37c 414 **********************************************************************/
grzemich 0:d7bd7384a37c 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
grzemich 0:d7bd7384a37c 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
grzemich 0:d7bd7384a37c 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
grzemich 0:d7bd7384a37c 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
grzemich 0:d7bd7384a37c 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
grzemich 0:d7bd7384a37c 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
grzemich 0:d7bd7384a37c 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
grzemich 0:d7bd7384a37c 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
grzemich 0:d7bd7384a37c 423 #define EMAC_PHY_REG_LPNPA 0x08
grzemich 0:d7bd7384a37c 424
grzemich 0:d7bd7384a37c 425 /*********************************************************************//**
grzemich 0:d7bd7384a37c 426 * Macro defines for PHY Extended Registers
grzemich 0:d7bd7384a37c 427 **********************************************************************/
grzemich 0:d7bd7384a37c 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
grzemich 0:d7bd7384a37c 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
grzemich 0:d7bd7384a37c 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
grzemich 0:d7bd7384a37c 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
grzemich 0:d7bd7384a37c 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
grzemich 0:d7bd7384a37c 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
grzemich 0:d7bd7384a37c 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
grzemich 0:d7bd7384a37c 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
grzemich 0:d7bd7384a37c 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
grzemich 0:d7bd7384a37c 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
grzemich 0:d7bd7384a37c 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
grzemich 0:d7bd7384a37c 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
grzemich 0:d7bd7384a37c 440
grzemich 0:d7bd7384a37c 441 /*********************************************************************//**
grzemich 0:d7bd7384a37c 442 * Macro defines for PHY Basic Mode Control Register
grzemich 0:d7bd7384a37c 443 **********************************************************************/
grzemich 0:d7bd7384a37c 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
grzemich 0:d7bd7384a37c 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
grzemich 0:d7bd7384a37c 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
grzemich 0:d7bd7384a37c 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
grzemich 0:d7bd7384a37c 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
grzemich 0:d7bd7384a37c 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
grzemich 0:d7bd7384a37c 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
grzemich 0:d7bd7384a37c 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
grzemich 0:d7bd7384a37c 452
grzemich 0:d7bd7384a37c 453 /*********************************************************************//**
grzemich 0:d7bd7384a37c 454 * Macro defines for PHY Basic Mode Status Status Register
grzemich 0:d7bd7384a37c 455 **********************************************************************/
grzemich 0:d7bd7384a37c 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
grzemich 0:d7bd7384a37c 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
grzemich 0:d7bd7384a37c 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
grzemich 0:d7bd7384a37c 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
grzemich 0:d7bd7384a37c 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
grzemich 0:d7bd7384a37c 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
grzemich 0:d7bd7384a37c 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
grzemich 0:d7bd7384a37c 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
grzemich 0:d7bd7384a37c 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
grzemich 0:d7bd7384a37c 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
grzemich 0:d7bd7384a37c 466
grzemich 0:d7bd7384a37c 467 /*********************************************************************//**
grzemich 0:d7bd7384a37c 468 * Macro defines for PHY Status Register
grzemich 0:d7bd7384a37c 469 **********************************************************************/
grzemich 0:d7bd7384a37c 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
grzemich 0:d7bd7384a37c 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
grzemich 0:d7bd7384a37c 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
grzemich 0:d7bd7384a37c 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
grzemich 0:d7bd7384a37c 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
grzemich 0:d7bd7384a37c 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
grzemich 0:d7bd7384a37c 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
grzemich 0:d7bd7384a37c 477
grzemich 0:d7bd7384a37c 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
grzemich 0:d7bd7384a37c 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
grzemich 0:d7bd7384a37c 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
grzemich 0:d7bd7384a37c 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
grzemich 0:d7bd7384a37c 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
grzemich 0:d7bd7384a37c 483
grzemich 0:d7bd7384a37c 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
grzemich 0:d7bd7384a37c 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
grzemich 0:d7bd7384a37c 486
grzemich 0:d7bd7384a37c 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
grzemich 0:d7bd7384a37c 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
grzemich 0:d7bd7384a37c 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
grzemich 0:d7bd7384a37c 490
grzemich 0:d7bd7384a37c 491 #elif defined(IAR_LPC_1768)
grzemich 0:d7bd7384a37c 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
grzemich 0:d7bd7384a37c 493 /** PHY device reset time out definition */
grzemich 0:d7bd7384a37c 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
grzemich 0:d7bd7384a37c 495
grzemich 0:d7bd7384a37c 496 /* ENET Device Revision ID */
grzemich 0:d7bd7384a37c 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
grzemich 0:d7bd7384a37c 498
grzemich 0:d7bd7384a37c 499 /*********************************************************************//**
grzemich 0:d7bd7384a37c 500 * Macro defines for KSZ8721BL PHY Registers
grzemich 0:d7bd7384a37c 501 **********************************************************************/
grzemich 0:d7bd7384a37c 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
grzemich 0:d7bd7384a37c 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
grzemich 0:d7bd7384a37c 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
grzemich 0:d7bd7384a37c 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
grzemich 0:d7bd7384a37c 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
grzemich 0:d7bd7384a37c 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
grzemich 0:d7bd7384a37c 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
grzemich 0:d7bd7384a37c 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
grzemich 0:d7bd7384a37c 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
grzemich 0:d7bd7384a37c 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
grzemich 0:d7bd7384a37c 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
grzemich 0:d7bd7384a37c 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
grzemich 0:d7bd7384a37c 514
grzemich 0:d7bd7384a37c 515 /*********************************************************************//**
grzemich 0:d7bd7384a37c 516 * Macro defines for PHY Basic Mode Control Register
grzemich 0:d7bd7384a37c 517 **********************************************************************/
grzemich 0:d7bd7384a37c 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
grzemich 0:d7bd7384a37c 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
grzemich 0:d7bd7384a37c 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
grzemich 0:d7bd7384a37c 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
grzemich 0:d7bd7384a37c 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
grzemich 0:d7bd7384a37c 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
grzemich 0:d7bd7384a37c 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
grzemich 0:d7bd7384a37c 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
grzemich 0:d7bd7384a37c 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
grzemich 0:d7bd7384a37c 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
grzemich 0:d7bd7384a37c 528
grzemich 0:d7bd7384a37c 529 /*********************************************************************//**
grzemich 0:d7bd7384a37c 530 * Macro defines for PHY Basic Mode Status Register
grzemich 0:d7bd7384a37c 531 **********************************************************************/
grzemich 0:d7bd7384a37c 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
grzemich 0:d7bd7384a37c 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
grzemich 0:d7bd7384a37c 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
grzemich 0:d7bd7384a37c 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
grzemich 0:d7bd7384a37c 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
grzemich 0:d7bd7384a37c 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
grzemich 0:d7bd7384a37c 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
grzemich 0:d7bd7384a37c 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
grzemich 0:d7bd7384a37c 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
grzemich 0:d7bd7384a37c 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
grzemich 0:d7bd7384a37c 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
grzemich 0:d7bd7384a37c 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
grzemich 0:d7bd7384a37c 544
grzemich 0:d7bd7384a37c 545 /*********************************************************************//**
grzemich 0:d7bd7384a37c 546 * Macro defines for PHY Identifier
grzemich 0:d7bd7384a37c 547 **********************************************************************/
grzemich 0:d7bd7384a37c 548 /* PHY Identifier 1 bitmap definitions */
grzemich 0:d7bd7384a37c 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
grzemich 0:d7bd7384a37c 550
grzemich 0:d7bd7384a37c 551 /* PHY Identifier 2 bitmap definitions */
grzemich 0:d7bd7384a37c 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
grzemich 0:d7bd7384a37c 553
grzemich 0:d7bd7384a37c 554 /*********************************************************************//**
grzemich 0:d7bd7384a37c 555 * Macro defines for Auto-Negotiation Advertisement
grzemich 0:d7bd7384a37c 556 **********************************************************************/
grzemich 0:d7bd7384a37c 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
grzemich 0:d7bd7384a37c 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
grzemich 0:d7bd7384a37c 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
grzemich 0:d7bd7384a37c 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
grzemich 0:d7bd7384a37c 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
grzemich 0:d7bd7384a37c 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
grzemich 0:d7bd7384a37c 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
grzemich 0:d7bd7384a37c 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
grzemich 0:d7bd7384a37c 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
grzemich 0:d7bd7384a37c 566
grzemich 0:d7bd7384a37c 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
grzemich 0:d7bd7384a37c 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
grzemich 0:d7bd7384a37c 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
grzemich 0:d7bd7384a37c 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
grzemich 0:d7bd7384a37c 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
grzemich 0:d7bd7384a37c 572
grzemich 0:d7bd7384a37c 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
grzemich 0:d7bd7384a37c 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
grzemich 0:d7bd7384a37c 575
grzemich 0:d7bd7384a37c 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
grzemich 0:d7bd7384a37c 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
grzemich 0:d7bd7384a37c 578 #endif
grzemich 0:d7bd7384a37c 579
grzemich 0:d7bd7384a37c 580 /**
grzemich 0:d7bd7384a37c 581 * @}
grzemich 0:d7bd7384a37c 582 */
grzemich 0:d7bd7384a37c 583
grzemich 0:d7bd7384a37c 584
grzemich 0:d7bd7384a37c 585 /* Public Types --------------------------------------------------------------- */
grzemich 0:d7bd7384a37c 586 /** @defgroup EMAC_Public_Types EMAC Public Types
grzemich 0:d7bd7384a37c 587 * @{
grzemich 0:d7bd7384a37c 588 */
grzemich 0:d7bd7384a37c 589
grzemich 0:d7bd7384a37c 590 /* Descriptor and status formats ---------------------------------------------- */
grzemich 0:d7bd7384a37c 591
grzemich 0:d7bd7384a37c 592 /**
grzemich 0:d7bd7384a37c 593 * @brief RX Descriptor structure type definition
grzemich 0:d7bd7384a37c 594 */
grzemich 0:d7bd7384a37c 595 typedef struct {
grzemich 0:d7bd7384a37c 596 uint32_t Packet; /**< Receive Packet Descriptor */
grzemich 0:d7bd7384a37c 597 uint32_t Ctrl; /**< Receive Control Descriptor */
grzemich 0:d7bd7384a37c 598 } RX_Desc;
grzemich 0:d7bd7384a37c 599
grzemich 0:d7bd7384a37c 600 /**
grzemich 0:d7bd7384a37c 601 * @brief RX Status structure type definition
grzemich 0:d7bd7384a37c 602 */
grzemich 0:d7bd7384a37c 603 typedef struct {
grzemich 0:d7bd7384a37c 604 uint32_t Info; /**< Receive Information Status */
grzemich 0:d7bd7384a37c 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
grzemich 0:d7bd7384a37c 606 } RX_Stat;
grzemich 0:d7bd7384a37c 607
grzemich 0:d7bd7384a37c 608 /**
grzemich 0:d7bd7384a37c 609 * @brief TX Descriptor structure type definition
grzemich 0:d7bd7384a37c 610 */
grzemich 0:d7bd7384a37c 611 typedef struct {
grzemich 0:d7bd7384a37c 612 uint32_t Packet; /**< Transmit Packet Descriptor */
grzemich 0:d7bd7384a37c 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
grzemich 0:d7bd7384a37c 614 } TX_Desc;
grzemich 0:d7bd7384a37c 615
grzemich 0:d7bd7384a37c 616 /**
grzemich 0:d7bd7384a37c 617 * @brief TX Status structure type definition
grzemich 0:d7bd7384a37c 618 */
grzemich 0:d7bd7384a37c 619 typedef struct {
grzemich 0:d7bd7384a37c 620 uint32_t Info; /**< Transmit Information Status */
grzemich 0:d7bd7384a37c 621 } TX_Stat;
grzemich 0:d7bd7384a37c 622
grzemich 0:d7bd7384a37c 623
grzemich 0:d7bd7384a37c 624 /**
grzemich 0:d7bd7384a37c 625 * @brief TX Data Buffer structure definition
grzemich 0:d7bd7384a37c 626 */
grzemich 0:d7bd7384a37c 627 typedef struct {
grzemich 0:d7bd7384a37c 628 uint32_t ulDataLen; /**< Data length */
grzemich 0:d7bd7384a37c 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
grzemich 0:d7bd7384a37c 630 } EMAC_PACKETBUF_Type;
grzemich 0:d7bd7384a37c 631
grzemich 0:d7bd7384a37c 632 /**
grzemich 0:d7bd7384a37c 633 * @brief EMAC configuration structure definition
grzemich 0:d7bd7384a37c 634 */
grzemich 0:d7bd7384a37c 635 typedef struct {
grzemich 0:d7bd7384a37c 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
grzemich 0:d7bd7384a37c 637 - EMAC_MODE_AUTO
grzemich 0:d7bd7384a37c 638 - EMAC_MODE_10M_FULL
grzemich 0:d7bd7384a37c 639 - EMAC_MODE_10M_HALF
grzemich 0:d7bd7384a37c 640 - EMAC_MODE_100M_FULL
grzemich 0:d7bd7384a37c 641 - EMAC_MODE_100M_HALF
grzemich 0:d7bd7384a37c 642 */
grzemich 0:d7bd7384a37c 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
grzemich 0:d7bd7384a37c 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
grzemich 0:d7bd7384a37c 645 */
grzemich 0:d7bd7384a37c 646 } EMAC_CFG_Type;
grzemich 0:d7bd7384a37c 647
grzemich 0:d7bd7384a37c 648 /** Ethernet block power/clock control bit*/
grzemich 0:d7bd7384a37c 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
grzemich 0:d7bd7384a37c 650
grzemich 0:d7bd7384a37c 651 #ifdef __cplusplus
grzemich 0:d7bd7384a37c 652 }
grzemich 0:d7bd7384a37c 653 #endif
grzemich 0:d7bd7384a37c 654
grzemich 0:d7bd7384a37c 655 #endif /* LPC17XX_EMAC_H_ */
grzemich 0:d7bd7384a37c 656
grzemich 0:d7bd7384a37c 657 /**
grzemich 0:d7bd7384a37c 658 * @}
grzemich 0:d7bd7384a37c 659 */
grzemich 0:d7bd7384a37c 660
grzemich 0:d7bd7384a37c 661 /* --------------------------------- End Of File ------------------------------ */