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lwip-eth/arch/TARGET_NXP/lpc17_emac.c@0:d7bd7384a37c, 2016-12-07 (annotated)

Committer:
grzemich
Date:
Wed Dec 07 23:47:50 2016 +0000
Revision:
0:d7bd7384a37c
dgd

Who changed what in which revision?

UserRevisionLine numberNew contents of line
grzemich 0:d7bd7384a37c 1 /**********************************************************************
grzemich 0:d7bd7384a37c 2 * $Id$ lpc17_emac.c 2011-11-20
grzemich 0:d7bd7384a37c 3 *//**
grzemich 0:d7bd7384a37c 4 * @file lpc17_emac.c
grzemich 0:d7bd7384a37c 5 * @brief LPC17 ethernet driver for LWIP
grzemich 0:d7bd7384a37c 6 * @version 1.0
grzemich 0:d7bd7384a37c 7 * @date 20. Nov. 2011
grzemich 0:d7bd7384a37c 8 * @author NXP MCU SW Application Team
grzemich 0:d7bd7384a37c 9 *
grzemich 0:d7bd7384a37c 10 * Copyright(C) 2011, NXP Semiconductor
grzemich 0:d7bd7384a37c 11 * All rights reserved.
grzemich 0:d7bd7384a37c 12 *
grzemich 0:d7bd7384a37c 13 ***********************************************************************
grzemich 0:d7bd7384a37c 14 * Software that is described herein is for illustrative purposes only
grzemich 0:d7bd7384a37c 15 * which provides customers with programming information regarding the
grzemich 0:d7bd7384a37c 16 * products. This software is supplied "AS IS" without any warranties.
grzemich 0:d7bd7384a37c 17 * NXP Semiconductors assumes no responsibility or liability for the
grzemich 0:d7bd7384a37c 18 * use of the software, conveys no license or title under any patent,
grzemich 0:d7bd7384a37c 19 * copyright, or mask work right to the product. NXP Semiconductors
grzemich 0:d7bd7384a37c 20 * reserves the right to make changes in the software without
grzemich 0:d7bd7384a37c 21 * notification. NXP Semiconductors also make no representation or
grzemich 0:d7bd7384a37c 22 * warranty that such application will be suitable for the specified
grzemich 0:d7bd7384a37c 23 * use without further testing or modification.
grzemich 0:d7bd7384a37c 24 **********************************************************************/
grzemich 0:d7bd7384a37c 25
grzemich 0:d7bd7384a37c 26 #include "lwip/opt.h"
grzemich 0:d7bd7384a37c 27 #include "lwip/sys.h"
grzemich 0:d7bd7384a37c 28 #include "lwip/def.h"
grzemich 0:d7bd7384a37c 29 #include "lwip/mem.h"
grzemich 0:d7bd7384a37c 30 #include "lwip/pbuf.h"
grzemich 0:d7bd7384a37c 31 #include "lwip/stats.h"
grzemich 0:d7bd7384a37c 32 #include "lwip/snmp.h"
grzemich 0:d7bd7384a37c 33 #include "netif/etharp.h"
grzemich 0:d7bd7384a37c 34 #include "netif/ppp_oe.h"
grzemich 0:d7bd7384a37c 35
grzemich 0:d7bd7384a37c 36 #include "lpc17xx_emac.h"
grzemich 0:d7bd7384a37c 37 #include "eth_arch.h"
grzemich 0:d7bd7384a37c 38 #include "lpc_emac_config.h"
grzemich 0:d7bd7384a37c 39 #include "lpc_phy.h"
grzemich 0:d7bd7384a37c 40 #include "sys_arch.h"
grzemich 0:d7bd7384a37c 41
grzemich 0:d7bd7384a37c 42 #include "mbed_interface.h"
grzemich 0:d7bd7384a37c 43 #include <string.h>
grzemich 0:d7bd7384a37c 44
grzemich 0:d7bd7384a37c 45 #ifndef LPC_EMAC_RMII
grzemich 0:d7bd7384a37c 46 #error LPC_EMAC_RMII is not defined!
grzemich 0:d7bd7384a37c 47 #endif
grzemich 0:d7bd7384a37c 48
grzemich 0:d7bd7384a37c 49 #if LPC_NUM_BUFF_TXDESCS < 2
grzemich 0:d7bd7384a37c 50 #error LPC_NUM_BUFF_TXDESCS must be at least 2
grzemich 0:d7bd7384a37c 51 #endif
grzemich 0:d7bd7384a37c 52
grzemich 0:d7bd7384a37c 53 #if LPC_NUM_BUFF_RXDESCS < 3
grzemich 0:d7bd7384a37c 54 #error LPC_NUM_BUFF_RXDESCS must be at least 3
grzemich 0:d7bd7384a37c 55 #endif
grzemich 0:d7bd7384a37c 56
grzemich 0:d7bd7384a37c 57 /** @defgroup lwip17xx_emac_DRIVER lpc17 EMAC driver for LWIP
grzemich 0:d7bd7384a37c 58 * @ingroup lwip_emac
grzemich 0:d7bd7384a37c 59 *
grzemich 0:d7bd7384a37c 60 * @{
grzemich 0:d7bd7384a37c 61 */
grzemich 0:d7bd7384a37c 62
grzemich 0:d7bd7384a37c 63 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 64 /** \brief Driver transmit and receive thread priorities
grzemich 0:d7bd7384a37c 65 *
grzemich 0:d7bd7384a37c 66 * Thread priorities for receive thread and TX cleanup thread. Alter
grzemich 0:d7bd7384a37c 67 * to prioritize receive or transmit bandwidth. In a heavily loaded
grzemich 0:d7bd7384a37c 68 * system or with LEIP_DEBUG enabled, the priorities might be better
grzemich 0:d7bd7384a37c 69 * the same. */
grzemich 0:d7bd7384a37c 70 #define RX_PRIORITY (osPriorityNormal)
grzemich 0:d7bd7384a37c 71 #define TX_PRIORITY (osPriorityNormal)
grzemich 0:d7bd7384a37c 72
grzemich 0:d7bd7384a37c 73 /** \brief Debug output formatter lock define
grzemich 0:d7bd7384a37c 74 *
grzemich 0:d7bd7384a37c 75 * When using FreeRTOS and with LWIP_DEBUG enabled, enabling this
grzemich 0:d7bd7384a37c 76 * define will allow RX debug messages to not interleave with the
grzemich 0:d7bd7384a37c 77 * TX messages (so they are actually readable). Not enabling this
grzemich 0:d7bd7384a37c 78 * define when the system is under load will cause the output to
grzemich 0:d7bd7384a37c 79 * be unreadable. There is a small tradeoff in performance for this
grzemich 0:d7bd7384a37c 80 * so use it only for debug. */
grzemich 0:d7bd7384a37c 81 //#define LOCK_RX_THREAD
grzemich 0:d7bd7384a37c 82
grzemich 0:d7bd7384a37c 83 /** \brief Receive group interrupts
grzemich 0:d7bd7384a37c 84 */
grzemich 0:d7bd7384a37c 85 #define RXINTGROUP (EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_DONE)
grzemich 0:d7bd7384a37c 86
grzemich 0:d7bd7384a37c 87 /** \brief Transmit group interrupts
grzemich 0:d7bd7384a37c 88 */
grzemich 0:d7bd7384a37c 89 #define TXINTGROUP (EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR | EMAC_INT_TX_DONE)
grzemich 0:d7bd7384a37c 90
grzemich 0:d7bd7384a37c 91 /** \brief Signal used for ethernet ISR to signal packet_rx() thread.
grzemich 0:d7bd7384a37c 92 */
grzemich 0:d7bd7384a37c 93 #define RX_SIGNAL 1
grzemich 0:d7bd7384a37c 94
grzemich 0:d7bd7384a37c 95 #else
grzemich 0:d7bd7384a37c 96 #define RXINTGROUP 0
grzemich 0:d7bd7384a37c 97 #define TXINTGROUP 0
grzemich 0:d7bd7384a37c 98 #endif
grzemich 0:d7bd7384a37c 99
grzemich 0:d7bd7384a37c 100 /** \brief Structure of a TX/RX descriptor
grzemich 0:d7bd7384a37c 101 */
grzemich 0:d7bd7384a37c 102 typedef struct
grzemich 0:d7bd7384a37c 103 {
grzemich 0:d7bd7384a37c 104 volatile u32_t packet; /**< Pointer to buffer */
grzemich 0:d7bd7384a37c 105 volatile u32_t control; /**< Control word */
grzemich 0:d7bd7384a37c 106 } LPC_TXRX_DESC_T;
grzemich 0:d7bd7384a37c 107
grzemich 0:d7bd7384a37c 108 /** \brief Structure of a RX status entry
grzemich 0:d7bd7384a37c 109 */
grzemich 0:d7bd7384a37c 110 typedef struct
grzemich 0:d7bd7384a37c 111 {
grzemich 0:d7bd7384a37c 112 volatile u32_t statusinfo; /**< RX status word */
grzemich 0:d7bd7384a37c 113 volatile u32_t statushashcrc; /**< RX hash CRC */
grzemich 0:d7bd7384a37c 114 } LPC_TXRX_STATUS_T;
grzemich 0:d7bd7384a37c 115
grzemich 0:d7bd7384a37c 116 /* LPC EMAC driver data structure */
grzemich 0:d7bd7384a37c 117 struct lpc_enetdata {
grzemich 0:d7bd7384a37c 118 /* prxs must be 8 byte aligned! */
grzemich 0:d7bd7384a37c 119 LPC_TXRX_STATUS_T prxs[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX statuses */
grzemich 0:d7bd7384a37c 120 struct netif *netif; /**< Reference back to LWIP parent netif */
grzemich 0:d7bd7384a37c 121 LPC_TXRX_DESC_T ptxd[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX descriptor list */
grzemich 0:d7bd7384a37c 122 LPC_TXRX_STATUS_T ptxs[LPC_NUM_BUFF_TXDESCS]; /**< Pointer to TX statuses */
grzemich 0:d7bd7384a37c 123 LPC_TXRX_DESC_T prxd[LPC_NUM_BUFF_RXDESCS]; /**< Pointer to RX descriptor list */
grzemich 0:d7bd7384a37c 124 struct pbuf *rxb[LPC_NUM_BUFF_RXDESCS]; /**< RX pbuf pointer list, zero-copy mode */
grzemich 0:d7bd7384a37c 125 u32_t rx_fill_desc_index; /**< RX descriptor next available index */
grzemich 0:d7bd7384a37c 126 volatile u32_t rx_free_descs; /**< Count of free RX descriptors */
grzemich 0:d7bd7384a37c 127 struct pbuf *txb[LPC_NUM_BUFF_TXDESCS]; /**< TX pbuf pointer list, zero-copy mode */
grzemich 0:d7bd7384a37c 128 u32_t lpc_last_tx_idx; /**< TX last descriptor index, zero-copy mode */
grzemich 0:d7bd7384a37c 129 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 130 sys_thread_t RxThread; /**< RX receive thread data object pointer */
grzemich 0:d7bd7384a37c 131 sys_sem_t TxCleanSem; /**< TX cleanup thread wakeup semaphore */
grzemich 0:d7bd7384a37c 132 sys_mutex_t TXLockMutex; /**< TX critical section mutex */
grzemich 0:d7bd7384a37c 133 sys_sem_t xTXDCountSem; /**< TX free buffer counting semaphore */
grzemich 0:d7bd7384a37c 134 #endif
grzemich 0:d7bd7384a37c 135 };
grzemich 0:d7bd7384a37c 136
grzemich 0:d7bd7384a37c 137 #if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
grzemich 0:d7bd7384a37c 138 # if defined (__ICCARM__)
grzemich 0:d7bd7384a37c 139 # define ETHMEM_SECTION
grzemich 0:d7bd7384a37c 140 # elif defined(TOOLCHAIN_GCC_CR)
grzemich 0:d7bd7384a37c 141 # define ETHMEM_SECTION __attribute__((section(".data.$RamPeriph32"), aligned))
grzemich 0:d7bd7384a37c 142 # else
grzemich 0:d7bd7384a37c 143 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
grzemich 0:d7bd7384a37c 144 # endif
grzemich 0:d7bd7384a37c 145 #elif defined(TARGET_LPC1768)
grzemich 0:d7bd7384a37c 146 # if defined(TOOLCHAIN_GCC_ARM)
grzemich 0:d7bd7384a37c 147 # define ETHMEM_SECTION __attribute__((section("AHBSRAM1"),aligned))
grzemich 0:d7bd7384a37c 148 # endif
grzemich 0:d7bd7384a37c 149 #endif
grzemich 0:d7bd7384a37c 150
grzemich 0:d7bd7384a37c 151 #ifndef ETHMEM_SECTION
grzemich 0:d7bd7384a37c 152 #define ETHMEM_SECTION ALIGNED(8)
grzemich 0:d7bd7384a37c 153 #endif
grzemich 0:d7bd7384a37c 154
grzemich 0:d7bd7384a37c 155 /** \brief LPC EMAC driver work data
grzemich 0:d7bd7384a37c 156 */
grzemich 0:d7bd7384a37c 157 ETHMEM_SECTION struct lpc_enetdata lpc_enetdata;
grzemich 0:d7bd7384a37c 158
grzemich 0:d7bd7384a37c 159 /** \brief Queues a pbuf into the RX descriptor list
grzemich 0:d7bd7384a37c 160 *
grzemich 0:d7bd7384a37c 161 * \param[in] lpc_enetif Pointer to the drvier data structure
grzemich 0:d7bd7384a37c 162 * \param[in] p Pointer to pbuf to queue
grzemich 0:d7bd7384a37c 163 */
grzemich 0:d7bd7384a37c 164 static void lpc_rxqueue_pbuf(struct lpc_enetdata *lpc_enetif, struct pbuf *p)
grzemich 0:d7bd7384a37c 165 {
grzemich 0:d7bd7384a37c 166 u32_t idx;
grzemich 0:d7bd7384a37c 167
grzemich 0:d7bd7384a37c 168 /* Get next free descriptor index */
grzemich 0:d7bd7384a37c 169 idx = lpc_enetif->rx_fill_desc_index;
grzemich 0:d7bd7384a37c 170
grzemich 0:d7bd7384a37c 171 /* Setup descriptor and clear statuses */
grzemich 0:d7bd7384a37c 172 lpc_enetif->prxd[idx].control = EMAC_RCTRL_INT | ((u32_t) (p->len - 1));
grzemich 0:d7bd7384a37c 173 lpc_enetif->prxd[idx].packet = (u32_t) p->payload;
grzemich 0:d7bd7384a37c 174 lpc_enetif->prxs[idx].statusinfo = 0xFFFFFFFF;
grzemich 0:d7bd7384a37c 175 lpc_enetif->prxs[idx].statushashcrc = 0xFFFFFFFF;
grzemich 0:d7bd7384a37c 176
grzemich 0:d7bd7384a37c 177 /* Save pbuf pointer for push to network layer later */
grzemich 0:d7bd7384a37c 178 lpc_enetif->rxb[idx] = p;
grzemich 0:d7bd7384a37c 179
grzemich 0:d7bd7384a37c 180 /* Wrap at end of descriptor list */
grzemich 0:d7bd7384a37c 181 idx++;
grzemich 0:d7bd7384a37c 182 if (idx >= LPC_NUM_BUFF_RXDESCS)
grzemich 0:d7bd7384a37c 183 idx = 0;
grzemich 0:d7bd7384a37c 184
grzemich 0:d7bd7384a37c 185 /* Queue descriptor(s) */
grzemich 0:d7bd7384a37c 186 lpc_enetif->rx_free_descs -= 1;
grzemich 0:d7bd7384a37c 187 lpc_enetif->rx_fill_desc_index = idx;
grzemich 0:d7bd7384a37c 188 LPC_EMAC->RxConsumeIndex = idx;
grzemich 0:d7bd7384a37c 189
grzemich 0:d7bd7384a37c 190 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 191 ("lpc_rxqueue_pbuf: pbuf packet queued: %p (free desc=%d)\n", p,
grzemich 0:d7bd7384a37c 192 lpc_enetif->rx_free_descs));
grzemich 0:d7bd7384a37c 193 }
grzemich 0:d7bd7384a37c 194
grzemich 0:d7bd7384a37c 195 /** \brief Attempt to allocate and requeue a new pbuf for RX
grzemich 0:d7bd7384a37c 196 *
grzemich 0:d7bd7384a37c 197 * \param[in] netif Pointer to the netif structure
grzemich 0:d7bd7384a37c 198 * \returns 1 if a packet was allocated and requeued, otherwise 0
grzemich 0:d7bd7384a37c 199 */
grzemich 0:d7bd7384a37c 200 s32_t lpc_rx_queue(struct netif *netif)
grzemich 0:d7bd7384a37c 201 {
grzemich 0:d7bd7384a37c 202 struct lpc_enetdata *lpc_enetif = netif->state;
grzemich 0:d7bd7384a37c 203 struct pbuf *p;
grzemich 0:d7bd7384a37c 204 s32_t queued = 0;
grzemich 0:d7bd7384a37c 205
grzemich 0:d7bd7384a37c 206 /* Attempt to requeue as many packets as possible */
grzemich 0:d7bd7384a37c 207 while (lpc_enetif->rx_free_descs > 0) {
grzemich 0:d7bd7384a37c 208 /* Allocate a pbuf from the pool. We need to allocate at the
grzemich 0:d7bd7384a37c 209 maximum size as we don't know the size of the yet to be
grzemich 0:d7bd7384a37c 210 received packet. */
grzemich 0:d7bd7384a37c 211 p = pbuf_alloc(PBUF_RAW, (u16_t) EMAC_ETH_MAX_FLEN, PBUF_RAM);
grzemich 0:d7bd7384a37c 212 if (p == NULL) {
grzemich 0:d7bd7384a37c 213 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 214 ("lpc_rx_queue: could not allocate RX pbuf (free desc=%d)\n",
grzemich 0:d7bd7384a37c 215 lpc_enetif->rx_free_descs));
grzemich 0:d7bd7384a37c 216 return queued;
grzemich 0:d7bd7384a37c 217 }
grzemich 0:d7bd7384a37c 218
grzemich 0:d7bd7384a37c 219 /* pbufs allocated from the RAM pool should be non-chained. */
grzemich 0:d7bd7384a37c 220 LWIP_ASSERT("lpc_rx_queue: pbuf is not contiguous (chained)",
grzemich 0:d7bd7384a37c 221 pbuf_clen(p) <= 1);
grzemich 0:d7bd7384a37c 222
grzemich 0:d7bd7384a37c 223 /* Queue packet */
grzemich 0:d7bd7384a37c 224 lpc_rxqueue_pbuf(lpc_enetif, p);
grzemich 0:d7bd7384a37c 225
grzemich 0:d7bd7384a37c 226 /* Update queued count */
grzemich 0:d7bd7384a37c 227 queued++;
grzemich 0:d7bd7384a37c 228 }
grzemich 0:d7bd7384a37c 229
grzemich 0:d7bd7384a37c 230 return queued;
grzemich 0:d7bd7384a37c 231 }
grzemich 0:d7bd7384a37c 232
grzemich 0:d7bd7384a37c 233 /** \brief Sets up the RX descriptor ring buffers.
grzemich 0:d7bd7384a37c 234 *
grzemich 0:d7bd7384a37c 235 * This function sets up the descriptor list used for receive packets.
grzemich 0:d7bd7384a37c 236 *
grzemich 0:d7bd7384a37c 237 * \param[in] lpc_enetif Pointer to driver data structure
grzemich 0:d7bd7384a37c 238 * \returns Always returns ERR_OK
grzemich 0:d7bd7384a37c 239 */
grzemich 0:d7bd7384a37c 240 static err_t lpc_rx_setup(struct lpc_enetdata *lpc_enetif)
grzemich 0:d7bd7384a37c 241 {
grzemich 0:d7bd7384a37c 242 /* Setup pointers to RX structures */
grzemich 0:d7bd7384a37c 243 LPC_EMAC->RxDescriptor = (u32_t) &lpc_enetif->prxd[0];
grzemich 0:d7bd7384a37c 244 LPC_EMAC->RxStatus = (u32_t) &lpc_enetif->prxs[0];
grzemich 0:d7bd7384a37c 245 LPC_EMAC->RxDescriptorNumber = LPC_NUM_BUFF_RXDESCS - 1;
grzemich 0:d7bd7384a37c 246
grzemich 0:d7bd7384a37c 247 lpc_enetif->rx_free_descs = LPC_NUM_BUFF_RXDESCS;
grzemich 0:d7bd7384a37c 248 lpc_enetif->rx_fill_desc_index = 0;
grzemich 0:d7bd7384a37c 249
grzemich 0:d7bd7384a37c 250 /* Build RX buffer and descriptors */
grzemich 0:d7bd7384a37c 251 lpc_rx_queue(lpc_enetif->netif);
grzemich 0:d7bd7384a37c 252
grzemich 0:d7bd7384a37c 253 return ERR_OK;
grzemich 0:d7bd7384a37c 254 }
grzemich 0:d7bd7384a37c 255
grzemich 0:d7bd7384a37c 256 /** \brief Allocates a pbuf and returns the data from the incoming packet.
grzemich 0:d7bd7384a37c 257 *
grzemich 0:d7bd7384a37c 258 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 259 * \return a pbuf filled with the received packet (including MAC header)
grzemich 0:d7bd7384a37c 260 * NULL on memory error
grzemich 0:d7bd7384a37c 261 */
grzemich 0:d7bd7384a37c 262 static struct pbuf *lpc_low_level_input(struct netif *netif)
grzemich 0:d7bd7384a37c 263 {
grzemich 0:d7bd7384a37c 264 struct lpc_enetdata *lpc_enetif = netif->state;
grzemich 0:d7bd7384a37c 265 struct pbuf *p = NULL;
grzemich 0:d7bd7384a37c 266 u32_t idx, length;
grzemich 0:d7bd7384a37c 267 u16_t origLength;
grzemich 0:d7bd7384a37c 268
grzemich 0:d7bd7384a37c 269 #ifdef LOCK_RX_THREAD
grzemich 0:d7bd7384a37c 270 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 271 /* Get exclusive access */
grzemich 0:d7bd7384a37c 272 sys_mutex_lock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 273 #endif
grzemich 0:d7bd7384a37c 274 #endif
grzemich 0:d7bd7384a37c 275
grzemich 0:d7bd7384a37c 276 /* Monitor RX overrun status. This should never happen unless
grzemich 0:d7bd7384a37c 277 (possibly) the internal bus is behing held up by something.
grzemich 0:d7bd7384a37c 278 Unless your system is running at a very low clock speed or
grzemich 0:d7bd7384a37c 279 there are possibilities that the internal buses may be held
grzemich 0:d7bd7384a37c 280 up for a long time, this can probably safely be removed. */
grzemich 0:d7bd7384a37c 281 if (LPC_EMAC->IntStatus & EMAC_INT_RX_OVERRUN) {
grzemich 0:d7bd7384a37c 282 LINK_STATS_INC(link.err);
grzemich 0:d7bd7384a37c 283 LINK_STATS_INC(link.drop);
grzemich 0:d7bd7384a37c 284
grzemich 0:d7bd7384a37c 285 /* Temporarily disable RX */
grzemich 0:d7bd7384a37c 286 LPC_EMAC->MAC1 &= ~EMAC_MAC1_REC_EN;
grzemich 0:d7bd7384a37c 287
grzemich 0:d7bd7384a37c 288 /* Reset the RX side */
grzemich 0:d7bd7384a37c 289 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_RX;
grzemich 0:d7bd7384a37c 290 LPC_EMAC->IntClear = EMAC_INT_RX_OVERRUN;
grzemich 0:d7bd7384a37c 291
grzemich 0:d7bd7384a37c 292 /* De-allocate all queued RX pbufs */
grzemich 0:d7bd7384a37c 293 for (idx = 0; idx < LPC_NUM_BUFF_RXDESCS; idx++) {
grzemich 0:d7bd7384a37c 294 if (lpc_enetif->rxb[idx] != NULL) {
grzemich 0:d7bd7384a37c 295 pbuf_free(lpc_enetif->rxb[idx]);
grzemich 0:d7bd7384a37c 296 lpc_enetif->rxb[idx] = NULL;
grzemich 0:d7bd7384a37c 297 }
grzemich 0:d7bd7384a37c 298 }
grzemich 0:d7bd7384a37c 299
grzemich 0:d7bd7384a37c 300 /* Start RX side again */
grzemich 0:d7bd7384a37c 301 lpc_rx_setup(lpc_enetif);
grzemich 0:d7bd7384a37c 302
grzemich 0:d7bd7384a37c 303 /* Re-enable RX */
grzemich 0:d7bd7384a37c 304 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
grzemich 0:d7bd7384a37c 305
grzemich 0:d7bd7384a37c 306 #ifdef LOCK_RX_THREAD
grzemich 0:d7bd7384a37c 307 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 308 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 309 #endif
grzemich 0:d7bd7384a37c 310 #endif
grzemich 0:d7bd7384a37c 311
grzemich 0:d7bd7384a37c 312 return NULL;
grzemich 0:d7bd7384a37c 313 }
grzemich 0:d7bd7384a37c 314
grzemich 0:d7bd7384a37c 315 /* Determine if a frame has been received */
grzemich 0:d7bd7384a37c 316 length = 0;
grzemich 0:d7bd7384a37c 317 idx = LPC_EMAC->RxConsumeIndex;
grzemich 0:d7bd7384a37c 318 if (LPC_EMAC->RxProduceIndex != idx) {
grzemich 0:d7bd7384a37c 319 /* Handle errors */
grzemich 0:d7bd7384a37c 320 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
grzemich 0:d7bd7384a37c 321 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_LEN_ERR)) {
grzemich 0:d7bd7384a37c 322 #if LINK_STATS
grzemich 0:d7bd7384a37c 323 if (lpc_enetif->prxs[idx].statusinfo & (EMAC_RINFO_CRC_ERR |
grzemich 0:d7bd7384a37c 324 EMAC_RINFO_SYM_ERR | EMAC_RINFO_ALIGN_ERR))
grzemich 0:d7bd7384a37c 325 LINK_STATS_INC(link.chkerr);
grzemich 0:d7bd7384a37c 326 if (lpc_enetif->prxs[idx].statusinfo & EMAC_RINFO_LEN_ERR)
grzemich 0:d7bd7384a37c 327 LINK_STATS_INC(link.lenerr);
grzemich 0:d7bd7384a37c 328 #endif
grzemich 0:d7bd7384a37c 329
grzemich 0:d7bd7384a37c 330 /* Drop the frame */
grzemich 0:d7bd7384a37c 331 LINK_STATS_INC(link.drop);
grzemich 0:d7bd7384a37c 332
grzemich 0:d7bd7384a37c 333 /* Re-queue the pbuf for receive */
grzemich 0:d7bd7384a37c 334 lpc_enetif->rx_free_descs++;
grzemich 0:d7bd7384a37c 335 p = lpc_enetif->rxb[idx];
grzemich 0:d7bd7384a37c 336 lpc_enetif->rxb[idx] = NULL;
grzemich 0:d7bd7384a37c 337 lpc_rxqueue_pbuf(lpc_enetif, p);
grzemich 0:d7bd7384a37c 338
grzemich 0:d7bd7384a37c 339 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 340 ("lpc_low_level_input: Packet dropped with errors (0x%x)\n",
grzemich 0:d7bd7384a37c 341 lpc_enetif->prxs[idx].statusinfo));
grzemich 0:d7bd7384a37c 342
grzemich 0:d7bd7384a37c 343 p = NULL;
grzemich 0:d7bd7384a37c 344 } else {
grzemich 0:d7bd7384a37c 345 /* A packet is waiting, get length */
grzemich 0:d7bd7384a37c 346 length = (lpc_enetif->prxs[idx].statusinfo & 0x7FF) + 1;
grzemich 0:d7bd7384a37c 347
grzemich 0:d7bd7384a37c 348 /* Zero-copy */
grzemich 0:d7bd7384a37c 349 p = lpc_enetif->rxb[idx];
grzemich 0:d7bd7384a37c 350 origLength = p->len;
grzemich 0:d7bd7384a37c 351 p->len = (u16_t) length;
grzemich 0:d7bd7384a37c 352
grzemich 0:d7bd7384a37c 353 /* Free pbuf from descriptor */
grzemich 0:d7bd7384a37c 354 lpc_enetif->rxb[idx] = NULL;
grzemich 0:d7bd7384a37c 355 lpc_enetif->rx_free_descs++;
grzemich 0:d7bd7384a37c 356
grzemich 0:d7bd7384a37c 357 /* Attempt to queue new buffer(s) */
grzemich 0:d7bd7384a37c 358 if (lpc_rx_queue(lpc_enetif->netif) == 0) {
grzemich 0:d7bd7384a37c 359 /* Drop the frame due to OOM. */
grzemich 0:d7bd7384a37c 360 LINK_STATS_INC(link.drop);
grzemich 0:d7bd7384a37c 361
grzemich 0:d7bd7384a37c 362 /* Re-queue the pbuf for receive */
grzemich 0:d7bd7384a37c 363 p->len = origLength;
grzemich 0:d7bd7384a37c 364 lpc_rxqueue_pbuf(lpc_enetif, p);
grzemich 0:d7bd7384a37c 365
grzemich 0:d7bd7384a37c 366 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 367 ("lpc_low_level_input: Packet index %d dropped for OOM\n",
grzemich 0:d7bd7384a37c 368 idx));
grzemich 0:d7bd7384a37c 369
grzemich 0:d7bd7384a37c 370 #ifdef LOCK_RX_THREAD
grzemich 0:d7bd7384a37c 371 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 372 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 373 #endif
grzemich 0:d7bd7384a37c 374 #endif
grzemich 0:d7bd7384a37c 375
grzemich 0:d7bd7384a37c 376 return NULL;
grzemich 0:d7bd7384a37c 377 }
grzemich 0:d7bd7384a37c 378
grzemich 0:d7bd7384a37c 379 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 380 ("lpc_low_level_input: Packet received: %p, size %d (index=%d)\n",
grzemich 0:d7bd7384a37c 381 p, length, idx));
grzemich 0:d7bd7384a37c 382
grzemich 0:d7bd7384a37c 383 /* Save size */
grzemich 0:d7bd7384a37c 384 p->tot_len = (u16_t) length;
grzemich 0:d7bd7384a37c 385 LINK_STATS_INC(link.recv);
grzemich 0:d7bd7384a37c 386 }
grzemich 0:d7bd7384a37c 387 }
grzemich 0:d7bd7384a37c 388
grzemich 0:d7bd7384a37c 389 #ifdef LOCK_RX_THREAD
grzemich 0:d7bd7384a37c 390 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 391 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 392 #endif
grzemich 0:d7bd7384a37c 393 #endif
grzemich 0:d7bd7384a37c 394
grzemich 0:d7bd7384a37c 395 return p;
grzemich 0:d7bd7384a37c 396 }
grzemich 0:d7bd7384a37c 397
grzemich 0:d7bd7384a37c 398 /** \brief Attempt to read a packet from the EMAC interface.
grzemich 0:d7bd7384a37c 399 *
grzemich 0:d7bd7384a37c 400 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 401 */
grzemich 0:d7bd7384a37c 402 void lpc_enetif_input(struct netif *netif)
grzemich 0:d7bd7384a37c 403 {
grzemich 0:d7bd7384a37c 404 struct eth_hdr *ethhdr;
grzemich 0:d7bd7384a37c 405 struct pbuf *p;
grzemich 0:d7bd7384a37c 406
grzemich 0:d7bd7384a37c 407 /* move received packet into a new pbuf */
grzemich 0:d7bd7384a37c 408 p = lpc_low_level_input(netif);
grzemich 0:d7bd7384a37c 409 if (p == NULL)
grzemich 0:d7bd7384a37c 410 return;
grzemich 0:d7bd7384a37c 411
grzemich 0:d7bd7384a37c 412 /* points to packet payload, which starts with an Ethernet header */
grzemich 0:d7bd7384a37c 413 ethhdr = p->payload;
grzemich 0:d7bd7384a37c 414
grzemich 0:d7bd7384a37c 415 switch (htons(ethhdr->type)) {
grzemich 0:d7bd7384a37c 416 case ETHTYPE_IP:
grzemich 0:d7bd7384a37c 417 case ETHTYPE_ARP:
grzemich 0:d7bd7384a37c 418 #if PPPOE_SUPPORT
grzemich 0:d7bd7384a37c 419 case ETHTYPE_PPPOEDISC:
grzemich 0:d7bd7384a37c 420 case ETHTYPE_PPPOE:
grzemich 0:d7bd7384a37c 421 #endif /* PPPOE_SUPPORT */
grzemich 0:d7bd7384a37c 422 /* full packet send to tcpip_thread to process */
grzemich 0:d7bd7384a37c 423 if (netif->input(p, netif) != ERR_OK) {
grzemich 0:d7bd7384a37c 424 LWIP_DEBUGF(NETIF_DEBUG, ("lpc_enetif_input: IP input error\n"));
grzemich 0:d7bd7384a37c 425 /* Free buffer */
grzemich 0:d7bd7384a37c 426 pbuf_free(p);
grzemich 0:d7bd7384a37c 427 }
grzemich 0:d7bd7384a37c 428 break;
grzemich 0:d7bd7384a37c 429
grzemich 0:d7bd7384a37c 430 default:
grzemich 0:d7bd7384a37c 431 /* Return buffer */
grzemich 0:d7bd7384a37c 432 pbuf_free(p);
grzemich 0:d7bd7384a37c 433 break;
grzemich 0:d7bd7384a37c 434 }
grzemich 0:d7bd7384a37c 435 }
grzemich 0:d7bd7384a37c 436
grzemich 0:d7bd7384a37c 437 /** \brief Determine if the passed address is usable for the ethernet
grzemich 0:d7bd7384a37c 438 * DMA controller.
grzemich 0:d7bd7384a37c 439 *
grzemich 0:d7bd7384a37c 440 * \param[in] addr Address of packet to check for DMA safe operation
grzemich 0:d7bd7384a37c 441 * \return 1 if the packet address is not safe, otherwise 0
grzemich 0:d7bd7384a37c 442 */
grzemich 0:d7bd7384a37c 443 static s32_t lpc_packet_addr_notsafe(void *addr) {
grzemich 0:d7bd7384a37c 444 /* Check for legal address ranges */
grzemich 0:d7bd7384a37c 445 #if defined(TARGET_LPC1768)
grzemich 0:d7bd7384a37c 446 if ((((u32_t) addr >= 0x2007C000) && ((u32_t) addr < 0x20083FFF))) {
grzemich 0:d7bd7384a37c 447 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
grzemich 0:d7bd7384a37c 448 if ((((u32_t) addr >= 0x20000000) && ((u32_t) addr < 0x20007FFF))) {
grzemich 0:d7bd7384a37c 449 #endif
grzemich 0:d7bd7384a37c 450 return 0;
grzemich 0:d7bd7384a37c 451 }
grzemich 0:d7bd7384a37c 452 return 1;
grzemich 0:d7bd7384a37c 453 }
grzemich 0:d7bd7384a37c 454
grzemich 0:d7bd7384a37c 455 /** \brief Sets up the TX descriptor ring buffers.
grzemich 0:d7bd7384a37c 456 *
grzemich 0:d7bd7384a37c 457 * This function sets up the descriptor list used for transmit packets.
grzemich 0:d7bd7384a37c 458 *
grzemich 0:d7bd7384a37c 459 * \param[in] lpc_enetif Pointer to driver data structure
grzemich 0:d7bd7384a37c 460 */
grzemich 0:d7bd7384a37c 461 static err_t lpc_tx_setup(struct lpc_enetdata *lpc_enetif)
grzemich 0:d7bd7384a37c 462 {
grzemich 0:d7bd7384a37c 463 s32_t idx;
grzemich 0:d7bd7384a37c 464
grzemich 0:d7bd7384a37c 465 /* Build TX descriptors for local buffers */
grzemich 0:d7bd7384a37c 466 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
grzemich 0:d7bd7384a37c 467 lpc_enetif->ptxd[idx].control = 0;
grzemich 0:d7bd7384a37c 468 lpc_enetif->ptxs[idx].statusinfo = 0xFFFFFFFF;
grzemich 0:d7bd7384a37c 469 }
grzemich 0:d7bd7384a37c 470
grzemich 0:d7bd7384a37c 471 /* Setup pointers to TX structures */
grzemich 0:d7bd7384a37c 472 LPC_EMAC->TxDescriptor = (u32_t) &lpc_enetif->ptxd[0];
grzemich 0:d7bd7384a37c 473 LPC_EMAC->TxStatus = (u32_t) &lpc_enetif->ptxs[0];
grzemich 0:d7bd7384a37c 474 LPC_EMAC->TxDescriptorNumber = LPC_NUM_BUFF_TXDESCS - 1;
grzemich 0:d7bd7384a37c 475
grzemich 0:d7bd7384a37c 476 lpc_enetif->lpc_last_tx_idx = 0;
grzemich 0:d7bd7384a37c 477
grzemich 0:d7bd7384a37c 478 return ERR_OK;
grzemich 0:d7bd7384a37c 479 }
grzemich 0:d7bd7384a37c 480
grzemich 0:d7bd7384a37c 481 /** \brief Free TX buffers that are complete
grzemich 0:d7bd7384a37c 482 *
grzemich 0:d7bd7384a37c 483 * \param[in] lpc_enetif Pointer to driver data structure
grzemich 0:d7bd7384a37c 484 * \param[in] cidx EMAC current descriptor comsumer index
grzemich 0:d7bd7384a37c 485 */
grzemich 0:d7bd7384a37c 486 static void lpc_tx_reclaim_st(struct lpc_enetdata *lpc_enetif, u32_t cidx)
grzemich 0:d7bd7384a37c 487 {
grzemich 0:d7bd7384a37c 488 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 489 /* Get exclusive access */
grzemich 0:d7bd7384a37c 490 sys_mutex_lock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 491 #endif
grzemich 0:d7bd7384a37c 492
grzemich 0:d7bd7384a37c 493 while (cidx != lpc_enetif->lpc_last_tx_idx) {
grzemich 0:d7bd7384a37c 494 if (lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] != NULL) {
grzemich 0:d7bd7384a37c 495 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 496 ("lpc_tx_reclaim_st: Freeing packet %p (index %d)\n",
grzemich 0:d7bd7384a37c 497 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx],
grzemich 0:d7bd7384a37c 498 lpc_enetif->lpc_last_tx_idx));
grzemich 0:d7bd7384a37c 499 pbuf_free(lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx]);
grzemich 0:d7bd7384a37c 500 lpc_enetif->txb[lpc_enetif->lpc_last_tx_idx] = NULL;
grzemich 0:d7bd7384a37c 501 }
grzemich 0:d7bd7384a37c 502
grzemich 0:d7bd7384a37c 503 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 504 osSemaphoreRelease(lpc_enetif->xTXDCountSem.id);
grzemich 0:d7bd7384a37c 505 #endif
grzemich 0:d7bd7384a37c 506 lpc_enetif->lpc_last_tx_idx++;
grzemich 0:d7bd7384a37c 507 if (lpc_enetif->lpc_last_tx_idx >= LPC_NUM_BUFF_TXDESCS)
grzemich 0:d7bd7384a37c 508 lpc_enetif->lpc_last_tx_idx = 0;
grzemich 0:d7bd7384a37c 509 }
grzemich 0:d7bd7384a37c 510
grzemich 0:d7bd7384a37c 511 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 512 /* Restore access */
grzemich 0:d7bd7384a37c 513 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 514 #endif
grzemich 0:d7bd7384a37c 515 }
grzemich 0:d7bd7384a37c 516
grzemich 0:d7bd7384a37c 517 /** \brief User call for freeingTX buffers that are complete
grzemich 0:d7bd7384a37c 518 *
grzemich 0:d7bd7384a37c 519 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 520 */
grzemich 0:d7bd7384a37c 521 void lpc_tx_reclaim(struct netif *netif)
grzemich 0:d7bd7384a37c 522 {
grzemich 0:d7bd7384a37c 523 lpc_tx_reclaim_st((struct lpc_enetdata *) netif->state,
grzemich 0:d7bd7384a37c 524 LPC_EMAC->TxConsumeIndex);
grzemich 0:d7bd7384a37c 525 }
grzemich 0:d7bd7384a37c 526
grzemich 0:d7bd7384a37c 527 /** \brief Polls if an available TX descriptor is ready. Can be used to
grzemich 0:d7bd7384a37c 528 * determine if the low level transmit function will block.
grzemich 0:d7bd7384a37c 529 *
grzemich 0:d7bd7384a37c 530 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 531 * \return 0 if no descriptors are read, or >0
grzemich 0:d7bd7384a37c 532 */
grzemich 0:d7bd7384a37c 533 s32_t lpc_tx_ready(struct netif *netif)
grzemich 0:d7bd7384a37c 534 {
grzemich 0:d7bd7384a37c 535 s32_t fb;
grzemich 0:d7bd7384a37c 536 u32_t idx, cidx;
grzemich 0:d7bd7384a37c 537
grzemich 0:d7bd7384a37c 538 cidx = LPC_EMAC->TxConsumeIndex;
grzemich 0:d7bd7384a37c 539 idx = LPC_EMAC->TxProduceIndex;
grzemich 0:d7bd7384a37c 540
grzemich 0:d7bd7384a37c 541 /* Determine number of free buffers */
grzemich 0:d7bd7384a37c 542 if (idx == cidx)
grzemich 0:d7bd7384a37c 543 fb = LPC_NUM_BUFF_TXDESCS;
grzemich 0:d7bd7384a37c 544 else if (cidx > idx)
grzemich 0:d7bd7384a37c 545 fb = (LPC_NUM_BUFF_TXDESCS - 1) -
grzemich 0:d7bd7384a37c 546 ((idx + LPC_NUM_BUFF_TXDESCS) - cidx);
grzemich 0:d7bd7384a37c 547 else
grzemich 0:d7bd7384a37c 548 fb = (LPC_NUM_BUFF_TXDESCS - 1) - (cidx - idx);
grzemich 0:d7bd7384a37c 549
grzemich 0:d7bd7384a37c 550 return fb;
grzemich 0:d7bd7384a37c 551 }
grzemich 0:d7bd7384a37c 552
grzemich 0:d7bd7384a37c 553 /** \brief Low level output of a packet. Never call this from an
grzemich 0:d7bd7384a37c 554 * interrupt context, as it may block until TX descriptors
grzemich 0:d7bd7384a37c 555 * become available.
grzemich 0:d7bd7384a37c 556 *
grzemich 0:d7bd7384a37c 557 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 558 * \param[in] p the MAC packet to send (e.g. IP packet including MAC addresses and type)
grzemich 0:d7bd7384a37c 559 * \return ERR_OK if the packet could be sent or an err_t value if the packet couldn't be sent
grzemich 0:d7bd7384a37c 560 */
grzemich 0:d7bd7384a37c 561 static err_t lpc_low_level_output(struct netif *netif, struct pbuf *p)
grzemich 0:d7bd7384a37c 562 {
grzemich 0:d7bd7384a37c 563 struct lpc_enetdata *lpc_enetif = netif->state;
grzemich 0:d7bd7384a37c 564 struct pbuf *q;
grzemich 0:d7bd7384a37c 565 u8_t *dst;
grzemich 0:d7bd7384a37c 566 u32_t idx, notdmasafe = 0;
grzemich 0:d7bd7384a37c 567 struct pbuf *np;
grzemich 0:d7bd7384a37c 568 s32_t dn;
grzemich 0:d7bd7384a37c 569
grzemich 0:d7bd7384a37c 570 /* Zero-copy TX buffers may be fragmented across mutliple payload
grzemich 0:d7bd7384a37c 571 chains. Determine the number of descriptors needed for the
grzemich 0:d7bd7384a37c 572 transfer. The pbuf chaining can be a mess! */
grzemich 0:d7bd7384a37c 573 dn = (s32_t) pbuf_clen(p);
grzemich 0:d7bd7384a37c 574
grzemich 0:d7bd7384a37c 575 /* Test to make sure packet addresses are DMA safe. A DMA safe
grzemich 0:d7bd7384a37c 576 address is once that uses external memory or periphheral RAM.
grzemich 0:d7bd7384a37c 577 IRAM and FLASH are not safe! */
grzemich 0:d7bd7384a37c 578 for (q = p; q != NULL; q = q->next)
grzemich 0:d7bd7384a37c 579 notdmasafe += lpc_packet_addr_notsafe(q->payload);
grzemich 0:d7bd7384a37c 580
grzemich 0:d7bd7384a37c 581 #if LPC_TX_PBUF_BOUNCE_EN==1
grzemich 0:d7bd7384a37c 582 /* If the pbuf is not DMA safe, a new bounce buffer (pbuf) will be
grzemich 0:d7bd7384a37c 583 created that will be used instead. This requires an copy from the
grzemich 0:d7bd7384a37c 584 non-safe DMA region to the new pbuf */
grzemich 0:d7bd7384a37c 585 if (notdmasafe) {
grzemich 0:d7bd7384a37c 586 /* Allocate a pbuf in DMA memory */
grzemich 0:d7bd7384a37c 587 np = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM);
grzemich 0:d7bd7384a37c 588 if (np == NULL)
grzemich 0:d7bd7384a37c 589 return ERR_MEM;
grzemich 0:d7bd7384a37c 590
grzemich 0:d7bd7384a37c 591 /* This buffer better be contiguous! */
grzemich 0:d7bd7384a37c 592 LWIP_ASSERT("lpc_low_level_output: New transmit pbuf is chained",
grzemich 0:d7bd7384a37c 593 (pbuf_clen(np) == 1));
grzemich 0:d7bd7384a37c 594
grzemich 0:d7bd7384a37c 595 /* Copy to DMA safe pbuf */
grzemich 0:d7bd7384a37c 596 dst = (u8_t *) np->payload;
grzemich 0:d7bd7384a37c 597 for(q = p; q != NULL; q = q->next) {
grzemich 0:d7bd7384a37c 598 /* Copy the buffer to the descriptor's buffer */
grzemich 0:d7bd7384a37c 599 MEMCPY(dst, (u8_t *) q->payload, q->len);
grzemich 0:d7bd7384a37c 600 dst += q->len;
grzemich 0:d7bd7384a37c 601 }
grzemich 0:d7bd7384a37c 602 np->len = p->tot_len;
grzemich 0:d7bd7384a37c 603
grzemich 0:d7bd7384a37c 604 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 605 ("lpc_low_level_output: Switched to DMA safe buffer, old=%p, new=%p\n",
grzemich 0:d7bd7384a37c 606 q, np));
grzemich 0:d7bd7384a37c 607
grzemich 0:d7bd7384a37c 608 /* use the new buffer for descrptor queueing. The original pbuf will
grzemich 0:d7bd7384a37c 609 be de-allocated outsuide this driver. */
grzemich 0:d7bd7384a37c 610 p = np;
grzemich 0:d7bd7384a37c 611 dn = 1;
grzemich 0:d7bd7384a37c 612 }
grzemich 0:d7bd7384a37c 613 #else
grzemich 0:d7bd7384a37c 614 if (notdmasafe)
grzemich 0:d7bd7384a37c 615 LWIP_ASSERT("lpc_low_level_output: Not a DMA safe pbuf",
grzemich 0:d7bd7384a37c 616 (notdmasafe == 0));
grzemich 0:d7bd7384a37c 617 #endif
grzemich 0:d7bd7384a37c 618
grzemich 0:d7bd7384a37c 619 /* Wait until enough descriptors are available for the transfer. */
grzemich 0:d7bd7384a37c 620 /* THIS WILL BLOCK UNTIL THERE ARE ENOUGH DESCRIPTORS AVAILABLE */
grzemich 0:d7bd7384a37c 621 while (dn > lpc_tx_ready(netif))
grzemich 0:d7bd7384a37c 622 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 623 osSemaphoreWait(lpc_enetif->xTXDCountSem.id, osWaitForever);
grzemich 0:d7bd7384a37c 624 #else
grzemich 0:d7bd7384a37c 625 osDelay(1);
grzemich 0:d7bd7384a37c 626 #endif
grzemich 0:d7bd7384a37c 627
grzemich 0:d7bd7384a37c 628 /* Get free TX buffer index */
grzemich 0:d7bd7384a37c 629 idx = LPC_EMAC->TxProduceIndex;
grzemich 0:d7bd7384a37c 630
grzemich 0:d7bd7384a37c 631 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 632 /* Get exclusive access */
grzemich 0:d7bd7384a37c 633 sys_mutex_lock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 634 #endif
grzemich 0:d7bd7384a37c 635
grzemich 0:d7bd7384a37c 636 /* Prevent LWIP from de-allocating this pbuf. The driver will
grzemich 0:d7bd7384a37c 637 free it once it's been transmitted. */
grzemich 0:d7bd7384a37c 638 if (!notdmasafe)
grzemich 0:d7bd7384a37c 639 pbuf_ref(p);
grzemich 0:d7bd7384a37c 640
grzemich 0:d7bd7384a37c 641 /* Setup transfers */
grzemich 0:d7bd7384a37c 642 q = p;
grzemich 0:d7bd7384a37c 643 while (dn > 0) {
grzemich 0:d7bd7384a37c 644 dn--;
grzemich 0:d7bd7384a37c 645
grzemich 0:d7bd7384a37c 646 /* Only save pointer to free on last descriptor */
grzemich 0:d7bd7384a37c 647 if (dn == 0) {
grzemich 0:d7bd7384a37c 648 /* Save size of packet and signal it's ready */
grzemich 0:d7bd7384a37c 649 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT |
grzemich 0:d7bd7384a37c 650 EMAC_TCTRL_LAST;
grzemich 0:d7bd7384a37c 651 lpc_enetif->txb[idx] = p;
grzemich 0:d7bd7384a37c 652 }
grzemich 0:d7bd7384a37c 653 else {
grzemich 0:d7bd7384a37c 654 /* Save size of packet, descriptor is not last */
grzemich 0:d7bd7384a37c 655 lpc_enetif->ptxd[idx].control = (q->len - 1) | EMAC_TCTRL_INT;
grzemich 0:d7bd7384a37c 656 lpc_enetif->txb[idx] = NULL;
grzemich 0:d7bd7384a37c 657 }
grzemich 0:d7bd7384a37c 658
grzemich 0:d7bd7384a37c 659 LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
grzemich 0:d7bd7384a37c 660 ("lpc_low_level_output: pbuf packet(%p) sent, chain#=%d,"
grzemich 0:d7bd7384a37c 661 " size = %d (index=%d)\n", q->payload, dn, q->len, idx));
grzemich 0:d7bd7384a37c 662
grzemich 0:d7bd7384a37c 663 lpc_enetif->ptxd[idx].packet = (u32_t) q->payload;
grzemich 0:d7bd7384a37c 664
grzemich 0:d7bd7384a37c 665 q = q->next;
grzemich 0:d7bd7384a37c 666
grzemich 0:d7bd7384a37c 667 idx++;
grzemich 0:d7bd7384a37c 668 if (idx >= LPC_NUM_BUFF_TXDESCS)
grzemich 0:d7bd7384a37c 669 idx = 0;
grzemich 0:d7bd7384a37c 670 }
grzemich 0:d7bd7384a37c 671
grzemich 0:d7bd7384a37c 672 LPC_EMAC->TxProduceIndex = idx;
grzemich 0:d7bd7384a37c 673
grzemich 0:d7bd7384a37c 674 LINK_STATS_INC(link.xmit);
grzemich 0:d7bd7384a37c 675
grzemich 0:d7bd7384a37c 676 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 677 /* Restore access */
grzemich 0:d7bd7384a37c 678 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 679 #endif
grzemich 0:d7bd7384a37c 680
grzemich 0:d7bd7384a37c 681 return ERR_OK;
grzemich 0:d7bd7384a37c 682 }
grzemich 0:d7bd7384a37c 683
grzemich 0:d7bd7384a37c 684 /** \brief LPC EMAC interrupt handler.
grzemich 0:d7bd7384a37c 685 *
grzemich 0:d7bd7384a37c 686 * This function handles the transmit, receive, and error interrupt of
grzemich 0:d7bd7384a37c 687 * the LPC177x_8x. This is meant to be used when NO_SYS=0.
grzemich 0:d7bd7384a37c 688 */
grzemich 0:d7bd7384a37c 689 void ENET_IRQHandler(void)
grzemich 0:d7bd7384a37c 690 {
grzemich 0:d7bd7384a37c 691 #if NO_SYS == 1
grzemich 0:d7bd7384a37c 692 /* Interrupts are not used without an RTOS */
grzemich 0:d7bd7384a37c 693 NVIC_DisableIRQ(ENET_IRQn);
grzemich 0:d7bd7384a37c 694 #else
grzemich 0:d7bd7384a37c 695 uint32_t ints;
grzemich 0:d7bd7384a37c 696
grzemich 0:d7bd7384a37c 697 /* Interrupts are of 2 groups - transmit or receive. Based on the
grzemich 0:d7bd7384a37c 698 interrupt, kick off the receive or transmit (cleanup) task */
grzemich 0:d7bd7384a37c 699
grzemich 0:d7bd7384a37c 700 /* Get pending interrupts */
grzemich 0:d7bd7384a37c 701 ints = LPC_EMAC->IntStatus;
grzemich 0:d7bd7384a37c 702
grzemich 0:d7bd7384a37c 703 if (ints & RXINTGROUP) {
grzemich 0:d7bd7384a37c 704 /* RX group interrupt(s): Give signal to wakeup RX receive task.*/
grzemich 0:d7bd7384a37c 705 osSignalSet(lpc_enetdata.RxThread->id, RX_SIGNAL);
grzemich 0:d7bd7384a37c 706 }
grzemich 0:d7bd7384a37c 707
grzemich 0:d7bd7384a37c 708 if (ints & TXINTGROUP) {
grzemich 0:d7bd7384a37c 709 /* TX group interrupt(s): Give semaphore to wakeup TX cleanup task. */
grzemich 0:d7bd7384a37c 710 sys_sem_signal(&lpc_enetdata.TxCleanSem);
grzemich 0:d7bd7384a37c 711 }
grzemich 0:d7bd7384a37c 712
grzemich 0:d7bd7384a37c 713 /* Clear pending interrupts */
grzemich 0:d7bd7384a37c 714 LPC_EMAC->IntClear = ints;
grzemich 0:d7bd7384a37c 715 #endif
grzemich 0:d7bd7384a37c 716 }
grzemich 0:d7bd7384a37c 717
grzemich 0:d7bd7384a37c 718 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 719 /** \brief Packet reception task
grzemich 0:d7bd7384a37c 720 *
grzemich 0:d7bd7384a37c 721 * This task is called when a packet is received. It will
grzemich 0:d7bd7384a37c 722 * pass the packet to the LWIP core.
grzemich 0:d7bd7384a37c 723 *
grzemich 0:d7bd7384a37c 724 * \param[in] pvParameters Not used yet
grzemich 0:d7bd7384a37c 725 */
grzemich 0:d7bd7384a37c 726 static void packet_rx(void* pvParameters) {
grzemich 0:d7bd7384a37c 727 struct lpc_enetdata *lpc_enetif = pvParameters;
grzemich 0:d7bd7384a37c 728
grzemich 0:d7bd7384a37c 729 while (1) {
grzemich 0:d7bd7384a37c 730 /* Wait for receive task to wakeup */
grzemich 0:d7bd7384a37c 731 osSignalWait(RX_SIGNAL, osWaitForever);
grzemich 0:d7bd7384a37c 732
grzemich 0:d7bd7384a37c 733 /* Process packets until all empty */
grzemich 0:d7bd7384a37c 734 while (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex)
grzemich 0:d7bd7384a37c 735 lpc_enetif_input(lpc_enetif->netif);
grzemich 0:d7bd7384a37c 736 }
grzemich 0:d7bd7384a37c 737 }
grzemich 0:d7bd7384a37c 738
grzemich 0:d7bd7384a37c 739 /** \brief Transmit cleanup task
grzemich 0:d7bd7384a37c 740 *
grzemich 0:d7bd7384a37c 741 * This task is called when a transmit interrupt occurs and
grzemich 0:d7bd7384a37c 742 * reclaims the pbuf and descriptor used for the packet once
grzemich 0:d7bd7384a37c 743 * the packet has been transferred.
grzemich 0:d7bd7384a37c 744 *
grzemich 0:d7bd7384a37c 745 * \param[in] pvParameters Not used yet
grzemich 0:d7bd7384a37c 746 */
grzemich 0:d7bd7384a37c 747 static void packet_tx(void* pvParameters) {
grzemich 0:d7bd7384a37c 748 struct lpc_enetdata *lpc_enetif = pvParameters;
grzemich 0:d7bd7384a37c 749 s32_t idx;
grzemich 0:d7bd7384a37c 750
grzemich 0:d7bd7384a37c 751 while (1) {
grzemich 0:d7bd7384a37c 752 /* Wait for transmit cleanup task to wakeup */
grzemich 0:d7bd7384a37c 753 sys_arch_sem_wait(&lpc_enetif->TxCleanSem, 0);
grzemich 0:d7bd7384a37c 754
grzemich 0:d7bd7384a37c 755 /* Error handling for TX underruns. This should never happen unless
grzemich 0:d7bd7384a37c 756 something is holding the bus or the clocks are going too slow. It
grzemich 0:d7bd7384a37c 757 can probably be safely removed. */
grzemich 0:d7bd7384a37c 758 if (LPC_EMAC->IntStatus & EMAC_INT_TX_UNDERRUN) {
grzemich 0:d7bd7384a37c 759 LINK_STATS_INC(link.err);
grzemich 0:d7bd7384a37c 760 LINK_STATS_INC(link.drop);
grzemich 0:d7bd7384a37c 761
grzemich 0:d7bd7384a37c 762 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 763 /* Get exclusive access */
grzemich 0:d7bd7384a37c 764 sys_mutex_lock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 765 #endif
grzemich 0:d7bd7384a37c 766 /* Reset the TX side */
grzemich 0:d7bd7384a37c 767 LPC_EMAC->MAC1 |= EMAC_MAC1_RES_TX;
grzemich 0:d7bd7384a37c 768 LPC_EMAC->IntClear = EMAC_INT_TX_UNDERRUN;
grzemich 0:d7bd7384a37c 769
grzemich 0:d7bd7384a37c 770 /* De-allocate all queued TX pbufs */
grzemich 0:d7bd7384a37c 771 for (idx = 0; idx < LPC_NUM_BUFF_TXDESCS; idx++) {
grzemich 0:d7bd7384a37c 772 if (lpc_enetif->txb[idx] != NULL) {
grzemich 0:d7bd7384a37c 773 pbuf_free(lpc_enetif->txb[idx]);
grzemich 0:d7bd7384a37c 774 lpc_enetif->txb[idx] = NULL;
grzemich 0:d7bd7384a37c 775 }
grzemich 0:d7bd7384a37c 776 }
grzemich 0:d7bd7384a37c 777
grzemich 0:d7bd7384a37c 778 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 779 /* Restore access */
grzemich 0:d7bd7384a37c 780 sys_mutex_unlock(&lpc_enetif->TXLockMutex);
grzemich 0:d7bd7384a37c 781 #endif
grzemich 0:d7bd7384a37c 782 /* Start TX side again */
grzemich 0:d7bd7384a37c 783 lpc_tx_setup(lpc_enetif);
grzemich 0:d7bd7384a37c 784 } else {
grzemich 0:d7bd7384a37c 785 /* Free TX buffers that are done sending */
grzemich 0:d7bd7384a37c 786 lpc_tx_reclaim(lpc_enetdata.netif);
grzemich 0:d7bd7384a37c 787 }
grzemich 0:d7bd7384a37c 788 }
grzemich 0:d7bd7384a37c 789 }
grzemich 0:d7bd7384a37c 790 #endif
grzemich 0:d7bd7384a37c 791
grzemich 0:d7bd7384a37c 792 /** \brief Low level init of the MAC and PHY.
grzemich 0:d7bd7384a37c 793 *
grzemich 0:d7bd7384a37c 794 * \param[in] netif Pointer to LWIP netif structure
grzemich 0:d7bd7384a37c 795 */
grzemich 0:d7bd7384a37c 796 static err_t low_level_init(struct netif *netif)
grzemich 0:d7bd7384a37c 797 {
grzemich 0:d7bd7384a37c 798 struct lpc_enetdata *lpc_enetif = netif->state;
grzemich 0:d7bd7384a37c 799 err_t err = ERR_OK;
grzemich 0:d7bd7384a37c 800
grzemich 0:d7bd7384a37c 801 /* Enable MII clocking */
grzemich 0:d7bd7384a37c 802 LPC_SC->PCONP |= CLKPWR_PCONP_PCENET;
grzemich 0:d7bd7384a37c 803
grzemich 0:d7bd7384a37c 804 #if defined(TARGET_LPC1768)
grzemich 0:d7bd7384a37c 805 LPC_PINCON->PINSEL2 = 0x50150105; /* Enable P1 Ethernet Pins. */
grzemich 0:d7bd7384a37c 806 LPC_PINCON->PINSEL3 = (LPC_PINCON->PINSEL3 & ~0x0000000F) | 0x00000005;
grzemich 0:d7bd7384a37c 807 #elif defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
grzemich 0:d7bd7384a37c 808 LPC_IOCON->P1_0 &= ~0x07; /* ENET I/O config */
grzemich 0:d7bd7384a37c 809 LPC_IOCON->P1_0 |= 0x01; /* ENET_TXD0 */
grzemich 0:d7bd7384a37c 810 LPC_IOCON->P1_1 &= ~0x07;
grzemich 0:d7bd7384a37c 811 LPC_IOCON->P1_1 |= 0x01; /* ENET_TXD1 */
grzemich 0:d7bd7384a37c 812 LPC_IOCON->P1_4 &= ~0x07;
grzemich 0:d7bd7384a37c 813 LPC_IOCON->P1_4 |= 0x01; /* ENET_TXEN */
grzemich 0:d7bd7384a37c 814 LPC_IOCON->P1_8 &= ~0x07;
grzemich 0:d7bd7384a37c 815 LPC_IOCON->P1_8 |= 0x01; /* ENET_CRS */
grzemich 0:d7bd7384a37c 816 LPC_IOCON->P1_9 &= ~0x07;
grzemich 0:d7bd7384a37c 817 LPC_IOCON->P1_9 |= 0x01; /* ENET_RXD0 */
grzemich 0:d7bd7384a37c 818 LPC_IOCON->P1_10 &= ~0x07;
grzemich 0:d7bd7384a37c 819 LPC_IOCON->P1_10 |= 0x01; /* ENET_RXD1 */
grzemich 0:d7bd7384a37c 820 LPC_IOCON->P1_14 &= ~0x07;
grzemich 0:d7bd7384a37c 821 LPC_IOCON->P1_14 |= 0x01; /* ENET_RX_ER */
grzemich 0:d7bd7384a37c 822 LPC_IOCON->P1_15 &= ~0x07;
grzemich 0:d7bd7384a37c 823 LPC_IOCON->P1_15 |= 0x01; /* ENET_REF_CLK */
grzemich 0:d7bd7384a37c 824 LPC_IOCON->P1_16 &= ~0x07; /* ENET/PHY I/O config */
grzemich 0:d7bd7384a37c 825 LPC_IOCON->P1_16 |= 0x01; /* ENET_MDC */
grzemich 0:d7bd7384a37c 826 LPC_IOCON->P1_17 &= ~0x07;
grzemich 0:d7bd7384a37c 827 LPC_IOCON->P1_17 |= 0x01; /* ENET_MDIO */
grzemich 0:d7bd7384a37c 828 #endif
grzemich 0:d7bd7384a37c 829
grzemich 0:d7bd7384a37c 830 /* Reset all MAC logic */
grzemich 0:d7bd7384a37c 831 LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX |
grzemich 0:d7bd7384a37c 832 EMAC_MAC1_RES_RX | EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES |
grzemich 0:d7bd7384a37c 833 EMAC_MAC1_SOFT_RES;
grzemich 0:d7bd7384a37c 834 LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES |
grzemich 0:d7bd7384a37c 835 EMAC_CR_PASS_RUNT_FRM;
grzemich 0:d7bd7384a37c 836 osDelay(10);
grzemich 0:d7bd7384a37c 837
grzemich 0:d7bd7384a37c 838 /* Initial MAC initialization */
grzemich 0:d7bd7384a37c 839 LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
grzemich 0:d7bd7384a37c 840 LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN |
grzemich 0:d7bd7384a37c 841 EMAC_MAC2_VLAN_PAD_EN;
grzemich 0:d7bd7384a37c 842 LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
grzemich 0:d7bd7384a37c 843
grzemich 0:d7bd7384a37c 844 /* Set RMII management clock rate to lowest speed */
grzemich 0:d7bd7384a37c 845 LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(11) | EMAC_MCFG_RES_MII;
grzemich 0:d7bd7384a37c 846 LPC_EMAC->MCFG &= ~EMAC_MCFG_RES_MII;
grzemich 0:d7bd7384a37c 847
grzemich 0:d7bd7384a37c 848 /* Maximum number of retries, 0x37 collision window, gap */
grzemich 0:d7bd7384a37c 849 LPC_EMAC->CLRT = EMAC_CLRT_DEF;
grzemich 0:d7bd7384a37c 850 LPC_EMAC->IPGR = EMAC_IPGR_P1_DEF | EMAC_IPGR_P2_DEF;
grzemich 0:d7bd7384a37c 851
grzemich 0:d7bd7384a37c 852 #if LPC_EMAC_RMII
grzemich 0:d7bd7384a37c 853 /* RMII setup */
grzemich 0:d7bd7384a37c 854 LPC_EMAC->Command = EMAC_CR_PASS_RUNT_FRM | EMAC_CR_RMII;
grzemich 0:d7bd7384a37c 855 #else
grzemich 0:d7bd7384a37c 856 /* MII setup */
grzemich 0:d7bd7384a37c 857 LPC_EMAC->CR = EMAC_CR_PASS_RUNT_FRM;
grzemich 0:d7bd7384a37c 858 #endif
grzemich 0:d7bd7384a37c 859
grzemich 0:d7bd7384a37c 860 /* Initialize the PHY and reset */
grzemich 0:d7bd7384a37c 861 err = lpc_phy_init(netif, LPC_EMAC_RMII);
grzemich 0:d7bd7384a37c 862 if (err != ERR_OK)
grzemich 0:d7bd7384a37c 863 return err;
grzemich 0:d7bd7384a37c 864
grzemich 0:d7bd7384a37c 865 /* Save station address */
grzemich 0:d7bd7384a37c 866 LPC_EMAC->SA2 = (u32_t) netif->hwaddr[0] |
grzemich 0:d7bd7384a37c 867 (((u32_t) netif->hwaddr[1]) << 8);
grzemich 0:d7bd7384a37c 868 LPC_EMAC->SA1 = (u32_t) netif->hwaddr[2] |
grzemich 0:d7bd7384a37c 869 (((u32_t) netif->hwaddr[3]) << 8);
grzemich 0:d7bd7384a37c 870 LPC_EMAC->SA0 = (u32_t) netif->hwaddr[4] |
grzemich 0:d7bd7384a37c 871 (((u32_t) netif->hwaddr[5]) << 8);
grzemich 0:d7bd7384a37c 872
grzemich 0:d7bd7384a37c 873 /* Setup transmit and receive descriptors */
grzemich 0:d7bd7384a37c 874 if (lpc_tx_setup(lpc_enetif) != ERR_OK)
grzemich 0:d7bd7384a37c 875 return ERR_BUF;
grzemich 0:d7bd7384a37c 876 if (lpc_rx_setup(lpc_enetif) != ERR_OK)
grzemich 0:d7bd7384a37c 877 return ERR_BUF;
grzemich 0:d7bd7384a37c 878
grzemich 0:d7bd7384a37c 879 /* Enable packet reception */
grzemich 0:d7bd7384a37c 880 #if IP_SOF_BROADCAST_RECV
grzemich 0:d7bd7384a37c 881 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_MCAST_EN;
grzemich 0:d7bd7384a37c 882 #else
grzemich 0:d7bd7384a37c 883 LPC_EMAC->RxFilterCtrl = EMAC_RFC_PERFECT_EN;
grzemich 0:d7bd7384a37c 884 #endif
grzemich 0:d7bd7384a37c 885
grzemich 0:d7bd7384a37c 886 /* Clear and enable rx/tx interrupts */
grzemich 0:d7bd7384a37c 887 LPC_EMAC->IntClear = 0xFFFF;
grzemich 0:d7bd7384a37c 888 LPC_EMAC->IntEnable = RXINTGROUP | TXINTGROUP;
grzemich 0:d7bd7384a37c 889
grzemich 0:d7bd7384a37c 890 /* Enable RX and TX */
grzemich 0:d7bd7384a37c 891 LPC_EMAC->Command |= EMAC_CR_RX_EN | EMAC_CR_TX_EN;
grzemich 0:d7bd7384a37c 892 LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
grzemich 0:d7bd7384a37c 893
grzemich 0:d7bd7384a37c 894 return err;
grzemich 0:d7bd7384a37c 895 }
grzemich 0:d7bd7384a37c 896
grzemich 0:d7bd7384a37c 897 /* This function provides a method for the PHY to setup the EMAC
grzemich 0:d7bd7384a37c 898 for the PHY negotiated duplex mode */
grzemich 0:d7bd7384a37c 899 void lpc_emac_set_duplex(int full_duplex)
grzemich 0:d7bd7384a37c 900 {
grzemich 0:d7bd7384a37c 901 if (full_duplex) {
grzemich 0:d7bd7384a37c 902 LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
grzemich 0:d7bd7384a37c 903 LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
grzemich 0:d7bd7384a37c 904 LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
grzemich 0:d7bd7384a37c 905 } else {
grzemich 0:d7bd7384a37c 906 LPC_EMAC->MAC2 &= ~EMAC_MAC2_FULL_DUP;
grzemich 0:d7bd7384a37c 907 LPC_EMAC->Command &= ~EMAC_CR_FULL_DUP;
grzemich 0:d7bd7384a37c 908 LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
grzemich 0:d7bd7384a37c 909 }
grzemich 0:d7bd7384a37c 910 }
grzemich 0:d7bd7384a37c 911
grzemich 0:d7bd7384a37c 912 /* This function provides a method for the PHY to setup the EMAC
grzemich 0:d7bd7384a37c 913 for the PHY negotiated bit rate */
grzemich 0:d7bd7384a37c 914 void lpc_emac_set_speed(int mbs_100)
grzemich 0:d7bd7384a37c 915 {
grzemich 0:d7bd7384a37c 916 if (mbs_100)
grzemich 0:d7bd7384a37c 917 LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
grzemich 0:d7bd7384a37c 918 else
grzemich 0:d7bd7384a37c 919 LPC_EMAC->SUPP = 0;
grzemich 0:d7bd7384a37c 920 }
grzemich 0:d7bd7384a37c 921
grzemich 0:d7bd7384a37c 922 /**
grzemich 0:d7bd7384a37c 923 * This function is the ethernet packet send function. It calls
grzemich 0:d7bd7384a37c 924 * etharp_output after checking link status.
grzemich 0:d7bd7384a37c 925 *
grzemich 0:d7bd7384a37c 926 * \param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 927 * \param[in] q Pointer to pbug to send
grzemich 0:d7bd7384a37c 928 * \param[in] ipaddr IP address
grzemich 0:d7bd7384a37c 929 * \return ERR_OK or error code
grzemich 0:d7bd7384a37c 930 */
grzemich 0:d7bd7384a37c 931 err_t lpc_etharp_output(struct netif *netif, struct pbuf *q,
grzemich 0:d7bd7384a37c 932 ip_addr_t *ipaddr)
grzemich 0:d7bd7384a37c 933 {
grzemich 0:d7bd7384a37c 934 /* Only send packet is link is up */
grzemich 0:d7bd7384a37c 935 if (netif->flags & NETIF_FLAG_LINK_UP)
grzemich 0:d7bd7384a37c 936 return etharp_output(netif, q, ipaddr);
grzemich 0:d7bd7384a37c 937
grzemich 0:d7bd7384a37c 938 return ERR_CONN;
grzemich 0:d7bd7384a37c 939 }
grzemich 0:d7bd7384a37c 940
grzemich 0:d7bd7384a37c 941 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 942 /* periodic PHY status update */
grzemich 0:d7bd7384a37c 943 void phy_update(void const *nif) {
grzemich 0:d7bd7384a37c 944 lpc_phy_sts_sm((struct netif*)nif);
grzemich 0:d7bd7384a37c 945 }
grzemich 0:d7bd7384a37c 946 osTimerDef(phy_update, phy_update);
grzemich 0:d7bd7384a37c 947 #endif
grzemich 0:d7bd7384a37c 948
grzemich 0:d7bd7384a37c 949 /**
grzemich 0:d7bd7384a37c 950 * Should be called at the beginning of the program to set up the
grzemich 0:d7bd7384a37c 951 * network interface.
grzemich 0:d7bd7384a37c 952 *
grzemich 0:d7bd7384a37c 953 * This function should be passed as a parameter to netif_add().
grzemich 0:d7bd7384a37c 954 *
grzemich 0:d7bd7384a37c 955 * @param[in] netif the lwip network interface structure for this lpc_enetif
grzemich 0:d7bd7384a37c 956 * @return ERR_OK if the loopif is initialized
grzemich 0:d7bd7384a37c 957 * ERR_MEM if private data couldn't be allocated
grzemich 0:d7bd7384a37c 958 * any other err_t on error
grzemich 0:d7bd7384a37c 959 */
grzemich 0:d7bd7384a37c 960 err_t eth_arch_enetif_init(struct netif *netif)
grzemich 0:d7bd7384a37c 961 {
grzemich 0:d7bd7384a37c 962 err_t err;
grzemich 0:d7bd7384a37c 963
grzemich 0:d7bd7384a37c 964 LWIP_ASSERT("netif != NULL", (netif != NULL));
grzemich 0:d7bd7384a37c 965
grzemich 0:d7bd7384a37c 966 lpc_enetdata.netif = netif;
grzemich 0:d7bd7384a37c 967
grzemich 0:d7bd7384a37c 968 /* set MAC hardware address */
grzemich 0:d7bd7384a37c 969 #if (MBED_MAC_ADDRESS_SUM != MBED_MAC_ADDR_INTERFACE)
grzemich 0:d7bd7384a37c 970 netif->hwaddr[0] = MBED_MAC_ADDR_0;
grzemich 0:d7bd7384a37c 971 netif->hwaddr[1] = MBED_MAC_ADDR_1;
grzemich 0:d7bd7384a37c 972 netif->hwaddr[2] = MBED_MAC_ADDR_2;
grzemich 0:d7bd7384a37c 973 netif->hwaddr[3] = MBED_MAC_ADDR_3;
grzemich 0:d7bd7384a37c 974 netif->hwaddr[4] = MBED_MAC_ADDR_4;
grzemich 0:d7bd7384a37c 975 netif->hwaddr[5] = MBED_MAC_ADDR_5;
grzemich 0:d7bd7384a37c 976 #else
grzemich 0:d7bd7384a37c 977 mbed_mac_address((char *)netif->hwaddr);
grzemich 0:d7bd7384a37c 978 #endif
grzemich 0:d7bd7384a37c 979 netif->hwaddr_len = ETHARP_HWADDR_LEN;
grzemich 0:d7bd7384a37c 980
grzemich 0:d7bd7384a37c 981 /* maximum transfer unit */
grzemich 0:d7bd7384a37c 982 netif->mtu = 1500;
grzemich 0:d7bd7384a37c 983
grzemich 0:d7bd7384a37c 984 /* device capabilities */
grzemich 0:d7bd7384a37c 985 netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_ETHERNET | NETIF_FLAG_IGMP;
grzemich 0:d7bd7384a37c 986
grzemich 0:d7bd7384a37c 987 /* Initialize the hardware */
grzemich 0:d7bd7384a37c 988 netif->state = &lpc_enetdata;
grzemich 0:d7bd7384a37c 989 err = low_level_init(netif);
grzemich 0:d7bd7384a37c 990 if (err != ERR_OK)
grzemich 0:d7bd7384a37c 991 return err;
grzemich 0:d7bd7384a37c 992
grzemich 0:d7bd7384a37c 993 #if LWIP_NETIF_HOSTNAME
grzemich 0:d7bd7384a37c 994 /* Initialize interface hostname */
grzemich 0:d7bd7384a37c 995 netif->hostname = "lwiplpc";
grzemich 0:d7bd7384a37c 996 #endif /* LWIP_NETIF_HOSTNAME */
grzemich 0:d7bd7384a37c 997
grzemich 0:d7bd7384a37c 998 netif->name[0] = 'e';
grzemich 0:d7bd7384a37c 999 netif->name[1] = 'n';
grzemich 0:d7bd7384a37c 1000
grzemich 0:d7bd7384a37c 1001 netif->output = lpc_etharp_output;
grzemich 0:d7bd7384a37c 1002 netif->linkoutput = lpc_low_level_output;
grzemich 0:d7bd7384a37c 1003
grzemich 0:d7bd7384a37c 1004 /* CMSIS-RTOS, start tasks */
grzemich 0:d7bd7384a37c 1005 #if NO_SYS == 0
grzemich 0:d7bd7384a37c 1006 #ifdef CMSIS_OS_RTX
grzemich 0:d7bd7384a37c 1007 memset(lpc_enetdata.xTXDCountSem.data, 0, sizeof(lpc_enetdata.xTXDCountSem.data));
grzemich 0:d7bd7384a37c 1008 lpc_enetdata.xTXDCountSem.def.semaphore = lpc_enetdata.xTXDCountSem.data;
grzemich 0:d7bd7384a37c 1009 #endif
grzemich 0:d7bd7384a37c 1010 lpc_enetdata.xTXDCountSem.id = osSemaphoreCreate(&lpc_enetdata.xTXDCountSem.def, LPC_NUM_BUFF_TXDESCS);
grzemich 0:d7bd7384a37c 1011 LWIP_ASSERT("xTXDCountSem creation error", (lpc_enetdata.xTXDCountSem.id != NULL));
grzemich 0:d7bd7384a37c 1012
grzemich 0:d7bd7384a37c 1013 err = sys_mutex_new(&lpc_enetdata.TXLockMutex);
grzemich 0:d7bd7384a37c 1014 LWIP_ASSERT("TXLockMutex creation error", (err == ERR_OK));
grzemich 0:d7bd7384a37c 1015
grzemich 0:d7bd7384a37c 1016 /* Packet receive task */
grzemich 0:d7bd7384a37c 1017 lpc_enetdata.RxThread = sys_thread_new("receive_thread", packet_rx, netif->state, DEFAULT_THREAD_STACKSIZE, RX_PRIORITY);
grzemich 0:d7bd7384a37c 1018 LWIP_ASSERT("RxThread creation error", (lpc_enetdata.RxThread));
grzemich 0:d7bd7384a37c 1019
grzemich 0:d7bd7384a37c 1020 /* Transmit cleanup task */
grzemich 0:d7bd7384a37c 1021 err = sys_sem_new(&lpc_enetdata.TxCleanSem, 0);
grzemich 0:d7bd7384a37c 1022 LWIP_ASSERT("TxCleanSem creation error", (err == ERR_OK));
grzemich 0:d7bd7384a37c 1023 sys_thread_new("txclean_thread", packet_tx, netif->state, DEFAULT_THREAD_STACKSIZE, TX_PRIORITY);
grzemich 0:d7bd7384a37c 1024
grzemich 0:d7bd7384a37c 1025 /* periodic PHY status update */
grzemich 0:d7bd7384a37c 1026 osTimerId phy_timer = osTimerCreate(osTimer(phy_update), osTimerPeriodic, (void *)netif);
grzemich 0:d7bd7384a37c 1027 osTimerStart(phy_timer, 250);
grzemich 0:d7bd7384a37c 1028 #endif
grzemich 0:d7bd7384a37c 1029
grzemich 0:d7bd7384a37c 1030 return ERR_OK;
grzemich 0:d7bd7384a37c 1031 }
grzemich 0:d7bd7384a37c 1032
grzemich 0:d7bd7384a37c 1033 void eth_arch_enable_interrupts(void) {
grzemich 0:d7bd7384a37c 1034 NVIC_SetPriority(ENET_IRQn, ((0x01 << 3) | 0x01));
grzemich 0:d7bd7384a37c 1035 NVIC_EnableIRQ(ENET_IRQn);
grzemich 0:d7bd7384a37c 1036 }
grzemich 0:d7bd7384a37c 1037
grzemich 0:d7bd7384a37c 1038 void eth_arch_disable_interrupts(void) {
grzemich 0:d7bd7384a37c 1039 NVIC_DisableIRQ(ENET_IRQn);
grzemich 0:d7bd7384a37c 1040 }
grzemich 0:d7bd7384a37c 1041
grzemich 0:d7bd7384a37c 1042 /**
grzemich 0:d7bd7384a37c 1043 * @}
grzemich 0:d7bd7384a37c 1044 */
grzemich 0:d7bd7384a37c 1045
grzemich 0:d7bd7384a37c 1046 /* --------------------------------- End Of File ------------------------------ */