Senior Design: Sound Monitor / STM32L4xx_HAL_Driver

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Src/stm32l4xx_hal_nand.c@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:
EricLew
Date:
Mon Nov 02 19:37:23 2015 +0000
Revision:
0:80ee8f3b695e
Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_hal_nand.c
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief NAND HAL module driver.
EricLew 0:80ee8f3b695e 8 * This file provides a generic firmware to drive NAND memories mounted
EricLew 0:80ee8f3b695e 9 * as external device.
EricLew 0:80ee8f3b695e 10 *
EricLew 0:80ee8f3b695e 11 @verbatim
EricLew 0:80ee8f3b695e 12 ==============================================================================
EricLew 0:80ee8f3b695e 13 ##### How to use this driver #####
EricLew 0:80ee8f3b695e 14 ==============================================================================
EricLew 0:80ee8f3b695e 15 [..]
EricLew 0:80ee8f3b695e 16 This driver is a generic layered driver which contains a set of APIs used to
EricLew 0:80ee8f3b695e 17 control NAND flash memories. It uses the FMC layer functions to interface
EricLew 0:80ee8f3b695e 18 with NAND devices. This driver is used as follows:
EricLew 0:80ee8f3b695e 19
EricLew 0:80ee8f3b695e 20 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
EricLew 0:80ee8f3b695e 21 with control and timing parameters for both common and attribute spaces.
EricLew 0:80ee8f3b695e 22
EricLew 0:80ee8f3b695e 23 (+) Read NAND flash memory maker and device IDs using the function
EricLew 0:80ee8f3b695e 24 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
EricLew 0:80ee8f3b695e 25 structure declared by the function caller.
EricLew 0:80ee8f3b695e 26
EricLew 0:80ee8f3b695e 27 (+) Access NAND flash memory by read/write operations using the functions
EricLew 0:80ee8f3b695e 28 HAL_NAND_Read_Page()/HAL_NAND_Read_SpareArea(), HAL_NAND_Write_Page()/HAL_NAND_Write_SpareArea()
EricLew 0:80ee8f3b695e 29 to read/write page(s)/spare area(s). These functions use specific device
EricLew 0:80ee8f3b695e 30 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
EricLew 0:80ee8f3b695e 31 structure. The read/write address information is contained by the Nand_Address_Typedef
EricLew 0:80ee8f3b695e 32 structure passed as parameter.
EricLew 0:80ee8f3b695e 33
EricLew 0:80ee8f3b695e 34 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
EricLew 0:80ee8f3b695e 35
EricLew 0:80ee8f3b695e 36 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
EricLew 0:80ee8f3b695e 37 The erase block address information is contained in the Nand_Address_Typedef
EricLew 0:80ee8f3b695e 38 structure passed as parameter.
EricLew 0:80ee8f3b695e 39
EricLew 0:80ee8f3b695e 40 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
EricLew 0:80ee8f3b695e 41
EricLew 0:80ee8f3b695e 42 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
EricLew 0:80ee8f3b695e 43 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
EricLew 0:80ee8f3b695e 44 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
EricLew 0:80ee8f3b695e 45
EricLew 0:80ee8f3b695e 46 (+) You can monitor the NAND device HAL state by calling the function
EricLew 0:80ee8f3b695e 47 HAL_NAND_GetState()
EricLew 0:80ee8f3b695e 48
EricLew 0:80ee8f3b695e 49 [..]
EricLew 0:80ee8f3b695e 50 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
EricLew 0:80ee8f3b695e 51 If a NAND flash device contains different operations and/or implementations,
EricLew 0:80ee8f3b695e 52 it should be implemented separately.
EricLew 0:80ee8f3b695e 53
EricLew 0:80ee8f3b695e 54 @endverbatim
EricLew 0:80ee8f3b695e 55 ******************************************************************************
EricLew 0:80ee8f3b695e 56 * @attention
EricLew 0:80ee8f3b695e 57 *
EricLew 0:80ee8f3b695e 58 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 59 *
EricLew 0:80ee8f3b695e 60 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 61 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 62 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 63 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 64 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 65 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 66 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 68 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 69 * without specific prior written permission.
EricLew 0:80ee8f3b695e 70 *
EricLew 0:80ee8f3b695e 71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 81 *
EricLew 0:80ee8f3b695e 82 ******************************************************************************
EricLew 0:80ee8f3b695e 83 */
EricLew 0:80ee8f3b695e 84
EricLew 0:80ee8f3b695e 85 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 86 #include "stm32l4xx_hal.h"
EricLew 0:80ee8f3b695e 87
EricLew 0:80ee8f3b695e 88 /** @addtogroup STM32L4xx_HAL_Driver
EricLew 0:80ee8f3b695e 89 * @{
EricLew 0:80ee8f3b695e 90 */
EricLew 0:80ee8f3b695e 91
EricLew 0:80ee8f3b695e 92 #ifdef HAL_NAND_MODULE_ENABLED
EricLew 0:80ee8f3b695e 93
EricLew 0:80ee8f3b695e 94 /** @defgroup NAND NAND
EricLew 0:80ee8f3b695e 95 * @brief NAND HAL module driver
EricLew 0:80ee8f3b695e 96 * @{
EricLew 0:80ee8f3b695e 97 */
EricLew 0:80ee8f3b695e 98
EricLew 0:80ee8f3b695e 99 /* Private typedef -----------------------------------------------------------*/
EricLew 0:80ee8f3b695e 100 /* Private define ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 101 /** @defgroup NAND_Private_Constants NAND Private Constants
EricLew 0:80ee8f3b695e 102 * @{
EricLew 0:80ee8f3b695e 103 */
EricLew 0:80ee8f3b695e 104
EricLew 0:80ee8f3b695e 105 /**
EricLew 0:80ee8f3b695e 106 * @}
EricLew 0:80ee8f3b695e 107 */
EricLew 0:80ee8f3b695e 108
EricLew 0:80ee8f3b695e 109 /* Private macro -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 110 /** @defgroup NAND_Private_Macros NAND Private Macros
EricLew 0:80ee8f3b695e 111 * @{
EricLew 0:80ee8f3b695e 112 */
EricLew 0:80ee8f3b695e 113
EricLew 0:80ee8f3b695e 114 /**
EricLew 0:80ee8f3b695e 115 * @}
EricLew 0:80ee8f3b695e 116 */
EricLew 0:80ee8f3b695e 117
EricLew 0:80ee8f3b695e 118 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 119 /* Private function prototypes -----------------------------------------------*/
EricLew 0:80ee8f3b695e 120 /** @defgroup NAND_Private_Functions NAND Private Functions
EricLew 0:80ee8f3b695e 121 * @{
EricLew 0:80ee8f3b695e 122 */
EricLew 0:80ee8f3b695e 123 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address);
EricLew 0:80ee8f3b695e 124 /**
EricLew 0:80ee8f3b695e 125 * @}
EricLew 0:80ee8f3b695e 126 */
EricLew 0:80ee8f3b695e 127
EricLew 0:80ee8f3b695e 128 /* Exported functions ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 129
EricLew 0:80ee8f3b695e 130 /** @defgroup NAND_Exported_Functions NAND Exported Functions
EricLew 0:80ee8f3b695e 131 * @{
EricLew 0:80ee8f3b695e 132 */
EricLew 0:80ee8f3b695e 133
EricLew 0:80ee8f3b695e 134 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
EricLew 0:80ee8f3b695e 135 * @brief Initialization and Configuration functions
EricLew 0:80ee8f3b695e 136 *
EricLew 0:80ee8f3b695e 137 @verbatim
EricLew 0:80ee8f3b695e 138 ==============================================================================
EricLew 0:80ee8f3b695e 139 ##### NAND Initialization and de-initialization functions #####
EricLew 0:80ee8f3b695e 140 ==============================================================================
EricLew 0:80ee8f3b695e 141 [..]
EricLew 0:80ee8f3b695e 142 This section provides functions allowing to initialize/de-initialize
EricLew 0:80ee8f3b695e 143 the NAND memory
EricLew 0:80ee8f3b695e 144
EricLew 0:80ee8f3b695e 145 @endverbatim
EricLew 0:80ee8f3b695e 146 * @{
EricLew 0:80ee8f3b695e 147 */
EricLew 0:80ee8f3b695e 148
EricLew 0:80ee8f3b695e 149 /**
EricLew 0:80ee8f3b695e 150 * @brief Perform NAND memory Initialization sequence.
EricLew 0:80ee8f3b695e 151 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 152 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 153 * @param ComSpace_Timing: pointer to Common space timing structure
EricLew 0:80ee8f3b695e 154 * @param AttSpace_Timing: pointer to Attribute space timing structure
EricLew 0:80ee8f3b695e 155 * @retval HAL status
EricLew 0:80ee8f3b695e 156 */
EricLew 0:80ee8f3b695e 157 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
EricLew 0:80ee8f3b695e 158 {
EricLew 0:80ee8f3b695e 159 /* Check the NAND handle state */
EricLew 0:80ee8f3b695e 160 if(hnand == NULL)
EricLew 0:80ee8f3b695e 161 {
EricLew 0:80ee8f3b695e 162 return HAL_ERROR;
EricLew 0:80ee8f3b695e 163 }
EricLew 0:80ee8f3b695e 164
EricLew 0:80ee8f3b695e 165 if(hnand->State == HAL_NAND_STATE_RESET)
EricLew 0:80ee8f3b695e 166 {
EricLew 0:80ee8f3b695e 167 /* Allocate lock resource and initialize it */
EricLew 0:80ee8f3b695e 168 hnand->Lock = HAL_UNLOCKED;
EricLew 0:80ee8f3b695e 169
EricLew 0:80ee8f3b695e 170 /* Initialize the low level hardware (MSP) */
EricLew 0:80ee8f3b695e 171 HAL_NAND_MspInit(hnand);
EricLew 0:80ee8f3b695e 172 }
EricLew 0:80ee8f3b695e 173
EricLew 0:80ee8f3b695e 174 /* Initialize NAND control Interface */
EricLew 0:80ee8f3b695e 175 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
EricLew 0:80ee8f3b695e 176
EricLew 0:80ee8f3b695e 177 /* Initialize NAND common space timing Interface */
EricLew 0:80ee8f3b695e 178 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
EricLew 0:80ee8f3b695e 179
EricLew 0:80ee8f3b695e 180 /* Initialize NAND attribute space timing Interface */
EricLew 0:80ee8f3b695e 181 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
EricLew 0:80ee8f3b695e 182
EricLew 0:80ee8f3b695e 183 /* Enable the NAND device */
EricLew 0:80ee8f3b695e 184 __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
EricLew 0:80ee8f3b695e 185
EricLew 0:80ee8f3b695e 186 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 187 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 188
EricLew 0:80ee8f3b695e 189 return HAL_OK;
EricLew 0:80ee8f3b695e 190 }
EricLew 0:80ee8f3b695e 191
EricLew 0:80ee8f3b695e 192 /**
EricLew 0:80ee8f3b695e 193 * @brief Perform NAND memory De-Initialization sequence.
EricLew 0:80ee8f3b695e 194 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 195 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 196 * @retval HAL status
EricLew 0:80ee8f3b695e 197 */
EricLew 0:80ee8f3b695e 198 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 199 {
EricLew 0:80ee8f3b695e 200 /* Initialize the low level hardware (MSP) */
EricLew 0:80ee8f3b695e 201 HAL_NAND_MspDeInit(hnand);
EricLew 0:80ee8f3b695e 202
EricLew 0:80ee8f3b695e 203 /* Configure the NAND registers with their reset values */
EricLew 0:80ee8f3b695e 204 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
EricLew 0:80ee8f3b695e 205
EricLew 0:80ee8f3b695e 206 /* Reset the NAND controller state */
EricLew 0:80ee8f3b695e 207 hnand->State = HAL_NAND_STATE_RESET;
EricLew 0:80ee8f3b695e 208
EricLew 0:80ee8f3b695e 209 /* Release Lock */
EricLew 0:80ee8f3b695e 210 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 211
EricLew 0:80ee8f3b695e 212 return HAL_OK;
EricLew 0:80ee8f3b695e 213 }
EricLew 0:80ee8f3b695e 214
EricLew 0:80ee8f3b695e 215 /**
EricLew 0:80ee8f3b695e 216 * @brief Initialize the NAND MSP.
EricLew 0:80ee8f3b695e 217 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 218 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 219 * @retval None
EricLew 0:80ee8f3b695e 220 */
EricLew 0:80ee8f3b695e 221 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 222 {
EricLew 0:80ee8f3b695e 223 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 224 the HAL_NAND_MspInit could be implemented in the user file
EricLew 0:80ee8f3b695e 225 */
EricLew 0:80ee8f3b695e 226 }
EricLew 0:80ee8f3b695e 227
EricLew 0:80ee8f3b695e 228 /**
EricLew 0:80ee8f3b695e 229 * @brief DeInitialize the NAND MSP.
EricLew 0:80ee8f3b695e 230 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 231 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 232 * @retval None
EricLew 0:80ee8f3b695e 233 */
EricLew 0:80ee8f3b695e 234 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 235 {
EricLew 0:80ee8f3b695e 236 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 237 the HAL_NAND_MspDeInit could be implemented in the user file
EricLew 0:80ee8f3b695e 238 */
EricLew 0:80ee8f3b695e 239 }
EricLew 0:80ee8f3b695e 240
EricLew 0:80ee8f3b695e 241
EricLew 0:80ee8f3b695e 242 /**
EricLew 0:80ee8f3b695e 243 * @brief This function handles NAND device interrupt request.
EricLew 0:80ee8f3b695e 244 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 245 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 246 * @retval HAL status
EricLew 0:80ee8f3b695e 247 */
EricLew 0:80ee8f3b695e 248 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 249 {
EricLew 0:80ee8f3b695e 250 /* Check NAND interrupt Rising edge flag */
EricLew 0:80ee8f3b695e 251 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
EricLew 0:80ee8f3b695e 252 {
EricLew 0:80ee8f3b695e 253 /* NAND interrupt callback*/
EricLew 0:80ee8f3b695e 254 HAL_NAND_ITCallback(hnand);
EricLew 0:80ee8f3b695e 255
EricLew 0:80ee8f3b695e 256 /* Clear NAND interrupt Rising edge pending bit */
EricLew 0:80ee8f3b695e 257 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
EricLew 0:80ee8f3b695e 258 }
EricLew 0:80ee8f3b695e 259
EricLew 0:80ee8f3b695e 260 /* Check NAND interrupt Level flag */
EricLew 0:80ee8f3b695e 261 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
EricLew 0:80ee8f3b695e 262 {
EricLew 0:80ee8f3b695e 263 /* NAND interrupt callback*/
EricLew 0:80ee8f3b695e 264 HAL_NAND_ITCallback(hnand);
EricLew 0:80ee8f3b695e 265
EricLew 0:80ee8f3b695e 266 /* Clear NAND interrupt Level pending bit */
EricLew 0:80ee8f3b695e 267 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
EricLew 0:80ee8f3b695e 268 }
EricLew 0:80ee8f3b695e 269
EricLew 0:80ee8f3b695e 270 /* Check NAND interrupt Falling edge flag */
EricLew 0:80ee8f3b695e 271 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
EricLew 0:80ee8f3b695e 272 {
EricLew 0:80ee8f3b695e 273 /* NAND interrupt callback*/
EricLew 0:80ee8f3b695e 274 HAL_NAND_ITCallback(hnand);
EricLew 0:80ee8f3b695e 275
EricLew 0:80ee8f3b695e 276 /* Clear NAND interrupt Falling edge pending bit */
EricLew 0:80ee8f3b695e 277 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
EricLew 0:80ee8f3b695e 278 }
EricLew 0:80ee8f3b695e 279
EricLew 0:80ee8f3b695e 280 /* Check NAND interrupt FIFO empty flag */
EricLew 0:80ee8f3b695e 281 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
EricLew 0:80ee8f3b695e 282 {
EricLew 0:80ee8f3b695e 283 /* NAND interrupt callback*/
EricLew 0:80ee8f3b695e 284 HAL_NAND_ITCallback(hnand);
EricLew 0:80ee8f3b695e 285
EricLew 0:80ee8f3b695e 286 /* Clear NAND interrupt FIFO empty pending bit */
EricLew 0:80ee8f3b695e 287 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
EricLew 0:80ee8f3b695e 288 }
EricLew 0:80ee8f3b695e 289 }
EricLew 0:80ee8f3b695e 290
EricLew 0:80ee8f3b695e 291 /**
EricLew 0:80ee8f3b695e 292 * @brief NAND interrupt feature callback.
EricLew 0:80ee8f3b695e 293 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 294 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 295 * @retval None
EricLew 0:80ee8f3b695e 296 */
EricLew 0:80ee8f3b695e 297 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 298 {
EricLew 0:80ee8f3b695e 299 /* NOTE : This function should not be modified, when the callback is needed,
EricLew 0:80ee8f3b695e 300 the HAL_NAND_ITCallback could be implemented in the user file
EricLew 0:80ee8f3b695e 301 */
EricLew 0:80ee8f3b695e 302 }
EricLew 0:80ee8f3b695e 303
EricLew 0:80ee8f3b695e 304 /**
EricLew 0:80ee8f3b695e 305 * @}
EricLew 0:80ee8f3b695e 306 */
EricLew 0:80ee8f3b695e 307
EricLew 0:80ee8f3b695e 308 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
EricLew 0:80ee8f3b695e 309 * @brief Input Output and memory control functions
EricLew 0:80ee8f3b695e 310 *
EricLew 0:80ee8f3b695e 311 @verbatim
EricLew 0:80ee8f3b695e 312 ==============================================================================
EricLew 0:80ee8f3b695e 313 ##### NAND Input and Output functions #####
EricLew 0:80ee8f3b695e 314 ==============================================================================
EricLew 0:80ee8f3b695e 315 [..]
EricLew 0:80ee8f3b695e 316 This section provides functions allowing to use and control the NAND
EricLew 0:80ee8f3b695e 317 memory
EricLew 0:80ee8f3b695e 318
EricLew 0:80ee8f3b695e 319 @endverbatim
EricLew 0:80ee8f3b695e 320 * @{
EricLew 0:80ee8f3b695e 321 */
EricLew 0:80ee8f3b695e 322
EricLew 0:80ee8f3b695e 323 /**
EricLew 0:80ee8f3b695e 324 * @brief Read the NAND memory electronic signature.
EricLew 0:80ee8f3b695e 325 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 326 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 327 * @param pNAND_ID: NAND ID structure
EricLew 0:80ee8f3b695e 328 * @retval HAL status
EricLew 0:80ee8f3b695e 329 */
EricLew 0:80ee8f3b695e 330 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
EricLew 0:80ee8f3b695e 331 {
EricLew 0:80ee8f3b695e 332 __IO uint32_t data = 0;
EricLew 0:80ee8f3b695e 333 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 334
EricLew 0:80ee8f3b695e 335 /* Process Locked */
EricLew 0:80ee8f3b695e 336 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 337
EricLew 0:80ee8f3b695e 338 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 339 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 340 {
EricLew 0:80ee8f3b695e 341 return HAL_BUSY;
EricLew 0:80ee8f3b695e 342 }
EricLew 0:80ee8f3b695e 343
EricLew 0:80ee8f3b695e 344 /* Identify the device address */
EricLew 0:80ee8f3b695e 345 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 346
EricLew 0:80ee8f3b695e 347 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 348 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 349
EricLew 0:80ee8f3b695e 350 /* Send Read ID command sequence */
EricLew 0:80ee8f3b695e 351 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
EricLew 0:80ee8f3b695e 352 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
EricLew 0:80ee8f3b695e 353
EricLew 0:80ee8f3b695e 354 /* Read the electronic signature from NAND flash */
EricLew 0:80ee8f3b695e 355 data = *(__IO uint32_t *)deviceaddress;
EricLew 0:80ee8f3b695e 356
EricLew 0:80ee8f3b695e 357 /* Return the data read */
EricLew 0:80ee8f3b695e 358 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
EricLew 0:80ee8f3b695e 359 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
EricLew 0:80ee8f3b695e 360 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
EricLew 0:80ee8f3b695e 361 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
EricLew 0:80ee8f3b695e 362
EricLew 0:80ee8f3b695e 363 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 364 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 365
EricLew 0:80ee8f3b695e 366 /* Process unlocked */
EricLew 0:80ee8f3b695e 367 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 368
EricLew 0:80ee8f3b695e 369 return HAL_OK;
EricLew 0:80ee8f3b695e 370 }
EricLew 0:80ee8f3b695e 371
EricLew 0:80ee8f3b695e 372 /**
EricLew 0:80ee8f3b695e 373 * @brief NAND memory reset.
EricLew 0:80ee8f3b695e 374 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 375 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 376 * @retval HAL status
EricLew 0:80ee8f3b695e 377 */
EricLew 0:80ee8f3b695e 378 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 379 {
EricLew 0:80ee8f3b695e 380 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 381
EricLew 0:80ee8f3b695e 382 /* Process Locked */
EricLew 0:80ee8f3b695e 383 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 384
EricLew 0:80ee8f3b695e 385 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 386 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 387 {
EricLew 0:80ee8f3b695e 388 return HAL_BUSY;
EricLew 0:80ee8f3b695e 389 }
EricLew 0:80ee8f3b695e 390
EricLew 0:80ee8f3b695e 391 /* Identify the device address */
EricLew 0:80ee8f3b695e 392 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 393
EricLew 0:80ee8f3b695e 394 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 395 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 396
EricLew 0:80ee8f3b695e 397 /* Send NAND reset command */
EricLew 0:80ee8f3b695e 398 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
EricLew 0:80ee8f3b695e 399
EricLew 0:80ee8f3b695e 400
EricLew 0:80ee8f3b695e 401 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 402 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 403
EricLew 0:80ee8f3b695e 404 /* Process unlocked */
EricLew 0:80ee8f3b695e 405 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 406
EricLew 0:80ee8f3b695e 407 return HAL_OK;
EricLew 0:80ee8f3b695e 408
EricLew 0:80ee8f3b695e 409 }
EricLew 0:80ee8f3b695e 410
EricLew 0:80ee8f3b695e 411 /**
EricLew 0:80ee8f3b695e 412 * @brief Read Page(s) from NAND memory block.
EricLew 0:80ee8f3b695e 413 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 414 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 415 * @param pAddress: pointer to NAND address structure
EricLew 0:80ee8f3b695e 416 * @param pBuffer: pointer to destination read buffer
EricLew 0:80ee8f3b695e 417 * @param NumPageToRead: number of pages to read from block
EricLew 0:80ee8f3b695e 418 * @retval HAL status
EricLew 0:80ee8f3b695e 419 */
EricLew 0:80ee8f3b695e 420 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
EricLew 0:80ee8f3b695e 421 {
EricLew 0:80ee8f3b695e 422 __IO uint32_t index = 0;
EricLew 0:80ee8f3b695e 423 uint32_t deviceaddress = 0, size = 0, numpagesread = 0, addressstatus = NAND_VALID_ADDRESS;
EricLew 0:80ee8f3b695e 424 NAND_AddressTypeDef nandaddress;
EricLew 0:80ee8f3b695e 425 uint32_t addressoffset = 0;
EricLew 0:80ee8f3b695e 426
EricLew 0:80ee8f3b695e 427 /* Process Locked */
EricLew 0:80ee8f3b695e 428 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 429
EricLew 0:80ee8f3b695e 430 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 431 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 432 {
EricLew 0:80ee8f3b695e 433 return HAL_BUSY;
EricLew 0:80ee8f3b695e 434 }
EricLew 0:80ee8f3b695e 435
EricLew 0:80ee8f3b695e 436 /* Identify the device address */
EricLew 0:80ee8f3b695e 437 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 438
EricLew 0:80ee8f3b695e 439 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 440 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 441
EricLew 0:80ee8f3b695e 442 /* Save the content of pAddress as it will be modified */
EricLew 0:80ee8f3b695e 443 nandaddress.Block = pAddress->Block;
EricLew 0:80ee8f3b695e 444 nandaddress.Page = pAddress->Page;
EricLew 0:80ee8f3b695e 445 nandaddress.Zone = pAddress->Zone;
EricLew 0:80ee8f3b695e 446
EricLew 0:80ee8f3b695e 447 /* Page(s) read loop */
EricLew 0:80ee8f3b695e 448 while((NumPageToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
EricLew 0:80ee8f3b695e 449 {
EricLew 0:80ee8f3b695e 450 /* update the buffer size */
EricLew 0:80ee8f3b695e 451 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpagesread);
EricLew 0:80ee8f3b695e 452
EricLew 0:80ee8f3b695e 453 /* Get the address offset */
EricLew 0:80ee8f3b695e 454 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
EricLew 0:80ee8f3b695e 455
EricLew 0:80ee8f3b695e 456 /* Send read page command sequence */
EricLew 0:80ee8f3b695e 457 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
EricLew 0:80ee8f3b695e 458
EricLew 0:80ee8f3b695e 459 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
EricLew 0:80ee8f3b695e 460 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 461 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 462 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 463
EricLew 0:80ee8f3b695e 464 /* for 512 and 1 GB devices, 4th cycle is required */
EricLew 0:80ee8f3b695e 465 if(hnand->Info.BlockNbr >= 1024)
EricLew 0:80ee8f3b695e 466 {
EricLew 0:80ee8f3b695e 467 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 468 }
EricLew 0:80ee8f3b695e 469
EricLew 0:80ee8f3b695e 470 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
EricLew 0:80ee8f3b695e 471
EricLew 0:80ee8f3b695e 472 /* Get Data into Buffer */
EricLew 0:80ee8f3b695e 473 for(; index < size; index++)
EricLew 0:80ee8f3b695e 474 {
EricLew 0:80ee8f3b695e 475 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
EricLew 0:80ee8f3b695e 476 }
EricLew 0:80ee8f3b695e 477
EricLew 0:80ee8f3b695e 478 /* Increment read pages number */
EricLew 0:80ee8f3b695e 479 numpagesread++;
EricLew 0:80ee8f3b695e 480
EricLew 0:80ee8f3b695e 481 /* Decrement pages to read */
EricLew 0:80ee8f3b695e 482 NumPageToRead--;
EricLew 0:80ee8f3b695e 483
EricLew 0:80ee8f3b695e 484 /* Increment the NAND address */
EricLew 0:80ee8f3b695e 485 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
EricLew 0:80ee8f3b695e 486 }
EricLew 0:80ee8f3b695e 487
EricLew 0:80ee8f3b695e 488 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 489 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 490
EricLew 0:80ee8f3b695e 491 /* Process unlocked */
EricLew 0:80ee8f3b695e 492 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 493
EricLew 0:80ee8f3b695e 494 return HAL_OK;
EricLew 0:80ee8f3b695e 495
EricLew 0:80ee8f3b695e 496 }
EricLew 0:80ee8f3b695e 497
EricLew 0:80ee8f3b695e 498 /**
EricLew 0:80ee8f3b695e 499 * @brief Write Page(s) to NAND memory block.
EricLew 0:80ee8f3b695e 500 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 501 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 502 * @param pAddress: pointer to NAND address structure
EricLew 0:80ee8f3b695e 503 * @param pBuffer: pointer to source buffer to write
EricLew 0:80ee8f3b695e 504 * @param NumPageToWrite: number of pages to write to block
EricLew 0:80ee8f3b695e 505 * @retval HAL status
EricLew 0:80ee8f3b695e 506 */
EricLew 0:80ee8f3b695e 507 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
EricLew 0:80ee8f3b695e 508 {
EricLew 0:80ee8f3b695e 509 __IO uint32_t index = 0;
EricLew 0:80ee8f3b695e 510 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 511 uint32_t deviceaddress = 0 , size = 0, numpageswritten = 0, addressstatus = NAND_VALID_ADDRESS;
EricLew 0:80ee8f3b695e 512 NAND_AddressTypeDef nandaddress;
EricLew 0:80ee8f3b695e 513 uint32_t addressoffset = 0;
EricLew 0:80ee8f3b695e 514
EricLew 0:80ee8f3b695e 515 /* Process Locked */
EricLew 0:80ee8f3b695e 516 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 517
EricLew 0:80ee8f3b695e 518 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 519 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 520 {
EricLew 0:80ee8f3b695e 521 return HAL_BUSY;
EricLew 0:80ee8f3b695e 522 }
EricLew 0:80ee8f3b695e 523
EricLew 0:80ee8f3b695e 524 /* Identify the device address */
EricLew 0:80ee8f3b695e 525 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 526
EricLew 0:80ee8f3b695e 527 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 528 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 529
EricLew 0:80ee8f3b695e 530 /* Save the content of pAddress as it will be modified */
EricLew 0:80ee8f3b695e 531 nandaddress.Block = pAddress->Block;
EricLew 0:80ee8f3b695e 532 nandaddress.Page = pAddress->Page;
EricLew 0:80ee8f3b695e 533 nandaddress.Zone = pAddress->Zone;
EricLew 0:80ee8f3b695e 534
EricLew 0:80ee8f3b695e 535 /* Page(s) write loop */
EricLew 0:80ee8f3b695e 536 while((NumPageToWrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
EricLew 0:80ee8f3b695e 537 {
EricLew 0:80ee8f3b695e 538 /* update the buffer size */
EricLew 0:80ee8f3b695e 539 size = hnand->Info.PageSize + ((hnand->Info.PageSize) * numpageswritten);
EricLew 0:80ee8f3b695e 540
EricLew 0:80ee8f3b695e 541 /* Get the address offset */
EricLew 0:80ee8f3b695e 542 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
EricLew 0:80ee8f3b695e 543
EricLew 0:80ee8f3b695e 544 /* Send write page command sequence */
EricLew 0:80ee8f3b695e 545 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
EricLew 0:80ee8f3b695e 546 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
EricLew 0:80ee8f3b695e 547
EricLew 0:80ee8f3b695e 548 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
EricLew 0:80ee8f3b695e 549 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 550 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 551 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 552
EricLew 0:80ee8f3b695e 553 /* for 512 and 1 GB devices, 4th cycle is required */
EricLew 0:80ee8f3b695e 554 if(hnand->Info.BlockNbr >= 1024)
EricLew 0:80ee8f3b695e 555 {
EricLew 0:80ee8f3b695e 556 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 557 }
EricLew 0:80ee8f3b695e 558
EricLew 0:80ee8f3b695e 559 /* Write data to memory */
EricLew 0:80ee8f3b695e 560 for(; index < size; index++)
EricLew 0:80ee8f3b695e 561 {
EricLew 0:80ee8f3b695e 562 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
EricLew 0:80ee8f3b695e 563 }
EricLew 0:80ee8f3b695e 564
EricLew 0:80ee8f3b695e 565 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
EricLew 0:80ee8f3b695e 566
EricLew 0:80ee8f3b695e 567 /* Get tick */
EricLew 0:80ee8f3b695e 568 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 569
EricLew 0:80ee8f3b695e 570 /* Read status until NAND is ready */
EricLew 0:80ee8f3b695e 571 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
EricLew 0:80ee8f3b695e 572 {
EricLew 0:80ee8f3b695e 573 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
EricLew 0:80ee8f3b695e 574 {
EricLew 0:80ee8f3b695e 575 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 576 }
EricLew 0:80ee8f3b695e 577 }
EricLew 0:80ee8f3b695e 578
EricLew 0:80ee8f3b695e 579 /* Increment written pages number */
EricLew 0:80ee8f3b695e 580 numpageswritten++;
EricLew 0:80ee8f3b695e 581
EricLew 0:80ee8f3b695e 582 /* Decrement pages to write */
EricLew 0:80ee8f3b695e 583 NumPageToWrite--;
EricLew 0:80ee8f3b695e 584
EricLew 0:80ee8f3b695e 585 /* Increment the NAND address */
EricLew 0:80ee8f3b695e 586 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
EricLew 0:80ee8f3b695e 587 }
EricLew 0:80ee8f3b695e 588
EricLew 0:80ee8f3b695e 589 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 590 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 591
EricLew 0:80ee8f3b695e 592 /* Process unlocked */
EricLew 0:80ee8f3b695e 593 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 594
EricLew 0:80ee8f3b695e 595 return HAL_OK;
EricLew 0:80ee8f3b695e 596 }
EricLew 0:80ee8f3b695e 597
EricLew 0:80ee8f3b695e 598 /**
EricLew 0:80ee8f3b695e 599 * @brief Read Spare area(s) from NAND memory.
EricLew 0:80ee8f3b695e 600 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 601 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 602 * @param pAddress: pointer to NAND address structure
EricLew 0:80ee8f3b695e 603 * @param pBuffer: pointer to source buffer to write
EricLew 0:80ee8f3b695e 604 * @param NumSpareAreaToRead: Number of spare area to read
EricLew 0:80ee8f3b695e 605 * @retval HAL status
EricLew 0:80ee8f3b695e 606 */
EricLew 0:80ee8f3b695e 607 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
EricLew 0:80ee8f3b695e 608 {
EricLew 0:80ee8f3b695e 609 __IO uint32_t index = 0;
EricLew 0:80ee8f3b695e 610 uint32_t deviceaddress = 0, size = 0, num_spare_area_read = 0, addressstatus = NAND_VALID_ADDRESS;
EricLew 0:80ee8f3b695e 611 NAND_AddressTypeDef nandaddress;
EricLew 0:80ee8f3b695e 612 uint32_t addressoffset = 0;
EricLew 0:80ee8f3b695e 613
EricLew 0:80ee8f3b695e 614 /* Process Locked */
EricLew 0:80ee8f3b695e 615 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 616
EricLew 0:80ee8f3b695e 617 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 618 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 619 {
EricLew 0:80ee8f3b695e 620 return HAL_BUSY;
EricLew 0:80ee8f3b695e 621 }
EricLew 0:80ee8f3b695e 622
EricLew 0:80ee8f3b695e 623 /* Identify the device address */
EricLew 0:80ee8f3b695e 624 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 625
EricLew 0:80ee8f3b695e 626 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 627 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 628
EricLew 0:80ee8f3b695e 629 /* Save the content of pAddress as it will be modified */
EricLew 0:80ee8f3b695e 630 nandaddress.Block = pAddress->Block;
EricLew 0:80ee8f3b695e 631 nandaddress.Page = pAddress->Page;
EricLew 0:80ee8f3b695e 632 nandaddress.Zone = pAddress->Zone;
EricLew 0:80ee8f3b695e 633
EricLew 0:80ee8f3b695e 634 /* Spare area(s) read loop */
EricLew 0:80ee8f3b695e 635 while((NumSpareAreaToRead != 0) && (addressstatus == NAND_VALID_ADDRESS))
EricLew 0:80ee8f3b695e 636 {
EricLew 0:80ee8f3b695e 637 /* update the buffer size */
EricLew 0:80ee8f3b695e 638 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_read);
EricLew 0:80ee8f3b695e 639
EricLew 0:80ee8f3b695e 640 /* Get the address offset */
EricLew 0:80ee8f3b695e 641 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
EricLew 0:80ee8f3b695e 642
EricLew 0:80ee8f3b695e 643 /* Send read spare area command sequence */
EricLew 0:80ee8f3b695e 644 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
EricLew 0:80ee8f3b695e 645
EricLew 0:80ee8f3b695e 646 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
EricLew 0:80ee8f3b695e 647 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 648 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 649 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 650
EricLew 0:80ee8f3b695e 651 /* for 512 and 1 GB devices, 4th cycle is required */
EricLew 0:80ee8f3b695e 652 if(hnand->Info.BlockNbr >= 1024)
EricLew 0:80ee8f3b695e 653 {
EricLew 0:80ee8f3b695e 654 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 655 }
EricLew 0:80ee8f3b695e 656
EricLew 0:80ee8f3b695e 657 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
EricLew 0:80ee8f3b695e 658
EricLew 0:80ee8f3b695e 659 /* Get Data into Buffer */
EricLew 0:80ee8f3b695e 660 for ( ;index < size; index++)
EricLew 0:80ee8f3b695e 661 {
EricLew 0:80ee8f3b695e 662 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
EricLew 0:80ee8f3b695e 663 }
EricLew 0:80ee8f3b695e 664
EricLew 0:80ee8f3b695e 665 /* Increment read spare areas number */
EricLew 0:80ee8f3b695e 666 num_spare_area_read++;
EricLew 0:80ee8f3b695e 667
EricLew 0:80ee8f3b695e 668 /* Decrement spare areas to read */
EricLew 0:80ee8f3b695e 669 NumSpareAreaToRead--;
EricLew 0:80ee8f3b695e 670
EricLew 0:80ee8f3b695e 671 /* Increment the NAND address */
EricLew 0:80ee8f3b695e 672 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
EricLew 0:80ee8f3b695e 673 }
EricLew 0:80ee8f3b695e 674
EricLew 0:80ee8f3b695e 675 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 676 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 677
EricLew 0:80ee8f3b695e 678 /* Process unlocked */
EricLew 0:80ee8f3b695e 679 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 680
EricLew 0:80ee8f3b695e 681 return HAL_OK;
EricLew 0:80ee8f3b695e 682 }
EricLew 0:80ee8f3b695e 683
EricLew 0:80ee8f3b695e 684 /**
EricLew 0:80ee8f3b695e 685 * @brief Write Spare area(s) to NAND memory.
EricLew 0:80ee8f3b695e 686 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 687 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 688 * @param pAddress: pointer to NAND address structure
EricLew 0:80ee8f3b695e 689 * @param pBuffer: pointer to source buffer to write
EricLew 0:80ee8f3b695e 690 * @param NumSpareAreaTowrite: number of spare areas to write to block
EricLew 0:80ee8f3b695e 691 * @retval HAL status
EricLew 0:80ee8f3b695e 692 */
EricLew 0:80ee8f3b695e 693 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
EricLew 0:80ee8f3b695e 694 {
EricLew 0:80ee8f3b695e 695 __IO uint32_t index = 0;
EricLew 0:80ee8f3b695e 696 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 697 uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS;
EricLew 0:80ee8f3b695e 698 NAND_AddressTypeDef nandaddress;
EricLew 0:80ee8f3b695e 699 uint32_t addressoffset = 0;
EricLew 0:80ee8f3b695e 700
EricLew 0:80ee8f3b695e 701 /* Process Locked */
EricLew 0:80ee8f3b695e 702 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 703
EricLew 0:80ee8f3b695e 704 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 705 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 706 {
EricLew 0:80ee8f3b695e 707 return HAL_BUSY;
EricLew 0:80ee8f3b695e 708 }
EricLew 0:80ee8f3b695e 709
EricLew 0:80ee8f3b695e 710 /* Identify the device address */
EricLew 0:80ee8f3b695e 711 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 712
EricLew 0:80ee8f3b695e 713 /* Update the FMC_NAND controller state */
EricLew 0:80ee8f3b695e 714 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 715
EricLew 0:80ee8f3b695e 716 /* Save the content of pAddress as it will be modified */
EricLew 0:80ee8f3b695e 717 nandaddress.Block = pAddress->Block;
EricLew 0:80ee8f3b695e 718 nandaddress.Page = pAddress->Page;
EricLew 0:80ee8f3b695e 719 nandaddress.Zone = pAddress->Zone;
EricLew 0:80ee8f3b695e 720
EricLew 0:80ee8f3b695e 721 /* Spare area(s) write loop */
EricLew 0:80ee8f3b695e 722 while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS))
EricLew 0:80ee8f3b695e 723 {
EricLew 0:80ee8f3b695e 724 /* update the buffer size */
EricLew 0:80ee8f3b695e 725 size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written);
EricLew 0:80ee8f3b695e 726
EricLew 0:80ee8f3b695e 727 /* Get the address offset */
EricLew 0:80ee8f3b695e 728 addressoffset = ARRAY_ADDRESS(&nandaddress, hnand);
EricLew 0:80ee8f3b695e 729
EricLew 0:80ee8f3b695e 730 /* Send write Spare area command sequence */
EricLew 0:80ee8f3b695e 731 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
EricLew 0:80ee8f3b695e 732 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
EricLew 0:80ee8f3b695e 733
EricLew 0:80ee8f3b695e 734 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
EricLew 0:80ee8f3b695e 735 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 736 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 737 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 738
EricLew 0:80ee8f3b695e 739 /* for 512 and 1 GB devices, 4th cycle is required */
EricLew 0:80ee8f3b695e 740 if(hnand->Info.BlockNbr >= 1024)
EricLew 0:80ee8f3b695e 741 {
EricLew 0:80ee8f3b695e 742 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset);
EricLew 0:80ee8f3b695e 743 }
EricLew 0:80ee8f3b695e 744
EricLew 0:80ee8f3b695e 745 /* Write data to memory */
EricLew 0:80ee8f3b695e 746 for(; index < size; index++)
EricLew 0:80ee8f3b695e 747 {
EricLew 0:80ee8f3b695e 748 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
EricLew 0:80ee8f3b695e 749 }
EricLew 0:80ee8f3b695e 750
EricLew 0:80ee8f3b695e 751 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
EricLew 0:80ee8f3b695e 752
EricLew 0:80ee8f3b695e 753 /* Get tick */
EricLew 0:80ee8f3b695e 754 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 755
EricLew 0:80ee8f3b695e 756 /* Read status until NAND is ready */
EricLew 0:80ee8f3b695e 757 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
EricLew 0:80ee8f3b695e 758 {
EricLew 0:80ee8f3b695e 759 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
EricLew 0:80ee8f3b695e 760 {
EricLew 0:80ee8f3b695e 761 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 762 }
EricLew 0:80ee8f3b695e 763 }
EricLew 0:80ee8f3b695e 764
EricLew 0:80ee8f3b695e 765 /* Increment written spare areas number */
EricLew 0:80ee8f3b695e 766 num_spare_area_written++;
EricLew 0:80ee8f3b695e 767
EricLew 0:80ee8f3b695e 768 /* Decrement spare areas to write */
EricLew 0:80ee8f3b695e 769 NumSpareAreaTowrite--;
EricLew 0:80ee8f3b695e 770
EricLew 0:80ee8f3b695e 771 /* Increment the NAND address */
EricLew 0:80ee8f3b695e 772 addressstatus = NAND_AddressIncrement(hnand, &nandaddress);
EricLew 0:80ee8f3b695e 773 }
EricLew 0:80ee8f3b695e 774
EricLew 0:80ee8f3b695e 775 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 776 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 777
EricLew 0:80ee8f3b695e 778 /* Process unlocked */
EricLew 0:80ee8f3b695e 779 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 780
EricLew 0:80ee8f3b695e 781 return HAL_OK;
EricLew 0:80ee8f3b695e 782 }
EricLew 0:80ee8f3b695e 783
EricLew 0:80ee8f3b695e 784 /**
EricLew 0:80ee8f3b695e 785 * @brief NAND memory Block erase.
EricLew 0:80ee8f3b695e 786 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 787 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 788 * @param pAddress: pointer to NAND address structure
EricLew 0:80ee8f3b695e 789 * @retval HAL status
EricLew 0:80ee8f3b695e 790 */
EricLew 0:80ee8f3b695e 791 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
EricLew 0:80ee8f3b695e 792 {
EricLew 0:80ee8f3b695e 793 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 794 uint32_t tickstart = 0;
EricLew 0:80ee8f3b695e 795
EricLew 0:80ee8f3b695e 796 /* Process Locked */
EricLew 0:80ee8f3b695e 797 __HAL_LOCK(hnand);
EricLew 0:80ee8f3b695e 798
EricLew 0:80ee8f3b695e 799 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 800 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 801 {
EricLew 0:80ee8f3b695e 802 return HAL_BUSY;
EricLew 0:80ee8f3b695e 803 }
EricLew 0:80ee8f3b695e 804
EricLew 0:80ee8f3b695e 805 /* Identify the device address */
EricLew 0:80ee8f3b695e 806 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 807
EricLew 0:80ee8f3b695e 808 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 809 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 810
EricLew 0:80ee8f3b695e 811 /* Send Erase block command sequence */
EricLew 0:80ee8f3b695e 812 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
EricLew 0:80ee8f3b695e 813
EricLew 0:80ee8f3b695e 814 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
EricLew 0:80ee8f3b695e 815 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
EricLew 0:80ee8f3b695e 816 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
EricLew 0:80ee8f3b695e 817
EricLew 0:80ee8f3b695e 818 /* for 512 and 1 GB devices, 4th cycle is required */
EricLew 0:80ee8f3b695e 819 if(hnand->Info.BlockNbr >= 1024)
EricLew 0:80ee8f3b695e 820 {
EricLew 0:80ee8f3b695e 821 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
EricLew 0:80ee8f3b695e 822 }
EricLew 0:80ee8f3b695e 823
EricLew 0:80ee8f3b695e 824 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
EricLew 0:80ee8f3b695e 825
EricLew 0:80ee8f3b695e 826 /* Update the NAND controller state */
EricLew 0:80ee8f3b695e 827 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 828
EricLew 0:80ee8f3b695e 829 /* Get tick */
EricLew 0:80ee8f3b695e 830 tickstart = HAL_GetTick();
EricLew 0:80ee8f3b695e 831
EricLew 0:80ee8f3b695e 832 /* Read status until NAND is ready */
EricLew 0:80ee8f3b695e 833 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
EricLew 0:80ee8f3b695e 834 {
EricLew 0:80ee8f3b695e 835 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
EricLew 0:80ee8f3b695e 836 {
EricLew 0:80ee8f3b695e 837 /* Process unlocked */
EricLew 0:80ee8f3b695e 838 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 839
EricLew 0:80ee8f3b695e 840 return HAL_TIMEOUT;
EricLew 0:80ee8f3b695e 841 }
EricLew 0:80ee8f3b695e 842 }
EricLew 0:80ee8f3b695e 843
EricLew 0:80ee8f3b695e 844 /* Process unlocked */
EricLew 0:80ee8f3b695e 845 __HAL_UNLOCK(hnand);
EricLew 0:80ee8f3b695e 846
EricLew 0:80ee8f3b695e 847 return HAL_OK;
EricLew 0:80ee8f3b695e 848 }
EricLew 0:80ee8f3b695e 849
EricLew 0:80ee8f3b695e 850 /**
EricLew 0:80ee8f3b695e 851 * @brief NAND memory read status.
EricLew 0:80ee8f3b695e 852 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 853 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 854 * @retval NAND status
EricLew 0:80ee8f3b695e 855 */
EricLew 0:80ee8f3b695e 856 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 857 {
EricLew 0:80ee8f3b695e 858 uint32_t data = 0;
EricLew 0:80ee8f3b695e 859 uint32_t deviceaddress = 0;
EricLew 0:80ee8f3b695e 860
EricLew 0:80ee8f3b695e 861 /* Identify the device address */
EricLew 0:80ee8f3b695e 862 deviceaddress = NAND_DEVICE;
EricLew 0:80ee8f3b695e 863
EricLew 0:80ee8f3b695e 864 /* Send Read status operation command */
EricLew 0:80ee8f3b695e 865 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
EricLew 0:80ee8f3b695e 866
EricLew 0:80ee8f3b695e 867 /* Read status register data */
EricLew 0:80ee8f3b695e 868 data = *(__IO uint8_t *)deviceaddress;
EricLew 0:80ee8f3b695e 869
EricLew 0:80ee8f3b695e 870 /* Return the status */
EricLew 0:80ee8f3b695e 871 if((data & NAND_ERROR) == NAND_ERROR)
EricLew 0:80ee8f3b695e 872 {
EricLew 0:80ee8f3b695e 873 return NAND_ERROR;
EricLew 0:80ee8f3b695e 874 }
EricLew 0:80ee8f3b695e 875 else if((data & NAND_READY) == NAND_READY)
EricLew 0:80ee8f3b695e 876 {
EricLew 0:80ee8f3b695e 877 return NAND_READY;
EricLew 0:80ee8f3b695e 878 }
EricLew 0:80ee8f3b695e 879
EricLew 0:80ee8f3b695e 880 return NAND_BUSY;
EricLew 0:80ee8f3b695e 881 }
EricLew 0:80ee8f3b695e 882
EricLew 0:80ee8f3b695e 883 /**
EricLew 0:80ee8f3b695e 884 * @brief Increment the NAND memory address.
EricLew 0:80ee8f3b695e 885 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 886 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 887 * @param pAddress: pointer to NAND address structure
EricLew 0:80ee8f3b695e 888 * @retval The new status of the increment address operation. It can be:
EricLew 0:80ee8f3b695e 889 * - NAND_VALID_ADDRESS: When the new address is valid address
EricLew 0:80ee8f3b695e 890 * - NAND_INVALID_ADDRESS: When the new address is invalid address
EricLew 0:80ee8f3b695e 891 */
EricLew 0:80ee8f3b695e 892 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
EricLew 0:80ee8f3b695e 893 {
EricLew 0:80ee8f3b695e 894 uint32_t status = NAND_VALID_ADDRESS;
EricLew 0:80ee8f3b695e 895
EricLew 0:80ee8f3b695e 896 /* Increment page address */
EricLew 0:80ee8f3b695e 897 pAddress->Page++;
EricLew 0:80ee8f3b695e 898
EricLew 0:80ee8f3b695e 899 /* Check NAND address is valid */
EricLew 0:80ee8f3b695e 900 if(pAddress->Page == hnand->Info.BlockSize)
EricLew 0:80ee8f3b695e 901 {
EricLew 0:80ee8f3b695e 902 pAddress->Page = 0;
EricLew 0:80ee8f3b695e 903 pAddress->Block++;
EricLew 0:80ee8f3b695e 904
EricLew 0:80ee8f3b695e 905 if(pAddress->Block == hnand->Info.ZoneSize)
EricLew 0:80ee8f3b695e 906 {
EricLew 0:80ee8f3b695e 907 pAddress->Block = 0;
EricLew 0:80ee8f3b695e 908 pAddress->Zone++;
EricLew 0:80ee8f3b695e 909
EricLew 0:80ee8f3b695e 910 if(pAddress->Zone == (hnand->Info.ZoneSize/ hnand->Info.BlockNbr))
EricLew 0:80ee8f3b695e 911 {
EricLew 0:80ee8f3b695e 912 status = NAND_INVALID_ADDRESS;
EricLew 0:80ee8f3b695e 913 }
EricLew 0:80ee8f3b695e 914 }
EricLew 0:80ee8f3b695e 915 }
EricLew 0:80ee8f3b695e 916
EricLew 0:80ee8f3b695e 917 return (status);
EricLew 0:80ee8f3b695e 918 }
EricLew 0:80ee8f3b695e 919 /**
EricLew 0:80ee8f3b695e 920 * @}
EricLew 0:80ee8f3b695e 921 */
EricLew 0:80ee8f3b695e 922
EricLew 0:80ee8f3b695e 923 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
EricLew 0:80ee8f3b695e 924 * @brief management functions
EricLew 0:80ee8f3b695e 925 *
EricLew 0:80ee8f3b695e 926 @verbatim
EricLew 0:80ee8f3b695e 927 ==============================================================================
EricLew 0:80ee8f3b695e 928 ##### NAND Control functions #####
EricLew 0:80ee8f3b695e 929 ==============================================================================
EricLew 0:80ee8f3b695e 930 [..]
EricLew 0:80ee8f3b695e 931 This subsection provides a set of functions allowing to control dynamically
EricLew 0:80ee8f3b695e 932 the NAND interface.
EricLew 0:80ee8f3b695e 933
EricLew 0:80ee8f3b695e 934 @endverbatim
EricLew 0:80ee8f3b695e 935 * @{
EricLew 0:80ee8f3b695e 936 */
EricLew 0:80ee8f3b695e 937
EricLew 0:80ee8f3b695e 938
EricLew 0:80ee8f3b695e 939 /**
EricLew 0:80ee8f3b695e 940 * @brief Enable dynamically NAND ECC feature.
EricLew 0:80ee8f3b695e 941 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 942 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 943 * @retval HAL status
EricLew 0:80ee8f3b695e 944 */
EricLew 0:80ee8f3b695e 945 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 946 {
EricLew 0:80ee8f3b695e 947 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 948 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 949 {
EricLew 0:80ee8f3b695e 950 return HAL_BUSY;
EricLew 0:80ee8f3b695e 951 }
EricLew 0:80ee8f3b695e 952
EricLew 0:80ee8f3b695e 953 /* Update the NAND state */
EricLew 0:80ee8f3b695e 954 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 955
EricLew 0:80ee8f3b695e 956 /* Enable ECC feature */
EricLew 0:80ee8f3b695e 957 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
EricLew 0:80ee8f3b695e 958
EricLew 0:80ee8f3b695e 959 /* Update the NAND state */
EricLew 0:80ee8f3b695e 960 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 961
EricLew 0:80ee8f3b695e 962 return HAL_OK;
EricLew 0:80ee8f3b695e 963 }
EricLew 0:80ee8f3b695e 964
EricLew 0:80ee8f3b695e 965 /**
EricLew 0:80ee8f3b695e 966 * @brief Disable dynamically NAND ECC feature.
EricLew 0:80ee8f3b695e 967 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 968 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 969 * @retval HAL status
EricLew 0:80ee8f3b695e 970 */
EricLew 0:80ee8f3b695e 971 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 972 {
EricLew 0:80ee8f3b695e 973 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 974 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 975 {
EricLew 0:80ee8f3b695e 976 return HAL_BUSY;
EricLew 0:80ee8f3b695e 977 }
EricLew 0:80ee8f3b695e 978
EricLew 0:80ee8f3b695e 979 /* Update the NAND state */
EricLew 0:80ee8f3b695e 980 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 981
EricLew 0:80ee8f3b695e 982 /* Disable ECC feature */
EricLew 0:80ee8f3b695e 983 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
EricLew 0:80ee8f3b695e 984
EricLew 0:80ee8f3b695e 985 /* Update the NAND state */
EricLew 0:80ee8f3b695e 986 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 987
EricLew 0:80ee8f3b695e 988 return HAL_OK;
EricLew 0:80ee8f3b695e 989 }
EricLew 0:80ee8f3b695e 990
EricLew 0:80ee8f3b695e 991 /**
EricLew 0:80ee8f3b695e 992 * @brief Disable dynamically NAND ECC feature.
EricLew 0:80ee8f3b695e 993 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 994 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 995 * @param ECCval: pointer to ECC value
EricLew 0:80ee8f3b695e 996 * @param Timeout: maximum timeout to wait
EricLew 0:80ee8f3b695e 997 * @retval HAL status
EricLew 0:80ee8f3b695e 998 */
EricLew 0:80ee8f3b695e 999 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
EricLew 0:80ee8f3b695e 1000 {
EricLew 0:80ee8f3b695e 1001 HAL_StatusTypeDef status = HAL_OK;
EricLew 0:80ee8f3b695e 1002
EricLew 0:80ee8f3b695e 1003 /* Check the NAND controller state */
EricLew 0:80ee8f3b695e 1004 if(hnand->State == HAL_NAND_STATE_BUSY)
EricLew 0:80ee8f3b695e 1005 {
EricLew 0:80ee8f3b695e 1006 return HAL_BUSY;
EricLew 0:80ee8f3b695e 1007 }
EricLew 0:80ee8f3b695e 1008
EricLew 0:80ee8f3b695e 1009 /* Update the NAND state */
EricLew 0:80ee8f3b695e 1010 hnand->State = HAL_NAND_STATE_BUSY;
EricLew 0:80ee8f3b695e 1011
EricLew 0:80ee8f3b695e 1012 /* Get NAND ECC value */
EricLew 0:80ee8f3b695e 1013 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
EricLew 0:80ee8f3b695e 1014
EricLew 0:80ee8f3b695e 1015 /* Update the NAND state */
EricLew 0:80ee8f3b695e 1016 hnand->State = HAL_NAND_STATE_READY;
EricLew 0:80ee8f3b695e 1017
EricLew 0:80ee8f3b695e 1018 return status;
EricLew 0:80ee8f3b695e 1019 }
EricLew 0:80ee8f3b695e 1020
EricLew 0:80ee8f3b695e 1021 /**
EricLew 0:80ee8f3b695e 1022 * @}
EricLew 0:80ee8f3b695e 1023 */
EricLew 0:80ee8f3b695e 1024
EricLew 0:80ee8f3b695e 1025
EricLew 0:80ee8f3b695e 1026 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
EricLew 0:80ee8f3b695e 1027 * @brief Peripheral State functions
EricLew 0:80ee8f3b695e 1028 *
EricLew 0:80ee8f3b695e 1029 @verbatim
EricLew 0:80ee8f3b695e 1030 ==============================================================================
EricLew 0:80ee8f3b695e 1031 ##### NAND State functions #####
EricLew 0:80ee8f3b695e 1032 ==============================================================================
EricLew 0:80ee8f3b695e 1033 [..]
EricLew 0:80ee8f3b695e 1034 This subsection permits to get in run-time the status of the NAND controller
EricLew 0:80ee8f3b695e 1035 and the data flow.
EricLew 0:80ee8f3b695e 1036
EricLew 0:80ee8f3b695e 1037 @endverbatim
EricLew 0:80ee8f3b695e 1038 * @{
EricLew 0:80ee8f3b695e 1039 */
EricLew 0:80ee8f3b695e 1040
EricLew 0:80ee8f3b695e 1041 /**
EricLew 0:80ee8f3b695e 1042 * @brief Return the NAND handle state.
EricLew 0:80ee8f3b695e 1043 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 1044 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 1045 * @retval HAL state
EricLew 0:80ee8f3b695e 1046 */
EricLew 0:80ee8f3b695e 1047 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
EricLew 0:80ee8f3b695e 1048 {
EricLew 0:80ee8f3b695e 1049 /* Return NAND handle state */
EricLew 0:80ee8f3b695e 1050 return hnand->State;
EricLew 0:80ee8f3b695e 1051 }
EricLew 0:80ee8f3b695e 1052
EricLew 0:80ee8f3b695e 1053 /**
EricLew 0:80ee8f3b695e 1054 * @}
EricLew 0:80ee8f3b695e 1055 */
EricLew 0:80ee8f3b695e 1056
EricLew 0:80ee8f3b695e 1057 /**
EricLew 0:80ee8f3b695e 1058 * @}
EricLew 0:80ee8f3b695e 1059 */
EricLew 0:80ee8f3b695e 1060
EricLew 0:80ee8f3b695e 1061 /** @addtogroup NAND_Private_Functions
EricLew 0:80ee8f3b695e 1062 * @{
EricLew 0:80ee8f3b695e 1063 */
EricLew 0:80ee8f3b695e 1064
EricLew 0:80ee8f3b695e 1065 /**
EricLew 0:80ee8f3b695e 1066 * @brief Increment the NAND memory address.
EricLew 0:80ee8f3b695e 1067 * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
EricLew 0:80ee8f3b695e 1068 * the configuration information for NAND module.
EricLew 0:80ee8f3b695e 1069 * @param Address: address to be incremented.
EricLew 0:80ee8f3b695e 1070 * @retval The new status of the increment address operation. It can be:
EricLew 0:80ee8f3b695e 1071 * - NAND_VALID_ADDRESS: When the new address is valid address
EricLew 0:80ee8f3b695e 1072 * - NAND_INVALID_ADDRESS: When the new address is invalid address
EricLew 0:80ee8f3b695e 1073 */
EricLew 0:80ee8f3b695e 1074 static uint32_t NAND_AddressIncrement(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef* Address)
EricLew 0:80ee8f3b695e 1075 {
EricLew 0:80ee8f3b695e 1076 uint32_t status = NAND_VALID_ADDRESS;
EricLew 0:80ee8f3b695e 1077
EricLew 0:80ee8f3b695e 1078 Address->Page++;
EricLew 0:80ee8f3b695e 1079
EricLew 0:80ee8f3b695e 1080 if(Address->Page == hnand->Info.BlockSize)
EricLew 0:80ee8f3b695e 1081 {
EricLew 0:80ee8f3b695e 1082 Address->Page = 0;
EricLew 0:80ee8f3b695e 1083 Address->Block++;
EricLew 0:80ee8f3b695e 1084
EricLew 0:80ee8f3b695e 1085 if(Address->Block == hnand->Info.ZoneSize)
EricLew 0:80ee8f3b695e 1086 {
EricLew 0:80ee8f3b695e 1087 Address->Block = 0;
EricLew 0:80ee8f3b695e 1088 Address->Zone++;
EricLew 0:80ee8f3b695e 1089
EricLew 0:80ee8f3b695e 1090 if(Address->Zone == hnand->Info.BlockNbr)
EricLew 0:80ee8f3b695e 1091 {
EricLew 0:80ee8f3b695e 1092 status = NAND_INVALID_ADDRESS;
EricLew 0:80ee8f3b695e 1093 }
EricLew 0:80ee8f3b695e 1094 }
EricLew 0:80ee8f3b695e 1095 }
EricLew 0:80ee8f3b695e 1096
EricLew 0:80ee8f3b695e 1097 return (status);
EricLew 0:80ee8f3b695e 1098 }
EricLew 0:80ee8f3b695e 1099
EricLew 0:80ee8f3b695e 1100 /**
EricLew 0:80ee8f3b695e 1101 * @}
EricLew 0:80ee8f3b695e 1102 */
EricLew 0:80ee8f3b695e 1103
EricLew 0:80ee8f3b695e 1104 /**
EricLew 0:80ee8f3b695e 1105 * @}
EricLew 0:80ee8f3b695e 1106 */
EricLew 0:80ee8f3b695e 1107
EricLew 0:80ee8f3b695e 1108 #endif /* HAL_NAND_MODULE_ENABLED */
EricLew 0:80ee8f3b695e 1109
EricLew 0:80ee8f3b695e 1110 /**
EricLew 0:80ee8f3b695e 1111 * @}
EricLew 0:80ee8f3b695e 1112 */
EricLew 0:80ee8f3b695e 1113
EricLew 0:80ee8f3b695e 1114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 1115