Senior Design: Sound Monitor / STM32L4xx_HAL_Driver

L4 HAL Drivers

Inc/stm32l4xx_ll_spi.h@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:
EricLew
Date:
Mon Nov 02 19:37:23 2015 +0000
Revision:
0:80ee8f3b695e
Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_ll_spi.h
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief Header file of SPI LL module.
EricLew 0:80ee8f3b695e 8 ******************************************************************************
EricLew 0:80ee8f3b695e 9 * @attention
EricLew 0:80ee8f3b695e 10 *
EricLew 0:80ee8f3b695e 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 12 *
EricLew 0:80ee8f3b695e 13 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 14 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 15 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 16 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 18 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 19 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 21 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 22 * without specific prior written permission.
EricLew 0:80ee8f3b695e 23 *
EricLew 0:80ee8f3b695e 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 34 *
EricLew 0:80ee8f3b695e 35 ******************************************************************************
EricLew 0:80ee8f3b695e 36 */
EricLew 0:80ee8f3b695e 37
EricLew 0:80ee8f3b695e 38 /* Define to prevent recursive inclusion -------------------------------------*/
EricLew 0:80ee8f3b695e 39 #ifndef __STM32L4xx_LL_SPI_H
EricLew 0:80ee8f3b695e 40 #define __STM32L4xx_LL_SPI_H
EricLew 0:80ee8f3b695e 41
EricLew 0:80ee8f3b695e 42 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 43 extern "C" {
EricLew 0:80ee8f3b695e 44 #endif
EricLew 0:80ee8f3b695e 45
EricLew 0:80ee8f3b695e 46 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 47 #include "stm32l4xx.h"
EricLew 0:80ee8f3b695e 48
EricLew 0:80ee8f3b695e 49 /** @addtogroup STM32L4xx_LL_Driver
EricLew 0:80ee8f3b695e 50 * @{
EricLew 0:80ee8f3b695e 51 */
EricLew 0:80ee8f3b695e 52
EricLew 0:80ee8f3b695e 53 #if defined (SPI1) || defined (SPI2) || defined (SPI3)
EricLew 0:80ee8f3b695e 54
EricLew 0:80ee8f3b695e 55 /** @defgroup SPI_LL SPI
EricLew 0:80ee8f3b695e 56 * @{
EricLew 0:80ee8f3b695e 57 */
EricLew 0:80ee8f3b695e 58
EricLew 0:80ee8f3b695e 59 /* Private types -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 60 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 61
EricLew 0:80ee8f3b695e 62 /* Private constants ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 63
EricLew 0:80ee8f3b695e 64 /* Private macros ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 65
EricLew 0:80ee8f3b695e 66 /* Exported types ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 67 /* Exported constants --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 68 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
EricLew 0:80ee8f3b695e 69 * @{
EricLew 0:80ee8f3b695e 70 */
EricLew 0:80ee8f3b695e 71
EricLew 0:80ee8f3b695e 72 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
EricLew 0:80ee8f3b695e 73 * @brief Flags defines which can be used with LL_SPI_ReadReg function
EricLew 0:80ee8f3b695e 74 * @{
EricLew 0:80ee8f3b695e 75 */
EricLew 0:80ee8f3b695e 76 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
EricLew 0:80ee8f3b695e 77 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
EricLew 0:80ee8f3b695e 78 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
EricLew 0:80ee8f3b695e 79 #define LL_SPI_SR_UDR SPI_SR_UDR /*!< Underrun flag */
EricLew 0:80ee8f3b695e 80 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
EricLew 0:80ee8f3b695e 81 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
EricLew 0:80ee8f3b695e 82 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
EricLew 0:80ee8f3b695e 83 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
EricLew 0:80ee8f3b695e 84 /**
EricLew 0:80ee8f3b695e 85 * @}
EricLew 0:80ee8f3b695e 86 */
EricLew 0:80ee8f3b695e 87
EricLew 0:80ee8f3b695e 88 /** @defgroup SPI_LL_EC_IT IT Defines
EricLew 0:80ee8f3b695e 89 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
EricLew 0:80ee8f3b695e 90 * @{
EricLew 0:80ee8f3b695e 91 */
EricLew 0:80ee8f3b695e 92 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
EricLew 0:80ee8f3b695e 93 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
EricLew 0:80ee8f3b695e 94 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
EricLew 0:80ee8f3b695e 95 /**
EricLew 0:80ee8f3b695e 96 * @}
EricLew 0:80ee8f3b695e 97 */
EricLew 0:80ee8f3b695e 98
EricLew 0:80ee8f3b695e 99 /** @defgroup SPI_LL_EC_MODE MODE
EricLew 0:80ee8f3b695e 100 * @{
EricLew 0:80ee8f3b695e 101 */
EricLew 0:80ee8f3b695e 102 #define LL_SPI_MODE_MASTER ((uint32_t)0x00000104) /*!< Master configuration */
EricLew 0:80ee8f3b695e 103 #define LL_SPI_MODE_SLAVE ((uint32_t)0x00000000) /*!< Slave configuration */
EricLew 0:80ee8f3b695e 104 /**
EricLew 0:80ee8f3b695e 105 * @}
EricLew 0:80ee8f3b695e 106 */
EricLew 0:80ee8f3b695e 107
EricLew 0:80ee8f3b695e 108 /** @defgroup SPI_LL_EC_PROTOCOL PROTOCOL
EricLew 0:80ee8f3b695e 109 * @{
EricLew 0:80ee8f3b695e 110 */
EricLew 0:80ee8f3b695e 111 #define LL_SPI_PROTOCOL_MOTOROLA ((uint32_t)0x00000000) /*!< Motorola mode. Used as default value */
EricLew 0:80ee8f3b695e 112 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
EricLew 0:80ee8f3b695e 113 /**
EricLew 0:80ee8f3b695e 114 * @}
EricLew 0:80ee8f3b695e 115 */
EricLew 0:80ee8f3b695e 116
EricLew 0:80ee8f3b695e 117 /** @defgroup SPI_LL_EC_PHASE PHASE
EricLew 0:80ee8f3b695e 118 * @{
EricLew 0:80ee8f3b695e 119 */
EricLew 0:80ee8f3b695e 120 #define LL_SPI_PHASE_1EDGE ((uint32_t)0x00000000) /*!< First clock transition is the first data capture edge */
EricLew 0:80ee8f3b695e 121 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
EricLew 0:80ee8f3b695e 122 /**
EricLew 0:80ee8f3b695e 123 * @}
EricLew 0:80ee8f3b695e 124 */
EricLew 0:80ee8f3b695e 125
EricLew 0:80ee8f3b695e 126 /** @defgroup SPI_LL_EC_POLARITY POLARITY
EricLew 0:80ee8f3b695e 127 * @{
EricLew 0:80ee8f3b695e 128 */
EricLew 0:80ee8f3b695e 129 #define LL_SPI_POLARITY_LOW ((uint32_t)0x00000000) /*!< Clock to 0 when idle */
EricLew 0:80ee8f3b695e 130 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
EricLew 0:80ee8f3b695e 131 /**
EricLew 0:80ee8f3b695e 132 * @}
EricLew 0:80ee8f3b695e 133 */
EricLew 0:80ee8f3b695e 134
EricLew 0:80ee8f3b695e 135 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER BAUDRATEPRESCALER
EricLew 0:80ee8f3b695e 136 * @{
EricLew 0:80ee8f3b695e 137 */
EricLew 0:80ee8f3b695e 138 #define LL_SPI_BAUDRATEPRESCALER_DIV2 ((uint32_t)0x00000000) /*!< Baudrate control equal to fPCLK/2 */
EricLew 0:80ee8f3b695e 139 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/4 */
EricLew 0:80ee8f3b695e 140 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< Baudrate control equal to fPCLK/8 */
EricLew 0:80ee8f3b695e 141 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/16 */
EricLew 0:80ee8f3b695e 142 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< Baudrate control equal to fPCLK/32 */
EricLew 0:80ee8f3b695e 143 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/64 */
EricLew 0:80ee8f3b695e 144 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< Baudrate control equal to fPCLK/128 */
EricLew 0:80ee8f3b695e 145 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< Baudrate control equal to fPCLK/256 */
EricLew 0:80ee8f3b695e 146 /**
EricLew 0:80ee8f3b695e 147 * @}
EricLew 0:80ee8f3b695e 148 */
EricLew 0:80ee8f3b695e 149
EricLew 0:80ee8f3b695e 150 /** @defgroup SPI_LL_EC_BIT_ORDER TRANSMISSION BIT ORDER
EricLew 0:80ee8f3b695e 151 * @{
EricLew 0:80ee8f3b695e 152 */
EricLew 0:80ee8f3b695e 153 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received withthe LSB first */
EricLew 0:80ee8f3b695e 154 #define LL_SPI_MSB_FIRST ((uint32_t)0x00000000) /*!< Data is transmitted/received withthe MSB first */
EricLew 0:80ee8f3b695e 155 /**
EricLew 0:80ee8f3b695e 156 * @}
EricLew 0:80ee8f3b695e 157 */
EricLew 0:80ee8f3b695e 158
EricLew 0:80ee8f3b695e 159 /** @defgroup SPI_LL_EC_TRANSFER_MODE TRANSFER MODE
EricLew 0:80ee8f3b695e 160 * @{
EricLew 0:80ee8f3b695e 161 */
EricLew 0:80ee8f3b695e 162 #define LL_SPI_FULL_DUPLEX ((uint32_t)0x00000000) /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
EricLew 0:80ee8f3b695e 163 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
EricLew 0:80ee8f3b695e 164 #define LL_SPI_HALF_DUPLEX (SPI_CR1_BIDIMODE) /*!< Half-Duplex mode. Rx or Tx transfer on 1 line */
EricLew 0:80ee8f3b695e 165 /**
EricLew 0:80ee8f3b695e 166 * @}
EricLew 0:80ee8f3b695e 167 */
EricLew 0:80ee8f3b695e 168
EricLew 0:80ee8f3b695e 169 /** @defgroup SPI_LL_EC_DIRECTION_HALF_DUPLEX DIRECTION HALF DUPLEX
EricLew 0:80ee8f3b695e 170 * @{
EricLew 0:80ee8f3b695e 171 */
EricLew 0:80ee8f3b695e 172 #define LL_SPI_DIRECTION_HALF_DUPLEX_TX (SPI_CR1_BIDIOE) /*!< Tx transfer selection for Half-Duplex mode */
EricLew 0:80ee8f3b695e 173 #define LL_SPI_DIRECTION_HALF_DUPLEX_RX (0x00000000) /*!< Rx transfer selection for Half-Duplex mode */
EricLew 0:80ee8f3b695e 174 /**
EricLew 0:80ee8f3b695e 175 * @}
EricLew 0:80ee8f3b695e 176 */
EricLew 0:80ee8f3b695e 177
EricLew 0:80ee8f3b695e 178 /** @defgroup SPI_LL_EC_DATAWIDTH DATAWIDTH
EricLew 0:80ee8f3b695e 179 * @{
EricLew 0:80ee8f3b695e 180 */
EricLew 0:80ee8f3b695e 181 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
EricLew 0:80ee8f3b695e 182 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
EricLew 0:80ee8f3b695e 183 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
EricLew 0:80ee8f3b695e 184 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
EricLew 0:80ee8f3b695e 185 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
EricLew 0:80ee8f3b695e 186 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
EricLew 0:80ee8f3b695e 187 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
EricLew 0:80ee8f3b695e 188 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
EricLew 0:80ee8f3b695e 189 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
EricLew 0:80ee8f3b695e 190 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
EricLew 0:80ee8f3b695e 191 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
EricLew 0:80ee8f3b695e 192 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
EricLew 0:80ee8f3b695e 193 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
EricLew 0:80ee8f3b695e 194 /**
EricLew 0:80ee8f3b695e 195 * @}
EricLew 0:80ee8f3b695e 196 */
EricLew 0:80ee8f3b695e 197
EricLew 0:80ee8f3b695e 198 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO THRESHOLD
EricLew 0:80ee8f3b695e 199 * @{
EricLew 0:80ee8f3b695e 200 */
EricLew 0:80ee8f3b695e 201 #define LL_SPI_RX_FIFO_TH_HALF ((uint32_t)0x00000000) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
EricLew 0:80ee8f3b695e 202 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
EricLew 0:80ee8f3b695e 203 /**
EricLew 0:80ee8f3b695e 204 * @}
EricLew 0:80ee8f3b695e 205 */
EricLew 0:80ee8f3b695e 206
EricLew 0:80ee8f3b695e 207 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC LENGTH
EricLew 0:80ee8f3b695e 208 * @{
EricLew 0:80ee8f3b695e 209 */
EricLew 0:80ee8f3b695e 210 #define LL_SPI_CRC_8BIT ((uint32_t)0x00000000) /*!< 8-bit CRC length */
EricLew 0:80ee8f3b695e 211 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
EricLew 0:80ee8f3b695e 212 /**
EricLew 0:80ee8f3b695e 213 * @}
EricLew 0:80ee8f3b695e 214 */
EricLew 0:80ee8f3b695e 215
EricLew 0:80ee8f3b695e 216 /** @defgroup SPI_LL_EC_NSS_MODE NSS MODE
EricLew 0:80ee8f3b695e 217 * @{
EricLew 0:80ee8f3b695e 218 */
EricLew 0:80ee8f3b695e 219 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
EricLew 0:80ee8f3b695e 220 #define LL_SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) /*!< NSS pin used in Input. Only used in Master mode */
EricLew 0:80ee8f3b695e 221 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
EricLew 0:80ee8f3b695e 222 /**
EricLew 0:80ee8f3b695e 223 * @}
EricLew 0:80ee8f3b695e 224 */
EricLew 0:80ee8f3b695e 225
EricLew 0:80ee8f3b695e 226 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO LEVEL
EricLew 0:80ee8f3b695e 227 * @{
EricLew 0:80ee8f3b695e 228 */
EricLew 0:80ee8f3b695e 229 #define LL_SPI_RX_FIFO_EMPTY ((uint32_t)0x00000000) /*!< FIFO reception empty */
EricLew 0:80ee8f3b695e 230 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
EricLew 0:80ee8f3b695e 231 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
EricLew 0:80ee8f3b695e 232 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
EricLew 0:80ee8f3b695e 233 /**
EricLew 0:80ee8f3b695e 234 * @}
EricLew 0:80ee8f3b695e 235 */
EricLew 0:80ee8f3b695e 236
EricLew 0:80ee8f3b695e 237 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO LEVEL
EricLew 0:80ee8f3b695e 238 * @{
EricLew 0:80ee8f3b695e 239 */
EricLew 0:80ee8f3b695e 240 #define LL_SPI_TX_FIFO_EMPTY ((uint32_t)0x00000000) /*!< FIFO transmission empty */
EricLew 0:80ee8f3b695e 241 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
EricLew 0:80ee8f3b695e 242 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
EricLew 0:80ee8f3b695e 243 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
EricLew 0:80ee8f3b695e 244 /**
EricLew 0:80ee8f3b695e 245 * @}
EricLew 0:80ee8f3b695e 246 */
EricLew 0:80ee8f3b695e 247
EricLew 0:80ee8f3b695e 248 /** @defgroup SPI_LL_EC_DMA_PARITY DMA PARITY
EricLew 0:80ee8f3b695e 249 * @{
EricLew 0:80ee8f3b695e 250 */
EricLew 0:80ee8f3b695e 251 #define LL_SPI_DMA_PARITY_EVEN ((uint32_t)0x00000000) /*!< Select DMA parity Even */
EricLew 0:80ee8f3b695e 252 #define LL_SPI_DMA_PARITY_ODD ((uint32_t)0x00000001) /*!< Select DMA parity Odd */
EricLew 0:80ee8f3b695e 253
EricLew 0:80ee8f3b695e 254 /**
EricLew 0:80ee8f3b695e 255 * @}
EricLew 0:80ee8f3b695e 256 */
EricLew 0:80ee8f3b695e 257
EricLew 0:80ee8f3b695e 258 /**
EricLew 0:80ee8f3b695e 259 * @}
EricLew 0:80ee8f3b695e 260 */
EricLew 0:80ee8f3b695e 261
EricLew 0:80ee8f3b695e 262 /* Exported macro ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 263 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
EricLew 0:80ee8f3b695e 264 * @{
EricLew 0:80ee8f3b695e 265 */
EricLew 0:80ee8f3b695e 266
EricLew 0:80ee8f3b695e 267 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
EricLew 0:80ee8f3b695e 268 * @{
EricLew 0:80ee8f3b695e 269 */
EricLew 0:80ee8f3b695e 270
EricLew 0:80ee8f3b695e 271 /**
EricLew 0:80ee8f3b695e 272 * @brief Write a value in SPI register
EricLew 0:80ee8f3b695e 273 * @param __INSTANCE__ SPI Instance
EricLew 0:80ee8f3b695e 274 * @param __REG__ Register to be written
EricLew 0:80ee8f3b695e 275 * @param __VALUE__ Value to be written in the register
EricLew 0:80ee8f3b695e 276 * @retval None
EricLew 0:80ee8f3b695e 277 */
EricLew 0:80ee8f3b695e 278 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
EricLew 0:80ee8f3b695e 279
EricLew 0:80ee8f3b695e 280 /**
EricLew 0:80ee8f3b695e 281 * @brief Read a value in SPI register
EricLew 0:80ee8f3b695e 282 * @param __INSTANCE__ SPI Instance
EricLew 0:80ee8f3b695e 283 * @param __REG__ Register to be read
EricLew 0:80ee8f3b695e 284 * @retval Register value
EricLew 0:80ee8f3b695e 285 */
EricLew 0:80ee8f3b695e 286 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
EricLew 0:80ee8f3b695e 287 /**
EricLew 0:80ee8f3b695e 288 * @}
EricLew 0:80ee8f3b695e 289 */
EricLew 0:80ee8f3b695e 290
EricLew 0:80ee8f3b695e 291 /**
EricLew 0:80ee8f3b695e 292 * @}
EricLew 0:80ee8f3b695e 293 */
EricLew 0:80ee8f3b695e 294
EricLew 0:80ee8f3b695e 295 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 296 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
EricLew 0:80ee8f3b695e 297 * @{
EricLew 0:80ee8f3b695e 298 */
EricLew 0:80ee8f3b695e 299
EricLew 0:80ee8f3b695e 300 /** @defgroup SPI_LL_EF_Configuration Configuration
EricLew 0:80ee8f3b695e 301 * @{
EricLew 0:80ee8f3b695e 302 */
EricLew 0:80ee8f3b695e 303
EricLew 0:80ee8f3b695e 304 /**
EricLew 0:80ee8f3b695e 305 * @brief Enable SPI peripheral
EricLew 0:80ee8f3b695e 306 * @rmtoll CR1 SPE LL_SPI_Enable
EricLew 0:80ee8f3b695e 307 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 308 * @retval None
EricLew 0:80ee8f3b695e 309 */
EricLew 0:80ee8f3b695e 310 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 311 {
EricLew 0:80ee8f3b695e 312 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
EricLew 0:80ee8f3b695e 313 }
EricLew 0:80ee8f3b695e 314
EricLew 0:80ee8f3b695e 315 /**
EricLew 0:80ee8f3b695e 316 * @brief Disable SPI peripheral
EricLew 0:80ee8f3b695e 317 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
EricLew 0:80ee8f3b695e 318 * @rmtoll CR1 SPE LL_SPI_Disable
EricLew 0:80ee8f3b695e 319 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 320 * @retval None
EricLew 0:80ee8f3b695e 321 */
EricLew 0:80ee8f3b695e 322 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 323 {
EricLew 0:80ee8f3b695e 324 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
EricLew 0:80ee8f3b695e 325 }
EricLew 0:80ee8f3b695e 326
EricLew 0:80ee8f3b695e 327 /**
EricLew 0:80ee8f3b695e 328 * @brief Check if SPI peripheral is enabled
EricLew 0:80ee8f3b695e 329 * @rmtoll CR1 SPE LL_SPI_IsEnabled
EricLew 0:80ee8f3b695e 330 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 331 * @retval None
EricLew 0:80ee8f3b695e 332 */
EricLew 0:80ee8f3b695e 333 __STATIC_INLINE void LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 334 {
EricLew 0:80ee8f3b695e 335 }
EricLew 0:80ee8f3b695e 336
EricLew 0:80ee8f3b695e 337 /**
EricLew 0:80ee8f3b695e 338 * @brief Set SPI Mode to Master or Slave
EricLew 0:80ee8f3b695e 339 * @note This bit should not be changed when communication is ongoing.
EricLew 0:80ee8f3b695e 340 * @rmtoll CR1 MSTR LL_SPI_SetMode\n
EricLew 0:80ee8f3b695e 341 * CR1 SSI LL_SPI_SetMode
EricLew 0:80ee8f3b695e 342 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 343 * @param Mode This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 344 * @arg @ref LL_SPI_MODE_MASTER
EricLew 0:80ee8f3b695e 345 * @arg @ref LL_SPI_MODE_SLAVE
EricLew 0:80ee8f3b695e 346 * @retval None
EricLew 0:80ee8f3b695e 347 */
EricLew 0:80ee8f3b695e 348 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
EricLew 0:80ee8f3b695e 349 {
EricLew 0:80ee8f3b695e 350 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
EricLew 0:80ee8f3b695e 351 }
EricLew 0:80ee8f3b695e 352
EricLew 0:80ee8f3b695e 353 /**
EricLew 0:80ee8f3b695e 354 * @brief Get SPI Mode (Master or Slave)
EricLew 0:80ee8f3b695e 355 * @rmtoll CR1 MSTR LL_SPI_GetMode\n
EricLew 0:80ee8f3b695e 356 * CR1 SSI LL_SPI_GetMode
EricLew 0:80ee8f3b695e 357 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 358 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 359 * @arg @ref LL_SPI_MODE_MASTER
EricLew 0:80ee8f3b695e 360 * @arg @ref LL_SPI_MODE_SLAVE
EricLew 0:80ee8f3b695e 361 */
EricLew 0:80ee8f3b695e 362 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 363 {
EricLew 0:80ee8f3b695e 364 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
EricLew 0:80ee8f3b695e 365 }
EricLew 0:80ee8f3b695e 366
EricLew 0:80ee8f3b695e 367 /**
EricLew 0:80ee8f3b695e 368 * @brief Set Serial protocol used
EricLew 0:80ee8f3b695e 369 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
EricLew 0:80ee8f3b695e 370 * @rmtoll CR2 FRF LL_SPI_SetStandard
EricLew 0:80ee8f3b695e 371 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 372 * @param Standard This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 373 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
EricLew 0:80ee8f3b695e 374 * @arg @ref LL_SPI_PROTOCOL_TI
EricLew 0:80ee8f3b695e 375 * @retval None
EricLew 0:80ee8f3b695e 376 */
EricLew 0:80ee8f3b695e 377 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
EricLew 0:80ee8f3b695e 378 {
EricLew 0:80ee8f3b695e 379 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
EricLew 0:80ee8f3b695e 380 }
EricLew 0:80ee8f3b695e 381
EricLew 0:80ee8f3b695e 382 /**
EricLew 0:80ee8f3b695e 383 * @brief Set Serial protocol used
EricLew 0:80ee8f3b695e 384 * @rmtoll CR2 FRF LL_SPI_GetStandard
EricLew 0:80ee8f3b695e 385 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 386 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 387 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
EricLew 0:80ee8f3b695e 388 * @arg @ref LL_SPI_PROTOCOL_TI
EricLew 0:80ee8f3b695e 389 */
EricLew 0:80ee8f3b695e 390 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 391 {
EricLew 0:80ee8f3b695e 392 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
EricLew 0:80ee8f3b695e 393 }
EricLew 0:80ee8f3b695e 394
EricLew 0:80ee8f3b695e 395 /**
EricLew 0:80ee8f3b695e 396 * @brief Set Clock phase
EricLew 0:80ee8f3b695e 397 * @note This bit should not be changed when communication is ongoing.
EricLew 0:80ee8f3b695e 398 * This bit is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 399 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase
EricLew 0:80ee8f3b695e 400 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 401 * @param ClockPhase This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 402 * @arg @ref LL_SPI_PHASE_1EDGE
EricLew 0:80ee8f3b695e 403 * @arg @ref LL_SPI_PHASE_2EDGE
EricLew 0:80ee8f3b695e 404 * @retval None
EricLew 0:80ee8f3b695e 405 */
EricLew 0:80ee8f3b695e 406 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
EricLew 0:80ee8f3b695e 407 {
EricLew 0:80ee8f3b695e 408 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
EricLew 0:80ee8f3b695e 409 }
EricLew 0:80ee8f3b695e 410
EricLew 0:80ee8f3b695e 411 /**
EricLew 0:80ee8f3b695e 412 * @brief Get Clock phase
EricLew 0:80ee8f3b695e 413 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase
EricLew 0:80ee8f3b695e 414 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 415 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 416 * @arg @ref LL_SPI_PHASE_1EDGE
EricLew 0:80ee8f3b695e 417 * @arg @ref LL_SPI_PHASE_2EDGE
EricLew 0:80ee8f3b695e 418 */
EricLew 0:80ee8f3b695e 419 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 420 {
EricLew 0:80ee8f3b695e 421 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
EricLew 0:80ee8f3b695e 422 }
EricLew 0:80ee8f3b695e 423
EricLew 0:80ee8f3b695e 424 /**
EricLew 0:80ee8f3b695e 425 * @brief Set Clock polarity
EricLew 0:80ee8f3b695e 426 * @note This bit should not be changed when communication is ongoing.
EricLew 0:80ee8f3b695e 427 * This bit is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 428 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
EricLew 0:80ee8f3b695e 429 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 430 * @param ClockPolarity This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 431 * @arg @ref LL_SPI_POLARITY_LOW
EricLew 0:80ee8f3b695e 432 * @arg @ref LL_SPI_POLARITY_HIGH
EricLew 0:80ee8f3b695e 433 * @retval None
EricLew 0:80ee8f3b695e 434 */
EricLew 0:80ee8f3b695e 435 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
EricLew 0:80ee8f3b695e 436 {
EricLew 0:80ee8f3b695e 437 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
EricLew 0:80ee8f3b695e 438 }
EricLew 0:80ee8f3b695e 439
EricLew 0:80ee8f3b695e 440 /**
EricLew 0:80ee8f3b695e 441 * @brief Get Clock polarity
EricLew 0:80ee8f3b695e 442 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
EricLew 0:80ee8f3b695e 443 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 444 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 445 * @arg @ref LL_SPI_POLARITY_LOW
EricLew 0:80ee8f3b695e 446 * @arg @ref LL_SPI_POLARITY_HIGH
EricLew 0:80ee8f3b695e 447 */
EricLew 0:80ee8f3b695e 448 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 449 {
EricLew 0:80ee8f3b695e 450 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
EricLew 0:80ee8f3b695e 451 }
EricLew 0:80ee8f3b695e 452
EricLew 0:80ee8f3b695e 453 /**
EricLew 0:80ee8f3b695e 454 * @brief Set Baudrate Prescaler
EricLew 0:80ee8f3b695e 455 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Pescaler.
EricLew 0:80ee8f3b695e 456 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
EricLew 0:80ee8f3b695e 457 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 458 * @param Baudrate This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 459 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
EricLew 0:80ee8f3b695e 460 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
EricLew 0:80ee8f3b695e 461 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
EricLew 0:80ee8f3b695e 462 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
EricLew 0:80ee8f3b695e 463 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
EricLew 0:80ee8f3b695e 464 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
EricLew 0:80ee8f3b695e 465 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
EricLew 0:80ee8f3b695e 466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
EricLew 0:80ee8f3b695e 467 * @retval None
EricLew 0:80ee8f3b695e 468 */
EricLew 0:80ee8f3b695e 469 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
EricLew 0:80ee8f3b695e 470 {
EricLew 0:80ee8f3b695e 471 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, Baudrate);
EricLew 0:80ee8f3b695e 472 }
EricLew 0:80ee8f3b695e 473
EricLew 0:80ee8f3b695e 474 /**
EricLew 0:80ee8f3b695e 475 * @brief Get Baudrate Prescaler
EricLew 0:80ee8f3b695e 476 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
EricLew 0:80ee8f3b695e 477 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 478 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 479 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
EricLew 0:80ee8f3b695e 480 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
EricLew 0:80ee8f3b695e 481 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
EricLew 0:80ee8f3b695e 482 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
EricLew 0:80ee8f3b695e 483 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
EricLew 0:80ee8f3b695e 484 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
EricLew 0:80ee8f3b695e 485 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
EricLew 0:80ee8f3b695e 486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
EricLew 0:80ee8f3b695e 487 */
EricLew 0:80ee8f3b695e 488 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 489 {
EricLew 0:80ee8f3b695e 490 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
EricLew 0:80ee8f3b695e 491 }
EricLew 0:80ee8f3b695e 492
EricLew 0:80ee8f3b695e 493 /**
EricLew 0:80ee8f3b695e 494 * @brief Set Transfer Bit Order
EricLew 0:80ee8f3b695e 495 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 496 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
EricLew 0:80ee8f3b695e 497 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 498 * @param BitOrder This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 499 * @arg @ref LL_SPI_LSB_FIRST
EricLew 0:80ee8f3b695e 500 * @arg @ref LL_SPI_MSB_FIRST
EricLew 0:80ee8f3b695e 501 * @retval None
EricLew 0:80ee8f3b695e 502 */
EricLew 0:80ee8f3b695e 503 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
EricLew 0:80ee8f3b695e 504 {
EricLew 0:80ee8f3b695e 505 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
EricLew 0:80ee8f3b695e 506 }
EricLew 0:80ee8f3b695e 507
EricLew 0:80ee8f3b695e 508 /**
EricLew 0:80ee8f3b695e 509 * @brief Get Transfer Bit Order
EricLew 0:80ee8f3b695e 510 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
EricLew 0:80ee8f3b695e 511 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 512 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 513 * @arg @ref LL_SPI_LSB_FIRST
EricLew 0:80ee8f3b695e 514 * @arg @ref LL_SPI_MSB_FIRST
EricLew 0:80ee8f3b695e 515 */
EricLew 0:80ee8f3b695e 516 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 517 {
EricLew 0:80ee8f3b695e 518 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
EricLew 0:80ee8f3b695e 519 }
EricLew 0:80ee8f3b695e 520
EricLew 0:80ee8f3b695e 521 /**
EricLew 0:80ee8f3b695e 522 * @brief Set Transfer Direction Mode
EricLew 0:80ee8f3b695e 523 * @note For Half-Duplex mode, Rx Direction is set by default.
EricLew 0:80ee8f3b695e 524 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
EricLew 0:80ee8f3b695e 525 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
EricLew 0:80ee8f3b695e 526 * CR1 BIDIMODE LL_SPI_SetTransferDirection
EricLew 0:80ee8f3b695e 527 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 528 * @param TransferDirection This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 529 * @arg @ref LL_SPI_FULL_DUPLEX
EricLew 0:80ee8f3b695e 530 * @arg @ref LL_SPI_SIMPLEX_RX
EricLew 0:80ee8f3b695e 531 * @arg @ref LL_SPI_HALF_DUPLEX
EricLew 0:80ee8f3b695e 532 * @retval None
EricLew 0:80ee8f3b695e 533 */
EricLew 0:80ee8f3b695e 534 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
EricLew 0:80ee8f3b695e 535 {
EricLew 0:80ee8f3b695e 536 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE, TransferDirection);
EricLew 0:80ee8f3b695e 537 }
EricLew 0:80ee8f3b695e 538
EricLew 0:80ee8f3b695e 539 /**
EricLew 0:80ee8f3b695e 540 * @brief Get Transfer Direction Mode
EricLew 0:80ee8f3b695e 541 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
EricLew 0:80ee8f3b695e 542 * CR1 BIDIMODE LL_SPI_GetTransferDirection
EricLew 0:80ee8f3b695e 543 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 544 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 545 * @arg @ref LL_SPI_FULL_DUPLEX
EricLew 0:80ee8f3b695e 546 * @arg @ref LL_SPI_SIMPLEX_RX
EricLew 0:80ee8f3b695e 547 * @arg @ref LL_SPI_HALF_DUPLEX
EricLew 0:80ee8f3b695e 548 */
EricLew 0:80ee8f3b695e 549 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 550 {
EricLew 0:80ee8f3b695e 551 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE));
EricLew 0:80ee8f3b695e 552 }
EricLew 0:80ee8f3b695e 553
EricLew 0:80ee8f3b695e 554 /**
EricLew 0:80ee8f3b695e 555 * @brief Set direction for Half-Duplex Mode
EricLew 0:80ee8f3b695e 556 * @note In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
EricLew 0:80ee8f3b695e 557 * @rmtoll CR1 BIDIOE LL_SPI_SetHalfDuplexDirection
EricLew 0:80ee8f3b695e 558 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 559 * @param HalfDuplexDirection This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 560 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_TX
EricLew 0:80ee8f3b695e 561 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_RX
EricLew 0:80ee8f3b695e 562 * @retval None
EricLew 0:80ee8f3b695e 563 */
EricLew 0:80ee8f3b695e 564 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
EricLew 0:80ee8f3b695e 565 {
EricLew 0:80ee8f3b695e 566 MODIFY_REG(SPIx->CR1, SPI_CR1_BIDIOE, HalfDuplexDirection);
EricLew 0:80ee8f3b695e 567 }
EricLew 0:80ee8f3b695e 568
EricLew 0:80ee8f3b695e 569 /**
EricLew 0:80ee8f3b695e 570 * @brief Get direction for Half-Duplex Mode
EricLew 0:80ee8f3b695e 571 * @note In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
EricLew 0:80ee8f3b695e 572 * @rmtoll CR1 BIDIOE LL_SPI_GetHalfDuplexDirection
EricLew 0:80ee8f3b695e 573 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 574 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 575 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_TX
EricLew 0:80ee8f3b695e 576 * @arg @ref LL_SPI_DIRECTION_HALF_DUPLEX_RX
EricLew 0:80ee8f3b695e 577 */
EricLew 0:80ee8f3b695e 578 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 579 {
EricLew 0:80ee8f3b695e 580 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BIDIOE));
EricLew 0:80ee8f3b695e 581 }
EricLew 0:80ee8f3b695e 582
EricLew 0:80ee8f3b695e 583 /**
EricLew 0:80ee8f3b695e 584 * @brief Set Frame Data Size
EricLew 0:80ee8f3b695e 585 * @rmtoll CR2 DS LL_SPI_SetDataWidth
EricLew 0:80ee8f3b695e 586 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 587 * @param DataWidth This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 588 * @arg @ref LL_SPI_DATAWIDTH_4BIT
EricLew 0:80ee8f3b695e 589 * @arg @ref LL_SPI_DATAWIDTH_5BIT
EricLew 0:80ee8f3b695e 590 * @arg @ref LL_SPI_DATAWIDTH_6BIT
EricLew 0:80ee8f3b695e 591 * @arg @ref LL_SPI_DATAWIDTH_7BIT
EricLew 0:80ee8f3b695e 592 * @arg @ref LL_SPI_DATAWIDTH_8BIT
EricLew 0:80ee8f3b695e 593 * @arg @ref LL_SPI_DATAWIDTH_9BIT
EricLew 0:80ee8f3b695e 594 * @arg @ref LL_SPI_DATAWIDTH_10BIT
EricLew 0:80ee8f3b695e 595 * @arg @ref LL_SPI_DATAWIDTH_11BIT
EricLew 0:80ee8f3b695e 596 * @arg @ref LL_SPI_DATAWIDTH_12BIT
EricLew 0:80ee8f3b695e 597 * @arg @ref LL_SPI_DATAWIDTH_13BIT
EricLew 0:80ee8f3b695e 598 * @arg @ref LL_SPI_DATAWIDTH_14BIT
EricLew 0:80ee8f3b695e 599 * @arg @ref LL_SPI_DATAWIDTH_15BIT
EricLew 0:80ee8f3b695e 600 * @arg @ref LL_SPI_DATAWIDTH_16BIT
EricLew 0:80ee8f3b695e 601 * @retval None
EricLew 0:80ee8f3b695e 602 */
EricLew 0:80ee8f3b695e 603 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
EricLew 0:80ee8f3b695e 604 {
EricLew 0:80ee8f3b695e 605 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
EricLew 0:80ee8f3b695e 606 }
EricLew 0:80ee8f3b695e 607
EricLew 0:80ee8f3b695e 608 /**
EricLew 0:80ee8f3b695e 609 * @brief Get Frame Data Size
EricLew 0:80ee8f3b695e 610 * @rmtoll CR2 DS LL_SPI_GetDataWidth
EricLew 0:80ee8f3b695e 611 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 612 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 613 * @arg @ref LL_SPI_DATAWIDTH_4BIT
EricLew 0:80ee8f3b695e 614 * @arg @ref LL_SPI_DATAWIDTH_5BIT
EricLew 0:80ee8f3b695e 615 * @arg @ref LL_SPI_DATAWIDTH_6BIT
EricLew 0:80ee8f3b695e 616 * @arg @ref LL_SPI_DATAWIDTH_7BIT
EricLew 0:80ee8f3b695e 617 * @arg @ref LL_SPI_DATAWIDTH_8BIT
EricLew 0:80ee8f3b695e 618 * @arg @ref LL_SPI_DATAWIDTH_9BIT
EricLew 0:80ee8f3b695e 619 * @arg @ref LL_SPI_DATAWIDTH_10BIT
EricLew 0:80ee8f3b695e 620 * @arg @ref LL_SPI_DATAWIDTH_11BIT
EricLew 0:80ee8f3b695e 621 * @arg @ref LL_SPI_DATAWIDTH_12BIT
EricLew 0:80ee8f3b695e 622 * @arg @ref LL_SPI_DATAWIDTH_13BIT
EricLew 0:80ee8f3b695e 623 * @arg @ref LL_SPI_DATAWIDTH_14BIT
EricLew 0:80ee8f3b695e 624 * @arg @ref LL_SPI_DATAWIDTH_15BIT
EricLew 0:80ee8f3b695e 625 * @arg @ref LL_SPI_DATAWIDTH_16BIT
EricLew 0:80ee8f3b695e 626 */
EricLew 0:80ee8f3b695e 627 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 628 {
EricLew 0:80ee8f3b695e 629 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
EricLew 0:80ee8f3b695e 630 }
EricLew 0:80ee8f3b695e 631
EricLew 0:80ee8f3b695e 632 /**
EricLew 0:80ee8f3b695e 633 * @brief Set threshold of RXFIFO that triggers an RXNE event
EricLew 0:80ee8f3b695e 634 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
EricLew 0:80ee8f3b695e 635 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 636 * @param Threshold This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 637 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
EricLew 0:80ee8f3b695e 638 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
EricLew 0:80ee8f3b695e 639 * @retval None
EricLew 0:80ee8f3b695e 640 */
EricLew 0:80ee8f3b695e 641 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
EricLew 0:80ee8f3b695e 642 {
EricLew 0:80ee8f3b695e 643 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
EricLew 0:80ee8f3b695e 644 }
EricLew 0:80ee8f3b695e 645
EricLew 0:80ee8f3b695e 646 /**
EricLew 0:80ee8f3b695e 647 * @brief Get threshold of RXFIFO that triggers an RXNE event
EricLew 0:80ee8f3b695e 648 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
EricLew 0:80ee8f3b695e 649 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 650 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 651 * @arg @ref LL_SPI_RX_FIFO_TH_HALF
EricLew 0:80ee8f3b695e 652 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
EricLew 0:80ee8f3b695e 653 */
EricLew 0:80ee8f3b695e 654 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 655 {
EricLew 0:80ee8f3b695e 656 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
EricLew 0:80ee8f3b695e 657 }
EricLew 0:80ee8f3b695e 658
EricLew 0:80ee8f3b695e 659 /**
EricLew 0:80ee8f3b695e 660 * @}
EricLew 0:80ee8f3b695e 661 */
EricLew 0:80ee8f3b695e 662
EricLew 0:80ee8f3b695e 663 /** @defgroup SPI_EF_CRC_Management CRC_Management
EricLew 0:80ee8f3b695e 664 * @{
EricLew 0:80ee8f3b695e 665 */
EricLew 0:80ee8f3b695e 666
EricLew 0:80ee8f3b695e 667 /**
EricLew 0:80ee8f3b695e 668 * @brief Enable CRC
EricLew 0:80ee8f3b695e 669 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
EricLew 0:80ee8f3b695e 670 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC
EricLew 0:80ee8f3b695e 671 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 672 * @retval None
EricLew 0:80ee8f3b695e 673 */
EricLew 0:80ee8f3b695e 674 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 675 {
EricLew 0:80ee8f3b695e 676 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
EricLew 0:80ee8f3b695e 677 }
EricLew 0:80ee8f3b695e 678
EricLew 0:80ee8f3b695e 679 /**
EricLew 0:80ee8f3b695e 680 * @brief Disable CRC
EricLew 0:80ee8f3b695e 681 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
EricLew 0:80ee8f3b695e 682 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC
EricLew 0:80ee8f3b695e 683 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 684 * @retval None
EricLew 0:80ee8f3b695e 685 */
EricLew 0:80ee8f3b695e 686 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 687 {
EricLew 0:80ee8f3b695e 688 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
EricLew 0:80ee8f3b695e 689 }
EricLew 0:80ee8f3b695e 690
EricLew 0:80ee8f3b695e 691 /**
EricLew 0:80ee8f3b695e 692 * @brief Check if CRC is enabled
EricLew 0:80ee8f3b695e 693 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
EricLew 0:80ee8f3b695e 694 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
EricLew 0:80ee8f3b695e 695 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 696 * @retval None
EricLew 0:80ee8f3b695e 697 */
EricLew 0:80ee8f3b695e 698 __STATIC_INLINE void LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 699 {
EricLew 0:80ee8f3b695e 700 }
EricLew 0:80ee8f3b695e 701
EricLew 0:80ee8f3b695e 702 /**
EricLew 0:80ee8f3b695e 703 * @brief Set CRC Length
EricLew 0:80ee8f3b695e 704 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
EricLew 0:80ee8f3b695e 705 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
EricLew 0:80ee8f3b695e 706 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 707 * @param CRCLength This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 708 * @arg @ref LL_SPI_CRC_8BIT
EricLew 0:80ee8f3b695e 709 * @arg @ref LL_SPI_CRC_16BIT
EricLew 0:80ee8f3b695e 710 * @retval None
EricLew 0:80ee8f3b695e 711 */
EricLew 0:80ee8f3b695e 712 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
EricLew 0:80ee8f3b695e 713 {
EricLew 0:80ee8f3b695e 714 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
EricLew 0:80ee8f3b695e 715 }
EricLew 0:80ee8f3b695e 716
EricLew 0:80ee8f3b695e 717 /**
EricLew 0:80ee8f3b695e 718 * @brief Get CRC Length
EricLew 0:80ee8f3b695e 719 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
EricLew 0:80ee8f3b695e 720 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 721 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 722 * @arg @ref LL_SPI_CRC_8BIT
EricLew 0:80ee8f3b695e 723 * @arg @ref LL_SPI_CRC_16BIT
EricLew 0:80ee8f3b695e 724 */
EricLew 0:80ee8f3b695e 725 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 726 {
EricLew 0:80ee8f3b695e 727 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
EricLew 0:80ee8f3b695e 728 }
EricLew 0:80ee8f3b695e 729
EricLew 0:80ee8f3b695e 730 /**
EricLew 0:80ee8f3b695e 731 * @brief Set CRCNext to transfer CRC on the line
EricLew 0:80ee8f3b695e 732 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
EricLew 0:80ee8f3b695e 733 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
EricLew 0:80ee8f3b695e 734 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 735 * @retval None
EricLew 0:80ee8f3b695e 736 */
EricLew 0:80ee8f3b695e 737 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 738 {
EricLew 0:80ee8f3b695e 739 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
EricLew 0:80ee8f3b695e 740 }
EricLew 0:80ee8f3b695e 741
EricLew 0:80ee8f3b695e 742 /**
EricLew 0:80ee8f3b695e 743 * @brief Set polynomial for CRC calculation
EricLew 0:80ee8f3b695e 744 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
EricLew 0:80ee8f3b695e 745 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 746 * @param CRCPoly 0..0xFFFF
EricLew 0:80ee8f3b695e 747 * @retval None
EricLew 0:80ee8f3b695e 748 */
EricLew 0:80ee8f3b695e 749 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
EricLew 0:80ee8f3b695e 750 {
EricLew 0:80ee8f3b695e 751 MODIFY_REG(SPIx->CRCPR, SPI_CRCPR_CRCPOLY, CRCPoly);
EricLew 0:80ee8f3b695e 752 }
EricLew 0:80ee8f3b695e 753
EricLew 0:80ee8f3b695e 754 /**
EricLew 0:80ee8f3b695e 755 * @brief Get polynomial for CRC calculation
EricLew 0:80ee8f3b695e 756 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
EricLew 0:80ee8f3b695e 757 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 758 * @retval 0..0xFFFF
EricLew 0:80ee8f3b695e 759 */
EricLew 0:80ee8f3b695e 760 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 761 {
EricLew 0:80ee8f3b695e 762 return (uint32_t)(READ_REG(SPIx->CRCPR));
EricLew 0:80ee8f3b695e 763 }
EricLew 0:80ee8f3b695e 764
EricLew 0:80ee8f3b695e 765 /**
EricLew 0:80ee8f3b695e 766 * @brief Get Rx CRC
EricLew 0:80ee8f3b695e 767 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
EricLew 0:80ee8f3b695e 768 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 769 * @retval 0..0xFFFF
EricLew 0:80ee8f3b695e 770 */
EricLew 0:80ee8f3b695e 771 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 772 {
EricLew 0:80ee8f3b695e 773 return (uint32_t)(READ_REG(SPIx->RXCRCR));
EricLew 0:80ee8f3b695e 774 }
EricLew 0:80ee8f3b695e 775
EricLew 0:80ee8f3b695e 776 /**
EricLew 0:80ee8f3b695e 777 * @brief Get Tx CRC
EricLew 0:80ee8f3b695e 778 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
EricLew 0:80ee8f3b695e 779 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 780 * @retval 0..0xFFFF
EricLew 0:80ee8f3b695e 781 */
EricLew 0:80ee8f3b695e 782 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 783 {
EricLew 0:80ee8f3b695e 784 return (uint32_t)(READ_REG(SPIx->TXCRCR));
EricLew 0:80ee8f3b695e 785 }
EricLew 0:80ee8f3b695e 786
EricLew 0:80ee8f3b695e 787 /**
EricLew 0:80ee8f3b695e 788 * @}
EricLew 0:80ee8f3b695e 789 */
EricLew 0:80ee8f3b695e 790
EricLew 0:80ee8f3b695e 791 /** @defgroup SPI_EF_NSS_Management NSS_Management
EricLew 0:80ee8f3b695e 792 * @{
EricLew 0:80ee8f3b695e 793 */
EricLew 0:80ee8f3b695e 794
EricLew 0:80ee8f3b695e 795 /**
EricLew 0:80ee8f3b695e 796 * @brief Set NSS Mode
EricLew 0:80ee8f3b695e 797 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 798 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
EricLew 0:80ee8f3b695e 799 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode
EricLew 0:80ee8f3b695e 800 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 801 * @param NSS This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 802 * @arg @ref LL_SPI_NSS_SOFT
EricLew 0:80ee8f3b695e 803 * @arg @ref LL_SPI_NSS_HARD_INPUT
EricLew 0:80ee8f3b695e 804 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
EricLew 0:80ee8f3b695e 805 * @retval None
EricLew 0:80ee8f3b695e 806 */
EricLew 0:80ee8f3b695e 807 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
EricLew 0:80ee8f3b695e 808 {
EricLew 0:80ee8f3b695e 809 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
EricLew 0:80ee8f3b695e 810 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16)));
EricLew 0:80ee8f3b695e 811 }
EricLew 0:80ee8f3b695e 812
EricLew 0:80ee8f3b695e 813 /**
EricLew 0:80ee8f3b695e 814 * @brief Get NSS Mode
EricLew 0:80ee8f3b695e 815 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
EricLew 0:80ee8f3b695e 816 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode
EricLew 0:80ee8f3b695e 817 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 818 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 819 * @arg @ref LL_SPI_NSS_SOFT
EricLew 0:80ee8f3b695e 820 * @arg @ref LL_SPI_NSS_HARD_INPUT
EricLew 0:80ee8f3b695e 821 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
EricLew 0:80ee8f3b695e 822 */
EricLew 0:80ee8f3b695e 823 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 824 {
EricLew 0:80ee8f3b695e 825 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
EricLew 0:80ee8f3b695e 826 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16);
EricLew 0:80ee8f3b695e 827 return (Ssm | Ssoe);
EricLew 0:80ee8f3b695e 828 }
EricLew 0:80ee8f3b695e 829
EricLew 0:80ee8f3b695e 830 /**
EricLew 0:80ee8f3b695e 831 * @brief Enable NSS pulse mgt
EricLew 0:80ee8f3b695e 832 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 833 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
EricLew 0:80ee8f3b695e 834 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 835 * @retval None
EricLew 0:80ee8f3b695e 836 */
EricLew 0:80ee8f3b695e 837 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 838 {
EricLew 0:80ee8f3b695e 839 SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
EricLew 0:80ee8f3b695e 840 }
EricLew 0:80ee8f3b695e 841
EricLew 0:80ee8f3b695e 842 /**
EricLew 0:80ee8f3b695e 843 * @brief Disable NSS pulse mgt
EricLew 0:80ee8f3b695e 844 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 845 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
EricLew 0:80ee8f3b695e 846 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 847 * @retval None
EricLew 0:80ee8f3b695e 848 */
EricLew 0:80ee8f3b695e 849 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 850 {
EricLew 0:80ee8f3b695e 851 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
EricLew 0:80ee8f3b695e 852 }
EricLew 0:80ee8f3b695e 853
EricLew 0:80ee8f3b695e 854 /**
EricLew 0:80ee8f3b695e 855 * @brief Check if NSS pulse is enabled
EricLew 0:80ee8f3b695e 856 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
EricLew 0:80ee8f3b695e 857 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
EricLew 0:80ee8f3b695e 858 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 859 * @retval None
EricLew 0:80ee8f3b695e 860 */
EricLew 0:80ee8f3b695e 861 __STATIC_INLINE void LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 862 {
EricLew 0:80ee8f3b695e 863 }
EricLew 0:80ee8f3b695e 864
EricLew 0:80ee8f3b695e 865 /**
EricLew 0:80ee8f3b695e 866 * @}
EricLew 0:80ee8f3b695e 867 */
EricLew 0:80ee8f3b695e 868
EricLew 0:80ee8f3b695e 869 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
EricLew 0:80ee8f3b695e 870 * @{
EricLew 0:80ee8f3b695e 871 */
EricLew 0:80ee8f3b695e 872
EricLew 0:80ee8f3b695e 873 /**
EricLew 0:80ee8f3b695e 874 * @brief Check if Rx buffer is not empty
EricLew 0:80ee8f3b695e 875 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
EricLew 0:80ee8f3b695e 876 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 877 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 878 */
EricLew 0:80ee8f3b695e 879 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 880 {
EricLew 0:80ee8f3b695e 881 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
EricLew 0:80ee8f3b695e 882 }
EricLew 0:80ee8f3b695e 883
EricLew 0:80ee8f3b695e 884 /**
EricLew 0:80ee8f3b695e 885 * @brief Check if Tx buffer is empty
EricLew 0:80ee8f3b695e 886 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
EricLew 0:80ee8f3b695e 887 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 888 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 889 */
EricLew 0:80ee8f3b695e 890 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 891 {
EricLew 0:80ee8f3b695e 892 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
EricLew 0:80ee8f3b695e 893 }
EricLew 0:80ee8f3b695e 894
EricLew 0:80ee8f3b695e 895 /**
EricLew 0:80ee8f3b695e 896 * @brief Get Underrun error flag
EricLew 0:80ee8f3b695e 897 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
EricLew 0:80ee8f3b695e 898 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 899 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 900 */
EricLew 0:80ee8f3b695e 901 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 902 {
EricLew 0:80ee8f3b695e 903 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
EricLew 0:80ee8f3b695e 904 }
EricLew 0:80ee8f3b695e 905
EricLew 0:80ee8f3b695e 906 /**
EricLew 0:80ee8f3b695e 907 * @brief Get CRC error flag
EricLew 0:80ee8f3b695e 908 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
EricLew 0:80ee8f3b695e 909 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 910 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 911 */
EricLew 0:80ee8f3b695e 912 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 913 {
EricLew 0:80ee8f3b695e 914 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
EricLew 0:80ee8f3b695e 915 }
EricLew 0:80ee8f3b695e 916
EricLew 0:80ee8f3b695e 917 /**
EricLew 0:80ee8f3b695e 918 * @brief Get Mode fault error flag
EricLew 0:80ee8f3b695e 919 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
EricLew 0:80ee8f3b695e 920 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 921 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 922 */
EricLew 0:80ee8f3b695e 923 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 924 {
EricLew 0:80ee8f3b695e 925 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
EricLew 0:80ee8f3b695e 926 }
EricLew 0:80ee8f3b695e 927
EricLew 0:80ee8f3b695e 928 /**
EricLew 0:80ee8f3b695e 929 * @brief Get Overrun error flag
EricLew 0:80ee8f3b695e 930 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
EricLew 0:80ee8f3b695e 931 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 932 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 933 */
EricLew 0:80ee8f3b695e 934 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 935 {
EricLew 0:80ee8f3b695e 936 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
EricLew 0:80ee8f3b695e 937 }
EricLew 0:80ee8f3b695e 938
EricLew 0:80ee8f3b695e 939 /**
EricLew 0:80ee8f3b695e 940 * @brief Get Busy flag
EricLew 0:80ee8f3b695e 941 * @note The BSY flag is cleared under any one of the following conditions:
EricLew 0:80ee8f3b695e 942 * -When the SPI is correctly disabled
EricLew 0:80ee8f3b695e 943 * -When a fault is detected in Master mode (MODF bit set to 1)
EricLew 0:80ee8f3b695e 944 * -In Master mode, when it finishes a data transmission and no new data is ready to be
EricLew 0:80ee8f3b695e 945 * sent
EricLew 0:80ee8f3b695e 946 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
EricLew 0:80ee8f3b695e 947 * each data transfer.
EricLew 0:80ee8f3b695e 948 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
EricLew 0:80ee8f3b695e 949 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 950 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 951 */
EricLew 0:80ee8f3b695e 952 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 953 {
EricLew 0:80ee8f3b695e 954 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
EricLew 0:80ee8f3b695e 955 }
EricLew 0:80ee8f3b695e 956
EricLew 0:80ee8f3b695e 957 /**
EricLew 0:80ee8f3b695e 958 * @brief Get Frame format error flag
EricLew 0:80ee8f3b695e 959 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
EricLew 0:80ee8f3b695e 960 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 961 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 962 */
EricLew 0:80ee8f3b695e 963 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 964 {
EricLew 0:80ee8f3b695e 965 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
EricLew 0:80ee8f3b695e 966 }
EricLew 0:80ee8f3b695e 967
EricLew 0:80ee8f3b695e 968 /**
EricLew 0:80ee8f3b695e 969 * @brief Get FIFO reception Level
EricLew 0:80ee8f3b695e 970 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
EricLew 0:80ee8f3b695e 971 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 972 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 973 * @arg @ref LL_SPI_RX_FIFO_EMPTY
EricLew 0:80ee8f3b695e 974 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
EricLew 0:80ee8f3b695e 975 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL
EricLew 0:80ee8f3b695e 976 * @arg @ref LL_SPI_RX_FIFO_FULL
EricLew 0:80ee8f3b695e 977 */
EricLew 0:80ee8f3b695e 978 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 979 {
EricLew 0:80ee8f3b695e 980 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
EricLew 0:80ee8f3b695e 981 }
EricLew 0:80ee8f3b695e 982
EricLew 0:80ee8f3b695e 983 /**
EricLew 0:80ee8f3b695e 984 * @brief Get FIFO Transmission Level
EricLew 0:80ee8f3b695e 985 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
EricLew 0:80ee8f3b695e 986 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 987 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 988 * @arg @ref LL_SPI_TX_FIFO_EMPTY
EricLew 0:80ee8f3b695e 989 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
EricLew 0:80ee8f3b695e 990 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL
EricLew 0:80ee8f3b695e 991 * @arg @ref LL_SPI_TX_FIFO_FULL
EricLew 0:80ee8f3b695e 992 */
EricLew 0:80ee8f3b695e 993 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 994 {
EricLew 0:80ee8f3b695e 995 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
EricLew 0:80ee8f3b695e 996 }
EricLew 0:80ee8f3b695e 997
EricLew 0:80ee8f3b695e 998 /**
EricLew 0:80ee8f3b695e 999 * @brief Clear Underrun error flag
EricLew 0:80ee8f3b695e 1000 * @rmtoll SR UDR LL_SPI_ClearFlag_UDR
EricLew 0:80ee8f3b695e 1001 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1002 * @retval None
EricLew 0:80ee8f3b695e 1003 */
EricLew 0:80ee8f3b695e 1004 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1005 {
EricLew 0:80ee8f3b695e 1006 __IO uint32_t tmpreg;
EricLew 0:80ee8f3b695e 1007 tmpreg = SPIx->SR;
EricLew 0:80ee8f3b695e 1008 (void) tmpreg;
EricLew 0:80ee8f3b695e 1009 }
EricLew 0:80ee8f3b695e 1010
EricLew 0:80ee8f3b695e 1011 /**
EricLew 0:80ee8f3b695e 1012 * @brief Clear CRC error flag
EricLew 0:80ee8f3b695e 1013 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
EricLew 0:80ee8f3b695e 1014 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1015 * @retval None
EricLew 0:80ee8f3b695e 1016 */
EricLew 0:80ee8f3b695e 1017 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1018 {
EricLew 0:80ee8f3b695e 1019 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
EricLew 0:80ee8f3b695e 1020 }
EricLew 0:80ee8f3b695e 1021
EricLew 0:80ee8f3b695e 1022 /**
EricLew 0:80ee8f3b695e 1023 * @brief Clear Mode fault error flag
EricLew 0:80ee8f3b695e 1024 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF
EricLew 0:80ee8f3b695e 1025 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1026 * @retval None
EricLew 0:80ee8f3b695e 1027 */
EricLew 0:80ee8f3b695e 1028 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1029 {
EricLew 0:80ee8f3b695e 1030 __IO uint32_t tmpreg;
EricLew 0:80ee8f3b695e 1031 tmpreg = SPIx->SR;
EricLew 0:80ee8f3b695e 1032 (void) tmpreg;
EricLew 0:80ee8f3b695e 1033 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
EricLew 0:80ee8f3b695e 1034 (void) tmpreg;
EricLew 0:80ee8f3b695e 1035 }
EricLew 0:80ee8f3b695e 1036
EricLew 0:80ee8f3b695e 1037 /**
EricLew 0:80ee8f3b695e 1038 * @brief Clear Overrun error flag
EricLew 0:80ee8f3b695e 1039 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR
EricLew 0:80ee8f3b695e 1040 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1041 * @retval None
EricLew 0:80ee8f3b695e 1042 */
EricLew 0:80ee8f3b695e 1043 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1044 {
EricLew 0:80ee8f3b695e 1045 __IO uint32_t tmpreg;
EricLew 0:80ee8f3b695e 1046 tmpreg = SPIx->DR;
EricLew 0:80ee8f3b695e 1047 (void) tmpreg;
EricLew 0:80ee8f3b695e 1048 tmpreg = SPIx->SR;
EricLew 0:80ee8f3b695e 1049 (void) tmpreg;
EricLew 0:80ee8f3b695e 1050 }
EricLew 0:80ee8f3b695e 1051
EricLew 0:80ee8f3b695e 1052 /**
EricLew 0:80ee8f3b695e 1053 * @brief Clear Frame format error flag
EricLew 0:80ee8f3b695e 1054 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE
EricLew 0:80ee8f3b695e 1055 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1056 * @retval None
EricLew 0:80ee8f3b695e 1057 */
EricLew 0:80ee8f3b695e 1058 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1059 {
EricLew 0:80ee8f3b695e 1060 __IO uint32_t tmpreg;
EricLew 0:80ee8f3b695e 1061 tmpreg = SPIx->SR;
EricLew 0:80ee8f3b695e 1062 (void) tmpreg;
EricLew 0:80ee8f3b695e 1063 }
EricLew 0:80ee8f3b695e 1064
EricLew 0:80ee8f3b695e 1065 /**
EricLew 0:80ee8f3b695e 1066 * @}
EricLew 0:80ee8f3b695e 1067 */
EricLew 0:80ee8f3b695e 1068
EricLew 0:80ee8f3b695e 1069 /** @defgroup SPI_LL_EF_IT_Management IT_Management
EricLew 0:80ee8f3b695e 1070 * @{
EricLew 0:80ee8f3b695e 1071 */
EricLew 0:80ee8f3b695e 1072
EricLew 0:80ee8f3b695e 1073 /**
EricLew 0:80ee8f3b695e 1074 * @brief Enable Error IT
EricLew 0:80ee8f3b695e 1075 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR,OVR, MODF in SPI mode, FRE at TI mode).
EricLew 0:80ee8f3b695e 1076 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
EricLew 0:80ee8f3b695e 1077 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1078 * @retval None
EricLew 0:80ee8f3b695e 1079 */
EricLew 0:80ee8f3b695e 1080 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1081 {
EricLew 0:80ee8f3b695e 1082 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
EricLew 0:80ee8f3b695e 1083 }
EricLew 0:80ee8f3b695e 1084
EricLew 0:80ee8f3b695e 1085 /**
EricLew 0:80ee8f3b695e 1086 * @brief Enable Rx buffer not empty IT
EricLew 0:80ee8f3b695e 1087 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
EricLew 0:80ee8f3b695e 1088 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1089 * @retval None
EricLew 0:80ee8f3b695e 1090 */
EricLew 0:80ee8f3b695e 1091 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1092 {
EricLew 0:80ee8f3b695e 1093 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
EricLew 0:80ee8f3b695e 1094 }
EricLew 0:80ee8f3b695e 1095
EricLew 0:80ee8f3b695e 1096 /**
EricLew 0:80ee8f3b695e 1097 * @brief Enable Tx buffer empty IT
EricLew 0:80ee8f3b695e 1098 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
EricLew 0:80ee8f3b695e 1099 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1100 * @retval None
EricLew 0:80ee8f3b695e 1101 */
EricLew 0:80ee8f3b695e 1102 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1103 {
EricLew 0:80ee8f3b695e 1104 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
EricLew 0:80ee8f3b695e 1105 }
EricLew 0:80ee8f3b695e 1106
EricLew 0:80ee8f3b695e 1107 /**
EricLew 0:80ee8f3b695e 1108 * @brief Disable Error IT
EricLew 0:80ee8f3b695e 1109 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
EricLew 0:80ee8f3b695e 1110 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
EricLew 0:80ee8f3b695e 1111 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1112 * @retval None
EricLew 0:80ee8f3b695e 1113 */
EricLew 0:80ee8f3b695e 1114 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1115 {
EricLew 0:80ee8f3b695e 1116 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
EricLew 0:80ee8f3b695e 1117 }
EricLew 0:80ee8f3b695e 1118
EricLew 0:80ee8f3b695e 1119 /**
EricLew 0:80ee8f3b695e 1120 * @brief Disable Rx buffer not empty IT
EricLew 0:80ee8f3b695e 1121 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
EricLew 0:80ee8f3b695e 1122 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1123 * @retval None
EricLew 0:80ee8f3b695e 1124 */
EricLew 0:80ee8f3b695e 1125 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1126 {
EricLew 0:80ee8f3b695e 1127 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
EricLew 0:80ee8f3b695e 1128 }
EricLew 0:80ee8f3b695e 1129
EricLew 0:80ee8f3b695e 1130 /**
EricLew 0:80ee8f3b695e 1131 * @brief Disable Tx buffer empty IT
EricLew 0:80ee8f3b695e 1132 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
EricLew 0:80ee8f3b695e 1133 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1134 * @retval None
EricLew 0:80ee8f3b695e 1135 */
EricLew 0:80ee8f3b695e 1136 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1137 {
EricLew 0:80ee8f3b695e 1138 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
EricLew 0:80ee8f3b695e 1139 }
EricLew 0:80ee8f3b695e 1140
EricLew 0:80ee8f3b695e 1141 /**
EricLew 0:80ee8f3b695e 1142 * @brief Check if ERR IT is enabled
EricLew 0:80ee8f3b695e 1143 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
EricLew 0:80ee8f3b695e 1144 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1145 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 1146 */
EricLew 0:80ee8f3b695e 1147 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1148 {
EricLew 0:80ee8f3b695e 1149 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
EricLew 0:80ee8f3b695e 1150 }
EricLew 0:80ee8f3b695e 1151
EricLew 0:80ee8f3b695e 1152 /**
EricLew 0:80ee8f3b695e 1153 * @brief Check if RXNE IT is enabled
EricLew 0:80ee8f3b695e 1154 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
EricLew 0:80ee8f3b695e 1155 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1156 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 1157 */
EricLew 0:80ee8f3b695e 1158 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1159 {
EricLew 0:80ee8f3b695e 1160 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
EricLew 0:80ee8f3b695e 1161 }
EricLew 0:80ee8f3b695e 1162
EricLew 0:80ee8f3b695e 1163 /**
EricLew 0:80ee8f3b695e 1164 * @brief Check if TXE IT is enabled
EricLew 0:80ee8f3b695e 1165 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
EricLew 0:80ee8f3b695e 1166 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1167 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 1168 */
EricLew 0:80ee8f3b695e 1169 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1170 {
EricLew 0:80ee8f3b695e 1171 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
EricLew 0:80ee8f3b695e 1172 }
EricLew 0:80ee8f3b695e 1173
EricLew 0:80ee8f3b695e 1174 /**
EricLew 0:80ee8f3b695e 1175 * @}
EricLew 0:80ee8f3b695e 1176 */
EricLew 0:80ee8f3b695e 1177
EricLew 0:80ee8f3b695e 1178 /** @defgroup SPI_LL_EF_DMA_Management DMA_Management
EricLew 0:80ee8f3b695e 1179 * @{
EricLew 0:80ee8f3b695e 1180 */
EricLew 0:80ee8f3b695e 1181
EricLew 0:80ee8f3b695e 1182 /**
EricLew 0:80ee8f3b695e 1183 * @brief Enable DMA Rx
EricLew 0:80ee8f3b695e 1184 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
EricLew 0:80ee8f3b695e 1185 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1186 * @retval None
EricLew 0:80ee8f3b695e 1187 */
EricLew 0:80ee8f3b695e 1188 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1189 {
EricLew 0:80ee8f3b695e 1190 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
EricLew 0:80ee8f3b695e 1191 }
EricLew 0:80ee8f3b695e 1192
EricLew 0:80ee8f3b695e 1193 /**
EricLew 0:80ee8f3b695e 1194 * @brief Disable DMA Rx
EricLew 0:80ee8f3b695e 1195 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
EricLew 0:80ee8f3b695e 1196 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1197 * @retval None
EricLew 0:80ee8f3b695e 1198 */
EricLew 0:80ee8f3b695e 1199 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1200 {
EricLew 0:80ee8f3b695e 1201 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
EricLew 0:80ee8f3b695e 1202 }
EricLew 0:80ee8f3b695e 1203
EricLew 0:80ee8f3b695e 1204 /**
EricLew 0:80ee8f3b695e 1205 * @brief Check if DMA Rx is enabled
EricLew 0:80ee8f3b695e 1206 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
EricLew 0:80ee8f3b695e 1207 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1208 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 1209 */
EricLew 0:80ee8f3b695e 1210 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1211 {
EricLew 0:80ee8f3b695e 1212 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
EricLew 0:80ee8f3b695e 1213 }
EricLew 0:80ee8f3b695e 1214
EricLew 0:80ee8f3b695e 1215 /**
EricLew 0:80ee8f3b695e 1216 * @brief Enable DMA Tx
EricLew 0:80ee8f3b695e 1217 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
EricLew 0:80ee8f3b695e 1218 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1219 * @retval None
EricLew 0:80ee8f3b695e 1220 */
EricLew 0:80ee8f3b695e 1221 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1222 {
EricLew 0:80ee8f3b695e 1223 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
EricLew 0:80ee8f3b695e 1224 }
EricLew 0:80ee8f3b695e 1225
EricLew 0:80ee8f3b695e 1226 /**
EricLew 0:80ee8f3b695e 1227 * @brief Disable DMA Tx
EricLew 0:80ee8f3b695e 1228 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
EricLew 0:80ee8f3b695e 1229 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1230 * @retval None
EricLew 0:80ee8f3b695e 1231 */
EricLew 0:80ee8f3b695e 1232 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1233 {
EricLew 0:80ee8f3b695e 1234 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
EricLew 0:80ee8f3b695e 1235 }
EricLew 0:80ee8f3b695e 1236
EricLew 0:80ee8f3b695e 1237 /**
EricLew 0:80ee8f3b695e 1238 * @brief Check if DMA Tx is enabled
EricLew 0:80ee8f3b695e 1239 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
EricLew 0:80ee8f3b695e 1240 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1241 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 1242 */
EricLew 0:80ee8f3b695e 1243 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1244 {
EricLew 0:80ee8f3b695e 1245 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
EricLew 0:80ee8f3b695e 1246 }
EricLew 0:80ee8f3b695e 1247
EricLew 0:80ee8f3b695e 1248 /**
EricLew 0:80ee8f3b695e 1249 * @brief Set parity of Last DMA reception
EricLew 0:80ee8f3b695e 1250 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
EricLew 0:80ee8f3b695e 1251 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1252 * @param Parity This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 1253 * @arg @ref LL_SPI_DMA_PARITY_ODD
EricLew 0:80ee8f3b695e 1254 * @arg @ref LL_SPI_DMA_PARITY_EVEN
EricLew 0:80ee8f3b695e 1255 * @retval None
EricLew 0:80ee8f3b695e 1256 */
EricLew 0:80ee8f3b695e 1257 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
EricLew 0:80ee8f3b695e 1258 {
EricLew 0:80ee8f3b695e 1259 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << POSITION_VAL(SPI_CR2_LDMARX)));
EricLew 0:80ee8f3b695e 1260 }
EricLew 0:80ee8f3b695e 1261
EricLew 0:80ee8f3b695e 1262 /**
EricLew 0:80ee8f3b695e 1263 * @brief Get parity configuration for Last DMA reception
EricLew 0:80ee8f3b695e 1264 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
EricLew 0:80ee8f3b695e 1265 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1266 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 1267 * @arg @ref LL_SPI_DMA_PARITY_ODD
EricLew 0:80ee8f3b695e 1268 * @arg @ref LL_SPI_DMA_PARITY_EVEN
EricLew 0:80ee8f3b695e 1269 */
EricLew 0:80ee8f3b695e 1270 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1271 {
EricLew 0:80ee8f3b695e 1272 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> POSITION_VAL(SPI_CR2_LDMARX));
EricLew 0:80ee8f3b695e 1273 }
EricLew 0:80ee8f3b695e 1274
EricLew 0:80ee8f3b695e 1275 /**
EricLew 0:80ee8f3b695e 1276 * @brief Set parity of Last DMA transmission
EricLew 0:80ee8f3b695e 1277 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
EricLew 0:80ee8f3b695e 1278 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1279 * @param Parity This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 1280 * @arg @ref LL_SPI_DMA_PARITY_ODD
EricLew 0:80ee8f3b695e 1281 * @arg @ref LL_SPI_DMA_PARITY_EVEN
EricLew 0:80ee8f3b695e 1282 * @retval None
EricLew 0:80ee8f3b695e 1283 */
EricLew 0:80ee8f3b695e 1284 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
EricLew 0:80ee8f3b695e 1285 {
EricLew 0:80ee8f3b695e 1286 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << POSITION_VAL(SPI_CR2_LDMATX)));
EricLew 0:80ee8f3b695e 1287 }
EricLew 0:80ee8f3b695e 1288
EricLew 0:80ee8f3b695e 1289 /**
EricLew 0:80ee8f3b695e 1290 * @brief Get parity configuration for Last DMA transmission
EricLew 0:80ee8f3b695e 1291 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
EricLew 0:80ee8f3b695e 1292 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1293 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 1294 * @arg @ref LL_SPI_DMA_PARITY_ODD
EricLew 0:80ee8f3b695e 1295 * @arg @ref LL_SPI_DMA_PARITY_EVEN
EricLew 0:80ee8f3b695e 1296 */
EricLew 0:80ee8f3b695e 1297 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1298 {
EricLew 0:80ee8f3b695e 1299 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> POSITION_VAL(SPI_CR2_LDMATX));
EricLew 0:80ee8f3b695e 1300 }
EricLew 0:80ee8f3b695e 1301
EricLew 0:80ee8f3b695e 1302 /**
EricLew 0:80ee8f3b695e 1303 * @brief Get the data register address used for DMA transfer
EricLew 0:80ee8f3b695e 1304 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr
EricLew 0:80ee8f3b695e 1305 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1306 * @retval Address of data register
EricLew 0:80ee8f3b695e 1307 */
EricLew 0:80ee8f3b695e 1308 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1309 {
EricLew 0:80ee8f3b695e 1310 return (uint32_t)&(SPIx->DR);
EricLew 0:80ee8f3b695e 1311 }
EricLew 0:80ee8f3b695e 1312
EricLew 0:80ee8f3b695e 1313 /**
EricLew 0:80ee8f3b695e 1314 * @}
EricLew 0:80ee8f3b695e 1315 */
EricLew 0:80ee8f3b695e 1316
EricLew 0:80ee8f3b695e 1317 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
EricLew 0:80ee8f3b695e 1318 * @{
EricLew 0:80ee8f3b695e 1319 */
EricLew 0:80ee8f3b695e 1320
EricLew 0:80ee8f3b695e 1321 /**
EricLew 0:80ee8f3b695e 1322 * @brief Read 8-Bits in the Data Register
EricLew 0:80ee8f3b695e 1323 * @rmtoll DR DR LL_SPI_ReceiveData8
EricLew 0:80ee8f3b695e 1324 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1325 * @retval RxData 0..0xFF
EricLew 0:80ee8f3b695e 1326 */
EricLew 0:80ee8f3b695e 1327 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1328 {
EricLew 0:80ee8f3b695e 1329 return (uint8_t)(READ_REG(SPIx->DR));
EricLew 0:80ee8f3b695e 1330 }
EricLew 0:80ee8f3b695e 1331
EricLew 0:80ee8f3b695e 1332 /**
EricLew 0:80ee8f3b695e 1333 * @brief Read 16-Bits in the Data Register
EricLew 0:80ee8f3b695e 1334 * @rmtoll DR DR LL_SPI_ReceiveData16
EricLew 0:80ee8f3b695e 1335 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1336 * @retval RxData 0..0xFFFF
EricLew 0:80ee8f3b695e 1337 */
EricLew 0:80ee8f3b695e 1338 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
EricLew 0:80ee8f3b695e 1339 {
EricLew 0:80ee8f3b695e 1340 return (uint16_t)(READ_REG(SPIx->DR));
EricLew 0:80ee8f3b695e 1341 }
EricLew 0:80ee8f3b695e 1342
EricLew 0:80ee8f3b695e 1343 /**
EricLew 0:80ee8f3b695e 1344 * @brief Write 8-Bits in the Data Register
EricLew 0:80ee8f3b695e 1345 * @rmtoll DR DR LL_SPI_TransmitData8
EricLew 0:80ee8f3b695e 1346 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1347 * @param TxData 0..0xFF
EricLew 0:80ee8f3b695e 1348 * @retval None
EricLew 0:80ee8f3b695e 1349 */
EricLew 0:80ee8f3b695e 1350 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
EricLew 0:80ee8f3b695e 1351 {
EricLew 0:80ee8f3b695e 1352 *((__IO uint8_t*)&SPIx->DR) = TxData;
EricLew 0:80ee8f3b695e 1353 }
EricLew 0:80ee8f3b695e 1354
EricLew 0:80ee8f3b695e 1355 /**
EricLew 0:80ee8f3b695e 1356 * @brief Write 16-Bits in the Data Register
EricLew 0:80ee8f3b695e 1357 * @rmtoll DR DR LL_SPI_TransmitData16
EricLew 0:80ee8f3b695e 1358 * @param SPIx SPI Instance
EricLew 0:80ee8f3b695e 1359 * @param TxData 0..0xFFFF
EricLew 0:80ee8f3b695e 1360 * @retval None
EricLew 0:80ee8f3b695e 1361 */
EricLew 0:80ee8f3b695e 1362 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
EricLew 0:80ee8f3b695e 1363 {
EricLew 0:80ee8f3b695e 1364 *((__IO uint16_t*)&SPIx->DR) = TxData;
EricLew 0:80ee8f3b695e 1365 }
EricLew 0:80ee8f3b695e 1366
EricLew 0:80ee8f3b695e 1367 /**
EricLew 0:80ee8f3b695e 1368 * @}
EricLew 0:80ee8f3b695e 1369 */
EricLew 0:80ee8f3b695e 1370
EricLew 0:80ee8f3b695e 1371 /**
EricLew 0:80ee8f3b695e 1372 * @}
EricLew 0:80ee8f3b695e 1373 */
EricLew 0:80ee8f3b695e 1374
EricLew 0:80ee8f3b695e 1375 /**
EricLew 0:80ee8f3b695e 1376 * @}
EricLew 0:80ee8f3b695e 1377 */
EricLew 0:80ee8f3b695e 1378
EricLew 0:80ee8f3b695e 1379 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */
EricLew 0:80ee8f3b695e 1380
EricLew 0:80ee8f3b695e 1381 /**
EricLew 0:80ee8f3b695e 1382 * @}
EricLew 0:80ee8f3b695e 1383 */
EricLew 0:80ee8f3b695e 1384
EricLew 0:80ee8f3b695e 1385 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 1386 }
EricLew 0:80ee8f3b695e 1387 #endif
EricLew 0:80ee8f3b695e 1388
EricLew 0:80ee8f3b695e 1389 #endif /* __STM32L4xx_LL_SPI_H */
EricLew 0:80ee8f3b695e 1390
EricLew 0:80ee8f3b695e 1391 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 1392