Senior Design: Sound Monitor / STM32L4xx_HAL_Driver

L4 HAL Drivers

Inc/stm32l4xx_ll_cortex.h@0:80ee8f3b695e, 2015-11-02 (annotated)

Committer:
EricLew
Date:
Mon Nov 02 19:37:23 2015 +0000
Revision:
0:80ee8f3b695e
Errors are with definitions of LCD and QSPI functions. I believe all .h and .c files are  uploaded, but there may need to be certain functions called.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:80ee8f3b695e 1 /**
EricLew 0:80ee8f3b695e 2 ******************************************************************************
EricLew 0:80ee8f3b695e 3 * @file stm32l4xx_ll_cortex.h
EricLew 0:80ee8f3b695e 4 * @author MCD Application Team
EricLew 0:80ee8f3b695e 5 * @version V1.1.0
EricLew 0:80ee8f3b695e 6 * @date 16-September-2015
EricLew 0:80ee8f3b695e 7 * @brief Header file of CORTEX LL module.
EricLew 0:80ee8f3b695e 8 @verbatim
EricLew 0:80ee8f3b695e 9 ==============================================================================
EricLew 0:80ee8f3b695e 10 ##### How to use this driver #####
EricLew 0:80ee8f3b695e 11 ==============================================================================
EricLew 0:80ee8f3b695e 12 [..]
EricLew 0:80ee8f3b695e 13 The LL CORTEX driver contains a set of generic APIs that can be
EricLew 0:80ee8f3b695e 14 used by user:
EricLew 0:80ee8f3b695e 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
EricLew 0:80ee8f3b695e 16 functions
EricLew 0:80ee8f3b695e 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
EricLew 0:80ee8f3b695e 18 (+) MPU API to configure and enable regions
EricLew 0:80ee8f3b695e 19 (+) API to access to MCU info (CPUID register)
EricLew 0:80ee8f3b695e 20 (+) API to enable fault handler (SHCSR accesses)
EricLew 0:80ee8f3b695e 21
EricLew 0:80ee8f3b695e 22 @endverbatim
EricLew 0:80ee8f3b695e 23 ******************************************************************************
EricLew 0:80ee8f3b695e 24 * @attention
EricLew 0:80ee8f3b695e 25 *
EricLew 0:80ee8f3b695e 26 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:80ee8f3b695e 27 *
EricLew 0:80ee8f3b695e 28 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:80ee8f3b695e 29 * are permitted provided that the following conditions are met:
EricLew 0:80ee8f3b695e 30 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:80ee8f3b695e 31 * this list of conditions and the following disclaimer.
EricLew 0:80ee8f3b695e 32 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:80ee8f3b695e 33 * this list of conditions and the following disclaimer in the documentation
EricLew 0:80ee8f3b695e 34 * and/or other materials provided with the distribution.
EricLew 0:80ee8f3b695e 35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:80ee8f3b695e 36 * may be used to endorse or promote products derived from this software
EricLew 0:80ee8f3b695e 37 * without specific prior written permission.
EricLew 0:80ee8f3b695e 38 *
EricLew 0:80ee8f3b695e 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:80ee8f3b695e 40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:80ee8f3b695e 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:80ee8f3b695e 42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:80ee8f3b695e 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:80ee8f3b695e 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:80ee8f3b695e 45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:80ee8f3b695e 46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:80ee8f3b695e 47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:80ee8f3b695e 48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:80ee8f3b695e 49 *
EricLew 0:80ee8f3b695e 50 ******************************************************************************
EricLew 0:80ee8f3b695e 51 */
EricLew 0:80ee8f3b695e 52
EricLew 0:80ee8f3b695e 53 /* Define to prevent recursive inclusion -------------------------------------*/
EricLew 0:80ee8f3b695e 54 #ifndef __STM32L4xx_LL_CORTEX_H
EricLew 0:80ee8f3b695e 55 #define __STM32L4xx_LL_CORTEX_H
EricLew 0:80ee8f3b695e 56
EricLew 0:80ee8f3b695e 57 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 58 extern "C" {
EricLew 0:80ee8f3b695e 59 #endif
EricLew 0:80ee8f3b695e 60
EricLew 0:80ee8f3b695e 61 /* Includes ------------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 62 #include "stm32l4xx.h"
EricLew 0:80ee8f3b695e 63
EricLew 0:80ee8f3b695e 64 /** @addtogroup STM32L4xx_LL_Driver
EricLew 0:80ee8f3b695e 65 * @{
EricLew 0:80ee8f3b695e 66 */
EricLew 0:80ee8f3b695e 67
EricLew 0:80ee8f3b695e 68 /** @defgroup CORTEX_LL CORTEX
EricLew 0:80ee8f3b695e 69 * @{
EricLew 0:80ee8f3b695e 70 */
EricLew 0:80ee8f3b695e 71
EricLew 0:80ee8f3b695e 72 /* Private types -------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 73 /* Private variables ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 74
EricLew 0:80ee8f3b695e 75 /* Private constants ---------------------------------------------------------*/
EricLew 0:80ee8f3b695e 76
EricLew 0:80ee8f3b695e 77 /* Private macros ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 78
EricLew 0:80ee8f3b695e 79 /* Exported types ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 80 /* Exported constants --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 81 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
EricLew 0:80ee8f3b695e 82 * @{
EricLew 0:80ee8f3b695e 83 */
EricLew 0:80ee8f3b695e 84
EricLew 0:80ee8f3b695e 85 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK CLK SOURCE
EricLew 0:80ee8f3b695e 86 * @{
EricLew 0:80ee8f3b695e 87 */
EricLew 0:80ee8f3b695e 88 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) /* AHB clock divided by 8 selected as SysTick clock source.*/
EricLew 0:80ee8f3b695e 89 #define LL_SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) /* AHB clock selected as SysTick clock source. */
EricLew 0:80ee8f3b695e 90 /**
EricLew 0:80ee8f3b695e 91 * @}
EricLew 0:80ee8f3b695e 92 */
EricLew 0:80ee8f3b695e 93
EricLew 0:80ee8f3b695e 94 /** @defgroup CORTEX_LL_EC_FAULT HANDLER FAULT
EricLew 0:80ee8f3b695e 95 * @{
EricLew 0:80ee8f3b695e 96 */
EricLew 0:80ee8f3b695e 97 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /* Usage fault */
EricLew 0:80ee8f3b695e 98 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /* Bus fault */
EricLew 0:80ee8f3b695e 99 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /* Memory management fault */
EricLew 0:80ee8f3b695e 100 /**
EricLew 0:80ee8f3b695e 101 * @}
EricLew 0:80ee8f3b695e 102 */
EricLew 0:80ee8f3b695e 103
EricLew 0:80ee8f3b695e 104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU CONTROL
EricLew 0:80ee8f3b695e 105 * @{
EricLew 0:80ee8f3b695e 106 */
EricLew 0:80ee8f3b695e 107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) /*!< Disable NMI and privileged SW access */
EricLew 0:80ee8f3b695e 108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
EricLew 0:80ee8f3b695e 109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
EricLew 0:80ee8f3b695e 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
EricLew 0:80ee8f3b695e 111 /**
EricLew 0:80ee8f3b695e 112 * @}
EricLew 0:80ee8f3b695e 113 */
EricLew 0:80ee8f3b695e 114
EricLew 0:80ee8f3b695e 115 /** @defgroup CORTEX_LL_EC_REGION MPU REGION NUMBER
EricLew 0:80ee8f3b695e 116 * @{
EricLew 0:80ee8f3b695e 117 */
EricLew 0:80ee8f3b695e 118 #define LL_MPU_REGION_NUMBER0 ((uint32_t)0x00) /*!< REGION Number 0 */
EricLew 0:80ee8f3b695e 119 #define LL_MPU_REGION_NUMBER1 ((uint32_t)0x01) /*!< REGION Number 1 */
EricLew 0:80ee8f3b695e 120 #define LL_MPU_REGION_NUMBER2 ((uint32_t)0x02) /*!< REGION Number 2 */
EricLew 0:80ee8f3b695e 121 #define LL_MPU_REGION_NUMBER3 ((uint32_t)0x03) /*!< REGION Number 3 */
EricLew 0:80ee8f3b695e 122 #define LL_MPU_REGION_NUMBER4 ((uint32_t)0x04) /*!< REGION Number 4 */
EricLew 0:80ee8f3b695e 123 #define LL_MPU_REGION_NUMBER5 ((uint32_t)0x05) /*!< REGION Number 5 */
EricLew 0:80ee8f3b695e 124 #define LL_MPU_REGION_NUMBER6 ((uint32_t)0x06) /*!< REGION Number 6 */
EricLew 0:80ee8f3b695e 125 #define LL_MPU_REGION_NUMBER7 ((uint32_t)0x07) /*!< REGION Number 7 */
EricLew 0:80ee8f3b695e 126 /**
EricLew 0:80ee8f3b695e 127 * @}
EricLew 0:80ee8f3b695e 128 */
EricLew 0:80ee8f3b695e 129
EricLew 0:80ee8f3b695e 130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU REGION SIZE
EricLew 0:80ee8f3b695e 131 * @{
EricLew 0:80ee8f3b695e 132 */
EricLew 0:80ee8f3b695e 133 #define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04 << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
EricLew 0:80ee8f3b695e 134 #define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05 << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
EricLew 0:80ee8f3b695e 135 #define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06 << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
EricLew 0:80ee8f3b695e 136 #define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07 << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
EricLew 0:80ee8f3b695e 137 #define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08 << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
EricLew 0:80ee8f3b695e 138 #define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09 << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 139 #define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0A << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 140 #define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0B << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 141 #define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0C << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 142 #define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0D << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 143 #define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0E << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 144 #define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0F << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 145 #define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10 << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 146 #define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11 << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 147 #define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12 << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 148 #define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13 << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 149 #define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14 << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 150 #define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15 << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 151 #define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16 << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 152 #define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17 << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 153 #define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18 << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 154 #define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19 << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 155 #define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1A << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 156 #define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1B << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 157 #define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1C << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 158 #define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1D << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 159 #define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1E << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 160 #define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1F << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
EricLew 0:80ee8f3b695e 161 /**
EricLew 0:80ee8f3b695e 162 * @}
EricLew 0:80ee8f3b695e 163 */
EricLew 0:80ee8f3b695e 164
EricLew 0:80ee8f3b695e 165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU REGION PRIVILEDGES
EricLew 0:80ee8f3b695e 166 * @{
EricLew 0:80ee8f3b695e 167 */
EricLew 0:80ee8f3b695e 168 #define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00 << MPU_RASR_AP_Pos)) /*!< No access*/
EricLew 0:80ee8f3b695e 169 #define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01 << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
EricLew 0:80ee8f3b695e 170 #define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02 << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
EricLew 0:80ee8f3b695e 171 #define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03 << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
EricLew 0:80ee8f3b695e 172 #define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05 << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
EricLew 0:80ee8f3b695e 173 #define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06 << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
EricLew 0:80ee8f3b695e 174 /**
EricLew 0:80ee8f3b695e 175 * @}
EricLew 0:80ee8f3b695e 176 */
EricLew 0:80ee8f3b695e 177
EricLew 0:80ee8f3b695e 178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX LEVEL
EricLew 0:80ee8f3b695e 179 * @{
EricLew 0:80ee8f3b695e 180 */
EricLew 0:80ee8f3b695e 181 #define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00 << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
EricLew 0:80ee8f3b695e 182 #define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01 << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
EricLew 0:80ee8f3b695e 183 #define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02 << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
EricLew 0:80ee8f3b695e 184 #define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04 << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
EricLew 0:80ee8f3b695e 185 /**
EricLew 0:80ee8f3b695e 186 * @}
EricLew 0:80ee8f3b695e 187 */
EricLew 0:80ee8f3b695e 188
EricLew 0:80ee8f3b695e 189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU INSTRUCTION ACCESS
EricLew 0:80ee8f3b695e 190 * @{
EricLew 0:80ee8f3b695e 191 */
EricLew 0:80ee8f3b695e 192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE ((uint32_t)0x00) /*!< Instruction fetches enabled */
EricLew 0:80ee8f3b695e 193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
EricLew 0:80ee8f3b695e 194 /**
EricLew 0:80ee8f3b695e 195 * @}
EricLew 0:80ee8f3b695e 196 */
EricLew 0:80ee8f3b695e 197
EricLew 0:80ee8f3b695e 198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU SHAREABLE ACCESS
EricLew 0:80ee8f3b695e 199 * @{
EricLew 0:80ee8f3b695e 200 */
EricLew 0:80ee8f3b695e 201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
EricLew 0:80ee8f3b695e 202 #define LL_MPU_ACCESS_NOT_SHAREABLE ((uint32_t)0x00) /*!< Not Shareable memory attribute */
EricLew 0:80ee8f3b695e 203 /**
EricLew 0:80ee8f3b695e 204 * @}
EricLew 0:80ee8f3b695e 205 */
EricLew 0:80ee8f3b695e 206
EricLew 0:80ee8f3b695e 207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU CACHEABLE ACCESS
EricLew 0:80ee8f3b695e 208 * @{
EricLew 0:80ee8f3b695e 209 */
EricLew 0:80ee8f3b695e 210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
EricLew 0:80ee8f3b695e 211 #define LL_MPU_ACCESS_NOT_CACHEABLE ((uint32_t)0x00) /*!< Not Cacheable memory attribute */
EricLew 0:80ee8f3b695e 212 /**
EricLew 0:80ee8f3b695e 213 * @}
EricLew 0:80ee8f3b695e 214 */
EricLew 0:80ee8f3b695e 215
EricLew 0:80ee8f3b695e 216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU BUFFERABLE ACCESS
EricLew 0:80ee8f3b695e 217 * @{
EricLew 0:80ee8f3b695e 218 */
EricLew 0:80ee8f3b695e 219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
EricLew 0:80ee8f3b695e 220 #define LL_MPU_ACCESS_NOT_BUFFERABLE ((uint32_t)0x00) /*!< Not Bufferable memory attribute */
EricLew 0:80ee8f3b695e 221 /**
EricLew 0:80ee8f3b695e 222 * @}
EricLew 0:80ee8f3b695e 223 */
EricLew 0:80ee8f3b695e 224
EricLew 0:80ee8f3b695e 225 /**
EricLew 0:80ee8f3b695e 226 * @}
EricLew 0:80ee8f3b695e 227 */
EricLew 0:80ee8f3b695e 228
EricLew 0:80ee8f3b695e 229 /* Exported macro ------------------------------------------------------------*/
EricLew 0:80ee8f3b695e 230
EricLew 0:80ee8f3b695e 231 /* Exported functions --------------------------------------------------------*/
EricLew 0:80ee8f3b695e 232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
EricLew 0:80ee8f3b695e 233 * @{
EricLew 0:80ee8f3b695e 234 */
EricLew 0:80ee8f3b695e 235
EricLew 0:80ee8f3b695e 236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
EricLew 0:80ee8f3b695e 237 * @{
EricLew 0:80ee8f3b695e 238 */
EricLew 0:80ee8f3b695e 239
EricLew 0:80ee8f3b695e 240 /**
EricLew 0:80ee8f3b695e 241 * @brief This function checks if the Systick counter flag is active or not.
EricLew 0:80ee8f3b695e 242 * @note It can be used in timeout function on application side.
EricLew 0:80ee8f3b695e 243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
EricLew 0:80ee8f3b695e 244 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 245 */
EricLew 0:80ee8f3b695e 246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
EricLew 0:80ee8f3b695e 247 {
EricLew 0:80ee8f3b695e 248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
EricLew 0:80ee8f3b695e 249 }
EricLew 0:80ee8f3b695e 250
EricLew 0:80ee8f3b695e 251 /**
EricLew 0:80ee8f3b695e 252 * @brief Configures the SysTick clock source
EricLew 0:80ee8f3b695e 253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
EricLew 0:80ee8f3b695e 254 * @param Source This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
EricLew 0:80ee8f3b695e 256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
EricLew 0:80ee8f3b695e 257 * @retval None
EricLew 0:80ee8f3b695e 258 */
EricLew 0:80ee8f3b695e 259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
EricLew 0:80ee8f3b695e 260 {
EricLew 0:80ee8f3b695e 261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
EricLew 0:80ee8f3b695e 262 {
EricLew 0:80ee8f3b695e 263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
EricLew 0:80ee8f3b695e 264 }
EricLew 0:80ee8f3b695e 265 else
EricLew 0:80ee8f3b695e 266 {
EricLew 0:80ee8f3b695e 267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
EricLew 0:80ee8f3b695e 268 }
EricLew 0:80ee8f3b695e 269 }
EricLew 0:80ee8f3b695e 270
EricLew 0:80ee8f3b695e 271 /**
EricLew 0:80ee8f3b695e 272 * @brief Get the SysTick clock source
EricLew 0:80ee8f3b695e 273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
EricLew 0:80ee8f3b695e 274 * @retval Returned value can be one of the following values:
EricLew 0:80ee8f3b695e 275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
EricLew 0:80ee8f3b695e 276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
EricLew 0:80ee8f3b695e 277 */
EricLew 0:80ee8f3b695e 278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
EricLew 0:80ee8f3b695e 279 {
EricLew 0:80ee8f3b695e 280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
EricLew 0:80ee8f3b695e 281 }
EricLew 0:80ee8f3b695e 282
EricLew 0:80ee8f3b695e 283 /**
EricLew 0:80ee8f3b695e 284 * @brief Enable SysTick exception request
EricLew 0:80ee8f3b695e 285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
EricLew 0:80ee8f3b695e 286 * @retval None
EricLew 0:80ee8f3b695e 287 */
EricLew 0:80ee8f3b695e 288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
EricLew 0:80ee8f3b695e 289 {
EricLew 0:80ee8f3b695e 290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
EricLew 0:80ee8f3b695e 291 }
EricLew 0:80ee8f3b695e 292
EricLew 0:80ee8f3b695e 293 /**
EricLew 0:80ee8f3b695e 294 * @brief Disable SysTick exception request
EricLew 0:80ee8f3b695e 295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
EricLew 0:80ee8f3b695e 296 * @retval None
EricLew 0:80ee8f3b695e 297 */
EricLew 0:80ee8f3b695e 298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
EricLew 0:80ee8f3b695e 299 {
EricLew 0:80ee8f3b695e 300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
EricLew 0:80ee8f3b695e 301 }
EricLew 0:80ee8f3b695e 302
EricLew 0:80ee8f3b695e 303 /**
EricLew 0:80ee8f3b695e 304 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
EricLew 0:80ee8f3b695e 305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
EricLew 0:80ee8f3b695e 306 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 307 */
EricLew 0:80ee8f3b695e 308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
EricLew 0:80ee8f3b695e 309 {
EricLew 0:80ee8f3b695e 310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
EricLew 0:80ee8f3b695e 311 }
EricLew 0:80ee8f3b695e 312
EricLew 0:80ee8f3b695e 313 /**
EricLew 0:80ee8f3b695e 314 * @}
EricLew 0:80ee8f3b695e 315 */
EricLew 0:80ee8f3b695e 316
EricLew 0:80ee8f3b695e 317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
EricLew 0:80ee8f3b695e 318 * @{
EricLew 0:80ee8f3b695e 319 */
EricLew 0:80ee8f3b695e 320
EricLew 0:80ee8f3b695e 321 /**
EricLew 0:80ee8f3b695e 322 * @brief Processor uses sleep as its low power mode
EricLew 0:80ee8f3b695e 323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
EricLew 0:80ee8f3b695e 324 * @retval None
EricLew 0:80ee8f3b695e 325 */
EricLew 0:80ee8f3b695e 326 __STATIC_INLINE void LL_LPM_EnableSleep(void)
EricLew 0:80ee8f3b695e 327 {
EricLew 0:80ee8f3b695e 328 /* Clear SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 330 }
EricLew 0:80ee8f3b695e 331
EricLew 0:80ee8f3b695e 332 /**
EricLew 0:80ee8f3b695e 333 * @brief Processor uses deep sleep as its low power mode
EricLew 0:80ee8f3b695e 334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
EricLew 0:80ee8f3b695e 335 * @retval None
EricLew 0:80ee8f3b695e 336 */
EricLew 0:80ee8f3b695e 337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
EricLew 0:80ee8f3b695e 338 {
EricLew 0:80ee8f3b695e 339 /* Set SLEEPDEEP bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
EricLew 0:80ee8f3b695e 341 }
EricLew 0:80ee8f3b695e 342
EricLew 0:80ee8f3b695e 343 /**
EricLew 0:80ee8f3b695e 344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
EricLew 0:80ee8f3b695e 345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
EricLew 0:80ee8f3b695e 346 * empty main application.
EricLew 0:80ee8f3b695e 347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
EricLew 0:80ee8f3b695e 348 * @retval None
EricLew 0:80ee8f3b695e 349 */
EricLew 0:80ee8f3b695e 350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
EricLew 0:80ee8f3b695e 351 {
EricLew 0:80ee8f3b695e 352 /* Set SLEEPONEXIT bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
EricLew 0:80ee8f3b695e 354 }
EricLew 0:80ee8f3b695e 355
EricLew 0:80ee8f3b695e 356 /**
EricLew 0:80ee8f3b695e 357 * @brief Do not sleep when returning to Thread mode.
EricLew 0:80ee8f3b695e 358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
EricLew 0:80ee8f3b695e 359 * @retval None
EricLew 0:80ee8f3b695e 360 */
EricLew 0:80ee8f3b695e 361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
EricLew 0:80ee8f3b695e 362 {
EricLew 0:80ee8f3b695e 363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
EricLew 0:80ee8f3b695e 365 }
EricLew 0:80ee8f3b695e 366
EricLew 0:80ee8f3b695e 367 /**
EricLew 0:80ee8f3b695e 368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
EricLew 0:80ee8f3b695e 369 * processor.
EricLew 0:80ee8f3b695e 370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
EricLew 0:80ee8f3b695e 371 * @retval None
EricLew 0:80ee8f3b695e 372 */
EricLew 0:80ee8f3b695e 373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
EricLew 0:80ee8f3b695e 374 {
EricLew 0:80ee8f3b695e 375 /* Set SEVEONPEND bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
EricLew 0:80ee8f3b695e 377 }
EricLew 0:80ee8f3b695e 378
EricLew 0:80ee8f3b695e 379 /**
EricLew 0:80ee8f3b695e 380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
EricLew 0:80ee8f3b695e 381 * excluded
EricLew 0:80ee8f3b695e 382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
EricLew 0:80ee8f3b695e 383 * @retval None
EricLew 0:80ee8f3b695e 384 */
EricLew 0:80ee8f3b695e 385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
EricLew 0:80ee8f3b695e 386 {
EricLew 0:80ee8f3b695e 387 /* Clear SEVEONPEND bit of Cortex System Control Register */
EricLew 0:80ee8f3b695e 388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
EricLew 0:80ee8f3b695e 389 }
EricLew 0:80ee8f3b695e 390
EricLew 0:80ee8f3b695e 391 /**
EricLew 0:80ee8f3b695e 392 * @}
EricLew 0:80ee8f3b695e 393 */
EricLew 0:80ee8f3b695e 394
EricLew 0:80ee8f3b695e 395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
EricLew 0:80ee8f3b695e 396 * @{
EricLew 0:80ee8f3b695e 397 */
EricLew 0:80ee8f3b695e 398
EricLew 0:80ee8f3b695e 399 /**
EricLew 0:80ee8f3b695e 400 * @brief Enable a fault in System handler control register (SHCSR)
EricLew 0:80ee8f3b695e 401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
EricLew 0:80ee8f3b695e 402 * @param Fault This parameter can be a combination of the following values:
EricLew 0:80ee8f3b695e 403 * @arg @ref LL_HANDLER_FAULT_USG
EricLew 0:80ee8f3b695e 404 * @arg @ref LL_HANDLER_FAULT_BUS
EricLew 0:80ee8f3b695e 405 * @arg @ref LL_HANDLER_FAULT_MEM
EricLew 0:80ee8f3b695e 406 * @retval None
EricLew 0:80ee8f3b695e 407 */
EricLew 0:80ee8f3b695e 408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
EricLew 0:80ee8f3b695e 409 {
EricLew 0:80ee8f3b695e 410 /* Enable the system handler fault */
EricLew 0:80ee8f3b695e 411 SET_BIT(SCB->SHCSR, Fault);
EricLew 0:80ee8f3b695e 412 }
EricLew 0:80ee8f3b695e 413
EricLew 0:80ee8f3b695e 414 /**
EricLew 0:80ee8f3b695e 415 * @brief Disable a fault in System handler control register (SHCSR)
EricLew 0:80ee8f3b695e 416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
EricLew 0:80ee8f3b695e 417 * @param Fault This parameter can be a combination of the following values:
EricLew 0:80ee8f3b695e 418 * @arg @ref LL_HANDLER_FAULT_USG
EricLew 0:80ee8f3b695e 419 * @arg @ref LL_HANDLER_FAULT_BUS
EricLew 0:80ee8f3b695e 420 * @arg @ref LL_HANDLER_FAULT_MEM
EricLew 0:80ee8f3b695e 421 * @retval None
EricLew 0:80ee8f3b695e 422 */
EricLew 0:80ee8f3b695e 423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
EricLew 0:80ee8f3b695e 424 {
EricLew 0:80ee8f3b695e 425 /* Disable the system handler fault */
EricLew 0:80ee8f3b695e 426 CLEAR_BIT(SCB->SHCSR, Fault);
EricLew 0:80ee8f3b695e 427 }
EricLew 0:80ee8f3b695e 428
EricLew 0:80ee8f3b695e 429 /**
EricLew 0:80ee8f3b695e 430 * @}
EricLew 0:80ee8f3b695e 431 */
EricLew 0:80ee8f3b695e 432
EricLew 0:80ee8f3b695e 433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
EricLew 0:80ee8f3b695e 434 * @{
EricLew 0:80ee8f3b695e 435 */
EricLew 0:80ee8f3b695e 436
EricLew 0:80ee8f3b695e 437 /**
EricLew 0:80ee8f3b695e 438 * @brief Get Implementer code
EricLew 0:80ee8f3b695e 439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
EricLew 0:80ee8f3b695e 440 * @retval Value should be equal to 0x41 for ARM
EricLew 0:80ee8f3b695e 441 */
EricLew 0:80ee8f3b695e 442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
EricLew 0:80ee8f3b695e 443 {
EricLew 0:80ee8f3b695e 444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
EricLew 0:80ee8f3b695e 445 }
EricLew 0:80ee8f3b695e 446
EricLew 0:80ee8f3b695e 447 /**
EricLew 0:80ee8f3b695e 448 * @brief Get Variant number (The r value in the rnpnproduct revision identifier)
EricLew 0:80ee8f3b695e 449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
EricLew 0:80ee8f3b695e 450 * @retval Value between 0 and 255 (0x0: revision 0)
EricLew 0:80ee8f3b695e 451 */
EricLew 0:80ee8f3b695e 452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
EricLew 0:80ee8f3b695e 453 {
EricLew 0:80ee8f3b695e 454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
EricLew 0:80ee8f3b695e 455 }
EricLew 0:80ee8f3b695e 456
EricLew 0:80ee8f3b695e 457 /**
EricLew 0:80ee8f3b695e 458 * @brief Get Constant number (architecture)
EricLew 0:80ee8f3b695e 459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
EricLew 0:80ee8f3b695e 460 * @retval Reads as 0xF
EricLew 0:80ee8f3b695e 461 */
EricLew 0:80ee8f3b695e 462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
EricLew 0:80ee8f3b695e 463 {
EricLew 0:80ee8f3b695e 464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
EricLew 0:80ee8f3b695e 465 }
EricLew 0:80ee8f3b695e 466
EricLew 0:80ee8f3b695e 467 /**
EricLew 0:80ee8f3b695e 468 * @brief Get Constant number (architecture)
EricLew 0:80ee8f3b695e 469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
EricLew 0:80ee8f3b695e 470 * @retval Value should be equal to 0xC24 for Cortex-M4
EricLew 0:80ee8f3b695e 471 */
EricLew 0:80ee8f3b695e 472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
EricLew 0:80ee8f3b695e 473 {
EricLew 0:80ee8f3b695e 474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
EricLew 0:80ee8f3b695e 475 }
EricLew 0:80ee8f3b695e 476
EricLew 0:80ee8f3b695e 477 /**
EricLew 0:80ee8f3b695e 478 * @brief Get Revision number (The p value in the rnpnproduct revision identifier, indicates patch release)
EricLew 0:80ee8f3b695e 479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
EricLew 0:80ee8f3b695e 480 * @retval Value between 0 and 255 (0x1: patch 1)
EricLew 0:80ee8f3b695e 481 */
EricLew 0:80ee8f3b695e 482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
EricLew 0:80ee8f3b695e 483 {
EricLew 0:80ee8f3b695e 484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
EricLew 0:80ee8f3b695e 485 }
EricLew 0:80ee8f3b695e 486
EricLew 0:80ee8f3b695e 487 /**
EricLew 0:80ee8f3b695e 488 * @}
EricLew 0:80ee8f3b695e 489 */
EricLew 0:80ee8f3b695e 490
EricLew 0:80ee8f3b695e 491 /** @defgroup CORTEX_LL_EF_MPU MPU
EricLew 0:80ee8f3b695e 492 * @{
EricLew 0:80ee8f3b695e 493 */
EricLew 0:80ee8f3b695e 494
EricLew 0:80ee8f3b695e 495 /**
EricLew 0:80ee8f3b695e 496 * @brief Enable MPU with input options
EricLew 0:80ee8f3b695e 497 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
EricLew 0:80ee8f3b695e 498 * @param Options This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 499 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
EricLew 0:80ee8f3b695e 500 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
EricLew 0:80ee8f3b695e 501 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
EricLew 0:80ee8f3b695e 502 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
EricLew 0:80ee8f3b695e 503 * @retval None
EricLew 0:80ee8f3b695e 504 */
EricLew 0:80ee8f3b695e 505 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
EricLew 0:80ee8f3b695e 506 {
EricLew 0:80ee8f3b695e 507 /* Enable the MPU*/
EricLew 0:80ee8f3b695e 508 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
EricLew 0:80ee8f3b695e 509 /* Ensure MPU settings take effects */
EricLew 0:80ee8f3b695e 510 __DSB();
EricLew 0:80ee8f3b695e 511 /* Sequence instruction fetches using update settings */
EricLew 0:80ee8f3b695e 512 __ISB();
EricLew 0:80ee8f3b695e 513 }
EricLew 0:80ee8f3b695e 514
EricLew 0:80ee8f3b695e 515 /**
EricLew 0:80ee8f3b695e 516 * @brief Disable MPU
EricLew 0:80ee8f3b695e 517 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
EricLew 0:80ee8f3b695e 518 * @retval None
EricLew 0:80ee8f3b695e 519 */
EricLew 0:80ee8f3b695e 520 __STATIC_INLINE void LL_MPU_Disable(void)
EricLew 0:80ee8f3b695e 521 {
EricLew 0:80ee8f3b695e 522 /* Make sure outstanding transfers are done */
EricLew 0:80ee8f3b695e 523 __DMB();
EricLew 0:80ee8f3b695e 524 /* Disable MPU*/
EricLew 0:80ee8f3b695e 525 WRITE_REG(MPU->CTRL, 0);
EricLew 0:80ee8f3b695e 526 }
EricLew 0:80ee8f3b695e 527
EricLew 0:80ee8f3b695e 528 /**
EricLew 0:80ee8f3b695e 529 * @brief Check if MPU is enabled or not
EricLew 0:80ee8f3b695e 530 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
EricLew 0:80ee8f3b695e 531 * @retval State of bit (1 or 0).
EricLew 0:80ee8f3b695e 532 */
EricLew 0:80ee8f3b695e 533 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
EricLew 0:80ee8f3b695e 534 {
EricLew 0:80ee8f3b695e 535 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
EricLew 0:80ee8f3b695e 536 }
EricLew 0:80ee8f3b695e 537
EricLew 0:80ee8f3b695e 538 /**
EricLew 0:80ee8f3b695e 539 * @brief Enable a MPU region
EricLew 0:80ee8f3b695e 540 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
EricLew 0:80ee8f3b695e 541 * @param Region This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 542 * @arg @ref LL_MPU_REGION_NUMBER0
EricLew 0:80ee8f3b695e 543 * @arg @ref LL_MPU_REGION_NUMBER1
EricLew 0:80ee8f3b695e 544 * @arg @ref LL_MPU_REGION_NUMBER2
EricLew 0:80ee8f3b695e 545 * @arg @ref LL_MPU_REGION_NUMBER3
EricLew 0:80ee8f3b695e 546 * @arg @ref LL_MPU_REGION_NUMBER4
EricLew 0:80ee8f3b695e 547 * @arg @ref LL_MPU_REGION_NUMBER5
EricLew 0:80ee8f3b695e 548 * @arg @ref LL_MPU_REGION_NUMBER6
EricLew 0:80ee8f3b695e 549 * @arg @ref LL_MPU_REGION_NUMBER7
EricLew 0:80ee8f3b695e 550 * @retval None
EricLew 0:80ee8f3b695e 551 */
EricLew 0:80ee8f3b695e 552 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
EricLew 0:80ee8f3b695e 553 {
EricLew 0:80ee8f3b695e 554 /* Set Region number */
EricLew 0:80ee8f3b695e 555 WRITE_REG(MPU->RNR, Region);
EricLew 0:80ee8f3b695e 556 /* Enable the MPU region */
EricLew 0:80ee8f3b695e 557 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
EricLew 0:80ee8f3b695e 558 }
EricLew 0:80ee8f3b695e 559
EricLew 0:80ee8f3b695e 560 /**
EricLew 0:80ee8f3b695e 561 * @brief Configure and enable a region
EricLew 0:80ee8f3b695e 562 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 563 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 564 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 565 * MPU_RASR XN LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 566 * MPU_RASR AP LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 567 * MPU_RASR S LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 568 * MPU_RASR C LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 569 * MPU_RASR B LL_MPU_ConfigRegion\n
EricLew 0:80ee8f3b695e 570 * MPU_RASR SIZE LL_MPU_ConfigRegion
EricLew 0:80ee8f3b695e 571 * @param Region This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 572 * @arg @ref LL_MPU_REGION_NUMBER0
EricLew 0:80ee8f3b695e 573 * @arg @ref LL_MPU_REGION_NUMBER1
EricLew 0:80ee8f3b695e 574 * @arg @ref LL_MPU_REGION_NUMBER2
EricLew 0:80ee8f3b695e 575 * @arg @ref LL_MPU_REGION_NUMBER3
EricLew 0:80ee8f3b695e 576 * @arg @ref LL_MPU_REGION_NUMBER4
EricLew 0:80ee8f3b695e 577 * @arg @ref LL_MPU_REGION_NUMBER5
EricLew 0:80ee8f3b695e 578 * @arg @ref LL_MPU_REGION_NUMBER6
EricLew 0:80ee8f3b695e 579 * @arg @ref LL_MPU_REGION_NUMBER7
EricLew 0:80ee8f3b695e 580 * @param Address Value of region base address
EricLew 0:80ee8f3b695e 581 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
EricLew 0:80ee8f3b695e 582 * @param Attributes This parameter can be a combination of the following values:
EricLew 0:80ee8f3b695e 583 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
EricLew 0:80ee8f3b695e 584 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
EricLew 0:80ee8f3b695e 585 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
EricLew 0:80ee8f3b695e 586 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
EricLew 0:80ee8f3b695e 587 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
EricLew 0:80ee8f3b695e 588 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
EricLew 0:80ee8f3b695e 589 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
EricLew 0:80ee8f3b695e 590 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
EricLew 0:80ee8f3b695e 591 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
EricLew 0:80ee8f3b695e 592 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
EricLew 0:80ee8f3b695e 593 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
EricLew 0:80ee8f3b695e 594 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
EricLew 0:80ee8f3b695e 595 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
EricLew 0:80ee8f3b695e 596 * @retval None
EricLew 0:80ee8f3b695e 597 */
EricLew 0:80ee8f3b695e 598 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
EricLew 0:80ee8f3b695e 599 {
EricLew 0:80ee8f3b695e 600 /* Set Region number */
EricLew 0:80ee8f3b695e 601 WRITE_REG(MPU->RNR, Region);
EricLew 0:80ee8f3b695e 602 /* Set base address */
EricLew 0:80ee8f3b695e 603 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0));
EricLew 0:80ee8f3b695e 604 /* Configure MPU */
EricLew 0:80ee8f3b695e 605 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
EricLew 0:80ee8f3b695e 606 }
EricLew 0:80ee8f3b695e 607
EricLew 0:80ee8f3b695e 608 /**
EricLew 0:80ee8f3b695e 609 * @brief Disable a region
EricLew 0:80ee8f3b695e 610 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
EricLew 0:80ee8f3b695e 611 * MPU_RASR ENABLE LL_MPU_DisableRegion
EricLew 0:80ee8f3b695e 612 * @param Region This parameter can be one of the following values:
EricLew 0:80ee8f3b695e 613 * @arg @ref LL_MPU_REGION_NUMBER0
EricLew 0:80ee8f3b695e 614 * @arg @ref LL_MPU_REGION_NUMBER1
EricLew 0:80ee8f3b695e 615 * @arg @ref LL_MPU_REGION_NUMBER2
EricLew 0:80ee8f3b695e 616 * @arg @ref LL_MPU_REGION_NUMBER3
EricLew 0:80ee8f3b695e 617 * @arg @ref LL_MPU_REGION_NUMBER4
EricLew 0:80ee8f3b695e 618 * @arg @ref LL_MPU_REGION_NUMBER5
EricLew 0:80ee8f3b695e 619 * @arg @ref LL_MPU_REGION_NUMBER6
EricLew 0:80ee8f3b695e 620 * @arg @ref LL_MPU_REGION_NUMBER7
EricLew 0:80ee8f3b695e 621 * @retval None
EricLew 0:80ee8f3b695e 622 */
EricLew 0:80ee8f3b695e 623 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
EricLew 0:80ee8f3b695e 624 {
EricLew 0:80ee8f3b695e 625 /* Set Region number */
EricLew 0:80ee8f3b695e 626 WRITE_REG(MPU->RNR, Region);
EricLew 0:80ee8f3b695e 627 /* Disable the MPU region */
EricLew 0:80ee8f3b695e 628 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
EricLew 0:80ee8f3b695e 629 }
EricLew 0:80ee8f3b695e 630
EricLew 0:80ee8f3b695e 631 /**
EricLew 0:80ee8f3b695e 632 * @}
EricLew 0:80ee8f3b695e 633 */
EricLew 0:80ee8f3b695e 634
EricLew 0:80ee8f3b695e 635 /**
EricLew 0:80ee8f3b695e 636 * @}
EricLew 0:80ee8f3b695e 637 */
EricLew 0:80ee8f3b695e 638
EricLew 0:80ee8f3b695e 639 /**
EricLew 0:80ee8f3b695e 640 * @}
EricLew 0:80ee8f3b695e 641 */
EricLew 0:80ee8f3b695e 642
EricLew 0:80ee8f3b695e 643 /**
EricLew 0:80ee8f3b695e 644 * @}
EricLew 0:80ee8f3b695e 645 */
EricLew 0:80ee8f3b695e 646
EricLew 0:80ee8f3b695e 647 #ifdef __cplusplus
EricLew 0:80ee8f3b695e 648 }
EricLew 0:80ee8f3b695e 649 #endif
EricLew 0:80ee8f3b695e 650
EricLew 0:80ee8f3b695e 651 #endif /* __STM32L4xx_LL_CORTEX_H */
EricLew 0:80ee8f3b695e 652
EricLew 0:80ee8f3b695e 653 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:80ee8f3b695e 654