OneHopeOnePrayer - AudioRecord

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Senior Design: Sound Monitor / OneHopeOnePrayer

AudioRecord

Dependencies: STM32L4xx_HAL_Driver CMSIS_DSP_401

stm32l476xx.h@3:ec7e3c37fe80, 2015-11-26 (annotated)

Committer:: EricLew
Date:: Thu Nov 26 22:32:56 2015 +0000
Revision:: 3:ec7e3c37fe80
Parent:: 0:d4e5ad7ad71c

FFT is currently not working and commented out

Who changed what in which revision?

User	Revision	Line number	New contents of line
EricLew	0:d4e5ad7ad71c	1	/**
EricLew	0:d4e5ad7ad71c	2	******************************************************************************
EricLew	0:d4e5ad7ad71c	3	* @file stm32l476xx.h
EricLew	0:d4e5ad7ad71c	4	* @author MCD Application Team
EricLew	0:d4e5ad7ad71c	5	* @version V1.0.1
EricLew	0:d4e5ad7ad71c	6	* @date 16-September-2015
EricLew	0:d4e5ad7ad71c	7	* @brief CMSIS STM32L476xx Device Peripheral Access Layer Header File.
EricLew	0:d4e5ad7ad71c	8	*
EricLew	0:d4e5ad7ad71c	9	* This file contains:
EricLew	0:d4e5ad7ad71c	10	* - Data structures and the address mapping for all peripherals
EricLew	0:d4e5ad7ad71c	11	* - Peripheral's registers declarations and bits definition
EricLew	0:d4e5ad7ad71c	12	* - Macros to access peripherals registers hardware
EricLew	0:d4e5ad7ad71c	13	*
EricLew	0:d4e5ad7ad71c	14	******************************************************************************
EricLew	0:d4e5ad7ad71c	15	* @attention
EricLew	0:d4e5ad7ad71c	16	*
EricLew	0:d4e5ad7ad71c	17	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew	0:d4e5ad7ad71c	18	*
EricLew	0:d4e5ad7ad71c	19	* Redistribution and use in source and binary forms, with or without modification,
EricLew	0:d4e5ad7ad71c	20	* are permitted provided that the following conditions are met:
EricLew	0:d4e5ad7ad71c	21	* 1. Redistributions of source code must retain the above copyright notice,
EricLew	0:d4e5ad7ad71c	22	* this list of conditions and the following disclaimer.
EricLew	0:d4e5ad7ad71c	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew	0:d4e5ad7ad71c	24	* this list of conditions and the following disclaimer in the documentation
EricLew	0:d4e5ad7ad71c	25	* and/or other materials provided with the distribution.
EricLew	0:d4e5ad7ad71c	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew	0:d4e5ad7ad71c	27	* may be used to endorse or promote products derived from this software
EricLew	0:d4e5ad7ad71c	28	* without specific prior written permission.
EricLew	0:d4e5ad7ad71c	29	*
EricLew	0:d4e5ad7ad71c	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew	0:d4e5ad7ad71c	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew	0:d4e5ad7ad71c	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew	0:d4e5ad7ad71c	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew	0:d4e5ad7ad71c	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew	0:d4e5ad7ad71c	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew	0:d4e5ad7ad71c	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew	0:d4e5ad7ad71c	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew	0:d4e5ad7ad71c	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew	0:d4e5ad7ad71c	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew	0:d4e5ad7ad71c	40	*
EricLew	0:d4e5ad7ad71c	41	******************************************************************************
EricLew	0:d4e5ad7ad71c	42	*/
EricLew	0:d4e5ad7ad71c	43
EricLew	0:d4e5ad7ad71c	44	/** @addtogroup CMSIS_Device
EricLew	0:d4e5ad7ad71c	45	* @{
EricLew	0:d4e5ad7ad71c	46	*/
EricLew	0:d4e5ad7ad71c	47
EricLew	0:d4e5ad7ad71c	48	/** @addtogroup stm32l476xx
EricLew	0:d4e5ad7ad71c	49	* @{
EricLew	0:d4e5ad7ad71c	50	*/
EricLew	0:d4e5ad7ad71c	51
EricLew	0:d4e5ad7ad71c	52	#ifndef __STM32L476xx_H
EricLew	0:d4e5ad7ad71c	53	#define __STM32L476xx_H
EricLew	0:d4e5ad7ad71c	54
EricLew	0:d4e5ad7ad71c	55	#ifdef __cplusplus
EricLew	0:d4e5ad7ad71c	56	extern "C" {
EricLew	0:d4e5ad7ad71c	57	#endif /* __cplusplus */
EricLew	0:d4e5ad7ad71c	58
EricLew	0:d4e5ad7ad71c	59	/** @addtogroup Configuration_section_for_CMSIS
EricLew	0:d4e5ad7ad71c	60	* @{
EricLew	0:d4e5ad7ad71c	61	*/
EricLew	0:d4e5ad7ad71c	62
EricLew	0:d4e5ad7ad71c	63	/**
EricLew	0:d4e5ad7ad71c	64	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
EricLew	0:d4e5ad7ad71c	65	*/
EricLew	0:d4e5ad7ad71c	66	#define __CM4_REV 0x0001 /!< Cortex-M4 revision r0p1 /
EricLew	0:d4e5ad7ad71c	67	#define __MPU_PRESENT 1 /!< STM32L4XX provides an MPU /
EricLew	0:d4e5ad7ad71c	68	#define __NVIC_PRIO_BITS 4 /!< STM32L4XX uses 4 Bits for the Priority Levels /
EricLew	0:d4e5ad7ad71c	69	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
EricLew	0:d4e5ad7ad71c	70	#define __FPU_PRESENT 1 /!< FPU present /
EricLew	0:d4e5ad7ad71c	71
EricLew	0:d4e5ad7ad71c	72	/**
EricLew	0:d4e5ad7ad71c	73	* @}
EricLew	0:d4e5ad7ad71c	74	*/
EricLew	0:d4e5ad7ad71c	75
EricLew	0:d4e5ad7ad71c	76	/** @addtogroup Peripheral_interrupt_number_definition
EricLew	0:d4e5ad7ad71c	77	* @{
EricLew	0:d4e5ad7ad71c	78	*/
EricLew	0:d4e5ad7ad71c	79
EricLew	0:d4e5ad7ad71c	80	/**
EricLew	0:d4e5ad7ad71c	81	* @brief STM32L4XX Interrupt Number Definition, according to the selected device
EricLew	0:d4e5ad7ad71c	82	* in @ref Library_configuration_section
EricLew	0:d4e5ad7ad71c	83	*/
EricLew	0:d4e5ad7ad71c	84	typedef enum
EricLew	0:d4e5ad7ad71c	85	{
EricLew	0:d4e5ad7ad71c	86	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
EricLew	0:d4e5ad7ad71c	87	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
EricLew	0:d4e5ad7ad71c	88	HardFault_IRQn = -13, /!< 4 Cortex-M4 Memory Management Interrupt /
EricLew	0:d4e5ad7ad71c	89	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
EricLew	0:d4e5ad7ad71c	90	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
EricLew	0:d4e5ad7ad71c	91	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
EricLew	0:d4e5ad7ad71c	92	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
EricLew	0:d4e5ad7ad71c	93	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
EricLew	0:d4e5ad7ad71c	94	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
EricLew	0:d4e5ad7ad71c	95	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
EricLew	0:d4e5ad7ad71c	96	/**** STM32 specific Interrupt Numbers ********************************************************************/
EricLew	0:d4e5ad7ad71c	97	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
EricLew	0:d4e5ad7ad71c	98	PVD_PVM_IRQn = 1, /!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts /
EricLew	0:d4e5ad7ad71c	99	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
EricLew	0:d4e5ad7ad71c	100	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
EricLew	0:d4e5ad7ad71c	101	FLASH_IRQn = 4, /!< FLASH global Interrupt /
EricLew	0:d4e5ad7ad71c	102	RCC_IRQn = 5, /!< RCC global Interrupt /
EricLew	0:d4e5ad7ad71c	103	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
EricLew	0:d4e5ad7ad71c	104	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
EricLew	0:d4e5ad7ad71c	105	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
EricLew	0:d4e5ad7ad71c	106	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
EricLew	0:d4e5ad7ad71c	107	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
EricLew	0:d4e5ad7ad71c	108	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
EricLew	0:d4e5ad7ad71c	109	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
EricLew	0:d4e5ad7ad71c	110	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
EricLew	0:d4e5ad7ad71c	111	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
EricLew	0:d4e5ad7ad71c	112	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
EricLew	0:d4e5ad7ad71c	113	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
EricLew	0:d4e5ad7ad71c	114	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
EricLew	0:d4e5ad7ad71c	115	ADC1_2_IRQn = 18, /!< ADC1, ADC2 SAR global Interrupts /
EricLew	0:d4e5ad7ad71c	116	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
EricLew	0:d4e5ad7ad71c	117	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
EricLew	0:d4e5ad7ad71c	118	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
EricLew	0:d4e5ad7ad71c	119	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
EricLew	0:d4e5ad7ad71c	120	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
EricLew	0:d4e5ad7ad71c	121	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break interrupt and TIM15 global interrupt /
EricLew	0:d4e5ad7ad71c	122	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update Interrupt and TIM16 global interrupt /
EricLew	0:d4e5ad7ad71c	123	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM17 global interrupt /
EricLew	0:d4e5ad7ad71c	124	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
EricLew	0:d4e5ad7ad71c	125	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
EricLew	0:d4e5ad7ad71c	126	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
EricLew	0:d4e5ad7ad71c	127	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
EricLew	0:d4e5ad7ad71c	128	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
EricLew	0:d4e5ad7ad71c	129	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
EricLew	0:d4e5ad7ad71c	130	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
EricLew	0:d4e5ad7ad71c	131	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
EricLew	0:d4e5ad7ad71c	132	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
EricLew	0:d4e5ad7ad71c	133	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
EricLew	0:d4e5ad7ad71c	134	USART1_IRQn = 37, /!< USART1 global Interrupt /
EricLew	0:d4e5ad7ad71c	135	USART2_IRQn = 38, /!< USART2 global Interrupt /
EricLew	0:d4e5ad7ad71c	136	USART3_IRQn = 39, /!< USART3 global Interrupt /
EricLew	0:d4e5ad7ad71c	137	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
EricLew	0:d4e5ad7ad71c	138	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
EricLew	0:d4e5ad7ad71c	139	DFSDM3_IRQn = 42, /!< SD Filter 3 global Interrupt /
EricLew	0:d4e5ad7ad71c	140	TIM8_BRK_IRQn = 43, /!< TIM8 Break Interrupt /
EricLew	0:d4e5ad7ad71c	141	TIM8_UP_IRQn = 44, /!< TIM8 Update Interrupt /
EricLew	0:d4e5ad7ad71c	142	TIM8_TRG_COM_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt /
EricLew	0:d4e5ad7ad71c	143	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
EricLew	0:d4e5ad7ad71c	144	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
EricLew	0:d4e5ad7ad71c	145	FMC_IRQn = 48, /!< FMC global Interrupt /
EricLew	0:d4e5ad7ad71c	146	SDMMC1_IRQn = 49, /!< SDMMC1 global Interrupt /
EricLew	0:d4e5ad7ad71c	147	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
EricLew	0:d4e5ad7ad71c	148	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
EricLew	0:d4e5ad7ad71c	149	UART4_IRQn = 52, /!< UART4 global Interrupt /
EricLew	0:d4e5ad7ad71c	150	UART5_IRQn = 53, /!< UART5 global Interrupt /
EricLew	0:d4e5ad7ad71c	151	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
EricLew	0:d4e5ad7ad71c	152	TIM7_IRQn = 55, /!< TIM7 global interrupt /
EricLew	0:d4e5ad7ad71c	153	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
EricLew	0:d4e5ad7ad71c	154	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
EricLew	0:d4e5ad7ad71c	155	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
EricLew	0:d4e5ad7ad71c	156	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
EricLew	0:d4e5ad7ad71c	157	DMA2_Channel5_IRQn = 60, /!< DMA2 Channel 5 global Interrupt /
EricLew	0:d4e5ad7ad71c	158	DFSDM0_IRQn = 61, /!< SD Filter 0 global Interrupt /
EricLew	0:d4e5ad7ad71c	159	DFSDM1_IRQn = 62, /!< SD Filter 1 global Interrupt /
EricLew	0:d4e5ad7ad71c	160	DFSDM2_IRQn = 63, /!< SD Filter 2 global Interrupt /
EricLew	0:d4e5ad7ad71c	161	COMP_IRQn = 64, /!< COMP1 and COMP2 Interrupts /
EricLew	0:d4e5ad7ad71c	162	LPTIM1_IRQn = 65, /!< LP TIM1 interrupt /
EricLew	0:d4e5ad7ad71c	163	LPTIM2_IRQn = 66, /!< LP TIM2 interrupt /
EricLew	0:d4e5ad7ad71c	164	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
EricLew	0:d4e5ad7ad71c	165	DMA2_Channel6_IRQn = 68, /!< DMA2 Channel 6 global interrupt /
EricLew	0:d4e5ad7ad71c	166	DMA2_Channel7_IRQn = 69, /!< DMA2 Channel 7 global interrupt /
EricLew	0:d4e5ad7ad71c	167	LPUART1_IRQn = 70, /!< LP UART1 interrupt /
EricLew	0:d4e5ad7ad71c	168	QUADSPI_IRQn = 71, /!< Quad SPI global interrupt /
EricLew	0:d4e5ad7ad71c	169	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
EricLew	0:d4e5ad7ad71c	170	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
EricLew	0:d4e5ad7ad71c	171	SAI1_IRQn = 74, /!< Serial Audio Interface 1 global interrupt /
EricLew	0:d4e5ad7ad71c	172	SAI2_IRQn = 75, /!< Serial Audio Interface 2 global interrupt /
EricLew	0:d4e5ad7ad71c	173	SWPMI1_IRQn = 76, /!< Serial Wire Interface 1 global interrupt /
EricLew	0:d4e5ad7ad71c	174	TSC_IRQn = 77, /!< Touch Sense Controller global interrupt /
EricLew	0:d4e5ad7ad71c	175	LCD_IRQn = 78, /!< LCD global interrupt /
EricLew	0:d4e5ad7ad71c	176	RNG_IRQn = 80, /!< RNG global interrupt /
EricLew	0:d4e5ad7ad71c	177	FPU_IRQn = 81 /!< FPU global interrupt /
EricLew	0:d4e5ad7ad71c	178	} IRQn_Type;
EricLew	0:d4e5ad7ad71c	179
EricLew	0:d4e5ad7ad71c	180	/**
EricLew	0:d4e5ad7ad71c	181	* @}
EricLew	0:d4e5ad7ad71c	182	*/
EricLew	0:d4e5ad7ad71c	183
EricLew	0:d4e5ad7ad71c	184	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
EricLew	0:d4e5ad7ad71c	185	#include "system_stm32l4xx.h"
EricLew	0:d4e5ad7ad71c	186	#include <stdint.h>
EricLew	0:d4e5ad7ad71c	187
EricLew	0:d4e5ad7ad71c	188	/** @addtogroup Peripheral_registers_structures
EricLew	0:d4e5ad7ad71c	189	* @{
EricLew	0:d4e5ad7ad71c	190	*/
EricLew	0:d4e5ad7ad71c	191
EricLew	0:d4e5ad7ad71c	192	/**
EricLew	0:d4e5ad7ad71c	193	* @brief Analog to Digital Converter
EricLew	0:d4e5ad7ad71c	194	*/
EricLew	0:d4e5ad7ad71c	195
EricLew	0:d4e5ad7ad71c	196	typedef struct
EricLew	0:d4e5ad7ad71c	197	{
EricLew	0:d4e5ad7ad71c	198	__IO uint32_t ISR; /!< ADC Interrupt and Status Register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	199	__IO uint32_t IER; /!< ADC Interrupt Enable Register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	200	__IO uint32_t CR; /!< ADC control register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	201	__IO uint32_t CFGR; /!< ADC Configuration register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	202	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	203	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	204	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	205	uint32_t RESERVED1; /!< Reserved, 0x01C /
EricLew	0:d4e5ad7ad71c	206	__IO uint32_t TR1; /!< ADC watchdog threshold register 1, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	207	__IO uint32_t TR2; /!< ADC watchdog threshold register 2, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	208	__IO uint32_t TR3; /!< ADC watchdog threshold register 3, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	209	uint32_t RESERVED2; /!< Reserved, 0x02C /
EricLew	0:d4e5ad7ad71c	210	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	211	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	212	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	213	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	214	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x40 /
EricLew	0:d4e5ad7ad71c	215	uint32_t RESERVED3; /!< Reserved, 0x044 /
EricLew	0:d4e5ad7ad71c	216	uint32_t RESERVED4; /!< Reserved, 0x048 /
EricLew	0:d4e5ad7ad71c	217	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	218	uint32_t RESERVED5[4]; /!< Reserved, 0x050 - 0x05C /
EricLew	0:d4e5ad7ad71c	219	__IO uint32_t OFR1; /!< ADC offset register 1, Address offset: 0x60 /
EricLew	0:d4e5ad7ad71c	220	__IO uint32_t OFR2; /!< ADC offset register 2, Address offset: 0x64 /
EricLew	0:d4e5ad7ad71c	221	__IO uint32_t OFR3; /!< ADC offset register 3, Address offset: 0x68 /
EricLew	0:d4e5ad7ad71c	222	__IO uint32_t OFR4; /!< ADC offset register 4, Address offset: 0x6C /
EricLew	0:d4e5ad7ad71c	223	uint32_t RESERVED6[4]; /!< Reserved, 0x070 - 0x07C /
EricLew	0:d4e5ad7ad71c	224	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x80 /
EricLew	0:d4e5ad7ad71c	225	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x84 /
EricLew	0:d4e5ad7ad71c	226	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x88 /
EricLew	0:d4e5ad7ad71c	227	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x8C /
EricLew	0:d4e5ad7ad71c	228	uint32_t RESERVED7[4]; /!< Reserved, 0x090 - 0x09C /
EricLew	0:d4e5ad7ad71c	229	__IO uint32_t AWD2CR; /!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 /
EricLew	0:d4e5ad7ad71c	230	__IO uint32_t AWD3CR; /!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 /
EricLew	0:d4e5ad7ad71c	231	uint32_t RESERVED8; /!< Reserved, 0x0A8 /
EricLew	0:d4e5ad7ad71c	232	uint32_t RESERVED9; /!< Reserved, 0x0AC /
EricLew	0:d4e5ad7ad71c	233	__IO uint32_t DIFSEL; /!< ADC Differential Mode Selection Register, Address offset: 0xB0 /
EricLew	0:d4e5ad7ad71c	234	__IO uint32_t CALFACT; /!< ADC Calibration Factors, Address offset: 0xB4 /
EricLew	0:d4e5ad7ad71c	235
EricLew	0:d4e5ad7ad71c	236	} ADC_TypeDef;
EricLew	0:d4e5ad7ad71c	237
EricLew	0:d4e5ad7ad71c	238	typedef struct
EricLew	0:d4e5ad7ad71c	239	{
EricLew	0:d4e5ad7ad71c	240	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
EricLew	0:d4e5ad7ad71c	241	uint32_t RESERVED; /!< Reserved, ADC1 base address + 0x304 /
EricLew	0:d4e5ad7ad71c	242	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x308 /
EricLew	0:d4e5ad7ad71c	243	__IO uint32_t CDR; /!< ADC common regular data register for dual Address offset: ADC1 base address + 0x30C /
EricLew	0:d4e5ad7ad71c	244	} ADC_Common_TypeDef;
EricLew	0:d4e5ad7ad71c	245
EricLew	0:d4e5ad7ad71c	246
EricLew	0:d4e5ad7ad71c	247	/**
EricLew	0:d4e5ad7ad71c	248	* @brief Controller Area Network TxMailBox
EricLew	0:d4e5ad7ad71c	249	*/
EricLew	0:d4e5ad7ad71c	250
EricLew	0:d4e5ad7ad71c	251	typedef struct
EricLew	0:d4e5ad7ad71c	252	{
EricLew	0:d4e5ad7ad71c	253	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
EricLew	0:d4e5ad7ad71c	254	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
EricLew	0:d4e5ad7ad71c	255	__IO uint32_t TDLR; /!< CAN mailbox data low register /
EricLew	0:d4e5ad7ad71c	256	__IO uint32_t TDHR; /!< CAN mailbox data high register /
EricLew	0:d4e5ad7ad71c	257	} CAN_TxMailBox_TypeDef;
EricLew	0:d4e5ad7ad71c	258
EricLew	0:d4e5ad7ad71c	259	/**
EricLew	0:d4e5ad7ad71c	260	* @brief Controller Area Network FIFOMailBox
EricLew	0:d4e5ad7ad71c	261	*/
EricLew	0:d4e5ad7ad71c	262
EricLew	0:d4e5ad7ad71c	263	typedef struct
EricLew	0:d4e5ad7ad71c	264	{
EricLew	0:d4e5ad7ad71c	265	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
EricLew	0:d4e5ad7ad71c	266	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
EricLew	0:d4e5ad7ad71c	267	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
EricLew	0:d4e5ad7ad71c	268	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
EricLew	0:d4e5ad7ad71c	269	} CAN_FIFOMailBox_TypeDef;
EricLew	0:d4e5ad7ad71c	270
EricLew	0:d4e5ad7ad71c	271	/**
EricLew	0:d4e5ad7ad71c	272	* @brief Controller Area Network FilterRegister
EricLew	0:d4e5ad7ad71c	273	*/
EricLew	0:d4e5ad7ad71c	274
EricLew	0:d4e5ad7ad71c	275	typedef struct
EricLew	0:d4e5ad7ad71c	276	{
EricLew	0:d4e5ad7ad71c	277	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
EricLew	0:d4e5ad7ad71c	278	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
EricLew	0:d4e5ad7ad71c	279	} CAN_FilterRegister_TypeDef;
EricLew	0:d4e5ad7ad71c	280
EricLew	0:d4e5ad7ad71c	281	/**
EricLew	0:d4e5ad7ad71c	282	* @brief Controller Area Network
EricLew	0:d4e5ad7ad71c	283	*/
EricLew	0:d4e5ad7ad71c	284
EricLew	0:d4e5ad7ad71c	285	typedef struct
EricLew	0:d4e5ad7ad71c	286	{
EricLew	0:d4e5ad7ad71c	287	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	288	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	289	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	290	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	291	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	292	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	293	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	294	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	295	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
EricLew	0:d4e5ad7ad71c	296	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
EricLew	0:d4e5ad7ad71c	297	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
EricLew	0:d4e5ad7ad71c	298	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
EricLew	0:d4e5ad7ad71c	299	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
EricLew	0:d4e5ad7ad71c	300	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
EricLew	0:d4e5ad7ad71c	301	uint32_t RESERVED2; /!< Reserved, 0x208 /
EricLew	0:d4e5ad7ad71c	302	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
EricLew	0:d4e5ad7ad71c	303	uint32_t RESERVED3; /!< Reserved, 0x210 /
EricLew	0:d4e5ad7ad71c	304	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
EricLew	0:d4e5ad7ad71c	305	uint32_t RESERVED4; /!< Reserved, 0x218 /
EricLew	0:d4e5ad7ad71c	306	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
EricLew	0:d4e5ad7ad71c	307	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
EricLew	0:d4e5ad7ad71c	308	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
EricLew	0:d4e5ad7ad71c	309	} CAN_TypeDef;
EricLew	0:d4e5ad7ad71c	310
EricLew	0:d4e5ad7ad71c	311
EricLew	0:d4e5ad7ad71c	312	/**
EricLew	0:d4e5ad7ad71c	313	* @brief Comparator
EricLew	0:d4e5ad7ad71c	314	*/
EricLew	0:d4e5ad7ad71c	315
EricLew	0:d4e5ad7ad71c	316	typedef struct
EricLew	0:d4e5ad7ad71c	317	{
EricLew	0:d4e5ad7ad71c	318	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	319	} COMP_TypeDef;
EricLew	0:d4e5ad7ad71c	320
EricLew	0:d4e5ad7ad71c	321
EricLew	0:d4e5ad7ad71c	322	/**
EricLew	0:d4e5ad7ad71c	323	* @brief CRC calculation unit
EricLew	0:d4e5ad7ad71c	324	*/
EricLew	0:d4e5ad7ad71c	325
EricLew	0:d4e5ad7ad71c	326	typedef struct
EricLew	0:d4e5ad7ad71c	327	{
EricLew	0:d4e5ad7ad71c	328	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	329	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	330	uint8_t RESERVED0; /!< Reserved, 0x05 /
EricLew	0:d4e5ad7ad71c	331	uint16_t RESERVED1; /!< Reserved, 0x06 /
EricLew	0:d4e5ad7ad71c	332	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	333	uint32_t RESERVED2; /!< Reserved, 0x0C /
EricLew	0:d4e5ad7ad71c	334	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	335	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	336	} CRC_TypeDef;
EricLew	0:d4e5ad7ad71c	337
EricLew	0:d4e5ad7ad71c	338	/**
EricLew	0:d4e5ad7ad71c	339	* @brief Digital to Analog Converter
EricLew	0:d4e5ad7ad71c	340	*/
EricLew	0:d4e5ad7ad71c	341
EricLew	0:d4e5ad7ad71c	342	typedef struct
EricLew	0:d4e5ad7ad71c	343	{
EricLew	0:d4e5ad7ad71c	344	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	345	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	346	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	347	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	348	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	349	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	350	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	351	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	352	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	353	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	354	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	355	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	356	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	357	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	358	__IO uint32_t CCR; /!< DAC calibration control register, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	359	__IO uint32_t MCR; /!< DAC mode control register, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	360	__IO uint32_t SHSR1; /!< DAC Sample and Hold sample time register 1, Address offset: 0x40 /
EricLew	0:d4e5ad7ad71c	361	__IO uint32_t SHSR2; /!< DAC Sample and Hold sample time register 2, Address offset: 0x44 /
EricLew	0:d4e5ad7ad71c	362	__IO uint32_t SHHR; /!< DAC Sample and Hold hold time register, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	363	__IO uint32_t SHRR; /!< DAC Sample and Hold refresh time register, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	364	} DAC_TypeDef;
EricLew	0:d4e5ad7ad71c	365
EricLew	0:d4e5ad7ad71c	366	/**
EricLew	0:d4e5ad7ad71c	367	* @brief DFSDM module registers
EricLew	0:d4e5ad7ad71c	368	*/
EricLew	0:d4e5ad7ad71c	369	typedef struct
EricLew	0:d4e5ad7ad71c	370	{
EricLew	0:d4e5ad7ad71c	371	__IO uint32_t CR1; /!< DFSDM control register1, Address offset: 0x100 /
EricLew	0:d4e5ad7ad71c	372	__IO uint32_t CR2; /!< DFSDM control register2, Address offset: 0x104 /
EricLew	0:d4e5ad7ad71c	373	__IO uint32_t ISR; /!< DFSDM interrupt and status register, Address offset: 0x108 /
EricLew	0:d4e5ad7ad71c	374	__IO uint32_t ICR; /!< DFSDM interrupt flag clear register, Address offset: 0x10C /
EricLew	0:d4e5ad7ad71c	375	__IO uint32_t JCHGR; /!< DFSDM injected channel group selection register, Address offset: 0x110 /
EricLew	0:d4e5ad7ad71c	376	__IO uint32_t FCR; /!< DFSDM filter control register, Address offset: 0x114 /
EricLew	0:d4e5ad7ad71c	377	__IO uint32_t JDATAR; /!< DFSDM data register for injected group, Address offset: 0x118 /
EricLew	0:d4e5ad7ad71c	378	__IO uint32_t RDATAR; /!< DFSDM data register for regular group, Address offset: 0x11C /
EricLew	0:d4e5ad7ad71c	379	__IO uint32_t AWHTR; /!< DFSDM analog watchdog high threshold register, Address offset: 0x120 /
EricLew	0:d4e5ad7ad71c	380	__IO uint32_t AWLTR; /!< DFSDM analog watchdog low threshold register, Address offset: 0x124 /
EricLew	0:d4e5ad7ad71c	381	__IO uint32_t AWSR; /!< DFSDM analog watchdog status register Address offset: 0x128 /
EricLew	0:d4e5ad7ad71c	382	__IO uint32_t AWCFR; /!< DFSDM analog watchdog clear flag register Address offset: 0x12C /
EricLew	0:d4e5ad7ad71c	383	__IO uint32_t EXMAX; /!< DFSDM extreme detector maximum register, Address offset: 0x130 /
EricLew	0:d4e5ad7ad71c	384	__IO uint32_t EXMIN; /!< DFSDM extreme detector minimum register Address offset: 0x134 /
EricLew	0:d4e5ad7ad71c	385	__IO uint32_t CNVTIMR; /!< DFSDM conversion timer, Address offset: 0x138 /
EricLew	0:d4e5ad7ad71c	386	} DFSDM_Filter_TypeDef;
EricLew	0:d4e5ad7ad71c	387
EricLew	0:d4e5ad7ad71c	388	/**
EricLew	0:d4e5ad7ad71c	389	* @brief DFSDM channel configuration registers
EricLew	0:d4e5ad7ad71c	390	*/
EricLew	0:d4e5ad7ad71c	391	typedef struct
EricLew	0:d4e5ad7ad71c	392	{
EricLew	0:d4e5ad7ad71c	393	__IO uint32_t CHCFGR1; /!< DFSDM channel configuration register1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	394	__IO uint32_t CHCFGR2; /!< DFSDM channel configuration register2, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	395	__IO uint32_t AWSCDR; /*!< DFSDM channel analog watchdog and
EricLew	0:d4e5ad7ad71c	396	short circuit detector register, Address offset: 0x08 */
EricLew	0:d4e5ad7ad71c	397	__IO uint32_t CHWDATAR; /!< DFSDM channel watchdog filter data register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	398	__IO uint32_t CHDATINR; /!< DFSDM channel data input register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	399	} DFSDM_Channel_TypeDef;
EricLew	0:d4e5ad7ad71c	400
EricLew	0:d4e5ad7ad71c	401	/**
EricLew	0:d4e5ad7ad71c	402	* @brief Debug MCU
EricLew	0:d4e5ad7ad71c	403	*/
EricLew	0:d4e5ad7ad71c	404
EricLew	0:d4e5ad7ad71c	405	typedef struct
EricLew	0:d4e5ad7ad71c	406	{
EricLew	0:d4e5ad7ad71c	407	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	408	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	409	__IO uint32_t APB1FZR1; /!< Debug MCU APB1 freeze register 1, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	410	__IO uint32_t APB1FZR2; /!< Debug MCU APB1 freeze register 2, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	411	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	412	} DBGMCU_TypeDef;
EricLew	0:d4e5ad7ad71c	413
EricLew	0:d4e5ad7ad71c	414
EricLew	0:d4e5ad7ad71c	415	/**
EricLew	0:d4e5ad7ad71c	416	* @brief DMA Controller
EricLew	0:d4e5ad7ad71c	417	*/
EricLew	0:d4e5ad7ad71c	418
EricLew	0:d4e5ad7ad71c	419	typedef struct
EricLew	0:d4e5ad7ad71c	420	{
EricLew	0:d4e5ad7ad71c	421	__IO uint32_t CCR; /!< DMA channel x configuration register /
EricLew	0:d4e5ad7ad71c	422	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
EricLew	0:d4e5ad7ad71c	423	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
EricLew	0:d4e5ad7ad71c	424	__IO uint32_t CMAR; /!< DMA channel x memory address register /
EricLew	0:d4e5ad7ad71c	425	} DMA_Channel_TypeDef;
EricLew	0:d4e5ad7ad71c	426
EricLew	0:d4e5ad7ad71c	427	typedef struct
EricLew	0:d4e5ad7ad71c	428	{
EricLew	0:d4e5ad7ad71c	429	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	430	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	431	} DMA_TypeDef;
EricLew	0:d4e5ad7ad71c	432
EricLew	0:d4e5ad7ad71c	433	typedef struct
EricLew	0:d4e5ad7ad71c	434	{
EricLew	0:d4e5ad7ad71c	435	__IO uint32_t CSELR; /!< DMA option register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	436	} DMA_request_TypeDef;
EricLew	0:d4e5ad7ad71c	437
EricLew	0:d4e5ad7ad71c	438
EricLew	0:d4e5ad7ad71c	439	/**
EricLew	0:d4e5ad7ad71c	440	* @brief External Interrupt/Event Controller
EricLew	0:d4e5ad7ad71c	441	*/
EricLew	0:d4e5ad7ad71c	442
EricLew	0:d4e5ad7ad71c	443	typedef struct
EricLew	0:d4e5ad7ad71c	444	{
EricLew	0:d4e5ad7ad71c	445	__IO uint32_t IMR1; /!< EXTI Interrupt mask register 1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	446	__IO uint32_t EMR1; /!< EXTI Event mask register 1, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	447	__IO uint32_t RTSR1; /!< EXTI Rising trigger selection register 1, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	448	__IO uint32_t FTSR1; /!< EXTI Falling trigger selection register 1, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	449	__IO uint32_t SWIER1; /!< EXTI Software interrupt event register 1, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	450	__IO uint32_t PR1; /!< EXTI Pending register 1, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	451	uint32_t RESERVED1; /!< Reserved, 0x18 /
EricLew	0:d4e5ad7ad71c	452	uint32_t RESERVED2; /!< Reserved, 0x1C /
EricLew	0:d4e5ad7ad71c	453	__IO uint32_t IMR2; /!< EXTI Interrupt mask register 2, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	454	__IO uint32_t EMR2; /!< EXTI Event mask register 2, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	455	__IO uint32_t RTSR2; /!< EXTI Rising trigger selection register 2, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	456	__IO uint32_t FTSR2; /!< EXTI Falling trigger selection register 2, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	457	__IO uint32_t SWIER2; /!< EXTI Software interrupt event register 2, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	458	__IO uint32_t PR2; /!< EXTI Pending register 2, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	459	} EXTI_TypeDef;
EricLew	0:d4e5ad7ad71c	460
EricLew	0:d4e5ad7ad71c	461
EricLew	0:d4e5ad7ad71c	462	/**
EricLew	0:d4e5ad7ad71c	463	* @brief Firewall
EricLew	0:d4e5ad7ad71c	464	*/
EricLew	0:d4e5ad7ad71c	465
EricLew	0:d4e5ad7ad71c	466	typedef struct
EricLew	0:d4e5ad7ad71c	467	{
EricLew	0:d4e5ad7ad71c	468	__IO uint32_t CSSA; /!< Code Segment Start Address register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	469	__IO uint32_t CSL; /!< Code Segment Length register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	470	__IO uint32_t NVDSSA; /!< NON volatile data Segment Start Address register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	471	__IO uint32_t NVDSL; /!< NON volatile data Segment Length register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	472	__IO uint32_t VDSSA ; /!< Volatile data Segment Start Address register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	473	__IO uint32_t VDSL ; /!< Volatile data Segment Length register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	474	uint32_t RESERVED1; /!< Reserved1, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	475	uint32_t RESERVED2; /!< Reserved2, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	476	__IO uint32_t CR ; /!< Configuration register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	477	} FIREWALL_TypeDef;
EricLew	0:d4e5ad7ad71c	478
EricLew	0:d4e5ad7ad71c	479
EricLew	0:d4e5ad7ad71c	480	/**
EricLew	0:d4e5ad7ad71c	481	* @brief FLASH Registers
EricLew	0:d4e5ad7ad71c	482	*/
EricLew	0:d4e5ad7ad71c	483
EricLew	0:d4e5ad7ad71c	484	typedef struct
EricLew	0:d4e5ad7ad71c	485	{
EricLew	0:d4e5ad7ad71c	486	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	487	__IO uint32_t PDKEYR; /!< FLASH power down key register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	488	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	489	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	490	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	491	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	492	__IO uint32_t ECCR; /!< FLASH ECC register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	493	__IO uint32_t RESERVED1; /!< Reserved1, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	494	__IO uint32_t OPTR; /!< FLASH option register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	495	__IO uint32_t PCROP1SR; /!< FLASH bank1 PCROP start address register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	496	__IO uint32_t PCROP1ER; /!< FLASH bank1 PCROP end address register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	497	__IO uint32_t WRP1AR; /!< FLASH bank1 WRP area A address register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	498	__IO uint32_t WRP1BR; /!< FLASH bank1 WRP area B address register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	499	uint32_t RESERVED2[4]; /!< Reserved2, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	500	__IO uint32_t PCROP2SR; /!< FLASH bank2 PCROP start address register, Address offset: 0x44 /
EricLew	0:d4e5ad7ad71c	501	__IO uint32_t PCROP2ER; /!< FLASH bank2 PCROP end address register, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	502	__IO uint32_t WRP2AR; /!< FLASH bank2 WRP area A address register, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	503	__IO uint32_t WRP2BR; /!< FLASH bank2 WRP area B address register, Address offset: 0x50 /
EricLew	0:d4e5ad7ad71c	504	} FLASH_TypeDef;
EricLew	0:d4e5ad7ad71c	505
EricLew	0:d4e5ad7ad71c	506
EricLew	0:d4e5ad7ad71c	507	/**
EricLew	0:d4e5ad7ad71c	508	* @brief Flexible Memory Controller
EricLew	0:d4e5ad7ad71c	509	*/
EricLew	0:d4e5ad7ad71c	510
EricLew	0:d4e5ad7ad71c	511	typedef struct
EricLew	0:d4e5ad7ad71c	512	{
EricLew	0:d4e5ad7ad71c	513	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
EricLew	0:d4e5ad7ad71c	514	} FMC_Bank1_TypeDef;
EricLew	0:d4e5ad7ad71c	515
EricLew	0:d4e5ad7ad71c	516	/**
EricLew	0:d4e5ad7ad71c	517	* @brief Flexible Memory Controller Bank1E
EricLew	0:d4e5ad7ad71c	518	*/
EricLew	0:d4e5ad7ad71c	519
EricLew	0:d4e5ad7ad71c	520	typedef struct
EricLew	0:d4e5ad7ad71c	521	{
EricLew	0:d4e5ad7ad71c	522	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
EricLew	0:d4e5ad7ad71c	523	} FMC_Bank1E_TypeDef;
EricLew	0:d4e5ad7ad71c	524
EricLew	0:d4e5ad7ad71c	525	/**
EricLew	0:d4e5ad7ad71c	526	* @brief Flexible Memory Controller Bank3
EricLew	0:d4e5ad7ad71c	527	*/
EricLew	0:d4e5ad7ad71c	528
EricLew	0:d4e5ad7ad71c	529	typedef struct
EricLew	0:d4e5ad7ad71c	530	{
EricLew	0:d4e5ad7ad71c	531	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
EricLew	0:d4e5ad7ad71c	532	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
EricLew	0:d4e5ad7ad71c	533	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
EricLew	0:d4e5ad7ad71c	534	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
EricLew	0:d4e5ad7ad71c	535	uint32_t RESERVED0; /!< Reserved, 0x90 /
EricLew	0:d4e5ad7ad71c	536	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
EricLew	0:d4e5ad7ad71c	537	} FMC_Bank3_TypeDef;
EricLew	0:d4e5ad7ad71c	538
EricLew	0:d4e5ad7ad71c	539	/**
EricLew	0:d4e5ad7ad71c	540	* @brief General Purpose I/O
EricLew	0:d4e5ad7ad71c	541	*/
EricLew	0:d4e5ad7ad71c	542
EricLew	0:d4e5ad7ad71c	543	typedef struct
EricLew	0:d4e5ad7ad71c	544	{
EricLew	0:d4e5ad7ad71c	545	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	546	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	547	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	548	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	549	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	550	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	551	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	552	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	553	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
EricLew	0:d4e5ad7ad71c	554	__IO uint32_t BRR; /!< GPIO Bit Reset register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	555	__IO uint32_t ASCR; /!< GPIO analog switch control register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	556
EricLew	0:d4e5ad7ad71c	557	} GPIO_TypeDef;
EricLew	0:d4e5ad7ad71c	558
EricLew	0:d4e5ad7ad71c	559
EricLew	0:d4e5ad7ad71c	560	/**
EricLew	0:d4e5ad7ad71c	561	* @brief Inter-integrated Circuit Interface
EricLew	0:d4e5ad7ad71c	562	*/
EricLew	0:d4e5ad7ad71c	563
EricLew	0:d4e5ad7ad71c	564	typedef struct
EricLew	0:d4e5ad7ad71c	565	{
EricLew	0:d4e5ad7ad71c	566	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	567	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	568	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	569	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	570	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	571	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	572	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	573	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	574	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	575	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	576	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	577	} I2C_TypeDef;
EricLew	0:d4e5ad7ad71c	578
EricLew	0:d4e5ad7ad71c	579	/**
EricLew	0:d4e5ad7ad71c	580	* @brief Independent WATCHDOG
EricLew	0:d4e5ad7ad71c	581	*/
EricLew	0:d4e5ad7ad71c	582
EricLew	0:d4e5ad7ad71c	583	typedef struct
EricLew	0:d4e5ad7ad71c	584	{
EricLew	0:d4e5ad7ad71c	585	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	586	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	587	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	588	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	589	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	590	} IWDG_TypeDef;
EricLew	0:d4e5ad7ad71c	591
EricLew	0:d4e5ad7ad71c	592	/**
EricLew	0:d4e5ad7ad71c	593	* @brief LCD
EricLew	0:d4e5ad7ad71c	594	*/
EricLew	0:d4e5ad7ad71c	595
EricLew	0:d4e5ad7ad71c	596	typedef struct
EricLew	0:d4e5ad7ad71c	597	{
EricLew	0:d4e5ad7ad71c	598	__IO uint32_t CR; /!< LCD control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	599	__IO uint32_t FCR; /!< LCD frame control register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	600	__IO uint32_t SR; /!< LCD status register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	601	__IO uint32_t CLR; /!< LCD clear register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	602	uint32_t RESERVED; /!< Reserved, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	603	__IO uint32_t RAM[16]; /!< LCD display memory, Address offset: 0x14-0x50 /
EricLew	0:d4e5ad7ad71c	604	} LCD_TypeDef;
EricLew	0:d4e5ad7ad71c	605
EricLew	0:d4e5ad7ad71c	606	/**
EricLew	0:d4e5ad7ad71c	607	* @brief LPTIMER
EricLew	0:d4e5ad7ad71c	608	*/
EricLew	0:d4e5ad7ad71c	609	typedef struct
EricLew	0:d4e5ad7ad71c	610	{
EricLew	0:d4e5ad7ad71c	611	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	612	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	613	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	614	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	615	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	616	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	617	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	618	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	619	__IO uint32_t OR; /!< LPTIM Option register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	620	} LPTIM_TypeDef;
EricLew	0:d4e5ad7ad71c	621
EricLew	0:d4e5ad7ad71c	622
EricLew	0:d4e5ad7ad71c	623	/**
EricLew	0:d4e5ad7ad71c	624	* @brief Operational Amplifier (OPAMP)
EricLew	0:d4e5ad7ad71c	625	*/
EricLew	0:d4e5ad7ad71c	626
EricLew	0:d4e5ad7ad71c	627	typedef struct
EricLew	0:d4e5ad7ad71c	628	{
EricLew	0:d4e5ad7ad71c	629	__IO uint32_t CSR; /!< OPAMP control/status register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	630	__IO uint32_t OTR; /!< OPAMP offset trimming register for normal mode, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	631	__IO uint32_t LPOTR; /!< OPAMP offset trimming register for low power mode, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	632	} OPAMP_TypeDef;
EricLew	0:d4e5ad7ad71c	633
EricLew	0:d4e5ad7ad71c	634
EricLew	0:d4e5ad7ad71c	635	/**
EricLew	0:d4e5ad7ad71c	636	* @brief Power Control
EricLew	0:d4e5ad7ad71c	637	*/
EricLew	0:d4e5ad7ad71c	638
EricLew	0:d4e5ad7ad71c	639	typedef struct
EricLew	0:d4e5ad7ad71c	640	{
EricLew	0:d4e5ad7ad71c	641	__IO uint32_t CR1; /!< PWR power control register 1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	642	__IO uint32_t CR2; /!< PWR power control register 2, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	643	__IO uint32_t CR3; /!< PWR power control register 3, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	644	__IO uint32_t CR4; /!< PWR power control register 4, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	645	__IO uint32_t SR1; /!< PWR power status register 1, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	646	__IO uint32_t SR2; /!< PWR power status register 2, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	647	__IO uint32_t SCR; /!< PWR power status reset register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	648	uint32_t RESERVED; /!< Reserved, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	649	__IO uint32_t PUCRA; /!< Pull_up control register of portA, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	650	__IO uint32_t PDCRA; /!< Pull_Down control register of portA, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	651	__IO uint32_t PUCRB; /!< Pull_up control register of portB, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	652	__IO uint32_t PDCRB; /!< Pull_Down control register of portB, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	653	__IO uint32_t PUCRC; /!< Pull_up control register of portC, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	654	__IO uint32_t PDCRC; /!< Pull_Down control register of portC, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	655	__IO uint32_t PUCRD; /!< Pull_up control register of portD, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	656	__IO uint32_t PDCRD; /!< Pull_Down control register of portD, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	657	__IO uint32_t PUCRE; /!< Pull_up control register of portE, Address offset: 0x40 /
EricLew	0:d4e5ad7ad71c	658	__IO uint32_t PDCRE; /!< Pull_Down control register of portE, Address offset: 0x44 /
EricLew	0:d4e5ad7ad71c	659	__IO uint32_t PUCRF; /!< Pull_up control register of portF, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	660	__IO uint32_t PDCRF; /!< Pull_Down control register of portF, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	661	__IO uint32_t PUCRG; /!< Pull_up control register of portG, Address offset: 0x50 /
EricLew	0:d4e5ad7ad71c	662	__IO uint32_t PDCRG; /!< Pull_Down control register of portG, Address offset: 0x54 /
EricLew	0:d4e5ad7ad71c	663	__IO uint32_t PUCRH; /!< Pull_up control register of portH, Address offset: 0x58 /
EricLew	0:d4e5ad7ad71c	664	__IO uint32_t PDCRH; /!< Pull_Down control register of portH, Address offset: 0x5C /
EricLew	0:d4e5ad7ad71c	665	} PWR_TypeDef;
EricLew	0:d4e5ad7ad71c	666
EricLew	0:d4e5ad7ad71c	667
EricLew	0:d4e5ad7ad71c	668	/**
EricLew	0:d4e5ad7ad71c	669	* @brief QUAD Serial Peripheral Interface
EricLew	0:d4e5ad7ad71c	670	*/
EricLew	0:d4e5ad7ad71c	671
EricLew	0:d4e5ad7ad71c	672	typedef struct
EricLew	0:d4e5ad7ad71c	673	{
EricLew	0:d4e5ad7ad71c	674	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	675	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	676	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	677	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	678	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	679	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	680	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	681	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	682	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	683	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	684	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	685	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	686	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	687	} QUADSPI_TypeDef;
EricLew	0:d4e5ad7ad71c	688
EricLew	0:d4e5ad7ad71c	689
EricLew	0:d4e5ad7ad71c	690	/**
EricLew	0:d4e5ad7ad71c	691	* @brief Reset and Clock Control
EricLew	0:d4e5ad7ad71c	692	*/
EricLew	0:d4e5ad7ad71c	693
EricLew	0:d4e5ad7ad71c	694	typedef struct
EricLew	0:d4e5ad7ad71c	695	{
EricLew	0:d4e5ad7ad71c	696	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	697	__IO uint32_t ICSCR; /!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	698	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	699	__IO uint32_t PLLCFGR; /!< RCC System PLL configuration register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	700	__IO uint32_t PLLSAI1CFGR; /!< RCC PLL SAI1 Configuration Register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	701	__IO uint32_t PLLSAI2CFGR; /!< RCC PLL SAI2 Configuration Register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	702	__IO uint32_t CIER; /!< RCC Clock Interrupt Enable Register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	703	__IO uint32_t CIFR; /!< RCC Clock Interrupt Flag Register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	704	__IO uint32_t CICR; /!< RCC Clock Interrupt Clear Register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	705	uint32_t RESERVED0; /!< Reserved, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	706	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	707	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	708	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	709	uint32_t RESERVED1; /!< Reserved, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	710	__IO uint32_t APB1RSTR1; /!< RCC APB1 macrocells resets Low Word, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	711	__IO uint32_t APB1RSTR2; /!< RCC APB1 macrocells resets High Word, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	712	__IO uint32_t APB2RSTR; /!< RCC APB2 macrocells resets, Address offset: 0x40 /
EricLew	0:d4e5ad7ad71c	713	uint32_t RESERVED2; /!< Reserved, Address offset: 0x44 /
EricLew	0:d4e5ad7ad71c	714	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock enable register, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	715	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock enable register, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	716	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock enable register, Address offset: 0x50 /
EricLew	0:d4e5ad7ad71c	717	uint32_t RESERVED3; /!< Reserved, Address offset: 0x54 /
EricLew	0:d4e5ad7ad71c	718	__IO uint32_t APB1ENR1; /!< RCC APB1 macrocells clock enables Low Word, Address offset: 0x58 /
EricLew	0:d4e5ad7ad71c	719	__IO uint32_t APB1ENR2; /!< RCC APB1 macrocells clock enables High Word, Address offset: 0x5C /
EricLew	0:d4e5ad7ad71c	720	__IO uint32_t APB2ENR; /!< RCC APB2 macrocells clock enabled, Address offset: 0x60 /
EricLew	0:d4e5ad7ad71c	721	uint32_t RESERVED4; /!< Reserved, Address offset: 0x64 /
EricLew	0:d4e5ad7ad71c	722	__IO uint32_t AHB1SMENR; /!< RCC AHB1 macrocells clocks enables in sleep mode, Address offset: 0x60 /
EricLew	0:d4e5ad7ad71c	723	__IO uint32_t AHB2SMENR; /!< RCC AHB2 macrocells clock enables in sleep mode, Address offset: 0x64 /
EricLew	0:d4e5ad7ad71c	724	__IO uint32_t AHB3SMENR; /!< RCC AHB3 macrocells clock enables in sleep mode, Address offset: 0x70 /
EricLew	0:d4e5ad7ad71c	725	uint32_t RESERVED5; /!< Reserved, Address offset: 0x74 /
EricLew	0:d4e5ad7ad71c	726	__IO uint32_t APB1SMENR1; /!< RCC APB1 macrocells clock enables in sleep mode Low Word, Address offset: 0x78 /
EricLew	0:d4e5ad7ad71c	727	__IO uint32_t APB1SMENR2; /!< RCC APB1 macrocells clock enables in sleep mode High Word, Address offset: 0x7C /
EricLew	0:d4e5ad7ad71c	728	__IO uint32_t APB2SMENR; /!< RCC APB2 macrocells clock enabled in sleep mode, Address offset: 0x80 /
EricLew	0:d4e5ad7ad71c	729	uint32_t RESERVED6; /!< Reserved, Address offset: 0x84 /
EricLew	0:d4e5ad7ad71c	730	__IO uint32_t CCIPR; /!< RCC IPs Clocks Configuration Register, Address offset: 0x88 /
EricLew	0:d4e5ad7ad71c	731	__IO uint32_t RESERVED7; /!< Reserved, Address offset: 0x8C /
EricLew	0:d4e5ad7ad71c	732	__IO uint32_t BDCR; /!< RCC Vswitch Backup Domain Control Register, Address offset: 0x90 /
EricLew	0:d4e5ad7ad71c	733	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x94 /
EricLew	0:d4e5ad7ad71c	734	} RCC_TypeDef;
EricLew	0:d4e5ad7ad71c	735
EricLew	0:d4e5ad7ad71c	736	/**
EricLew	0:d4e5ad7ad71c	737	* @brief Real-Time Clock
EricLew	0:d4e5ad7ad71c	738	*/
EricLew	0:d4e5ad7ad71c	739
EricLew	0:d4e5ad7ad71c	740	typedef struct
EricLew	0:d4e5ad7ad71c	741	{
EricLew	0:d4e5ad7ad71c	742	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	743	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	744	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	745	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	746	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	747	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	748	uint32_t reserved; /!< Reserved /
EricLew	0:d4e5ad7ad71c	749	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	750	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	751	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	752	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	753	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	754	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	755	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	756	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	757	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	758	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
EricLew	0:d4e5ad7ad71c	759	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
EricLew	0:d4e5ad7ad71c	760	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	761	__IO uint32_t OR; /!< RTC option register, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	762	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
EricLew	0:d4e5ad7ad71c	763	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
EricLew	0:d4e5ad7ad71c	764	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
EricLew	0:d4e5ad7ad71c	765	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
EricLew	0:d4e5ad7ad71c	766	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
EricLew	0:d4e5ad7ad71c	767	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
EricLew	0:d4e5ad7ad71c	768	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
EricLew	0:d4e5ad7ad71c	769	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
EricLew	0:d4e5ad7ad71c	770	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
EricLew	0:d4e5ad7ad71c	771	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
EricLew	0:d4e5ad7ad71c	772	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
EricLew	0:d4e5ad7ad71c	773	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
EricLew	0:d4e5ad7ad71c	774	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
EricLew	0:d4e5ad7ad71c	775	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
EricLew	0:d4e5ad7ad71c	776	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
EricLew	0:d4e5ad7ad71c	777	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
EricLew	0:d4e5ad7ad71c	778	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
EricLew	0:d4e5ad7ad71c	779	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
EricLew	0:d4e5ad7ad71c	780	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
EricLew	0:d4e5ad7ad71c	781	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
EricLew	0:d4e5ad7ad71c	782	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
EricLew	0:d4e5ad7ad71c	783	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
EricLew	0:d4e5ad7ad71c	784	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
EricLew	0:d4e5ad7ad71c	785	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
EricLew	0:d4e5ad7ad71c	786	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
EricLew	0:d4e5ad7ad71c	787	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
EricLew	0:d4e5ad7ad71c	788	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
EricLew	0:d4e5ad7ad71c	789	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
EricLew	0:d4e5ad7ad71c	790	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
EricLew	0:d4e5ad7ad71c	791	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
EricLew	0:d4e5ad7ad71c	792	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
EricLew	0:d4e5ad7ad71c	793	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
EricLew	0:d4e5ad7ad71c	794	} RTC_TypeDef;
EricLew	0:d4e5ad7ad71c	795
EricLew	0:d4e5ad7ad71c	796
EricLew	0:d4e5ad7ad71c	797	/**
EricLew	0:d4e5ad7ad71c	798	* @brief Serial Audio Interface
EricLew	0:d4e5ad7ad71c	799	*/
EricLew	0:d4e5ad7ad71c	800
EricLew	0:d4e5ad7ad71c	801	typedef struct
EricLew	0:d4e5ad7ad71c	802	{
EricLew	0:d4e5ad7ad71c	803	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	804	} SAI_TypeDef;
EricLew	0:d4e5ad7ad71c	805
EricLew	0:d4e5ad7ad71c	806	typedef struct
EricLew	0:d4e5ad7ad71c	807	{
EricLew	0:d4e5ad7ad71c	808	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	809	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	810	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	811	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	812	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	813	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	814	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	815	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	816	} SAI_Block_TypeDef;
EricLew	0:d4e5ad7ad71c	817
EricLew	0:d4e5ad7ad71c	818
EricLew	0:d4e5ad7ad71c	819	/**
EricLew	0:d4e5ad7ad71c	820	* @brief Secure digital input/output Interface
EricLew	0:d4e5ad7ad71c	821	*/
EricLew	0:d4e5ad7ad71c	822
EricLew	0:d4e5ad7ad71c	823	typedef struct
EricLew	0:d4e5ad7ad71c	824	{
EricLew	0:d4e5ad7ad71c	825	__IO uint32_t POWER; /!< SDMMC power control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	826	__IO uint32_t CLKCR; /!< SDMMC clock control register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	827	__IO uint32_t ARG; /!< SDMMC argument register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	828	__IO uint32_t CMD; /!< SDMMC command register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	829	__I uint32_t RESPCMD; /!< SDMMC command response register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	830	__I uint32_t RESP1; /!< SDMMC response 1 register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	831	__I uint32_t RESP2; /!< SDMMC response 2 register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	832	__I uint32_t RESP3; /!< SDMMC response 3 register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	833	__I uint32_t RESP4; /!< SDMMC response 4 register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	834	__IO uint32_t DTIMER; /!< SDMMC data timer register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	835	__IO uint32_t DLEN; /!< SDMMC data length register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	836	__IO uint32_t DCTRL; /!< SDMMC data control register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	837	__I uint32_t DCOUNT; /!< SDMMC data counter register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	838	__I uint32_t STA; /!< SDMMC status register, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	839	__IO uint32_t ICR; /!< SDMMC interrupt clear register, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	840	__IO uint32_t MASK; /!< SDMMC mask register, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	841	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
EricLew	0:d4e5ad7ad71c	842	__I uint32_t FIFOCNT; /!< SDMMC FIFO counter register, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	843	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
EricLew	0:d4e5ad7ad71c	844	__IO uint32_t FIFO; /!< SDMMC data FIFO register, Address offset: 0x80 /
EricLew	0:d4e5ad7ad71c	845	} SDMMC_TypeDef;
EricLew	0:d4e5ad7ad71c	846
EricLew	0:d4e5ad7ad71c	847
EricLew	0:d4e5ad7ad71c	848	/**
EricLew	0:d4e5ad7ad71c	849	* @brief Serial Peripheral Interface
EricLew	0:d4e5ad7ad71c	850	*/
EricLew	0:d4e5ad7ad71c	851
EricLew	0:d4e5ad7ad71c	852	typedef struct
EricLew	0:d4e5ad7ad71c	853	{
EricLew	0:d4e5ad7ad71c	854	__IO uint32_t CR1; /!< SPI Control register 1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	855	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	856	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	857	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	858	__IO uint32_t CRCPR; /!< SPI CRC polynomial register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	859	__IO uint32_t RXCRCR; /!< SPI Rx CRC register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	860	__IO uint32_t TXCRCR; /!< SPI Tx CRC register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	861	uint32_t RESERVED1; /!< Reserved, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	862	uint32_t RESERVED2; /!< Reserved, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	863	} SPI_TypeDef;
EricLew	0:d4e5ad7ad71c	864
EricLew	0:d4e5ad7ad71c	865
EricLew	0:d4e5ad7ad71c	866	/**
EricLew	0:d4e5ad7ad71c	867	* @brief Single Wire Protocol Master Interface SPWMI
EricLew	0:d4e5ad7ad71c	868	*/
EricLew	0:d4e5ad7ad71c	869
EricLew	0:d4e5ad7ad71c	870	typedef struct
EricLew	0:d4e5ad7ad71c	871	{
EricLew	0:d4e5ad7ad71c	872	__IO uint32_t CR; /!< SWPMI Configuration/Control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	873	__IO uint32_t BRR; /!< SWPMI bitrate register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	874	uint32_t RESERVED1; /!< Reserved, 0x08 /
EricLew	0:d4e5ad7ad71c	875	__IO uint32_t ISR; /!< SWPMI Interrupt and Status register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	876	__IO uint32_t ICR; /!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	877	__IO uint32_t IER; /!< SWPMI Interrupt Enable register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	878	__IO uint32_t RFL; /!< SWPMI Receive Frame Length register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	879	__IO uint32_t TDR; /!< SWPMI Transmit data register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	880	__IO uint32_t RDR; /!< SWPMI Receive data register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	881	__IO uint32_t OR; /!< SWPMI Option register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	882	} SWPMI_TypeDef;
EricLew	0:d4e5ad7ad71c	883
EricLew	0:d4e5ad7ad71c	884
EricLew	0:d4e5ad7ad71c	885	/**
EricLew	0:d4e5ad7ad71c	886	* @brief System configuration controller
EricLew	0:d4e5ad7ad71c	887	*/
EricLew	0:d4e5ad7ad71c	888
EricLew	0:d4e5ad7ad71c	889	typedef struct
EricLew	0:d4e5ad7ad71c	890	{
EricLew	0:d4e5ad7ad71c	891	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	892	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	893	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
EricLew	0:d4e5ad7ad71c	894	__IO uint32_t SCSR; /!< SYSCFG SRAM2 control and status register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	895	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	896	__IO uint32_t SWPR; /!< SYSCFG SRAM2 write protection register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	897	__IO uint32_t SKR; /!< SYSCFG SRAM2 key register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	898	} SYSCFG_TypeDef;
EricLew	0:d4e5ad7ad71c	899
EricLew	0:d4e5ad7ad71c	900
EricLew	0:d4e5ad7ad71c	901	/**
EricLew	0:d4e5ad7ad71c	902	* @brief TIM
EricLew	0:d4e5ad7ad71c	903	*/
EricLew	0:d4e5ad7ad71c	904
EricLew	0:d4e5ad7ad71c	905	typedef struct
EricLew	0:d4e5ad7ad71c	906	{
EricLew	0:d4e5ad7ad71c	907	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	908	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	909	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	910	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	911	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	912	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	913	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	914	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	915	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	916	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	917	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	918	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	919	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	920	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
EricLew	0:d4e5ad7ad71c	921	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
EricLew	0:d4e5ad7ad71c	922	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
EricLew	0:d4e5ad7ad71c	923	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
EricLew	0:d4e5ad7ad71c	924	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
EricLew	0:d4e5ad7ad71c	925	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
EricLew	0:d4e5ad7ad71c	926	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
EricLew	0:d4e5ad7ad71c	927	__IO uint32_t OR1; /!< TIM option register 1, Address offset: 0x50 /
EricLew	0:d4e5ad7ad71c	928	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
EricLew	0:d4e5ad7ad71c	929	__IO uint32_t CCR5; /!< TIM capture/compare register5, Address offset: 0x58 /
EricLew	0:d4e5ad7ad71c	930	__IO uint32_t CCR6; /!< TIM capture/compare register6, Address offset: 0x5C /
EricLew	0:d4e5ad7ad71c	931	__IO uint32_t OR2; /!< TIM option register 2, Address offset: 0x60 /
EricLew	0:d4e5ad7ad71c	932	__IO uint32_t OR3; /!< TIM option register 3, Address offset: 0x64 /
EricLew	0:d4e5ad7ad71c	933	} TIM_TypeDef;
EricLew	0:d4e5ad7ad71c	934
EricLew	0:d4e5ad7ad71c	935
EricLew	0:d4e5ad7ad71c	936	/**
EricLew	0:d4e5ad7ad71c	937	* @brief Touch Sensing Controller (TSC)
EricLew	0:d4e5ad7ad71c	938	*/
EricLew	0:d4e5ad7ad71c	939
EricLew	0:d4e5ad7ad71c	940	typedef struct
EricLew	0:d4e5ad7ad71c	941	{
EricLew	0:d4e5ad7ad71c	942	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	943	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	944	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	945	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	946	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	947	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	948	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	949	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	950	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	951	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	952	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	953	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
EricLew	0:d4e5ad7ad71c	954	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
EricLew	0:d4e5ad7ad71c	955	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
EricLew	0:d4e5ad7ad71c	956	} TSC_TypeDef;
EricLew	0:d4e5ad7ad71c	957
EricLew	0:d4e5ad7ad71c	958
EricLew	0:d4e5ad7ad71c	959	/**
EricLew	0:d4e5ad7ad71c	960	* @brief Universal Synchronous Asynchronous Receiver Transmitter
EricLew	0:d4e5ad7ad71c	961	*/
EricLew	0:d4e5ad7ad71c	962
EricLew	0:d4e5ad7ad71c	963	typedef struct
EricLew	0:d4e5ad7ad71c	964	{
EricLew	0:d4e5ad7ad71c	965	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	966	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	967	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	968	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
EricLew	0:d4e5ad7ad71c	969	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
EricLew	0:d4e5ad7ad71c	970	uint16_t RESERVED2; /!< Reserved, 0x12 /
EricLew	0:d4e5ad7ad71c	971	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
EricLew	0:d4e5ad7ad71c	972	__IO uint16_t RQR; /!< USART Request register, Address offset: 0x18 /
EricLew	0:d4e5ad7ad71c	973	uint16_t RESERVED3; /!< Reserved, 0x1A /
EricLew	0:d4e5ad7ad71c	974	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
EricLew	0:d4e5ad7ad71c	975	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
EricLew	0:d4e5ad7ad71c	976	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
EricLew	0:d4e5ad7ad71c	977	uint16_t RESERVED4; /!< Reserved, 0x26 /
EricLew	0:d4e5ad7ad71c	978	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
EricLew	0:d4e5ad7ad71c	979	uint16_t RESERVED5; /!< Reserved, 0x2A /
EricLew	0:d4e5ad7ad71c	980	} USART_TypeDef;
EricLew	0:d4e5ad7ad71c	981
EricLew	0:d4e5ad7ad71c	982
EricLew	0:d4e5ad7ad71c	983	/**
EricLew	0:d4e5ad7ad71c	984	* @brief VREFBUF
EricLew	0:d4e5ad7ad71c	985	*/
EricLew	0:d4e5ad7ad71c	986
EricLew	0:d4e5ad7ad71c	987	typedef struct
EricLew	0:d4e5ad7ad71c	988	{
EricLew	0:d4e5ad7ad71c	989	__IO uint32_t CSR; /!< VREFBUF control and status register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	990	__IO uint32_t CCR; /!< VREFBUF calibration and control register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	991	} VREFBUF_TypeDef;
EricLew	0:d4e5ad7ad71c	992
EricLew	0:d4e5ad7ad71c	993	/**
EricLew	0:d4e5ad7ad71c	994	* @brief Window WATCHDOG
EricLew	0:d4e5ad7ad71c	995	*/
EricLew	0:d4e5ad7ad71c	996
EricLew	0:d4e5ad7ad71c	997	typedef struct
EricLew	0:d4e5ad7ad71c	998	{
EricLew	0:d4e5ad7ad71c	999	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	1000	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	1001	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	1002	} WWDG_TypeDef;
EricLew	0:d4e5ad7ad71c	1003
EricLew	0:d4e5ad7ad71c	1004
EricLew	0:d4e5ad7ad71c	1005
EricLew	0:d4e5ad7ad71c	1006	/**
EricLew	0:d4e5ad7ad71c	1007	* @brief RNG
EricLew	0:d4e5ad7ad71c	1008	*/
EricLew	0:d4e5ad7ad71c	1009
EricLew	0:d4e5ad7ad71c	1010	typedef struct
EricLew	0:d4e5ad7ad71c	1011	{
EricLew	0:d4e5ad7ad71c	1012	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
EricLew	0:d4e5ad7ad71c	1013	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
EricLew	0:d4e5ad7ad71c	1014	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
EricLew	0:d4e5ad7ad71c	1015	} RNG_TypeDef;
EricLew	0:d4e5ad7ad71c	1016
EricLew	0:d4e5ad7ad71c	1017	/**
EricLew	0:d4e5ad7ad71c	1018	* @brief USB_OTG_Core_register
EricLew	0:d4e5ad7ad71c	1019	*/
EricLew	0:d4e5ad7ad71c	1020	typedef struct
EricLew	0:d4e5ad7ad71c	1021	{
EricLew	0:d4e5ad7ad71c	1022	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h/
EricLew	0:d4e5ad7ad71c	1023	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h/
EricLew	0:d4e5ad7ad71c	1024	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h/
EricLew	0:d4e5ad7ad71c	1025	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch/
EricLew	0:d4e5ad7ad71c	1026	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h/
EricLew	0:d4e5ad7ad71c	1027	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h/
EricLew	0:d4e5ad7ad71c	1028	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h/
EricLew	0:d4e5ad7ad71c	1029	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch/
EricLew	0:d4e5ad7ad71c	1030	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h/
EricLew	0:d4e5ad7ad71c	1031	__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
EricLew	0:d4e5ad7ad71c	1032	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h/
EricLew	0:d4e5ad7ad71c	1033	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch/
EricLew	0:d4e5ad7ad71c	1034	uint32_t Reserved30[2]; /* Reserved 030h*/
EricLew	0:d4e5ad7ad71c	1035	__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
EricLew	0:d4e5ad7ad71c	1036	__IO uint32_t CID; /* User ID Register 03Ch*/
EricLew	0:d4e5ad7ad71c	1037	uint32_t Reserved5[3]; /* Reserved 040h-048h*/
EricLew	0:d4e5ad7ad71c	1038	__IO uint32_t GHWCFG3; /* User HW config3 04Ch*/
EricLew	0:d4e5ad7ad71c	1039	uint32_t Reserved6; /* Reserved 050h*/
EricLew	0:d4e5ad7ad71c	1040	__IO uint32_t GLPMCFG; /* LPM Register 054h*/
EricLew	0:d4e5ad7ad71c	1041	__IO uint32_t GPWRDN; /* Power Down Register 058h*/
EricLew	0:d4e5ad7ad71c	1042	__IO uint32_t GDFIFOCFG; /* DFIFO Software Config Register 05Ch*/
EricLew	0:d4e5ad7ad71c	1043	__IO uint32_t GADPCTL; /* ADP Timer, Control and Status Register 60Ch*/
EricLew	0:d4e5ad7ad71c	1044	uint32_t Reserved43[39]; /* Reserved 058h-0FFh*/
EricLew	0:d4e5ad7ad71c	1045	__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
EricLew	0:d4e5ad7ad71c	1046	__IO uint32_t DIEPTXF[0x0F]; /* dev Periodic Transmit FIFO */
EricLew	0:d4e5ad7ad71c	1047	} USB_OTG_GlobalTypeDef;
EricLew	0:d4e5ad7ad71c	1048
EricLew	0:d4e5ad7ad71c	1049	/**
EricLew	0:d4e5ad7ad71c	1050	* @brief USB_OTG_device_Registers
EricLew	0:d4e5ad7ad71c	1051	*/
EricLew	0:d4e5ad7ad71c	1052	typedef struct
EricLew	0:d4e5ad7ad71c	1053	{
EricLew	0:d4e5ad7ad71c	1054	__IO uint32_t DCFG; /* dev Configuration Register 800h*/
EricLew	0:d4e5ad7ad71c	1055	__IO uint32_t DCTL; /* dev Control Register 804h*/
EricLew	0:d4e5ad7ad71c	1056	__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
EricLew	0:d4e5ad7ad71c	1057	uint32_t Reserved0C; /* Reserved 80Ch*/
EricLew	0:d4e5ad7ad71c	1058	__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
EricLew	0:d4e5ad7ad71c	1059	__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
EricLew	0:d4e5ad7ad71c	1060	__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
EricLew	0:d4e5ad7ad71c	1061	__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
EricLew	0:d4e5ad7ad71c	1062	uint32_t Reserved20; /* Reserved 820h*/
EricLew	0:d4e5ad7ad71c	1063	uint32_t Reserved9; /* Reserved 824h*/
EricLew	0:d4e5ad7ad71c	1064	__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
EricLew	0:d4e5ad7ad71c	1065	__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
EricLew	0:d4e5ad7ad71c	1066	__IO uint32_t DTHRCTL; /* dev thr 830h*/
EricLew	0:d4e5ad7ad71c	1067	__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
EricLew	0:d4e5ad7ad71c	1068	__IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/
EricLew	0:d4e5ad7ad71c	1069	__IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/
EricLew	0:d4e5ad7ad71c	1070	uint32_t Reserved40; /* dedicated EP mask 840h*/
EricLew	0:d4e5ad7ad71c	1071	__IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/
EricLew	0:d4e5ad7ad71c	1072	uint32_t Reserved44[15]; /* Reserved 844-87Ch*/
EricLew	0:d4e5ad7ad71c	1073	__IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/
EricLew	0:d4e5ad7ad71c	1074	} USB_OTG_DeviceTypeDef;
EricLew	0:d4e5ad7ad71c	1075
EricLew	0:d4e5ad7ad71c	1076	/**
EricLew	0:d4e5ad7ad71c	1077	* @brief USB_OTG_IN_Endpoint-Specific_Register
EricLew	0:d4e5ad7ad71c	1078	*/
EricLew	0:d4e5ad7ad71c	1079	typedef struct
EricLew	0:d4e5ad7ad71c	1080	{
EricLew	0:d4e5ad7ad71c	1081	__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
EricLew	0:d4e5ad7ad71c	1082	uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
EricLew	0:d4e5ad7ad71c	1083	__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
EricLew	0:d4e5ad7ad71c	1084	uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
EricLew	0:d4e5ad7ad71c	1085	__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
EricLew	0:d4e5ad7ad71c	1086	__IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/
EricLew	0:d4e5ad7ad71c	1087	__IO uint32_t DTXFSTS; /IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h*/
EricLew	0:d4e5ad7ad71c	1088	uint32_t Reserved18; /* Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num 20h) + 1Ch*/
EricLew	0:d4e5ad7ad71c	1089	} USB_OTG_INEndpointTypeDef;
EricLew	0:d4e5ad7ad71c	1090
EricLew	0:d4e5ad7ad71c	1091	/**
EricLew	0:d4e5ad7ad71c	1092	* @brief USB_OTG_OUT_Endpoint-Specific_Registers
EricLew	0:d4e5ad7ad71c	1093	*/
EricLew	0:d4e5ad7ad71c	1094	typedef struct
EricLew	0:d4e5ad7ad71c	1095	{
EricLew	0:d4e5ad7ad71c	1096	__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
EricLew	0:d4e5ad7ad71c	1097	uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
EricLew	0:d4e5ad7ad71c	1098	__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
EricLew	0:d4e5ad7ad71c	1099	uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
EricLew	0:d4e5ad7ad71c	1100	__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
EricLew	0:d4e5ad7ad71c	1101	__IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/
EricLew	0:d4e5ad7ad71c	1102	uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/
EricLew	0:d4e5ad7ad71c	1103	} USB_OTG_OUTEndpointTypeDef;
EricLew	0:d4e5ad7ad71c	1104
EricLew	0:d4e5ad7ad71c	1105	/**
EricLew	0:d4e5ad7ad71c	1106	* @brief USB_OTG_Host_Mode_Register_Structures
EricLew	0:d4e5ad7ad71c	1107	*/
EricLew	0:d4e5ad7ad71c	1108	typedef struct
EricLew	0:d4e5ad7ad71c	1109	{
EricLew	0:d4e5ad7ad71c	1110	__IO uint32_t HCFG; /* Host Configuration Register 400h*/
EricLew	0:d4e5ad7ad71c	1111	__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
EricLew	0:d4e5ad7ad71c	1112	__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
EricLew	0:d4e5ad7ad71c	1113	uint32_t Reserved40C; /* Reserved 40Ch*/
EricLew	0:d4e5ad7ad71c	1114	__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
EricLew	0:d4e5ad7ad71c	1115	__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
EricLew	0:d4e5ad7ad71c	1116	__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
EricLew	0:d4e5ad7ad71c	1117	} USB_OTG_HostTypeDef;
EricLew	0:d4e5ad7ad71c	1118
EricLew	0:d4e5ad7ad71c	1119	/**
EricLew	0:d4e5ad7ad71c	1120	* @brief USB_OTG_Host_Channel_Specific_Registers
EricLew	0:d4e5ad7ad71c	1121	*/
EricLew	0:d4e5ad7ad71c	1122	typedef struct
EricLew	0:d4e5ad7ad71c	1123	{
EricLew	0:d4e5ad7ad71c	1124	__IO uint32_t HCCHAR;
EricLew	0:d4e5ad7ad71c	1125	__IO uint32_t HCSPLT;
EricLew	0:d4e5ad7ad71c	1126	__IO uint32_t HCINT;
EricLew	0:d4e5ad7ad71c	1127	__IO uint32_t HCINTMSK;
EricLew	0:d4e5ad7ad71c	1128	__IO uint32_t HCTSIZ;
EricLew	0:d4e5ad7ad71c	1129	__IO uint32_t HCDMA;
EricLew	0:d4e5ad7ad71c	1130	uint32_t Reserved[2];
EricLew	0:d4e5ad7ad71c	1131	} USB_OTG_HostChannelTypeDef;
EricLew	0:d4e5ad7ad71c	1132
EricLew	0:d4e5ad7ad71c	1133	/**
EricLew	0:d4e5ad7ad71c	1134	* @}
EricLew	0:d4e5ad7ad71c	1135	*/
EricLew	0:d4e5ad7ad71c	1136
EricLew	0:d4e5ad7ad71c	1137	/** @addtogroup Peripheral_memory_map
EricLew	0:d4e5ad7ad71c	1138	* @{
EricLew	0:d4e5ad7ad71c	1139	*/
EricLew	0:d4e5ad7ad71c	1140	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH(up to 1 MB) base address /
EricLew	0:d4e5ad7ad71c	1141	#define SRAM1_BASE ((uint32_t)0x20000000) /!< SRAM1(96 KB) base address/
EricLew	0:d4e5ad7ad71c	1142	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address /
EricLew	0:d4e5ad7ad71c	1143	#define FMC_BASE ((uint32_t)0x60000000) /!< FMC base address /
EricLew	0:d4e5ad7ad71c	1144	#define SRAM2_BASE ((uint32_t)0x10000000) /!< SRAM2(32 KB) base address/
EricLew	0:d4e5ad7ad71c	1145	#define FMC_R_BASE ((uint32_t)0xA0000000) /!< FMC control registers base address /
EricLew	0:d4e5ad7ad71c	1146	#define QSPI_R_BASE ((uint32_t)0xA0001000) /!< QUADSPI control registers base address /
EricLew	0:d4e5ad7ad71c	1147	#define SRAM1_BB_BASE ((uint32_t)0x22000000) /!< SRAM1(96 KB) base address in the bit-band region /
EricLew	0:d4e5ad7ad71c	1148	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
EricLew	0:d4e5ad7ad71c	1149	#define SRAM2_BB_BASE ((uint32_t)0x12000000) /!< SRAM2(32 KB) base address in the bit-band region /
EricLew	0:d4e5ad7ad71c	1150
EricLew	0:d4e5ad7ad71c	1151	/* Legacy defines */
EricLew	0:d4e5ad7ad71c	1152	#define SRAM_BASE SRAM1_BASE
EricLew	0:d4e5ad7ad71c	1153	#define SRAM_BB_BASE SRAM1_BB_BASE
EricLew	0:d4e5ad7ad71c	1154
EricLew	0:d4e5ad7ad71c	1155	#define SRAM1_SIZE_MAX ((uint32_t)0x00018000) /!< maximum SRAM1 size (up to 96 KBytes) /
EricLew	0:d4e5ad7ad71c	1156	#define SRAM2_SIZE ((uint32_t)0x00008000) /!< SRAM2 size (32 KBytes) /
EricLew	0:d4e5ad7ad71c	1157
EricLew	0:d4e5ad7ad71c	1158	/!< Peripheral memory map /
EricLew	0:d4e5ad7ad71c	1159	#define APB1PERIPH_BASE PERIPH_BASE
EricLew	0:d4e5ad7ad71c	1160	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
EricLew	0:d4e5ad7ad71c	1161	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
EricLew	0:d4e5ad7ad71c	1162	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
EricLew	0:d4e5ad7ad71c	1163
EricLew	0:d4e5ad7ad71c	1164	#define FMC_BANK1 FMC_BASE
EricLew	0:d4e5ad7ad71c	1165	#define FMC_BANK1_1 FMC_BANK1
EricLew	0:d4e5ad7ad71c	1166	#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000)
EricLew	0:d4e5ad7ad71c	1167	#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000)
EricLew	0:d4e5ad7ad71c	1168	#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000)
EricLew	0:d4e5ad7ad71c	1169	#define FMC_BANK3 (FMC_BASE + 0x20000000)
EricLew	0:d4e5ad7ad71c	1170
EricLew	0:d4e5ad7ad71c	1171	/!< APB1 peripherals /
EricLew	0:d4e5ad7ad71c	1172	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
EricLew	0:d4e5ad7ad71c	1173	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
EricLew	0:d4e5ad7ad71c	1174	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
EricLew	0:d4e5ad7ad71c	1175	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
EricLew	0:d4e5ad7ad71c	1176	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
EricLew	0:d4e5ad7ad71c	1177	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
EricLew	0:d4e5ad7ad71c	1178	#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
EricLew	0:d4e5ad7ad71c	1179	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
EricLew	0:d4e5ad7ad71c	1180	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
EricLew	0:d4e5ad7ad71c	1181	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
EricLew	0:d4e5ad7ad71c	1182	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
EricLew	0:d4e5ad7ad71c	1183	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
EricLew	0:d4e5ad7ad71c	1184	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
EricLew	0:d4e5ad7ad71c	1185	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
EricLew	0:d4e5ad7ad71c	1186	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
EricLew	0:d4e5ad7ad71c	1187	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
EricLew	0:d4e5ad7ad71c	1188	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
EricLew	0:d4e5ad7ad71c	1189	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
EricLew	0:d4e5ad7ad71c	1190	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
EricLew	0:d4e5ad7ad71c	1191	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
EricLew	0:d4e5ad7ad71c	1192	#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00)
EricLew	0:d4e5ad7ad71c	1193	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
EricLew	0:d4e5ad7ad71c	1194	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
EricLew	0:d4e5ad7ad71c	1195	#define DAC1_BASE (APB1PERIPH_BASE + 0x7400)
EricLew	0:d4e5ad7ad71c	1196	#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800)
EricLew	0:d4e5ad7ad71c	1197	#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800)
EricLew	0:d4e5ad7ad71c	1198	#define OPAMP2_BASE (APB1PERIPH_BASE + 0x7810)
EricLew	0:d4e5ad7ad71c	1199	#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000)
EricLew	0:d4e5ad7ad71c	1200	#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800)
EricLew	0:d4e5ad7ad71c	1201	#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400)
EricLew	0:d4e5ad7ad71c	1202
EricLew	0:d4e5ad7ad71c	1203
EricLew	0:d4e5ad7ad71c	1204	/!< APB2 peripherals /
EricLew	0:d4e5ad7ad71c	1205	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
EricLew	0:d4e5ad7ad71c	1206	#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030)
EricLew	0:d4e5ad7ad71c	1207	#define COMP1_BASE (APB2PERIPH_BASE + 0x0200)
EricLew	0:d4e5ad7ad71c	1208	#define COMP2_BASE (APB2PERIPH_BASE + 0x0204)
EricLew	0:d4e5ad7ad71c	1209	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
EricLew	0:d4e5ad7ad71c	1210	#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00)
EricLew	0:d4e5ad7ad71c	1211	#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800)
EricLew	0:d4e5ad7ad71c	1212	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
EricLew	0:d4e5ad7ad71c	1213	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
EricLew	0:d4e5ad7ad71c	1214	#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
EricLew	0:d4e5ad7ad71c	1215	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
EricLew	0:d4e5ad7ad71c	1216	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
EricLew	0:d4e5ad7ad71c	1217	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
EricLew	0:d4e5ad7ad71c	1218	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
EricLew	0:d4e5ad7ad71c	1219	#define SAI1_BASE (APB2PERIPH_BASE + 0x5400)
EricLew	0:d4e5ad7ad71c	1220	#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
EricLew	0:d4e5ad7ad71c	1221	#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
EricLew	0:d4e5ad7ad71c	1222	#define SAI2_BASE (APB2PERIPH_BASE + 0x5800)
EricLew	0:d4e5ad7ad71c	1223	#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
EricLew	0:d4e5ad7ad71c	1224	#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
EricLew	0:d4e5ad7ad71c	1225	#define DFSDM_BASE (APB2PERIPH_BASE + 0x6000)
EricLew	0:d4e5ad7ad71c	1226	#define DFSDM_Channel0_BASE (DFSDM_BASE + 0x00)
EricLew	0:d4e5ad7ad71c	1227	#define DFSDM_Channel1_BASE (DFSDM_BASE + 0x20)
EricLew	0:d4e5ad7ad71c	1228	#define DFSDM_Channel2_BASE (DFSDM_BASE + 0x40)
EricLew	0:d4e5ad7ad71c	1229	#define DFSDM_Channel3_BASE (DFSDM_BASE + 0x60)
EricLew	0:d4e5ad7ad71c	1230	#define DFSDM_Channel4_BASE (DFSDM_BASE + 0x80)
EricLew	0:d4e5ad7ad71c	1231	#define DFSDM_Channel5_BASE (DFSDM_BASE + 0xA0)
EricLew	0:d4e5ad7ad71c	1232	#define DFSDM_Channel6_BASE (DFSDM_BASE + 0xC0)
EricLew	0:d4e5ad7ad71c	1233	#define DFSDM_Channel7_BASE (DFSDM_BASE + 0xE0)
EricLew	0:d4e5ad7ad71c	1234	#define DFSDM_Filter0_BASE (DFSDM_BASE + 0x100)
EricLew	0:d4e5ad7ad71c	1235	#define DFSDM_Filter1_BASE (DFSDM_BASE + 0x180)
EricLew	0:d4e5ad7ad71c	1236	#define DFSDM_Filter2_BASE (DFSDM_BASE + 0x200)
EricLew	0:d4e5ad7ad71c	1237	#define DFSDM_Filter3_BASE (DFSDM_BASE + 0x280)
EricLew	0:d4e5ad7ad71c	1238
EricLew	0:d4e5ad7ad71c	1239	/!< AHB1 peripherals /
EricLew	0:d4e5ad7ad71c	1240	#define DMA1_BASE (AHB1PERIPH_BASE)
EricLew	0:d4e5ad7ad71c	1241	#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400)
EricLew	0:d4e5ad7ad71c	1242	#define RCC_BASE (AHB1PERIPH_BASE + 0x1000)
EricLew	0:d4e5ad7ad71c	1243	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000)
EricLew	0:d4e5ad7ad71c	1244	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
EricLew	0:d4e5ad7ad71c	1245	#define TSC_BASE (AHB1PERIPH_BASE + 0x4000)
EricLew	0:d4e5ad7ad71c	1246
EricLew	0:d4e5ad7ad71c	1247
EricLew	0:d4e5ad7ad71c	1248	#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
EricLew	0:d4e5ad7ad71c	1249	#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
EricLew	0:d4e5ad7ad71c	1250	#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
EricLew	0:d4e5ad7ad71c	1251	#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
EricLew	0:d4e5ad7ad71c	1252	#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
EricLew	0:d4e5ad7ad71c	1253	#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
EricLew	0:d4e5ad7ad71c	1254	#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
EricLew	0:d4e5ad7ad71c	1255	#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8)
EricLew	0:d4e5ad7ad71c	1256
EricLew	0:d4e5ad7ad71c	1257
EricLew	0:d4e5ad7ad71c	1258	#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
EricLew	0:d4e5ad7ad71c	1259	#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
EricLew	0:d4e5ad7ad71c	1260	#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
EricLew	0:d4e5ad7ad71c	1261	#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
EricLew	0:d4e5ad7ad71c	1262	#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
EricLew	0:d4e5ad7ad71c	1263	#define DMA2_Channel6_BASE (DMA2_BASE + 0x006C)
EricLew	0:d4e5ad7ad71c	1264	#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080)
EricLew	0:d4e5ad7ad71c	1265	#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8)
EricLew	0:d4e5ad7ad71c	1266
EricLew	0:d4e5ad7ad71c	1267
EricLew	0:d4e5ad7ad71c	1268	/!< AHB2 peripherals /
EricLew	0:d4e5ad7ad71c	1269	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
EricLew	0:d4e5ad7ad71c	1270	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
EricLew	0:d4e5ad7ad71c	1271	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
EricLew	0:d4e5ad7ad71c	1272	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
EricLew	0:d4e5ad7ad71c	1273	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
EricLew	0:d4e5ad7ad71c	1274	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
EricLew	0:d4e5ad7ad71c	1275	#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800)
EricLew	0:d4e5ad7ad71c	1276	#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00)
EricLew	0:d4e5ad7ad71c	1277
EricLew	0:d4e5ad7ad71c	1278	#define USBOTG_BASE (AHB2PERIPH_BASE + 0x08000000)
EricLew	0:d4e5ad7ad71c	1279
EricLew	0:d4e5ad7ad71c	1280	#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000)
EricLew	0:d4e5ad7ad71c	1281	#define ADC2_BASE (AHB2PERIPH_BASE + 0x08040100)
EricLew	0:d4e5ad7ad71c	1282	#define ADC3_BASE (AHB2PERIPH_BASE + 0x08040200)
EricLew	0:d4e5ad7ad71c	1283	#define ADC123_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300)
EricLew	0:d4e5ad7ad71c	1284
EricLew	0:d4e5ad7ad71c	1285
EricLew	0:d4e5ad7ad71c	1286	#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800)
EricLew	0:d4e5ad7ad71c	1287
EricLew	0:d4e5ad7ad71c	1288	/!< FMC Banks registers base address /
EricLew	0:d4e5ad7ad71c	1289	#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
EricLew	0:d4e5ad7ad71c	1290	#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
EricLew	0:d4e5ad7ad71c	1291	#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
EricLew	0:d4e5ad7ad71c	1292	#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
EricLew	0:d4e5ad7ad71c	1293	#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
EricLew	0:d4e5ad7ad71c	1294
EricLew	0:d4e5ad7ad71c	1295	/* Debug MCU registers base address */
EricLew	0:d4e5ad7ad71c	1296	#define DBGMCU_BASE ((uint32_t )0xE0042000)
EricLew	0:d4e5ad7ad71c	1297
EricLew	0:d4e5ad7ad71c	1298	/!< USB registers base address /
EricLew	0:d4e5ad7ad71c	1299	#define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
EricLew	0:d4e5ad7ad71c	1300
EricLew	0:d4e5ad7ad71c	1301	#define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
EricLew	0:d4e5ad7ad71c	1302	#define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
EricLew	0:d4e5ad7ad71c	1303	#define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
EricLew	0:d4e5ad7ad71c	1304	#define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
EricLew	0:d4e5ad7ad71c	1305	#define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
EricLew	0:d4e5ad7ad71c	1306	#define USB_OTG_HOST_BASE ((uint32_t )0x400)
EricLew	0:d4e5ad7ad71c	1307	#define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
EricLew	0:d4e5ad7ad71c	1308	#define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
EricLew	0:d4e5ad7ad71c	1309	#define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
EricLew	0:d4e5ad7ad71c	1310	#define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
EricLew	0:d4e5ad7ad71c	1311	#define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
EricLew	0:d4e5ad7ad71c	1312	#define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
EricLew	0:d4e5ad7ad71c	1313
EricLew	0:d4e5ad7ad71c	1314	/**
EricLew	0:d4e5ad7ad71c	1315	* @}
EricLew	0:d4e5ad7ad71c	1316	*/
EricLew	0:d4e5ad7ad71c	1317
EricLew	0:d4e5ad7ad71c	1318	/** @addtogroup Peripheral_declaration
EricLew	0:d4e5ad7ad71c	1319	* @{
EricLew	0:d4e5ad7ad71c	1320	*/
EricLew	0:d4e5ad7ad71c	1321	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
EricLew	0:d4e5ad7ad71c	1322	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
EricLew	0:d4e5ad7ad71c	1323	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
EricLew	0:d4e5ad7ad71c	1324	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
EricLew	0:d4e5ad7ad71c	1325	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
EricLew	0:d4e5ad7ad71c	1326	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
EricLew	0:d4e5ad7ad71c	1327	#define LCD ((LCD_TypeDef *) LCD_BASE)
EricLew	0:d4e5ad7ad71c	1328	#define RTC ((RTC_TypeDef *) RTC_BASE)
EricLew	0:d4e5ad7ad71c	1329	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
EricLew	0:d4e5ad7ad71c	1330	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
EricLew	0:d4e5ad7ad71c	1331	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
EricLew	0:d4e5ad7ad71c	1332	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
EricLew	0:d4e5ad7ad71c	1333	#define USART2 ((USART_TypeDef *) USART2_BASE)
EricLew	0:d4e5ad7ad71c	1334	#define USART3 ((USART_TypeDef *) USART3_BASE)
EricLew	0:d4e5ad7ad71c	1335	#define UART4 ((USART_TypeDef *) UART4_BASE)
EricLew	0:d4e5ad7ad71c	1336	#define UART5 ((USART_TypeDef *) UART5_BASE)
EricLew	0:d4e5ad7ad71c	1337	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
EricLew	0:d4e5ad7ad71c	1338	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
EricLew	0:d4e5ad7ad71c	1339	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
EricLew	0:d4e5ad7ad71c	1340	#define CAN ((CAN_TypeDef *) CAN1_BASE)
EricLew	0:d4e5ad7ad71c	1341	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
EricLew	0:d4e5ad7ad71c	1342	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
EricLew	0:d4e5ad7ad71c	1343	#define PWR ((PWR_TypeDef *) PWR_BASE)
EricLew	0:d4e5ad7ad71c	1344	#define DAC ((DAC_TypeDef *) DAC1_BASE)
EricLew	0:d4e5ad7ad71c	1345	#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
EricLew	0:d4e5ad7ad71c	1346	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
EricLew	0:d4e5ad7ad71c	1347	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
EricLew	0:d4e5ad7ad71c	1348	#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
EricLew	0:d4e5ad7ad71c	1349	#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
EricLew	0:d4e5ad7ad71c	1350	#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
EricLew	0:d4e5ad7ad71c	1351	#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
EricLew	0:d4e5ad7ad71c	1352
EricLew	0:d4e5ad7ad71c	1353	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
EricLew	0:d4e5ad7ad71c	1354	#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
EricLew	0:d4e5ad7ad71c	1355	#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
EricLew	0:d4e5ad7ad71c	1356	#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
EricLew	0:d4e5ad7ad71c	1357	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
EricLew	0:d4e5ad7ad71c	1358	#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
EricLew	0:d4e5ad7ad71c	1359	#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
EricLew	0:d4e5ad7ad71c	1360	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
EricLew	0:d4e5ad7ad71c	1361	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
EricLew	0:d4e5ad7ad71c	1362	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
EricLew	0:d4e5ad7ad71c	1363	#define USART1 ((USART_TypeDef *) USART1_BASE)
EricLew	0:d4e5ad7ad71c	1364	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
EricLew	0:d4e5ad7ad71c	1365	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
EricLew	0:d4e5ad7ad71c	1366	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
EricLew	0:d4e5ad7ad71c	1367	#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
EricLew	0:d4e5ad7ad71c	1368	#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
EricLew	0:d4e5ad7ad71c	1369	#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
EricLew	0:d4e5ad7ad71c	1370	#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
EricLew	0:d4e5ad7ad71c	1371	#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
EricLew	0:d4e5ad7ad71c	1372	#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
EricLew	0:d4e5ad7ad71c	1373	#define DFSDM_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM_Channel0_BASE)
EricLew	0:d4e5ad7ad71c	1374	#define DFSDM_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM_Channel1_BASE)
EricLew	0:d4e5ad7ad71c	1375	#define DFSDM_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM_Channel2_BASE)
EricLew	0:d4e5ad7ad71c	1376	#define DFSDM_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM_Channel3_BASE)
EricLew	0:d4e5ad7ad71c	1377	#define DFSDM_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM_Channel4_BASE)
EricLew	0:d4e5ad7ad71c	1378	#define DFSDM_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM_Channel5_BASE)
EricLew	0:d4e5ad7ad71c	1379	#define DFSDM_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM_Channel6_BASE)
EricLew	0:d4e5ad7ad71c	1380	#define DFSDM_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM_Channel7_BASE)
EricLew	0:d4e5ad7ad71c	1381	#define DFSDM_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM_Filter0_BASE)
EricLew	0:d4e5ad7ad71c	1382	#define DFSDM_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM_Filter1_BASE)
EricLew	0:d4e5ad7ad71c	1383	#define DFSDM_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM_Filter2_BASE)
EricLew	0:d4e5ad7ad71c	1384	#define DFSDM_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM_Filter3_BASE)
EricLew	0:d4e5ad7ad71c	1385	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
EricLew	0:d4e5ad7ad71c	1386	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
EricLew	0:d4e5ad7ad71c	1387	#define RCC ((RCC_TypeDef *) RCC_BASE)
EricLew	0:d4e5ad7ad71c	1388	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
EricLew	0:d4e5ad7ad71c	1389	#define CRC ((CRC_TypeDef *) CRC_BASE)
EricLew	0:d4e5ad7ad71c	1390	#define TSC ((TSC_TypeDef *) TSC_BASE)
EricLew	0:d4e5ad7ad71c	1391
EricLew	0:d4e5ad7ad71c	1392	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
EricLew	0:d4e5ad7ad71c	1393	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
EricLew	0:d4e5ad7ad71c	1394	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
EricLew	0:d4e5ad7ad71c	1395	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
EricLew	0:d4e5ad7ad71c	1396	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
EricLew	0:d4e5ad7ad71c	1397	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
EricLew	0:d4e5ad7ad71c	1398	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
EricLew	0:d4e5ad7ad71c	1399	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
EricLew	0:d4e5ad7ad71c	1400	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
EricLew	0:d4e5ad7ad71c	1401	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
EricLew	0:d4e5ad7ad71c	1402	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
EricLew	0:d4e5ad7ad71c	1403	#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
EricLew	0:d4e5ad7ad71c	1404	#define RNG ((RNG_TypeDef *) RNG_BASE)
EricLew	0:d4e5ad7ad71c	1405
EricLew	0:d4e5ad7ad71c	1406
EricLew	0:d4e5ad7ad71c	1407	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
EricLew	0:d4e5ad7ad71c	1408	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
EricLew	0:d4e5ad7ad71c	1409	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
EricLew	0:d4e5ad7ad71c	1410	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
EricLew	0:d4e5ad7ad71c	1411	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
EricLew	0:d4e5ad7ad71c	1412	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
EricLew	0:d4e5ad7ad71c	1413	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
EricLew	0:d4e5ad7ad71c	1414	#define DMA1_CSELR ((DMA_request_TypeDef *) DMA1_CSELR_BASE)
EricLew	0:d4e5ad7ad71c	1415
EricLew	0:d4e5ad7ad71c	1416
EricLew	0:d4e5ad7ad71c	1417	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
EricLew	0:d4e5ad7ad71c	1418	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
EricLew	0:d4e5ad7ad71c	1419	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
EricLew	0:d4e5ad7ad71c	1420	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
EricLew	0:d4e5ad7ad71c	1421	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
EricLew	0:d4e5ad7ad71c	1422	#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
EricLew	0:d4e5ad7ad71c	1423	#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
EricLew	0:d4e5ad7ad71c	1424	#define DMA2_CSELR ((DMA_request_TypeDef *) DMA2_CSELR_BASE)
EricLew	0:d4e5ad7ad71c	1425
EricLew	0:d4e5ad7ad71c	1426
EricLew	0:d4e5ad7ad71c	1427	#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
EricLew	0:d4e5ad7ad71c	1428	#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
EricLew	0:d4e5ad7ad71c	1429	#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
EricLew	0:d4e5ad7ad71c	1430
EricLew	0:d4e5ad7ad71c	1431	#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
EricLew	0:d4e5ad7ad71c	1432
EricLew	0:d4e5ad7ad71c	1433	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
EricLew	0:d4e5ad7ad71c	1434
EricLew	0:d4e5ad7ad71c	1435	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
EricLew	0:d4e5ad7ad71c	1436	/**
EricLew	0:d4e5ad7ad71c	1437	* @}
EricLew	0:d4e5ad7ad71c	1438	*/
EricLew	0:d4e5ad7ad71c	1439
EricLew	0:d4e5ad7ad71c	1440	/** @addtogroup Exported_constants
EricLew	0:d4e5ad7ad71c	1441	* @{
EricLew	0:d4e5ad7ad71c	1442	*/
EricLew	0:d4e5ad7ad71c	1443
EricLew	0:d4e5ad7ad71c	1444	/** @addtogroup Peripheral_Registers_Bits_Definition
EricLew	0:d4e5ad7ad71c	1445	* @{
EricLew	0:d4e5ad7ad71c	1446	*/
EricLew	0:d4e5ad7ad71c	1447
EricLew	0:d4e5ad7ad71c	1448	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	1449	/* Peripheral Registers_Bits_Definition */
EricLew	0:d4e5ad7ad71c	1450	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	1451
EricLew	0:d4e5ad7ad71c	1452	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	1453	/* */
EricLew	0:d4e5ad7ad71c	1454	/* Analog to Digital Converter */
EricLew	0:d4e5ad7ad71c	1455	/* */
EricLew	0:d4e5ad7ad71c	1456	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	1457	/****************** Bit definition for ADC_ISR register ******************/
EricLew	0:d4e5ad7ad71c	1458	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) flag /
EricLew	0:d4e5ad7ad71c	1459	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling flag /
EricLew	0:d4e5ad7ad71c	1460	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion flag /
EricLew	0:d4e5ad7ad71c	1461	#define ADC_ISR_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions flag /
EricLew	0:d4e5ad7ad71c	1462	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< ADC overrun flag /
EricLew	0:d4e5ad7ad71c	1463	#define ADC_ISR_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion flag /
EricLew	0:d4e5ad7ad71c	1464	#define ADC_ISR_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions flag /
EricLew	0:d4e5ad7ad71c	1465	#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 flag /
EricLew	0:d4e5ad7ad71c	1466	#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 flag /
EricLew	0:d4e5ad7ad71c	1467	#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 flag /
EricLew	0:d4e5ad7ad71c	1468	#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow flag /
EricLew	0:d4e5ad7ad71c	1469
EricLew	0:d4e5ad7ad71c	1470	/****************** Bit definition for ADC_IER register ******************/
EricLew	0:d4e5ad7ad71c	1471	#define ADC_IER_ADRDY ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) interrupt source /
EricLew	0:d4e5ad7ad71c	1472	#define ADC_IER_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling interrupt source /
EricLew	0:d4e5ad7ad71c	1473	#define ADC_IER_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion interrupt source /
EricLew	0:d4e5ad7ad71c	1474	#define ADC_IER_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions interrupt source /
EricLew	0:d4e5ad7ad71c	1475	#define ADC_IER_OVR ((uint32_t)0x00000010) /!< ADC overrun interrupt source /
EricLew	0:d4e5ad7ad71c	1476	#define ADC_IER_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion interrupt source /
EricLew	0:d4e5ad7ad71c	1477	#define ADC_IER_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions interrupt source /
EricLew	0:d4e5ad7ad71c	1478	#define ADC_IER_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 interrupt source /
EricLew	0:d4e5ad7ad71c	1479	#define ADC_IER_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 interrupt source /
EricLew	0:d4e5ad7ad71c	1480	#define ADC_IER_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 interrupt source /
EricLew	0:d4e5ad7ad71c	1481	#define ADC_IER_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow interrupt source /
EricLew	0:d4e5ad7ad71c	1482
EricLew	0:d4e5ad7ad71c	1483	/****************** Bit definition for ADC_CR register ******************/
EricLew	0:d4e5ad7ad71c	1484	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC Enable control /
EricLew	0:d4e5ad7ad71c	1485	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC Disable command /
EricLew	0:d4e5ad7ad71c	1486	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC Start of Regular conversion /
EricLew	0:d4e5ad7ad71c	1487	#define ADC_CR_JADSTART ((uint32_t)0x00000008) /!< ADC Start of injected conversion /
EricLew	0:d4e5ad7ad71c	1488	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC Stop of Regular conversion /
EricLew	0:d4e5ad7ad71c	1489	#define ADC_CR_JADSTP ((uint32_t)0x00000020) /!< ADC Stop of injected conversion /
EricLew	0:d4e5ad7ad71c	1490	#define ADC_CR_ADVREGEN ((uint32_t)0x10000000) /!< ADC Voltage regulator Enable /
EricLew	0:d4e5ad7ad71c	1491	#define ADC_CR_DEEPPWD ((uint32_t)0x20000000) /!< ADC Deep power down Enable /
EricLew	0:d4e5ad7ad71c	1492	#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /!< ADC Differential Mode for calibration /
EricLew	0:d4e5ad7ad71c	1493	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC Calibration /
EricLew	0:d4e5ad7ad71c	1494
EricLew	0:d4e5ad7ad71c	1495	/****************** Bit definition for ADC_CFGR register ******************/
EricLew	0:d4e5ad7ad71c	1496	#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /!< ADC DMA Enable /
EricLew	0:d4e5ad7ad71c	1497	#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /!< ADC DMA configuration /
EricLew	0:d4e5ad7ad71c	1498
EricLew	0:d4e5ad7ad71c	1499	#define ADC_CFGR_RES ((uint32_t)0x00000018) /!< ADC Data resolution /
EricLew	0:d4e5ad7ad71c	1500	#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /!< ADC RES bit 0 /
EricLew	0:d4e5ad7ad71c	1501	#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /!< ADC RES bit 1 /
EricLew	0:d4e5ad7ad71c	1502
EricLew	0:d4e5ad7ad71c	1503	#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /!< ADC Data Alignement /
EricLew	0:d4e5ad7ad71c	1504
EricLew	0:d4e5ad7ad71c	1505	#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /!< ADC External trigger selection for regular group /
EricLew	0:d4e5ad7ad71c	1506	#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /!< ADC EXTSEL bit 0 /
EricLew	0:d4e5ad7ad71c	1507	#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /!< ADC EXTSEL bit 1 /
EricLew	0:d4e5ad7ad71c	1508	#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /!< ADC EXTSEL bit 2 /
EricLew	0:d4e5ad7ad71c	1509	#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /!< ADC EXTSEL bit 3 /
EricLew	0:d4e5ad7ad71c	1510
EricLew	0:d4e5ad7ad71c	1511	#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /!< ADC External trigger enable and polarity selection for regular channels /
EricLew	0:d4e5ad7ad71c	1512	#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /!< ADC EXTEN bit 0 /
EricLew	0:d4e5ad7ad71c	1513	#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /!< ADC EXTEN bit 1 /
EricLew	0:d4e5ad7ad71c	1514
EricLew	0:d4e5ad7ad71c	1515	#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /!< ADC overrun mode /
EricLew	0:d4e5ad7ad71c	1516	#define ADC_CFGR_CONT ((uint32_t)0x00002000) /!< ADC Single/continuous conversion mode for regular conversion /
EricLew	0:d4e5ad7ad71c	1517	#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /!< ADC Delayed conversion mode /
EricLew	0:d4e5ad7ad71c	1518
EricLew	0:d4e5ad7ad71c	1519	#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /!< ADC Discontinuous mode for regular channels /
EricLew	0:d4e5ad7ad71c	1520
EricLew	0:d4e5ad7ad71c	1521	#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /!< ADC Discontinuous mode channel count /
EricLew	0:d4e5ad7ad71c	1522	#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /!< ADC DISCNUM bit 0 /
EricLew	0:d4e5ad7ad71c	1523	#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /!< ADC DISCNUM bit 1 /
EricLew	0:d4e5ad7ad71c	1524	#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /!< ADC DISCNUM bit 2 /
EricLew	0:d4e5ad7ad71c	1525
EricLew	0:d4e5ad7ad71c	1526	#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /!< ADC Discontinuous mode on injected channels /
EricLew	0:d4e5ad7ad71c	1527	#define ADC_CFGR_JQM ((uint32_t)0x00200000) /!< ADC JSQR Queue mode /
EricLew	0:d4e5ad7ad71c	1528	#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /!< Enable the watchdog 1 on a single channel or on all channels /
EricLew	0:d4e5ad7ad71c	1529	#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /!< ADC Analog watchdog 1 enable on regular Channels /
EricLew	0:d4e5ad7ad71c	1530	#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /!< ADC Analog watchdog 1 enable on injected Channels /
EricLew	0:d4e5ad7ad71c	1531	#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /!< ADC Automatic injected group conversion /
EricLew	0:d4e5ad7ad71c	1532
EricLew	0:d4e5ad7ad71c	1533	#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /!< ADC Analog watchdog 1 Channel selection /
EricLew	0:d4e5ad7ad71c	1534	#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /!< ADC AWD1CH bit 0 /
EricLew	0:d4e5ad7ad71c	1535	#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /!< ADC AWD1CH bit 1 /
EricLew	0:d4e5ad7ad71c	1536	#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /!< ADC AWD1CH bit 2 /
EricLew	0:d4e5ad7ad71c	1537	#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /!< ADC AWD1CH bit 3 /
EricLew	0:d4e5ad7ad71c	1538	#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /!< ADC AWD1CH bit 4 /
EricLew	0:d4e5ad7ad71c	1539
EricLew	0:d4e5ad7ad71c	1540	#define ADC_CFGR_JQDIS ((uint32_t)0x80000000) /!< ADC Injected queue disable /
EricLew	0:d4e5ad7ad71c	1541
EricLew	0:d4e5ad7ad71c	1542	/****************** Bit definition for ADC_CFGR2 register ******************/
EricLew	0:d4e5ad7ad71c	1543	#define ADC_CFGR2_ROVSE ((uint32_t)0x00000001) /!< ADC Regular group oversampler enable /
EricLew	0:d4e5ad7ad71c	1544	#define ADC_CFGR2_JOVSE ((uint32_t)0x00000002) /!< ADC Injected group oversampler enable /
EricLew	0:d4e5ad7ad71c	1545
EricLew	0:d4e5ad7ad71c	1546	#define ADC_CFGR2_OVSR ((uint32_t)0x0000001C) /!< ADC Regular group oversampler enable /
EricLew	0:d4e5ad7ad71c	1547	#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004) /!< ADC OVSR bit 0 /
EricLew	0:d4e5ad7ad71c	1548	#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008) /!< ADC OVSR bit 1 /
EricLew	0:d4e5ad7ad71c	1549	#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010) /!< ADC OVSR bit 2 /
EricLew	0:d4e5ad7ad71c	1550
EricLew	0:d4e5ad7ad71c	1551	#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0) /!< ADC Regular Oversampling shift /
EricLew	0:d4e5ad7ad71c	1552	#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020) /!< ADC OVSS bit 0 /
EricLew	0:d4e5ad7ad71c	1553	#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040) /!< ADC OVSS bit 1 /
EricLew	0:d4e5ad7ad71c	1554	#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080) /!< ADC OVSS bit 2 /
EricLew	0:d4e5ad7ad71c	1555	#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100) /!< ADC OVSS bit 3 /
EricLew	0:d4e5ad7ad71c	1556
EricLew	0:d4e5ad7ad71c	1557	#define ADC_CFGR2_TROVS ((uint32_t)0x00000200) /!< ADC Triggered regular Oversampling /
EricLew	0:d4e5ad7ad71c	1558	#define ADC_CFGR2_ROVSM ((uint32_t)0x00000400) /!< ADC Regular oversampling mode /
EricLew	0:d4e5ad7ad71c	1559
EricLew	0:d4e5ad7ad71c	1560	/****************** Bit definition for ADC_SMPR1 register ******************/
EricLew	0:d4e5ad7ad71c	1561	#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /!< ADC Channel 0 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1562	#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /!< ADC SMP0 bit 0 /
EricLew	0:d4e5ad7ad71c	1563	#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /!< ADC SMP0 bit 1 /
EricLew	0:d4e5ad7ad71c	1564	#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /!< ADC SMP0 bit 2 /
EricLew	0:d4e5ad7ad71c	1565
EricLew	0:d4e5ad7ad71c	1566	#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /!< ADC Channel 1 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1567	#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /!< ADC SMP1 bit 0 /
EricLew	0:d4e5ad7ad71c	1568	#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /!< ADC SMP1 bit 1 /
EricLew	0:d4e5ad7ad71c	1569	#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /!< ADC SMP1 bit 2 /
EricLew	0:d4e5ad7ad71c	1570
EricLew	0:d4e5ad7ad71c	1571	#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /!< ADC Channel 2 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1572	#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /!< ADC SMP2 bit 0 /
EricLew	0:d4e5ad7ad71c	1573	#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /!< ADC SMP2 bit 1 /
EricLew	0:d4e5ad7ad71c	1574	#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /!< ADC SMP2 bit 2 /
EricLew	0:d4e5ad7ad71c	1575
EricLew	0:d4e5ad7ad71c	1576	#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /!< ADC Channel 3 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1577	#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /!< ADC SMP3 bit 0 /
EricLew	0:d4e5ad7ad71c	1578	#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /!< ADC SMP3 bit 1 /
EricLew	0:d4e5ad7ad71c	1579	#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /!< ADC SMP3 bit 2 /
EricLew	0:d4e5ad7ad71c	1580
EricLew	0:d4e5ad7ad71c	1581	#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /!< ADC Channel 4 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1582	#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /!< ADC SMP4 bit 0 /
EricLew	0:d4e5ad7ad71c	1583	#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /!< ADC SMP4 bit 1 /
EricLew	0:d4e5ad7ad71c	1584	#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /!< ADC SMP4 bit 2 /
EricLew	0:d4e5ad7ad71c	1585
EricLew	0:d4e5ad7ad71c	1586	#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /!< ADC Channel 5 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1587	#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /!< ADC SMP5 bit 0 /
EricLew	0:d4e5ad7ad71c	1588	#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /!< ADC SMP5 bit 1 /
EricLew	0:d4e5ad7ad71c	1589	#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /!< ADC SMP5 bit 2 /
EricLew	0:d4e5ad7ad71c	1590
EricLew	0:d4e5ad7ad71c	1591	#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /!< ADC Channel 6 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1592	#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /!< ADC SMP6 bit 0 /
EricLew	0:d4e5ad7ad71c	1593	#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /!< ADC SMP6 bit 1 /
EricLew	0:d4e5ad7ad71c	1594	#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /!< ADC SMP6 bit 2 /
EricLew	0:d4e5ad7ad71c	1595
EricLew	0:d4e5ad7ad71c	1596	#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /!< ADC Channel 7 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1597	#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /!< ADC SMP7 bit 0 /
EricLew	0:d4e5ad7ad71c	1598	#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /!< ADC SMP7 bit 1 /
EricLew	0:d4e5ad7ad71c	1599	#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /!< ADC SMP7 bit 2 /
EricLew	0:d4e5ad7ad71c	1600
EricLew	0:d4e5ad7ad71c	1601	#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /!< ADC Channel 8 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1602	#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /!< ADC SMP8 bit 0 /
EricLew	0:d4e5ad7ad71c	1603	#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /!< ADC SMP8 bit 1 /
EricLew	0:d4e5ad7ad71c	1604	#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /!< ADC SMP8 bit 2 /
EricLew	0:d4e5ad7ad71c	1605
EricLew	0:d4e5ad7ad71c	1606	#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /!< ADC Channel 9 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1607	#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /!< ADC SMP9 bit 0 /
EricLew	0:d4e5ad7ad71c	1608	#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /!< ADC SMP9 bit 1 /
EricLew	0:d4e5ad7ad71c	1609	#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /!< ADC SMP9 bit 2 /
EricLew	0:d4e5ad7ad71c	1610
EricLew	0:d4e5ad7ad71c	1611	/****************** Bit definition for ADC_SMPR2 register ******************/
EricLew	0:d4e5ad7ad71c	1612	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< ADC Channel 10 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1613	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< ADC SMP10 bit 0 /
EricLew	0:d4e5ad7ad71c	1614	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< ADC SMP10 bit 1 /
EricLew	0:d4e5ad7ad71c	1615	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< ADC SMP10 bit 2 /
EricLew	0:d4e5ad7ad71c	1616
EricLew	0:d4e5ad7ad71c	1617	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< ADC Channel 11 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1618	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< ADC SMP11 bit 0 /
EricLew	0:d4e5ad7ad71c	1619	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< ADC SMP11 bit 1 /
EricLew	0:d4e5ad7ad71c	1620	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< ADC SMP11 bit 2 /
EricLew	0:d4e5ad7ad71c	1621
EricLew	0:d4e5ad7ad71c	1622	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< ADC Channel 12 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1623	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< ADC SMP12 bit 0 /
EricLew	0:d4e5ad7ad71c	1624	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< ADC SMP12 bit 1 /
EricLew	0:d4e5ad7ad71c	1625	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< ADC SMP12 bit 2 /
EricLew	0:d4e5ad7ad71c	1626
EricLew	0:d4e5ad7ad71c	1627	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< ADC Channel 13 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1628	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< ADC SMP13 bit 0 /
EricLew	0:d4e5ad7ad71c	1629	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< ADC SMP13 bit 1 /
EricLew	0:d4e5ad7ad71c	1630	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< ADC SMP13 bit 2 /
EricLew	0:d4e5ad7ad71c	1631
EricLew	0:d4e5ad7ad71c	1632	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< ADC Channel 14 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1633	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< ADC SMP14 bit 0 /
EricLew	0:d4e5ad7ad71c	1634	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< ADC SMP14 bit 1 /
EricLew	0:d4e5ad7ad71c	1635	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< ADC SMP14 bit 2 /
EricLew	0:d4e5ad7ad71c	1636
EricLew	0:d4e5ad7ad71c	1637	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< ADC Channel 15 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1638	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< ADC SMP15 bit 0 /
EricLew	0:d4e5ad7ad71c	1639	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< ADC SMP15 bit 1 /
EricLew	0:d4e5ad7ad71c	1640	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< ADC SMP15 bit 2 /
EricLew	0:d4e5ad7ad71c	1641
EricLew	0:d4e5ad7ad71c	1642	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< ADC Channel 16 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1643	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< ADC SMP16 bit 0 /
EricLew	0:d4e5ad7ad71c	1644	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< ADC SMP16 bit 1 /
EricLew	0:d4e5ad7ad71c	1645	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< ADC SMP16 bit 2 /
EricLew	0:d4e5ad7ad71c	1646
EricLew	0:d4e5ad7ad71c	1647	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< ADC Channel 17 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1648	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< ADC SMP17 bit 0 /
EricLew	0:d4e5ad7ad71c	1649	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< ADC SMP17 bit 1 /
EricLew	0:d4e5ad7ad71c	1650	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< ADC SMP17 bit 2 /
EricLew	0:d4e5ad7ad71c	1651
EricLew	0:d4e5ad7ad71c	1652	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< ADC Channel 18 Sampling time selection /
EricLew	0:d4e5ad7ad71c	1653	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< ADC SMP18 bit 0 /
EricLew	0:d4e5ad7ad71c	1654	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< ADC SMP18 bit 1 /
EricLew	0:d4e5ad7ad71c	1655	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< ADC SMP18 bit 2 /
EricLew	0:d4e5ad7ad71c	1656
EricLew	0:d4e5ad7ad71c	1657	/****************** Bit definition for ADC_TR1 register ******************/
EricLew	0:d4e5ad7ad71c	1658	#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /!< ADC Analog watchdog 1 lower threshold /
EricLew	0:d4e5ad7ad71c	1659	#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /!< ADC LT1 bit 0 /
EricLew	0:d4e5ad7ad71c	1660	#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /!< ADC LT1 bit 1 /
EricLew	0:d4e5ad7ad71c	1661	#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /!< ADC LT1 bit 2 /
EricLew	0:d4e5ad7ad71c	1662	#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /!< ADC LT1 bit 3 /
EricLew	0:d4e5ad7ad71c	1663	#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /!< ADC LT1 bit 4 /
EricLew	0:d4e5ad7ad71c	1664	#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /!< ADC LT1 bit 5 /
EricLew	0:d4e5ad7ad71c	1665	#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /!< ADC LT1 bit 6 /
EricLew	0:d4e5ad7ad71c	1666	#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /!< ADC LT1 bit 7 /
EricLew	0:d4e5ad7ad71c	1667	#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /!< ADC LT1 bit 8 /
EricLew	0:d4e5ad7ad71c	1668	#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /!< ADC LT1 bit 9 /
EricLew	0:d4e5ad7ad71c	1669	#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /!< ADC LT1 bit 10 /
EricLew	0:d4e5ad7ad71c	1670	#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /!< ADC LT1 bit 11 /
EricLew	0:d4e5ad7ad71c	1671
EricLew	0:d4e5ad7ad71c	1672	#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /!< ADC Analog watchdog 1 higher threshold /
EricLew	0:d4e5ad7ad71c	1673	#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /!< ADC HT1 bit 0 /
EricLew	0:d4e5ad7ad71c	1674	#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /!< ADC HT1 bit 1 /
EricLew	0:d4e5ad7ad71c	1675	#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /!< ADC HT1 bit 2 /
EricLew	0:d4e5ad7ad71c	1676	#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /!< ADC HT1 bit 3 /
EricLew	0:d4e5ad7ad71c	1677	#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /!< ADC HT1 bit 4 /
EricLew	0:d4e5ad7ad71c	1678	#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /!< ADC HT1 bit 5 /
EricLew	0:d4e5ad7ad71c	1679	#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /!< ADC HT1 bit 6 /
EricLew	0:d4e5ad7ad71c	1680	#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /!< ADC HT1 bit 7 /
EricLew	0:d4e5ad7ad71c	1681	#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /!< ADC HT1 bit 8 /
EricLew	0:d4e5ad7ad71c	1682	#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /!< ADC HT1 bit 9 /
EricLew	0:d4e5ad7ad71c	1683	#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /!< ADC HT1 bit 10 /
EricLew	0:d4e5ad7ad71c	1684	#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /!< ADC HT1 bit 11 /
EricLew	0:d4e5ad7ad71c	1685
EricLew	0:d4e5ad7ad71c	1686	/****************** Bit definition for ADC_TR2 register ******************/
EricLew	0:d4e5ad7ad71c	1687	#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 2 lower threshold /
EricLew	0:d4e5ad7ad71c	1688	#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /!< ADC LT2 bit 0 /
EricLew	0:d4e5ad7ad71c	1689	#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /!< ADC LT2 bit 1 /
EricLew	0:d4e5ad7ad71c	1690	#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /!< ADC LT2 bit 2 /
EricLew	0:d4e5ad7ad71c	1691	#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /!< ADC LT2 bit 3 /
EricLew	0:d4e5ad7ad71c	1692	#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /!< ADC LT2 bit 4 /
EricLew	0:d4e5ad7ad71c	1693	#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /!< ADC LT2 bit 5 /
EricLew	0:d4e5ad7ad71c	1694	#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /!< ADC LT2 bit 6 /
EricLew	0:d4e5ad7ad71c	1695	#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /!< ADC LT2 bit 7 /
EricLew	0:d4e5ad7ad71c	1696
EricLew	0:d4e5ad7ad71c	1697	#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 2 higher threshold /
EricLew	0:d4e5ad7ad71c	1698	#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /!< ADC HT2 bit 0 /
EricLew	0:d4e5ad7ad71c	1699	#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /!< ADC HT2 bit 1 /
EricLew	0:d4e5ad7ad71c	1700	#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /!< ADC HT2 bit 2 /
EricLew	0:d4e5ad7ad71c	1701	#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /!< ADC HT2 bit 3 /
EricLew	0:d4e5ad7ad71c	1702	#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /!< ADC HT2 bit 4 /
EricLew	0:d4e5ad7ad71c	1703	#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /!< ADC HT2 bit 5 /
EricLew	0:d4e5ad7ad71c	1704	#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /!< ADC HT2 bit 6 /
EricLew	0:d4e5ad7ad71c	1705	#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /!< ADC HT2 bit 7 /
EricLew	0:d4e5ad7ad71c	1706
EricLew	0:d4e5ad7ad71c	1707	/****************** Bit definition for ADC_TR3 register ******************/
EricLew	0:d4e5ad7ad71c	1708	#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 3 lower threshold /
EricLew	0:d4e5ad7ad71c	1709	#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /!< ADC LT3 bit 0 /
EricLew	0:d4e5ad7ad71c	1710	#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /!< ADC LT3 bit 1 /
EricLew	0:d4e5ad7ad71c	1711	#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /!< ADC LT3 bit 2 /
EricLew	0:d4e5ad7ad71c	1712	#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /!< ADC LT3 bit 3 /
EricLew	0:d4e5ad7ad71c	1713	#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /!< ADC LT3 bit 4 /
EricLew	0:d4e5ad7ad71c	1714	#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /!< ADC LT3 bit 5 /
EricLew	0:d4e5ad7ad71c	1715	#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /!< ADC LT3 bit 6 /
EricLew	0:d4e5ad7ad71c	1716	#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /!< ADC LT3 bit 7 /
EricLew	0:d4e5ad7ad71c	1717
EricLew	0:d4e5ad7ad71c	1718	#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 3 higher threshold /
EricLew	0:d4e5ad7ad71c	1719	#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /!< ADC HT3 bit 0 /
EricLew	0:d4e5ad7ad71c	1720	#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /!< ADC HT3 bit 1 /
EricLew	0:d4e5ad7ad71c	1721	#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /!< ADC HT3 bit 2 /
EricLew	0:d4e5ad7ad71c	1722	#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /!< ADC HT3 bit 3 /
EricLew	0:d4e5ad7ad71c	1723	#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /!< ADC HT3 bit 4 /
EricLew	0:d4e5ad7ad71c	1724	#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /!< ADC HT3 bit 5 /
EricLew	0:d4e5ad7ad71c	1725	#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /!< ADC HT3 bit 6 /
EricLew	0:d4e5ad7ad71c	1726	#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /!< ADC HT3 bit 7 /
EricLew	0:d4e5ad7ad71c	1727
EricLew	0:d4e5ad7ad71c	1728	/****************** Bit definition for ADC_SQR1 register ******************/
EricLew	0:d4e5ad7ad71c	1729	#define ADC_SQR1_L ((uint32_t)0x0000000F) /!< ADC regular channel sequence lenght /
EricLew	0:d4e5ad7ad71c	1730	#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /!< ADC L bit 0 /
EricLew	0:d4e5ad7ad71c	1731	#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /!< ADC L bit 1 /
EricLew	0:d4e5ad7ad71c	1732	#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /!< ADC L bit 2 /
EricLew	0:d4e5ad7ad71c	1733	#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /!< ADC L bit 3 /
EricLew	0:d4e5ad7ad71c	1734
EricLew	0:d4e5ad7ad71c	1735	#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /!< ADC 1st conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1736	#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /!< ADC SQ1 bit 0 /
EricLew	0:d4e5ad7ad71c	1737	#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /!< ADC SQ1 bit 1 /
EricLew	0:d4e5ad7ad71c	1738	#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /!< ADC SQ1 bit 2 /
EricLew	0:d4e5ad7ad71c	1739	#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /!< ADC SQ1 bit 3 /
EricLew	0:d4e5ad7ad71c	1740	#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /!< ADC SQ1 bit 4 /
EricLew	0:d4e5ad7ad71c	1741
EricLew	0:d4e5ad7ad71c	1742	#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /!< ADC 2nd conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1743	#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /!< ADC SQ2 bit 0 /
EricLew	0:d4e5ad7ad71c	1744	#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /!< ADC SQ2 bit 1 /
EricLew	0:d4e5ad7ad71c	1745	#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /!< ADC SQ2 bit 2 /
EricLew	0:d4e5ad7ad71c	1746	#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /!< ADC SQ2 bit 3 /
EricLew	0:d4e5ad7ad71c	1747	#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /!< ADC SQ2 bit 4 /
EricLew	0:d4e5ad7ad71c	1748
EricLew	0:d4e5ad7ad71c	1749	#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /!< ADC 3rd conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1750	#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /!< ADC SQ3 bit 0 /
EricLew	0:d4e5ad7ad71c	1751	#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /!< ADC SQ3 bit 1 /
EricLew	0:d4e5ad7ad71c	1752	#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /!< ADC SQ3 bit 2 /
EricLew	0:d4e5ad7ad71c	1753	#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /!< ADC SQ3 bit 3 /
EricLew	0:d4e5ad7ad71c	1754	#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /!< ADC SQ3 bit 4 /
EricLew	0:d4e5ad7ad71c	1755
EricLew	0:d4e5ad7ad71c	1756	#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /!< ADC 4th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1757	#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /!< ADC SQ4 bit 0 /
EricLew	0:d4e5ad7ad71c	1758	#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /!< ADC SQ4 bit 1 /
EricLew	0:d4e5ad7ad71c	1759	#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /!< ADC SQ4 bit 2 /
EricLew	0:d4e5ad7ad71c	1760	#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /!< ADC SQ4 bit 3 /
EricLew	0:d4e5ad7ad71c	1761	#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /!< ADC SQ4 bit 4 /
EricLew	0:d4e5ad7ad71c	1762
EricLew	0:d4e5ad7ad71c	1763	/****************** Bit definition for ADC_SQR2 register ******************/
EricLew	0:d4e5ad7ad71c	1764	#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /!< ADC 5th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1765	#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /!< ADC SQ5 bit 0 /
EricLew	0:d4e5ad7ad71c	1766	#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /!< ADC SQ5 bit 1 /
EricLew	0:d4e5ad7ad71c	1767	#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /!< ADC SQ5 bit 2 /
EricLew	0:d4e5ad7ad71c	1768	#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /!< ADC SQ5 bit 3 /
EricLew	0:d4e5ad7ad71c	1769	#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /!< ADC SQ5 bit 4 /
EricLew	0:d4e5ad7ad71c	1770
EricLew	0:d4e5ad7ad71c	1771	#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /!< ADC 6th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1772	#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /!< ADC SQ6 bit 0 /
EricLew	0:d4e5ad7ad71c	1773	#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /!< ADC SQ6 bit 1 /
EricLew	0:d4e5ad7ad71c	1774	#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /!< ADC SQ6 bit 2 /
EricLew	0:d4e5ad7ad71c	1775	#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /!< ADC SQ6 bit 3 /
EricLew	0:d4e5ad7ad71c	1776	#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /!< ADC SQ6 bit 4 /
EricLew	0:d4e5ad7ad71c	1777
EricLew	0:d4e5ad7ad71c	1778	#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /!< ADC 7th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1779	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /!< ADC SQ7 bit 0 /
EricLew	0:d4e5ad7ad71c	1780	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /!< ADC SQ7 bit 1 /
EricLew	0:d4e5ad7ad71c	1781	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /!< ADC SQ7 bit 2 /
EricLew	0:d4e5ad7ad71c	1782	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /!< ADC SQ7 bit 3 /
EricLew	0:d4e5ad7ad71c	1783	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /!< ADC SQ7 bit 4 /
EricLew	0:d4e5ad7ad71c	1784
EricLew	0:d4e5ad7ad71c	1785	#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /!< ADC 8th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1786	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /!< ADC SQ8 bit 0 /
EricLew	0:d4e5ad7ad71c	1787	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /!< ADC SQ8 bit 1 /
EricLew	0:d4e5ad7ad71c	1788	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /!< ADC SQ8 bit 2 /
EricLew	0:d4e5ad7ad71c	1789	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /!< ADC SQ8 bit 3 /
EricLew	0:d4e5ad7ad71c	1790	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /!< ADC SQ8 bit 4 /
EricLew	0:d4e5ad7ad71c	1791
EricLew	0:d4e5ad7ad71c	1792	#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /!< ADC 9th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1793	#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /!< ADC SQ9 bit 0 /
EricLew	0:d4e5ad7ad71c	1794	#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /!< ADC SQ9 bit 1 /
EricLew	0:d4e5ad7ad71c	1795	#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /!< ADC SQ9 bit 2 /
EricLew	0:d4e5ad7ad71c	1796	#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /!< ADC SQ9 bit 3 /
EricLew	0:d4e5ad7ad71c	1797	#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /!< ADC SQ9 bit 4 /
EricLew	0:d4e5ad7ad71c	1798
EricLew	0:d4e5ad7ad71c	1799	/****************** Bit definition for ADC_SQR3 register ******************/
EricLew	0:d4e5ad7ad71c	1800	#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /!< ADC 10th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1801	#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /!< ADC SQ10 bit 0 /
EricLew	0:d4e5ad7ad71c	1802	#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /!< ADC SQ10 bit 1 /
EricLew	0:d4e5ad7ad71c	1803	#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /!< ADC SQ10 bit 2 /
EricLew	0:d4e5ad7ad71c	1804	#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /!< ADC SQ10 bit 3 /
EricLew	0:d4e5ad7ad71c	1805	#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /!< ADC SQ10 bit 4 /
EricLew	0:d4e5ad7ad71c	1806
EricLew	0:d4e5ad7ad71c	1807	#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /!< ADC 11th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1808	#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /!< ADC SQ11 bit 0 /
EricLew	0:d4e5ad7ad71c	1809	#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /!< ADC SQ11 bit 1 /
EricLew	0:d4e5ad7ad71c	1810	#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /!< ADC SQ11 bit 2 /
EricLew	0:d4e5ad7ad71c	1811	#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /!< ADC SQ11 bit 3 /
EricLew	0:d4e5ad7ad71c	1812	#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /!< ADC SQ11 bit 4 /
EricLew	0:d4e5ad7ad71c	1813
EricLew	0:d4e5ad7ad71c	1814	#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /!< ADC 12th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1815	#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /!< ADC SQ12 bit 0 /
EricLew	0:d4e5ad7ad71c	1816	#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /!< ADC SQ12 bit 1 /
EricLew	0:d4e5ad7ad71c	1817	#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /!< ADC SQ12 bit 2 /
EricLew	0:d4e5ad7ad71c	1818	#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /!< ADC SQ12 bit 3 /
EricLew	0:d4e5ad7ad71c	1819	#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /!< ADC SQ12 bit 4 /
EricLew	0:d4e5ad7ad71c	1820
EricLew	0:d4e5ad7ad71c	1821	#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /!< ADC 13th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1822	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /!< ADC SQ13 bit 0 /
EricLew	0:d4e5ad7ad71c	1823	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /!< ADC SQ13 bit 1 /
EricLew	0:d4e5ad7ad71c	1824	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /!< ADC SQ13 bit 2 /
EricLew	0:d4e5ad7ad71c	1825	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /!< ADC SQ13 bit 3 /
EricLew	0:d4e5ad7ad71c	1826	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /!< ADC SQ13 bit 4 /
EricLew	0:d4e5ad7ad71c	1827
EricLew	0:d4e5ad7ad71c	1828	#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /!< ADC 14th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1829	#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /!< ADC SQ14 bit 0 /
EricLew	0:d4e5ad7ad71c	1830	#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /!< ADC SQ14 bit 1 /
EricLew	0:d4e5ad7ad71c	1831	#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /!< ADC SQ14 bit 2 /
EricLew	0:d4e5ad7ad71c	1832	#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /!< ADC SQ14 bit 3 /
EricLew	0:d4e5ad7ad71c	1833	#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /!< ADC SQ14 bit 4 /
EricLew	0:d4e5ad7ad71c	1834
EricLew	0:d4e5ad7ad71c	1835	/****************** Bit definition for ADC_SQR4 register ******************/
EricLew	0:d4e5ad7ad71c	1836	#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /!< ADC 15th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1837	#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /!< ADC SQ15 bit 0 /
EricLew	0:d4e5ad7ad71c	1838	#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /!< ADC SQ15 bit 1 /
EricLew	0:d4e5ad7ad71c	1839	#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /!< ADC SQ15 bit 2 /
EricLew	0:d4e5ad7ad71c	1840	#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /!< ADC SQ15 bit 3 /
EricLew	0:d4e5ad7ad71c	1841	#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /!< ADC SQ105 bit 4 /
EricLew	0:d4e5ad7ad71c	1842
EricLew	0:d4e5ad7ad71c	1843	#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /!< ADC 16th conversion in regular sequence /
EricLew	0:d4e5ad7ad71c	1844	#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /!< ADC SQ16 bit 0 /
EricLew	0:d4e5ad7ad71c	1845	#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /!< ADC SQ16 bit 1 /
EricLew	0:d4e5ad7ad71c	1846	#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /!< ADC SQ16 bit 2 /
EricLew	0:d4e5ad7ad71c	1847	#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /!< ADC SQ16 bit 3 /
EricLew	0:d4e5ad7ad71c	1848	#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /!< ADC SQ16 bit 4 /
EricLew	0:d4e5ad7ad71c	1849
EricLew	0:d4e5ad7ad71c	1850	/****************** Bit definition for ADC_DR register ******************/
EricLew	0:d4e5ad7ad71c	1851	#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /!< ADC regular Data converted /
EricLew	0:d4e5ad7ad71c	1852	#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /!< ADC RDATA bit 0 /
EricLew	0:d4e5ad7ad71c	1853	#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /!< ADC RDATA bit 1 /
EricLew	0:d4e5ad7ad71c	1854	#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /!< ADC RDATA bit 2 /
EricLew	0:d4e5ad7ad71c	1855	#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /!< ADC RDATA bit 3 /
EricLew	0:d4e5ad7ad71c	1856	#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /!< ADC RDATA bit 4 /
EricLew	0:d4e5ad7ad71c	1857	#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /!< ADC RDATA bit 5 /
EricLew	0:d4e5ad7ad71c	1858	#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /!< ADC RDATA bit 6 /
EricLew	0:d4e5ad7ad71c	1859	#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /!< ADC RDATA bit 7 /
EricLew	0:d4e5ad7ad71c	1860	#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /!< ADC RDATA bit 8 /
EricLew	0:d4e5ad7ad71c	1861	#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /!< ADC RDATA bit 9 /
EricLew	0:d4e5ad7ad71c	1862	#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /!< ADC RDATA bit 10 /
EricLew	0:d4e5ad7ad71c	1863	#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /!< ADC RDATA bit 11 /
EricLew	0:d4e5ad7ad71c	1864	#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /!< ADC RDATA bit 12 /
EricLew	0:d4e5ad7ad71c	1865	#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /!< ADC RDATA bit 13 /
EricLew	0:d4e5ad7ad71c	1866	#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /!< ADC RDATA bit 14 /
EricLew	0:d4e5ad7ad71c	1867	#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /!< ADC RDATA bit 15 /
EricLew	0:d4e5ad7ad71c	1868
EricLew	0:d4e5ad7ad71c	1869	/****************** Bit definition for ADC_JSQR register ******************/
EricLew	0:d4e5ad7ad71c	1870	#define ADC_JSQR_JL ((uint32_t)0x00000003) /!< ADC injected channel sequence length /
EricLew	0:d4e5ad7ad71c	1871	#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /!< ADC JL bit 0 /
EricLew	0:d4e5ad7ad71c	1872	#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /!< ADC JL bit 1 /
EricLew	0:d4e5ad7ad71c	1873
EricLew	0:d4e5ad7ad71c	1874	#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /!< ADC external trigger selection for injected group /
EricLew	0:d4e5ad7ad71c	1875	#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /!< ADC JEXTSEL bit 0 /
EricLew	0:d4e5ad7ad71c	1876	#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /!< ADC JEXTSEL bit 1 /
EricLew	0:d4e5ad7ad71c	1877	#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /!< ADC JEXTSEL bit 2 /
EricLew	0:d4e5ad7ad71c	1878	#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /!< ADC JEXTSEL bit 3 /
EricLew	0:d4e5ad7ad71c	1879
EricLew	0:d4e5ad7ad71c	1880	#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /!< ADC external trigger enable and polarity selection for injected channels /
EricLew	0:d4e5ad7ad71c	1881	#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /!< ADC JEXTEN bit 0 /
EricLew	0:d4e5ad7ad71c	1882	#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /!< ADC JEXTEN bit 1 /
EricLew	0:d4e5ad7ad71c	1883
EricLew	0:d4e5ad7ad71c	1884	#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /!< ADC 1st conversion in injected sequence /
EricLew	0:d4e5ad7ad71c	1885	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /!< ADC JSQ1 bit 0 /
EricLew	0:d4e5ad7ad71c	1886	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /!< ADC JSQ1 bit 1 /
EricLew	0:d4e5ad7ad71c	1887	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /!< ADC JSQ1 bit 2 /
EricLew	0:d4e5ad7ad71c	1888	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /!< ADC JSQ1 bit 3 /
EricLew	0:d4e5ad7ad71c	1889	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /!< ADC JSQ1 bit 4 /
EricLew	0:d4e5ad7ad71c	1890
EricLew	0:d4e5ad7ad71c	1891	#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /!< ADC 2nd conversion in injected sequence /
EricLew	0:d4e5ad7ad71c	1892	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /!< ADC JSQ2 bit 0 /
EricLew	0:d4e5ad7ad71c	1893	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /!< ADC JSQ2 bit 1 /
EricLew	0:d4e5ad7ad71c	1894	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /!< ADC JSQ2 bit 2 /
EricLew	0:d4e5ad7ad71c	1895	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /!< ADC JSQ2 bit 3 /
EricLew	0:d4e5ad7ad71c	1896	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /!< ADC JSQ2 bit 4 /
EricLew	0:d4e5ad7ad71c	1897
EricLew	0:d4e5ad7ad71c	1898	#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /!< ADC 3rd conversion in injected sequence /
EricLew	0:d4e5ad7ad71c	1899	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /!< ADC JSQ3 bit 0 /
EricLew	0:d4e5ad7ad71c	1900	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /!< ADC JSQ3 bit 1 /
EricLew	0:d4e5ad7ad71c	1901	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /!< ADC JSQ3 bit 2 /
EricLew	0:d4e5ad7ad71c	1902	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /!< ADC JSQ3 bit 3 /
EricLew	0:d4e5ad7ad71c	1903	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /!< ADC JSQ3 bit 4 /
EricLew	0:d4e5ad7ad71c	1904
EricLew	0:d4e5ad7ad71c	1905	#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /!< ADC 4th conversion in injected sequence /
EricLew	0:d4e5ad7ad71c	1906	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /!< ADC JSQ4 bit 0 /
EricLew	0:d4e5ad7ad71c	1907	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /!< ADC JSQ4 bit 1 /
EricLew	0:d4e5ad7ad71c	1908	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /!< ADC JSQ4 bit 2 /
EricLew	0:d4e5ad7ad71c	1909	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /!< ADC JSQ4 bit 3 /
EricLew	0:d4e5ad7ad71c	1910	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /!< ADC JSQ4 bit 4 /
EricLew	0:d4e5ad7ad71c	1911
EricLew	0:d4e5ad7ad71c	1912
EricLew	0:d4e5ad7ad71c	1913	/****************** Bit definition for ADC_OFR1 register ******************/
EricLew	0:d4e5ad7ad71c	1914	#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] /
EricLew	0:d4e5ad7ad71c	1915	#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /!< ADC OFFSET1 bit 0 /
EricLew	0:d4e5ad7ad71c	1916	#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /!< ADC OFFSET1 bit 1 /
EricLew	0:d4e5ad7ad71c	1917	#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /!< ADC OFFSET1 bit 2 /
EricLew	0:d4e5ad7ad71c	1918	#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /!< ADC OFFSET1 bit 3 /
EricLew	0:d4e5ad7ad71c	1919	#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /!< ADC OFFSET1 bit 4 /
EricLew	0:d4e5ad7ad71c	1920	#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /!< ADC OFFSET1 bit 5 /
EricLew	0:d4e5ad7ad71c	1921	#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /!< ADC OFFSET1 bit 6 /
EricLew	0:d4e5ad7ad71c	1922	#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /!< ADC OFFSET1 bit 7 /
EricLew	0:d4e5ad7ad71c	1923	#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /!< ADC OFFSET1 bit 8 /
EricLew	0:d4e5ad7ad71c	1924	#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /!< ADC OFFSET1 bit 9 /
EricLew	0:d4e5ad7ad71c	1925	#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /!< ADC OFFSET1 bit 10 /
EricLew	0:d4e5ad7ad71c	1926	#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /!< ADC OFFSET1 bit 11 /
EricLew	0:d4e5ad7ad71c	1927
EricLew	0:d4e5ad7ad71c	1928	#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 1 /
EricLew	0:d4e5ad7ad71c	1929	#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET1_CH bit 0 /
EricLew	0:d4e5ad7ad71c	1930	#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET1_CH bit 1 /
EricLew	0:d4e5ad7ad71c	1931	#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET1_CH bit 2 /
EricLew	0:d4e5ad7ad71c	1932	#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET1_CH bit 3 /
EricLew	0:d4e5ad7ad71c	1933	#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET1_CH bit 4 /
EricLew	0:d4e5ad7ad71c	1934
EricLew	0:d4e5ad7ad71c	1935	#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /!< ADC offset 1 enable /
EricLew	0:d4e5ad7ad71c	1936
EricLew	0:d4e5ad7ad71c	1937	/****************** Bit definition for ADC_OFR2 register ******************/
EricLew	0:d4e5ad7ad71c	1938	#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] /
EricLew	0:d4e5ad7ad71c	1939	#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /!< ADC OFFSET2 bit 0 /
EricLew	0:d4e5ad7ad71c	1940	#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /!< ADC OFFSET2 bit 1 /
EricLew	0:d4e5ad7ad71c	1941	#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /!< ADC OFFSET2 bit 2 /
EricLew	0:d4e5ad7ad71c	1942	#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /!< ADC OFFSET2 bit 3 /
EricLew	0:d4e5ad7ad71c	1943	#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /!< ADC OFFSET2 bit 4 /
EricLew	0:d4e5ad7ad71c	1944	#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /!< ADC OFFSET2 bit 5 /
EricLew	0:d4e5ad7ad71c	1945	#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /!< ADC OFFSET2 bit 6 /
EricLew	0:d4e5ad7ad71c	1946	#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /!< ADC OFFSET2 bit 7 /
EricLew	0:d4e5ad7ad71c	1947	#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /!< ADC OFFSET2 bit 8 /
EricLew	0:d4e5ad7ad71c	1948	#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /!< ADC OFFSET2 bit 9 /
EricLew	0:d4e5ad7ad71c	1949	#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /!< ADC OFFSET2 bit 10 /
EricLew	0:d4e5ad7ad71c	1950	#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /!< ADC OFFSET2 bit 11 /
EricLew	0:d4e5ad7ad71c	1951
EricLew	0:d4e5ad7ad71c	1952	#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 2 /
EricLew	0:d4e5ad7ad71c	1953	#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET2_CH bit 0 /
EricLew	0:d4e5ad7ad71c	1954	#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET2_CH bit 1 /
EricLew	0:d4e5ad7ad71c	1955	#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET2_CH bit 2 /
EricLew	0:d4e5ad7ad71c	1956	#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET2_CH bit 3 /
EricLew	0:d4e5ad7ad71c	1957	#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET2_CH bit 4 /
EricLew	0:d4e5ad7ad71c	1958
EricLew	0:d4e5ad7ad71c	1959	#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /!< ADC offset 2 enable /
EricLew	0:d4e5ad7ad71c	1960
EricLew	0:d4e5ad7ad71c	1961	/****************** Bit definition for ADC_OFR3 register ******************/
EricLew	0:d4e5ad7ad71c	1962	#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] /
EricLew	0:d4e5ad7ad71c	1963	#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /!< ADC OFFSET3 bit 0 /
EricLew	0:d4e5ad7ad71c	1964	#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /!< ADC OFFSET3 bit 1 /
EricLew	0:d4e5ad7ad71c	1965	#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /!< ADC OFFSET3 bit 2 /
EricLew	0:d4e5ad7ad71c	1966	#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /!< ADC OFFSET3 bit 3 /
EricLew	0:d4e5ad7ad71c	1967	#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /!< ADC OFFSET3 bit 4 /
EricLew	0:d4e5ad7ad71c	1968	#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /!< ADC OFFSET3 bit 5 /
EricLew	0:d4e5ad7ad71c	1969	#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /!< ADC OFFSET3 bit 6 /
EricLew	0:d4e5ad7ad71c	1970	#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /!< ADC OFFSET3 bit 7 /
EricLew	0:d4e5ad7ad71c	1971	#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /!< ADC OFFSET3 bit 8 /
EricLew	0:d4e5ad7ad71c	1972	#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /!< ADC OFFSET3 bit 9 /
EricLew	0:d4e5ad7ad71c	1973	#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /!< ADC OFFSET3 bit 10 /
EricLew	0:d4e5ad7ad71c	1974	#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /!< ADC OFFSET3 bit 11 /
EricLew	0:d4e5ad7ad71c	1975
EricLew	0:d4e5ad7ad71c	1976	#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 3 /
EricLew	0:d4e5ad7ad71c	1977	#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET3_CH bit 0 /
EricLew	0:d4e5ad7ad71c	1978	#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET3_CH bit 1 /
EricLew	0:d4e5ad7ad71c	1979	#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET3_CH bit 2 /
EricLew	0:d4e5ad7ad71c	1980	#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET3_CH bit 3 /
EricLew	0:d4e5ad7ad71c	1981	#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET3_CH bit 4 /
EricLew	0:d4e5ad7ad71c	1982
EricLew	0:d4e5ad7ad71c	1983	#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /!< ADC offset 3 enable /
EricLew	0:d4e5ad7ad71c	1984
EricLew	0:d4e5ad7ad71c	1985	/****************** Bit definition for ADC_OFR4 register ******************/
EricLew	0:d4e5ad7ad71c	1986	#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] /
EricLew	0:d4e5ad7ad71c	1987	#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /!< ADC OFFSET4 bit 0 /
EricLew	0:d4e5ad7ad71c	1988	#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /!< ADC OFFSET4 bit 1 /
EricLew	0:d4e5ad7ad71c	1989	#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /!< ADC OFFSET4 bit 2 /
EricLew	0:d4e5ad7ad71c	1990	#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /!< ADC OFFSET4 bit 3 /
EricLew	0:d4e5ad7ad71c	1991	#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /!< ADC OFFSET4 bit 4 /
EricLew	0:d4e5ad7ad71c	1992	#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /!< ADC OFFSET4 bit 5 /
EricLew	0:d4e5ad7ad71c	1993	#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /!< ADC OFFSET4 bit 6 /
EricLew	0:d4e5ad7ad71c	1994	#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /!< ADC OFFSET4 bit 7 /
EricLew	0:d4e5ad7ad71c	1995	#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /!< ADC OFFSET4 bit 8 /
EricLew	0:d4e5ad7ad71c	1996	#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /!< ADC OFFSET4 bit 9 /
EricLew	0:d4e5ad7ad71c	1997	#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /!< ADC OFFSET4 bit 10 /
EricLew	0:d4e5ad7ad71c	1998	#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /!< ADC OFFSET4 bit 11 /
EricLew	0:d4e5ad7ad71c	1999
EricLew	0:d4e5ad7ad71c	2000	#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 4 /
EricLew	0:d4e5ad7ad71c	2001	#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET4_CH bit 0 /
EricLew	0:d4e5ad7ad71c	2002	#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET4_CH bit 1 /
EricLew	0:d4e5ad7ad71c	2003	#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET4_CH bit 2 /
EricLew	0:d4e5ad7ad71c	2004	#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET4_CH bit 3 /
EricLew	0:d4e5ad7ad71c	2005	#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET4_CH bit 4 /
EricLew	0:d4e5ad7ad71c	2006
EricLew	0:d4e5ad7ad71c	2007	#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /!< ADC offset 4 enable /
EricLew	0:d4e5ad7ad71c	2008
EricLew	0:d4e5ad7ad71c	2009	/****************** Bit definition for ADC_JDR1 register ******************/
EricLew	0:d4e5ad7ad71c	2010	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
EricLew	0:d4e5ad7ad71c	2011	#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
EricLew	0:d4e5ad7ad71c	2012	#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
EricLew	0:d4e5ad7ad71c	2013	#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
EricLew	0:d4e5ad7ad71c	2014	#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
EricLew	0:d4e5ad7ad71c	2015	#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
EricLew	0:d4e5ad7ad71c	2016	#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
EricLew	0:d4e5ad7ad71c	2017	#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
EricLew	0:d4e5ad7ad71c	2018	#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
EricLew	0:d4e5ad7ad71c	2019	#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
EricLew	0:d4e5ad7ad71c	2020	#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
EricLew	0:d4e5ad7ad71c	2021	#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
EricLew	0:d4e5ad7ad71c	2022	#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
EricLew	0:d4e5ad7ad71c	2023	#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
EricLew	0:d4e5ad7ad71c	2024	#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
EricLew	0:d4e5ad7ad71c	2025	#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
EricLew	0:d4e5ad7ad71c	2026	#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
EricLew	0:d4e5ad7ad71c	2027
EricLew	0:d4e5ad7ad71c	2028	/****************** Bit definition for ADC_JDR2 register ******************/
EricLew	0:d4e5ad7ad71c	2029	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
EricLew	0:d4e5ad7ad71c	2030	#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
EricLew	0:d4e5ad7ad71c	2031	#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
EricLew	0:d4e5ad7ad71c	2032	#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
EricLew	0:d4e5ad7ad71c	2033	#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
EricLew	0:d4e5ad7ad71c	2034	#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
EricLew	0:d4e5ad7ad71c	2035	#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
EricLew	0:d4e5ad7ad71c	2036	#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
EricLew	0:d4e5ad7ad71c	2037	#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
EricLew	0:d4e5ad7ad71c	2038	#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
EricLew	0:d4e5ad7ad71c	2039	#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
EricLew	0:d4e5ad7ad71c	2040	#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
EricLew	0:d4e5ad7ad71c	2041	#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
EricLew	0:d4e5ad7ad71c	2042	#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
EricLew	0:d4e5ad7ad71c	2043	#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
EricLew	0:d4e5ad7ad71c	2044	#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
EricLew	0:d4e5ad7ad71c	2045	#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
EricLew	0:d4e5ad7ad71c	2046
EricLew	0:d4e5ad7ad71c	2047	/****************** Bit definition for ADC_JDR3 register ******************/
EricLew	0:d4e5ad7ad71c	2048	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
EricLew	0:d4e5ad7ad71c	2049	#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
EricLew	0:d4e5ad7ad71c	2050	#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
EricLew	0:d4e5ad7ad71c	2051	#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
EricLew	0:d4e5ad7ad71c	2052	#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
EricLew	0:d4e5ad7ad71c	2053	#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
EricLew	0:d4e5ad7ad71c	2054	#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
EricLew	0:d4e5ad7ad71c	2055	#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
EricLew	0:d4e5ad7ad71c	2056	#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
EricLew	0:d4e5ad7ad71c	2057	#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
EricLew	0:d4e5ad7ad71c	2058	#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
EricLew	0:d4e5ad7ad71c	2059	#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
EricLew	0:d4e5ad7ad71c	2060	#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
EricLew	0:d4e5ad7ad71c	2061	#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
EricLew	0:d4e5ad7ad71c	2062	#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
EricLew	0:d4e5ad7ad71c	2063	#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
EricLew	0:d4e5ad7ad71c	2064	#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
EricLew	0:d4e5ad7ad71c	2065
EricLew	0:d4e5ad7ad71c	2066	/****************** Bit definition for ADC_JDR4 register ******************/
EricLew	0:d4e5ad7ad71c	2067	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
EricLew	0:d4e5ad7ad71c	2068	#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
EricLew	0:d4e5ad7ad71c	2069	#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
EricLew	0:d4e5ad7ad71c	2070	#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
EricLew	0:d4e5ad7ad71c	2071	#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
EricLew	0:d4e5ad7ad71c	2072	#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
EricLew	0:d4e5ad7ad71c	2073	#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
EricLew	0:d4e5ad7ad71c	2074	#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
EricLew	0:d4e5ad7ad71c	2075	#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
EricLew	0:d4e5ad7ad71c	2076	#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
EricLew	0:d4e5ad7ad71c	2077	#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
EricLew	0:d4e5ad7ad71c	2078	#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
EricLew	0:d4e5ad7ad71c	2079	#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
EricLew	0:d4e5ad7ad71c	2080	#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
EricLew	0:d4e5ad7ad71c	2081	#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
EricLew	0:d4e5ad7ad71c	2082	#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
EricLew	0:d4e5ad7ad71c	2083	#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
EricLew	0:d4e5ad7ad71c	2084
EricLew	0:d4e5ad7ad71c	2085	/****************** Bit definition for ADC_AWD2CR register ******************/
EricLew	0:d4e5ad7ad71c	2086	#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFF) /!< ADC Analog watchdog 2 channel selection /
EricLew	0:d4e5ad7ad71c	2087	#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000001) /!< ADC AWD2CH bit 0 /
EricLew	0:d4e5ad7ad71c	2088	#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000002) /!< ADC AWD2CH bit 1 /
EricLew	0:d4e5ad7ad71c	2089	#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000004) /!< ADC AWD2CH bit 2 /
EricLew	0:d4e5ad7ad71c	2090	#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000008) /!< ADC AWD2CH bit 3 /
EricLew	0:d4e5ad7ad71c	2091	#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000010) /!< ADC AWD2CH bit 4 /
EricLew	0:d4e5ad7ad71c	2092	#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000020) /!< ADC AWD2CH bit 5 /
EricLew	0:d4e5ad7ad71c	2093	#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000040) /!< ADC AWD2CH bit 6 /
EricLew	0:d4e5ad7ad71c	2094	#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000080) /!< ADC AWD2CH bit 7 /
EricLew	0:d4e5ad7ad71c	2095	#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000100) /!< ADC AWD2CH bit 8 /
EricLew	0:d4e5ad7ad71c	2096	#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000200) /!< ADC AWD2CH bit 9 /
EricLew	0:d4e5ad7ad71c	2097	#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000400) /!< ADC AWD2CH bit 10 /
EricLew	0:d4e5ad7ad71c	2098	#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00000800) /!< ADC AWD2CH bit 11 /
EricLew	0:d4e5ad7ad71c	2099	#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00001000) /!< ADC AWD2CH bit 12 /
EricLew	0:d4e5ad7ad71c	2100	#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00002000) /!< ADC AWD2CH bit 13 /
EricLew	0:d4e5ad7ad71c	2101	#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00004000) /!< ADC AWD2CH bit 14 /
EricLew	0:d4e5ad7ad71c	2102	#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00008000) /!< ADC AWD2CH bit 15 /
EricLew	0:d4e5ad7ad71c	2103	#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00010000) /!< ADC AWD2CH bit 16 /
EricLew	0:d4e5ad7ad71c	2104	#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00020000) /!< ADC AWD2CH bit 17 /
EricLew	0:d4e5ad7ad71c	2105	#define ADC_AWD2CR_AWD2CH_18 ((uint32_t)0x00040000) /!< ADC AWD2CH bit 18 /
EricLew	0:d4e5ad7ad71c	2106
EricLew	0:d4e5ad7ad71c	2107	/****************** Bit definition for ADC_AWD3CR register ******************/
EricLew	0:d4e5ad7ad71c	2108	#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFF) /!< ADC Analog watchdog 3 channel selection /
EricLew	0:d4e5ad7ad71c	2109	#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000001) /!< ADC AWD3CH bit 0 /
EricLew	0:d4e5ad7ad71c	2110	#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000002) /!< ADC AWD3CH bit 1 /
EricLew	0:d4e5ad7ad71c	2111	#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000004) /!< ADC AWD3CH bit 2 /
EricLew	0:d4e5ad7ad71c	2112	#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000008) /!< ADC AWD3CH bit 3 /
EricLew	0:d4e5ad7ad71c	2113	#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000010) /!< ADC AWD3CH bit 4 /
EricLew	0:d4e5ad7ad71c	2114	#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000020) /!< ADC AWD3CH bit 5 /
EricLew	0:d4e5ad7ad71c	2115	#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000040) /!< ADC AWD3CH bit 6 /
EricLew	0:d4e5ad7ad71c	2116	#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000080) /!< ADC AWD3CH bit 7 /
EricLew	0:d4e5ad7ad71c	2117	#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000100) /!< ADC AWD3CH bit 8 /
EricLew	0:d4e5ad7ad71c	2118	#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000200) /!< ADC AWD3CH bit 9 /
EricLew	0:d4e5ad7ad71c	2119	#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000400) /!< ADC AWD3CH bit 10 /
EricLew	0:d4e5ad7ad71c	2120	#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00000800) /!< ADC AWD3CH bit 11 /
EricLew	0:d4e5ad7ad71c	2121	#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00001000) /!< ADC AWD3CH bit 12 /
EricLew	0:d4e5ad7ad71c	2122	#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00002000) /!< ADC AWD3CH bit 13 /
EricLew	0:d4e5ad7ad71c	2123	#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00004000) /!< ADC AWD3CH bit 14 /
EricLew	0:d4e5ad7ad71c	2124	#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00008000) /!< ADC AWD3CH bit 15 /
EricLew	0:d4e5ad7ad71c	2125	#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00010000) /!< ADC AWD3CH bit 16 /
EricLew	0:d4e5ad7ad71c	2126	#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00020000) /!< ADC AWD3CH bit 17 /
EricLew	0:d4e5ad7ad71c	2127	#define ADC_AWD3CR_AWD3CH_18 ((uint32_t)0x00040000) /!< ADC AWD3CH bit 18 /
EricLew	0:d4e5ad7ad71c	2128
EricLew	0:d4e5ad7ad71c	2129	/****************** Bit definition for ADC_DIFSEL register ******************/
EricLew	0:d4e5ad7ad71c	2130	#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFF) /!< ADC differential modes for channels 1 to 18 /
EricLew	0:d4e5ad7ad71c	2131	#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000001) /!< ADC DIFSEL bit 0 /
EricLew	0:d4e5ad7ad71c	2132	#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000002) /!< ADC DIFSEL bit 1 /
EricLew	0:d4e5ad7ad71c	2133	#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000004) /!< ADC DIFSEL bit 2 /
EricLew	0:d4e5ad7ad71c	2134	#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000008) /!< ADC DIFSEL bit 3 /
EricLew	0:d4e5ad7ad71c	2135	#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000010) /!< ADC DIFSEL bit 4 /
EricLew	0:d4e5ad7ad71c	2136	#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000020) /!< ADC DIFSEL bit 5 /
EricLew	0:d4e5ad7ad71c	2137	#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000040) /!< ADC DIFSEL bit 6 /
EricLew	0:d4e5ad7ad71c	2138	#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000080) /!< ADC DIFSEL bit 7 /
EricLew	0:d4e5ad7ad71c	2139	#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000100) /!< ADC DIFSEL bit 8 /
EricLew	0:d4e5ad7ad71c	2140	#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000200) /!< ADC DIFSEL bit 9 /
EricLew	0:d4e5ad7ad71c	2141	#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000400) /!< ADC DIFSEL bit 10 /
EricLew	0:d4e5ad7ad71c	2142	#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00000800) /!< ADC DIFSEL bit 11 /
EricLew	0:d4e5ad7ad71c	2143	#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00001000) /!< ADC DIFSEL bit 12 /
EricLew	0:d4e5ad7ad71c	2144	#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00002000) /!< ADC DIFSEL bit 13 /
EricLew	0:d4e5ad7ad71c	2145	#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00004000) /!< ADC DIFSEL bit 14 /
EricLew	0:d4e5ad7ad71c	2146	#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00008000) /!< ADC DIFSEL bit 15 /
EricLew	0:d4e5ad7ad71c	2147	#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00010000) /!< ADC DIFSEL bit 16 /
EricLew	0:d4e5ad7ad71c	2148	#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00020000) /!< ADC DIFSEL bit 17 /
EricLew	0:d4e5ad7ad71c	2149	#define ADC_DIFSEL_DIFSEL_18 ((uint32_t)0x00040000) /!< ADC DIFSEL bit 18 /
EricLew	0:d4e5ad7ad71c	2150
EricLew	0:d4e5ad7ad71c	2151	/****************** Bit definition for ADC_CALFACT register ******************/
EricLew	0:d4e5ad7ad71c	2152	#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /!< ADC calibration factors in single-ended mode /
EricLew	0:d4e5ad7ad71c	2153	#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /!< ADC CALFACT_S bit 0 /
EricLew	0:d4e5ad7ad71c	2154	#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /!< ADC CALFACT_S bit 1 /
EricLew	0:d4e5ad7ad71c	2155	#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /!< ADC CALFACT_S bit 2 /
EricLew	0:d4e5ad7ad71c	2156	#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /!< ADC CALFACT_S bit 3 /
EricLew	0:d4e5ad7ad71c	2157	#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /!< ADC CALFACT_S bit 4 /
EricLew	0:d4e5ad7ad71c	2158	#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /!< ADC CALFACT_S bit 5 /
EricLew	0:d4e5ad7ad71c	2159	#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /!< ADC CALFACT_S bit 6 /
EricLew	0:d4e5ad7ad71c	2160
EricLew	0:d4e5ad7ad71c	2161	#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /!< ADC calibration factors in differential mode /
EricLew	0:d4e5ad7ad71c	2162	#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /!< ADC CALFACT_D bit 0 /
EricLew	0:d4e5ad7ad71c	2163	#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /!< ADC CALFACT_D bit 1 /
EricLew	0:d4e5ad7ad71c	2164	#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /!< ADC CALFACT_D bit 2 /
EricLew	0:d4e5ad7ad71c	2165	#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /!< ADC CALFACT_D bit 3 /
EricLew	0:d4e5ad7ad71c	2166	#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /!< ADC CALFACT_D bit 4 /
EricLew	0:d4e5ad7ad71c	2167	#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /!< ADC CALFACT_D bit 5 /
EricLew	0:d4e5ad7ad71c	2168	#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /!< ADC CALFACT_D bit 6 /
EricLew	0:d4e5ad7ad71c	2169
EricLew	0:d4e5ad7ad71c	2170	/*********************** ADC Common registers ***************************/
EricLew	0:d4e5ad7ad71c	2171	/****************** Bit definition for ADC_CSR register ******************/
EricLew	0:d4e5ad7ad71c	2172	#define ADC_CSR_ADRDY_MST ((uint32_t)0x00000001) /!< Master ADC ready /
EricLew	0:d4e5ad7ad71c	2173	#define ADC_CSR_EOSMP_MST ((uint32_t)0x00000002) /!< End of sampling phase flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2174	#define ADC_CSR_EOC_MST ((uint32_t)0x00000004) /!< End of regular conversion of the master ADC /
EricLew	0:d4e5ad7ad71c	2175	#define ADC_CSR_EOS_MST ((uint32_t)0x00000008) /!< End of regular sequence flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2176	#define ADC_CSR_OVR_MST ((uint32_t)0x00000010) /!< Overrun flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2177	#define ADC_CSR_JEOC_MST ((uint32_t)0x00000020) /!< End of injected conversion of the master ADC /
EricLew	0:d4e5ad7ad71c	2178	#define ADC_CSR_JEOS_MST ((uint32_t)0x00000040) /!< End of injected sequence flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2179	#define ADC_CSR_AWD1_MST ((uint32_t)0x00000080) /!< Analog watchdog 1 flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2180	#define ADC_CSR_AWD2_MST ((uint32_t)0x00000100) /!< Analog watchdog 2 flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2181	#define ADC_CSR_AWD3_MST ((uint32_t)0x00000200) /!< Analog watchdog 3 flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2182	#define ADC_CSR_JQOVF_MST ((uint32_t)0x00000400) /!< Injected context queue overflow flag of the master ADC /
EricLew	0:d4e5ad7ad71c	2183
EricLew	0:d4e5ad7ad71c	2184	#define ADC_CSR_ADRDY_SLV ((uint32_t)0x00010000) /!< Slave ADC ready /
EricLew	0:d4e5ad7ad71c	2185	#define ADC_CSR_EOSMP_SLV ((uint32_t)0x00020000) /!< End of sampling phase flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2186	#define ADC_CSR_EOC_SLV ((uint32_t)0x00040000) /!< End of regular conversion of the slave ADC /
EricLew	0:d4e5ad7ad71c	2187	#define ADC_CSR_EOS_SLV ((uint32_t)0x00080000) /!< End of regular sequence flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2188	#define ADC_CSR_OVR_SLV ((uint32_t)0x00100000) /!< Overrun flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2189	#define ADC_CSR_JEOC_SLV ((uint32_t)0x00200000) /!< End of injected conversion of the slave ADC /
EricLew	0:d4e5ad7ad71c	2190	#define ADC_CSR_JEOS_SLV ((uint32_t)0x00400000) /!< End of injected sequence flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2191	#define ADC_CSR_AWD1_SLV ((uint32_t)0x00800000) /!< Analog watchdog 1 flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2192	#define ADC_CSR_AWD2_SLV ((uint32_t)0x01000000) /!< Analog watchdog 2 flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2193	#define ADC_CSR_AWD3_SLV ((uint32_t)0x02000000) /!< Analog watchdog 3 flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2194	#define ADC_CSR_JQOVF_SLV ((uint32_t)0x04000000) /!< Injected context queue overflow flag of the slave ADC /
EricLew	0:d4e5ad7ad71c	2195
EricLew	0:d4e5ad7ad71c	2196	/****************** Bit definition for ADC_CCR register ******************/
EricLew	0:d4e5ad7ad71c	2197	#define ADC_CCR_DUAL ((uint32_t)0x0000001F) /!< Dual ADC mode selection /
EricLew	0:d4e5ad7ad71c	2198	#define ADC_CCR_DUAL_0 ((uint32_t)0x00000001) /!< Dual bit 0 /
EricLew	0:d4e5ad7ad71c	2199	#define ADC_CCR_DUAL_1 ((uint32_t)0x00000002) /!< Dual bit 1 /
EricLew	0:d4e5ad7ad71c	2200	#define ADC_CCR_DUAL_2 ((uint32_t)0x00000004) /!< Dual bit 2 /
EricLew	0:d4e5ad7ad71c	2201	#define ADC_CCR_DUAL_3 ((uint32_t)0x00000008) /!< Dual bit 3 /
EricLew	0:d4e5ad7ad71c	2202	#define ADC_CCR_DUAL_4 ((uint32_t)0x00000010) /!< Dual bit 4 /
EricLew	0:d4e5ad7ad71c	2203
EricLew	0:d4e5ad7ad71c	2204	#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /!< Delay between 2 sampling phases /
EricLew	0:d4e5ad7ad71c	2205	#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /!< DELAY bit 0 /
EricLew	0:d4e5ad7ad71c	2206	#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /!< DELAY bit 1 /
EricLew	0:d4e5ad7ad71c	2207	#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /!< DELAY bit 2 /
EricLew	0:d4e5ad7ad71c	2208	#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /!< DELAY bit 3 /
EricLew	0:d4e5ad7ad71c	2209
EricLew	0:d4e5ad7ad71c	2210	#define ADC_CCR_DMACFG ((uint32_t)0x00002000) /!< DMA configuration for multi-ADC mode /
EricLew	0:d4e5ad7ad71c	2211
EricLew	0:d4e5ad7ad71c	2212	#define ADC_CCR_MDMA ((uint32_t)0x0000C000) /!< DMA mode for multi-ADC mode /
EricLew	0:d4e5ad7ad71c	2213	#define ADC_CCR_MDMA_0 ((uint32_t)0x00004000) /!< MDMA bit 0 /
EricLew	0:d4e5ad7ad71c	2214	#define ADC_CCR_MDMA_1 ((uint32_t)0x00008000) /!< MDMA bit 1 /
EricLew	0:d4e5ad7ad71c	2215
EricLew	0:d4e5ad7ad71c	2216	#define ADC_CCR_CKMODE ((uint32_t)0x00030000) /!< ADC clock mode /
EricLew	0:d4e5ad7ad71c	2217	#define ADC_CCR_CKMODE_0 ((uint32_t)0x00010000) /!< CKMODE bit 0 /
EricLew	0:d4e5ad7ad71c	2218	#define ADC_CCR_CKMODE_1 ((uint32_t)0x00020000) /!< CKMODE bit 1 /
EricLew	0:d4e5ad7ad71c	2219
EricLew	0:d4e5ad7ad71c	2220	#define ADC_CCR_PRESC ((uint32_t)0x003C0000) /!< ADC prescaler /
EricLew	0:d4e5ad7ad71c	2221	#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000) /!< ADC prescaler bit 0 /
EricLew	0:d4e5ad7ad71c	2222	#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000) /!< ADC prescaler bit 1 /
EricLew	0:d4e5ad7ad71c	2223	#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000) /!< ADC prescaler bit 2 /
EricLew	0:d4e5ad7ad71c	2224	#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000) /!< ADC prescaler bit 3 /
EricLew	0:d4e5ad7ad71c	2225
EricLew	0:d4e5ad7ad71c	2226	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< VREFINT enable /
EricLew	0:d4e5ad7ad71c	2227	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Temperature sensor enable /
EricLew	0:d4e5ad7ad71c	2228	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< VBAT enable /
EricLew	0:d4e5ad7ad71c	2229
EricLew	0:d4e5ad7ad71c	2230	/****************** Bit definition for ADC_CDR register ******************/
EricLew	0:d4e5ad7ad71c	2231	#define ADC_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /!< Regular Data of the master ADC /
EricLew	0:d4e5ad7ad71c	2232	#define ADC_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /!< RDATA_MST bit 0 /
EricLew	0:d4e5ad7ad71c	2233	#define ADC_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /!< RDATA_MST bit 1 /
EricLew	0:d4e5ad7ad71c	2234	#define ADC_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /!< RDATA_MST bit 2 /
EricLew	0:d4e5ad7ad71c	2235	#define ADC_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /!< RDATA_MST bit 3 /
EricLew	0:d4e5ad7ad71c	2236	#define ADC_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /!< RDATA_MST bit 4 /
EricLew	0:d4e5ad7ad71c	2237	#define ADC_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /!< RDATA_MST bit 5 /
EricLew	0:d4e5ad7ad71c	2238	#define ADC_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /!< RDATA_MST bit 6 /
EricLew	0:d4e5ad7ad71c	2239	#define ADC_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /!< RDATA_MST bit 7 /
EricLew	0:d4e5ad7ad71c	2240	#define ADC_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /!< RDATA_MST bit 8 /
EricLew	0:d4e5ad7ad71c	2241	#define ADC_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /!< RDATA_MST bit 9 /
EricLew	0:d4e5ad7ad71c	2242	#define ADC_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /!< RDATA_MST bit 10 /
EricLew	0:d4e5ad7ad71c	2243	#define ADC_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /!< RDATA_MST bit 11 /
EricLew	0:d4e5ad7ad71c	2244	#define ADC_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /!< RDATA_MST bit 12 /
EricLew	0:d4e5ad7ad71c	2245	#define ADC_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /!< RDATA_MST bit 13 /
EricLew	0:d4e5ad7ad71c	2246	#define ADC_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /!< RDATA_MST bit 14 /
EricLew	0:d4e5ad7ad71c	2247	#define ADC_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /!< RDATA_MST bit 15 /
EricLew	0:d4e5ad7ad71c	2248
EricLew	0:d4e5ad7ad71c	2249	#define ADC_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /!< Regular Data of the master ADC /
EricLew	0:d4e5ad7ad71c	2250	#define ADC_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /!< RDATA_SLV bit 0 /
EricLew	0:d4e5ad7ad71c	2251	#define ADC_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /!< RDATA_SLV bit 1 /
EricLew	0:d4e5ad7ad71c	2252	#define ADC_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /!< RDATA_SLV bit 2 /
EricLew	0:d4e5ad7ad71c	2253	#define ADC_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /!< RDATA_SLV bit 3 /
EricLew	0:d4e5ad7ad71c	2254	#define ADC_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /!< RDATA_SLV bit 4 /
EricLew	0:d4e5ad7ad71c	2255	#define ADC_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /!< RDATA_SLV bit 5 /
EricLew	0:d4e5ad7ad71c	2256	#define ADC_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /!< RDATA_SLV bit 6 /
EricLew	0:d4e5ad7ad71c	2257	#define ADC_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /!< RDATA_SLV bit 7 /
EricLew	0:d4e5ad7ad71c	2258	#define ADC_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /!< RDATA_SLV bit 8 /
EricLew	0:d4e5ad7ad71c	2259	#define ADC_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /!< RDATA_SLV bit 9 /
EricLew	0:d4e5ad7ad71c	2260	#define ADC_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /!< RDATA_SLV bit 10 /
EricLew	0:d4e5ad7ad71c	2261	#define ADC_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /!< RDATA_SLV bit 11 /
EricLew	0:d4e5ad7ad71c	2262	#define ADC_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /!< RDATA_SLV bit 12 /
EricLew	0:d4e5ad7ad71c	2263	#define ADC_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /!< RDATA_SLV bit 13 /
EricLew	0:d4e5ad7ad71c	2264	#define ADC_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /!< RDATA_SLV bit 14 /
EricLew	0:d4e5ad7ad71c	2265	#define ADC_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /!< RDATA_SLV bit 15 /
EricLew	0:d4e5ad7ad71c	2266
EricLew	0:d4e5ad7ad71c	2267	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	2268	/* */
EricLew	0:d4e5ad7ad71c	2269	/* Controller Area Network */
EricLew	0:d4e5ad7ad71c	2270	/* */
EricLew	0:d4e5ad7ad71c	2271	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	2272	/!<CAN control and status registers /
EricLew	0:d4e5ad7ad71c	2273	/***************** Bit definition for CAN_MCR register ******************/
EricLew	0:d4e5ad7ad71c	2274	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
EricLew	0:d4e5ad7ad71c	2275	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
EricLew	0:d4e5ad7ad71c	2276	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
EricLew	0:d4e5ad7ad71c	2277	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
EricLew	0:d4e5ad7ad71c	2278	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
EricLew	0:d4e5ad7ad71c	2279	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
EricLew	0:d4e5ad7ad71c	2280	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
EricLew	0:d4e5ad7ad71c	2281	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
EricLew	0:d4e5ad7ad71c	2282	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
EricLew	0:d4e5ad7ad71c	2283
EricLew	0:d4e5ad7ad71c	2284	/***************** Bit definition for CAN_MSR register ******************/
EricLew	0:d4e5ad7ad71c	2285	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
EricLew	0:d4e5ad7ad71c	2286	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
EricLew	0:d4e5ad7ad71c	2287	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
EricLew	0:d4e5ad7ad71c	2288	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
EricLew	0:d4e5ad7ad71c	2289	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
EricLew	0:d4e5ad7ad71c	2290	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
EricLew	0:d4e5ad7ad71c	2291	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
EricLew	0:d4e5ad7ad71c	2292	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
EricLew	0:d4e5ad7ad71c	2293	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
EricLew	0:d4e5ad7ad71c	2294
EricLew	0:d4e5ad7ad71c	2295	/***************** Bit definition for CAN_TSR register ******************/
EricLew	0:d4e5ad7ad71c	2296	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
EricLew	0:d4e5ad7ad71c	2297	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
EricLew	0:d4e5ad7ad71c	2298	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
EricLew	0:d4e5ad7ad71c	2299	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
EricLew	0:d4e5ad7ad71c	2300	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
EricLew	0:d4e5ad7ad71c	2301	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
EricLew	0:d4e5ad7ad71c	2302	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
EricLew	0:d4e5ad7ad71c	2303	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
EricLew	0:d4e5ad7ad71c	2304	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
EricLew	0:d4e5ad7ad71c	2305	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
EricLew	0:d4e5ad7ad71c	2306	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
EricLew	0:d4e5ad7ad71c	2307	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
EricLew	0:d4e5ad7ad71c	2308	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
EricLew	0:d4e5ad7ad71c	2309	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
EricLew	0:d4e5ad7ad71c	2310	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
EricLew	0:d4e5ad7ad71c	2311	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
EricLew	0:d4e5ad7ad71c	2312
EricLew	0:d4e5ad7ad71c	2313	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
EricLew	0:d4e5ad7ad71c	2314	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
EricLew	0:d4e5ad7ad71c	2315	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
EricLew	0:d4e5ad7ad71c	2316	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
EricLew	0:d4e5ad7ad71c	2317
EricLew	0:d4e5ad7ad71c	2318	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
EricLew	0:d4e5ad7ad71c	2319	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
EricLew	0:d4e5ad7ad71c	2320	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
EricLew	0:d4e5ad7ad71c	2321	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
EricLew	0:d4e5ad7ad71c	2322
EricLew	0:d4e5ad7ad71c	2323	/***************** Bit definition for CAN_RF0R register *****************/
EricLew	0:d4e5ad7ad71c	2324	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
EricLew	0:d4e5ad7ad71c	2325	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
EricLew	0:d4e5ad7ad71c	2326	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
EricLew	0:d4e5ad7ad71c	2327	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
EricLew	0:d4e5ad7ad71c	2328
EricLew	0:d4e5ad7ad71c	2329	/***************** Bit definition for CAN_RF1R register *****************/
EricLew	0:d4e5ad7ad71c	2330	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
EricLew	0:d4e5ad7ad71c	2331	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
EricLew	0:d4e5ad7ad71c	2332	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
EricLew	0:d4e5ad7ad71c	2333	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
EricLew	0:d4e5ad7ad71c	2334
EricLew	0:d4e5ad7ad71c	2335	/****************** Bit definition for CAN_IER register *****************/
EricLew	0:d4e5ad7ad71c	2336	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2337	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2338	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2339	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2340	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2341	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2342	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2343	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2344	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2345	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2346	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2347	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2348	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2349	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
EricLew	0:d4e5ad7ad71c	2350
EricLew	0:d4e5ad7ad71c	2351	/****************** Bit definition for CAN_ESR register *****************/
EricLew	0:d4e5ad7ad71c	2352	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
EricLew	0:d4e5ad7ad71c	2353	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
EricLew	0:d4e5ad7ad71c	2354	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
EricLew	0:d4e5ad7ad71c	2355
EricLew	0:d4e5ad7ad71c	2356	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
EricLew	0:d4e5ad7ad71c	2357	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	2358	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	2359	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	2360
EricLew	0:d4e5ad7ad71c	2361	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
EricLew	0:d4e5ad7ad71c	2362	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
EricLew	0:d4e5ad7ad71c	2363
EricLew	0:d4e5ad7ad71c	2364	/***************** Bit definition for CAN_BTR register ******************/
EricLew	0:d4e5ad7ad71c	2365	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
EricLew	0:d4e5ad7ad71c	2366	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
EricLew	0:d4e5ad7ad71c	2367	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
EricLew	0:d4e5ad7ad71c	2368	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
EricLew	0:d4e5ad7ad71c	2369	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
EricLew	0:d4e5ad7ad71c	2370	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
EricLew	0:d4e5ad7ad71c	2371	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
EricLew	0:d4e5ad7ad71c	2372	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
EricLew	0:d4e5ad7ad71c	2373	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
EricLew	0:d4e5ad7ad71c	2374	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
EricLew	0:d4e5ad7ad71c	2375	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
EricLew	0:d4e5ad7ad71c	2376	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
EricLew	0:d4e5ad7ad71c	2377	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
EricLew	0:d4e5ad7ad71c	2378	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
EricLew	0:d4e5ad7ad71c	2379	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
EricLew	0:d4e5ad7ad71c	2380
EricLew	0:d4e5ad7ad71c	2381	/!<Mailbox registers /
EricLew	0:d4e5ad7ad71c	2382	/**************** Bit definition for CAN_TI0R register ******************/
EricLew	0:d4e5ad7ad71c	2383	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
EricLew	0:d4e5ad7ad71c	2384	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
EricLew	0:d4e5ad7ad71c	2385	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
EricLew	0:d4e5ad7ad71c	2386	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
EricLew	0:d4e5ad7ad71c	2387	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
EricLew	0:d4e5ad7ad71c	2388
EricLew	0:d4e5ad7ad71c	2389	/**************** Bit definition for CAN_TDT0R register *****************/
EricLew	0:d4e5ad7ad71c	2390	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
EricLew	0:d4e5ad7ad71c	2391	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
EricLew	0:d4e5ad7ad71c	2392	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
EricLew	0:d4e5ad7ad71c	2393
EricLew	0:d4e5ad7ad71c	2394	/**************** Bit definition for CAN_TDL0R register *****************/
EricLew	0:d4e5ad7ad71c	2395	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
EricLew	0:d4e5ad7ad71c	2396	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
EricLew	0:d4e5ad7ad71c	2397	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
EricLew	0:d4e5ad7ad71c	2398	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
EricLew	0:d4e5ad7ad71c	2399
EricLew	0:d4e5ad7ad71c	2400	/**************** Bit definition for CAN_TDH0R register *****************/
EricLew	0:d4e5ad7ad71c	2401	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
EricLew	0:d4e5ad7ad71c	2402	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
EricLew	0:d4e5ad7ad71c	2403	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
EricLew	0:d4e5ad7ad71c	2404	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
EricLew	0:d4e5ad7ad71c	2405
EricLew	0:d4e5ad7ad71c	2406	/***************** Bit definition for CAN_TI1R register *****************/
EricLew	0:d4e5ad7ad71c	2407	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
EricLew	0:d4e5ad7ad71c	2408	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
EricLew	0:d4e5ad7ad71c	2409	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
EricLew	0:d4e5ad7ad71c	2410	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
EricLew	0:d4e5ad7ad71c	2411	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
EricLew	0:d4e5ad7ad71c	2412
EricLew	0:d4e5ad7ad71c	2413	/***************** Bit definition for CAN_TDT1R register ****************/
EricLew	0:d4e5ad7ad71c	2414	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
EricLew	0:d4e5ad7ad71c	2415	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
EricLew	0:d4e5ad7ad71c	2416	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
EricLew	0:d4e5ad7ad71c	2417
EricLew	0:d4e5ad7ad71c	2418	/***************** Bit definition for CAN_TDL1R register ****************/
EricLew	0:d4e5ad7ad71c	2419	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
EricLew	0:d4e5ad7ad71c	2420	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
EricLew	0:d4e5ad7ad71c	2421	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
EricLew	0:d4e5ad7ad71c	2422	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
EricLew	0:d4e5ad7ad71c	2423
EricLew	0:d4e5ad7ad71c	2424	/***************** Bit definition for CAN_TDH1R register ****************/
EricLew	0:d4e5ad7ad71c	2425	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
EricLew	0:d4e5ad7ad71c	2426	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
EricLew	0:d4e5ad7ad71c	2427	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
EricLew	0:d4e5ad7ad71c	2428	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
EricLew	0:d4e5ad7ad71c	2429
EricLew	0:d4e5ad7ad71c	2430	/***************** Bit definition for CAN_TI2R register *****************/
EricLew	0:d4e5ad7ad71c	2431	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
EricLew	0:d4e5ad7ad71c	2432	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
EricLew	0:d4e5ad7ad71c	2433	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
EricLew	0:d4e5ad7ad71c	2434	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
EricLew	0:d4e5ad7ad71c	2435	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
EricLew	0:d4e5ad7ad71c	2436
EricLew	0:d4e5ad7ad71c	2437	/***************** Bit definition for CAN_TDT2R register ****************/
EricLew	0:d4e5ad7ad71c	2438	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
EricLew	0:d4e5ad7ad71c	2439	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
EricLew	0:d4e5ad7ad71c	2440	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
EricLew	0:d4e5ad7ad71c	2441
EricLew	0:d4e5ad7ad71c	2442	/***************** Bit definition for CAN_TDL2R register ****************/
EricLew	0:d4e5ad7ad71c	2443	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
EricLew	0:d4e5ad7ad71c	2444	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
EricLew	0:d4e5ad7ad71c	2445	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
EricLew	0:d4e5ad7ad71c	2446	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
EricLew	0:d4e5ad7ad71c	2447
EricLew	0:d4e5ad7ad71c	2448	/***************** Bit definition for CAN_TDH2R register ****************/
EricLew	0:d4e5ad7ad71c	2449	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
EricLew	0:d4e5ad7ad71c	2450	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
EricLew	0:d4e5ad7ad71c	2451	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
EricLew	0:d4e5ad7ad71c	2452	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
EricLew	0:d4e5ad7ad71c	2453
EricLew	0:d4e5ad7ad71c	2454	/***************** Bit definition for CAN_RI0R register *****************/
EricLew	0:d4e5ad7ad71c	2455	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
EricLew	0:d4e5ad7ad71c	2456	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
EricLew	0:d4e5ad7ad71c	2457	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
EricLew	0:d4e5ad7ad71c	2458	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
EricLew	0:d4e5ad7ad71c	2459
EricLew	0:d4e5ad7ad71c	2460	/***************** Bit definition for CAN_RDT0R register ****************/
EricLew	0:d4e5ad7ad71c	2461	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
EricLew	0:d4e5ad7ad71c	2462	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
EricLew	0:d4e5ad7ad71c	2463	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
EricLew	0:d4e5ad7ad71c	2464
EricLew	0:d4e5ad7ad71c	2465	/***************** Bit definition for CAN_RDL0R register ****************/
EricLew	0:d4e5ad7ad71c	2466	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
EricLew	0:d4e5ad7ad71c	2467	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
EricLew	0:d4e5ad7ad71c	2468	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
EricLew	0:d4e5ad7ad71c	2469	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
EricLew	0:d4e5ad7ad71c	2470
EricLew	0:d4e5ad7ad71c	2471	/***************** Bit definition for CAN_RDH0R register ****************/
EricLew	0:d4e5ad7ad71c	2472	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
EricLew	0:d4e5ad7ad71c	2473	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
EricLew	0:d4e5ad7ad71c	2474	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
EricLew	0:d4e5ad7ad71c	2475	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
EricLew	0:d4e5ad7ad71c	2476
EricLew	0:d4e5ad7ad71c	2477	/***************** Bit definition for CAN_RI1R register *****************/
EricLew	0:d4e5ad7ad71c	2478	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
EricLew	0:d4e5ad7ad71c	2479	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
EricLew	0:d4e5ad7ad71c	2480	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
EricLew	0:d4e5ad7ad71c	2481	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
EricLew	0:d4e5ad7ad71c	2482
EricLew	0:d4e5ad7ad71c	2483	/***************** Bit definition for CAN_RDT1R register ****************/
EricLew	0:d4e5ad7ad71c	2484	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
EricLew	0:d4e5ad7ad71c	2485	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
EricLew	0:d4e5ad7ad71c	2486	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
EricLew	0:d4e5ad7ad71c	2487
EricLew	0:d4e5ad7ad71c	2488	/***************** Bit definition for CAN_RDL1R register ****************/
EricLew	0:d4e5ad7ad71c	2489	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
EricLew	0:d4e5ad7ad71c	2490	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
EricLew	0:d4e5ad7ad71c	2491	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
EricLew	0:d4e5ad7ad71c	2492	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
EricLew	0:d4e5ad7ad71c	2493
EricLew	0:d4e5ad7ad71c	2494	/***************** Bit definition for CAN_RDH1R register ****************/
EricLew	0:d4e5ad7ad71c	2495	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
EricLew	0:d4e5ad7ad71c	2496	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
EricLew	0:d4e5ad7ad71c	2497	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
EricLew	0:d4e5ad7ad71c	2498	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
EricLew	0:d4e5ad7ad71c	2499
EricLew	0:d4e5ad7ad71c	2500	/!<CAN filter registers /
EricLew	0:d4e5ad7ad71c	2501	/***************** Bit definition for CAN_FMR register ******************/
EricLew	0:d4e5ad7ad71c	2502	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
EricLew	0:d4e5ad7ad71c	2503
EricLew	0:d4e5ad7ad71c	2504	/***************** Bit definition for CAN_FM1R register *****************/
EricLew	0:d4e5ad7ad71c	2505	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
EricLew	0:d4e5ad7ad71c	2506	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
EricLew	0:d4e5ad7ad71c	2507	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
EricLew	0:d4e5ad7ad71c	2508	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
EricLew	0:d4e5ad7ad71c	2509	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
EricLew	0:d4e5ad7ad71c	2510	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
EricLew	0:d4e5ad7ad71c	2511	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
EricLew	0:d4e5ad7ad71c	2512	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
EricLew	0:d4e5ad7ad71c	2513	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
EricLew	0:d4e5ad7ad71c	2514	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
EricLew	0:d4e5ad7ad71c	2515	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
EricLew	0:d4e5ad7ad71c	2516	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
EricLew	0:d4e5ad7ad71c	2517	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
EricLew	0:d4e5ad7ad71c	2518	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
EricLew	0:d4e5ad7ad71c	2519	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
EricLew	0:d4e5ad7ad71c	2520
EricLew	0:d4e5ad7ad71c	2521	/***************** Bit definition for CAN_FS1R register *****************/
EricLew	0:d4e5ad7ad71c	2522	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
EricLew	0:d4e5ad7ad71c	2523	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
EricLew	0:d4e5ad7ad71c	2524	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
EricLew	0:d4e5ad7ad71c	2525	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
EricLew	0:d4e5ad7ad71c	2526	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
EricLew	0:d4e5ad7ad71c	2527	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
EricLew	0:d4e5ad7ad71c	2528	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
EricLew	0:d4e5ad7ad71c	2529	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
EricLew	0:d4e5ad7ad71c	2530	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
EricLew	0:d4e5ad7ad71c	2531	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
EricLew	0:d4e5ad7ad71c	2532	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
EricLew	0:d4e5ad7ad71c	2533	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
EricLew	0:d4e5ad7ad71c	2534	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
EricLew	0:d4e5ad7ad71c	2535	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
EricLew	0:d4e5ad7ad71c	2536	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
EricLew	0:d4e5ad7ad71c	2537
EricLew	0:d4e5ad7ad71c	2538	/**************** Bit definition for CAN_FFA1R register *****************/
EricLew	0:d4e5ad7ad71c	2539	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
EricLew	0:d4e5ad7ad71c	2540	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
EricLew	0:d4e5ad7ad71c	2541	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
EricLew	0:d4e5ad7ad71c	2542	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
EricLew	0:d4e5ad7ad71c	2543	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
EricLew	0:d4e5ad7ad71c	2544	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
EricLew	0:d4e5ad7ad71c	2545	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
EricLew	0:d4e5ad7ad71c	2546	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
EricLew	0:d4e5ad7ad71c	2547	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
EricLew	0:d4e5ad7ad71c	2548	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
EricLew	0:d4e5ad7ad71c	2549	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
EricLew	0:d4e5ad7ad71c	2550	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
EricLew	0:d4e5ad7ad71c	2551	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
EricLew	0:d4e5ad7ad71c	2552	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
EricLew	0:d4e5ad7ad71c	2553	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
EricLew	0:d4e5ad7ad71c	2554
EricLew	0:d4e5ad7ad71c	2555	/***************** Bit definition for CAN_FA1R register *****************/
EricLew	0:d4e5ad7ad71c	2556	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
EricLew	0:d4e5ad7ad71c	2557	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
EricLew	0:d4e5ad7ad71c	2558	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
EricLew	0:d4e5ad7ad71c	2559	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
EricLew	0:d4e5ad7ad71c	2560	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
EricLew	0:d4e5ad7ad71c	2561	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
EricLew	0:d4e5ad7ad71c	2562	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
EricLew	0:d4e5ad7ad71c	2563	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
EricLew	0:d4e5ad7ad71c	2564	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
EricLew	0:d4e5ad7ad71c	2565	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
EricLew	0:d4e5ad7ad71c	2566	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
EricLew	0:d4e5ad7ad71c	2567	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
EricLew	0:d4e5ad7ad71c	2568	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
EricLew	0:d4e5ad7ad71c	2569	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
EricLew	0:d4e5ad7ad71c	2570	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
EricLew	0:d4e5ad7ad71c	2571
EricLew	0:d4e5ad7ad71c	2572	/***************** Bit definition for CAN_F0R1 register *****************/
EricLew	0:d4e5ad7ad71c	2573	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2574	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2575	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2576	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2577	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2578	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2579	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2580	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2581	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2582	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2583	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2584	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2585	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2586	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2587	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2588	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2589	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2590	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2591	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2592	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2593	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2594	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2595	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2596	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2597	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2598	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2599	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2600	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2601	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2602	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2603	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2604	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2605
EricLew	0:d4e5ad7ad71c	2606	/***************** Bit definition for CAN_F1R1 register *****************/
EricLew	0:d4e5ad7ad71c	2607	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2608	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2609	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2610	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2611	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2612	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2613	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2614	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2615	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2616	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2617	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2618	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2619	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2620	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2621	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2622	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2623	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2624	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2625	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2626	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2627	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2628	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2629	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2630	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2631	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2632	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2633	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2634	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2635	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2636	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2637	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2638	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2639
EricLew	0:d4e5ad7ad71c	2640	/***************** Bit definition for CAN_F2R1 register *****************/
EricLew	0:d4e5ad7ad71c	2641	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2642	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2643	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2644	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2645	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2646	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2647	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2648	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2649	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2650	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2651	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2652	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2653	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2654	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2655	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2656	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2657	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2658	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2659	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2660	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2661	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2662	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2663	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2664	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2665	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2666	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2667	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2668	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2669	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2670	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2671	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2672	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2673
EricLew	0:d4e5ad7ad71c	2674	/***************** Bit definition for CAN_F3R1 register *****************/
EricLew	0:d4e5ad7ad71c	2675	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2676	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2677	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2678	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2679	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2680	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2681	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2682	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2683	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2684	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2685	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2686	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2687	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2688	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2689	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2690	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2691	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2692	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2693	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2694	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2695	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2696	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2697	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2698	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2699	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2700	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2701	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2702	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2703	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2704	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2705	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2706	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2707
EricLew	0:d4e5ad7ad71c	2708	/***************** Bit definition for CAN_F4R1 register *****************/
EricLew	0:d4e5ad7ad71c	2709	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2710	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2711	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2712	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2713	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2714	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2715	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2716	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2717	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2718	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2719	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2720	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2721	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2722	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2723	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2724	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2725	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2726	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2727	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2728	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2729	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2730	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2731	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2732	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2733	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2734	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2735	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2736	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2737	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2738	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2739	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2740	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2741
EricLew	0:d4e5ad7ad71c	2742	/***************** Bit definition for CAN_F5R1 register *****************/
EricLew	0:d4e5ad7ad71c	2743	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2744	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2745	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2746	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2747	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2748	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2749	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2750	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2751	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2752	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2753	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2754	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2755	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2756	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2757	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2758	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2759	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2760	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2761	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2762	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2763	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2764	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2765	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2766	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2767	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2768	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2769	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2770	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2771	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2772	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2773	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2774	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2775
EricLew	0:d4e5ad7ad71c	2776	/***************** Bit definition for CAN_F6R1 register *****************/
EricLew	0:d4e5ad7ad71c	2777	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2778	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2779	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2780	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2781	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2782	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2783	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2784	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2785	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2786	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2787	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2788	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2789	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2790	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2791	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2792	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2793	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2794	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2795	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2796	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2797	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2798	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2799	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2800	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2801	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2802	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2803	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2804	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2805	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2806	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2807	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2808	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2809
EricLew	0:d4e5ad7ad71c	2810	/***************** Bit definition for CAN_F7R1 register *****************/
EricLew	0:d4e5ad7ad71c	2811	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2812	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2813	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2814	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2815	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2816	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2817	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2818	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2819	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2820	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2821	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2822	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2823	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2824	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2825	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2826	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2827	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2828	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2829	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2830	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2831	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2832	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2833	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2834	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2835	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2836	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2837	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2838	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2839	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2840	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2841	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2842	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2843
EricLew	0:d4e5ad7ad71c	2844	/***************** Bit definition for CAN_F8R1 register *****************/
EricLew	0:d4e5ad7ad71c	2845	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2846	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2847	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2848	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2849	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2850	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2851	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2852	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2853	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2854	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2855	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2856	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2857	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2858	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2859	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2860	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2861	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2862	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2863	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2864	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2865	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2866	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2867	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2868	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2869	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2870	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2871	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2872	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2873	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2874	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2875	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2876	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2877
EricLew	0:d4e5ad7ad71c	2878	/***************** Bit definition for CAN_F9R1 register *****************/
EricLew	0:d4e5ad7ad71c	2879	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2880	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2881	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2882	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2883	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2884	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2885	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2886	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2887	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2888	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2889	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2890	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2891	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2892	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2893	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2894	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2895	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2896	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2897	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2898	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2899	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2900	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2901	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2902	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2903	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2904	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2905	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2906	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2907	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2908	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2909	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2910	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2911
EricLew	0:d4e5ad7ad71c	2912	/***************** Bit definition for CAN_F10R1 register ****************/
EricLew	0:d4e5ad7ad71c	2913	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2914	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2915	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2916	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2917	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2918	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2919	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2920	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2921	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2922	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2923	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2924	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2925	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2926	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2927	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2928	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2929	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2930	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2931	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2932	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2933	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2934	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2935	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2936	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2937	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2938	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2939	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2940	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2941	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2942	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2943	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2944	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2945
EricLew	0:d4e5ad7ad71c	2946	/***************** Bit definition for CAN_F11R1 register ****************/
EricLew	0:d4e5ad7ad71c	2947	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2948	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2949	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2950	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2951	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2952	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2953	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2954	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2955	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2956	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2957	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2958	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2959	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2960	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2961	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2962	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2963	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2964	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2965	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	2966	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	2967	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	2968	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	2969	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	2970	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	2971	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	2972	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	2973	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	2974	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	2975	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	2976	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	2977	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	2978	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	2979
EricLew	0:d4e5ad7ad71c	2980	/***************** Bit definition for CAN_F12R1 register ****************/
EricLew	0:d4e5ad7ad71c	2981	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	2982	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	2983	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	2984	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	2985	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	2986	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	2987	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	2988	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	2989	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	2990	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	2991	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	2992	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	2993	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	2994	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	2995	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	2996	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	2997	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	2998	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	2999	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3000	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3001	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3002	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3003	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3004	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3005	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3006	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3007	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3008	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3009	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3010	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3011	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3012	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3013
EricLew	0:d4e5ad7ad71c	3014	/***************** Bit definition for CAN_F13R1 register ****************/
EricLew	0:d4e5ad7ad71c	3015	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3016	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3017	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3018	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3019	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3020	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3021	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3022	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3023	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3024	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3025	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3026	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3027	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3028	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3029	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3030	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3031	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3032	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3033	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3034	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3035	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3036	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3037	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3038	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3039	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3040	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3041	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3042	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3043	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3044	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3045	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3046	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3047
EricLew	0:d4e5ad7ad71c	3048	/***************** Bit definition for CAN_F0R2 register *****************/
EricLew	0:d4e5ad7ad71c	3049	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3050	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3051	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3052	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3053	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3054	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3055	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3056	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3057	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3058	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3059	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3060	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3061	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3062	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3063	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3064	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3065	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3066	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3067	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3068	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3069	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3070	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3071	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3072	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3073	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3074	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3075	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3076	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3077	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3078	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3079	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3080	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3081
EricLew	0:d4e5ad7ad71c	3082	/***************** Bit definition for CAN_F1R2 register *****************/
EricLew	0:d4e5ad7ad71c	3083	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3084	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3085	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3086	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3087	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3088	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3089	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3090	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3091	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3092	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3093	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3094	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3095	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3096	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3097	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3098	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3099	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3100	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3101	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3102	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3103	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3104	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3105	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3106	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3107	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3108	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3109	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3110	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3111	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3112	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3113	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3114	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3115
EricLew	0:d4e5ad7ad71c	3116	/***************** Bit definition for CAN_F2R2 register *****************/
EricLew	0:d4e5ad7ad71c	3117	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3118	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3119	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3120	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3121	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3122	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3123	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3124	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3125	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3126	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3127	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3128	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3129	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3130	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3131	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3132	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3133	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3134	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3135	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3136	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3137	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3138	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3139	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3140	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3141	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3142	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3143	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3144	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3145	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3146	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3147	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3148	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3149
EricLew	0:d4e5ad7ad71c	3150	/***************** Bit definition for CAN_F3R2 register *****************/
EricLew	0:d4e5ad7ad71c	3151	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3152	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3153	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3154	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3155	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3156	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3157	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3158	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3159	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3160	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3161	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3162	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3163	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3164	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3165	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3166	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3167	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3168	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3169	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3170	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3171	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3172	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3173	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3174	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3175	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3176	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3177	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3178	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3179	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3180	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3181	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3182	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3183
EricLew	0:d4e5ad7ad71c	3184	/***************** Bit definition for CAN_F4R2 register *****************/
EricLew	0:d4e5ad7ad71c	3185	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3186	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3187	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3188	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3189	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3190	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3191	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3192	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3193	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3194	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3195	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3196	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3197	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3198	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3199	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3200	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3201	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3202	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3203	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3204	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3205	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3206	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3207	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3208	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3209	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3210	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3211	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3212	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3213	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3214	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3215	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3216	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3217
EricLew	0:d4e5ad7ad71c	3218	/***************** Bit definition for CAN_F5R2 register *****************/
EricLew	0:d4e5ad7ad71c	3219	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3220	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3221	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3222	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3223	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3224	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3225	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3226	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3227	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3228	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3229	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3230	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3231	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3232	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3233	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3234	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3235	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3236	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3237	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3238	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3239	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3240	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3241	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3242	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3243	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3244	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3245	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3246	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3247	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3248	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3249	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3250	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3251
EricLew	0:d4e5ad7ad71c	3252	/***************** Bit definition for CAN_F6R2 register *****************/
EricLew	0:d4e5ad7ad71c	3253	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3254	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3255	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3256	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3257	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3258	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3259	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3260	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3261	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3262	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3263	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3264	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3265	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3266	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3267	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3268	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3269	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3270	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3271	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3272	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3273	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3274	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3275	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3276	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3277	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3278	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3279	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3280	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3281	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3282	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3283	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3284	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3285
EricLew	0:d4e5ad7ad71c	3286	/***************** Bit definition for CAN_F7R2 register *****************/
EricLew	0:d4e5ad7ad71c	3287	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3288	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3289	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3290	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3291	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3292	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3293	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3294	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3295	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3296	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3297	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3298	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3299	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3300	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3301	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3302	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3303	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3304	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3305	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3306	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3307	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3308	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3309	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3310	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3311	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3312	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3313	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3314	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3315	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3316	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3317	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3318	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3319
EricLew	0:d4e5ad7ad71c	3320	/***************** Bit definition for CAN_F8R2 register *****************/
EricLew	0:d4e5ad7ad71c	3321	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3322	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3323	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3324	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3325	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3326	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3327	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3328	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3329	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3330	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3331	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3332	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3333	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3334	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3335	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3336	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3337	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3338	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3339	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3340	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3341	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3342	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3343	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3344	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3345	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3346	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3347	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3348	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3349	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3350	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3351	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3352	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3353
EricLew	0:d4e5ad7ad71c	3354	/***************** Bit definition for CAN_F9R2 register *****************/
EricLew	0:d4e5ad7ad71c	3355	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3356	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3357	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3358	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3359	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3360	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3361	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3362	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3363	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3364	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3365	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3366	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3367	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3368	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3369	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3370	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3371	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3372	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3373	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3374	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3375	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3376	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3377	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3378	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3379	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3380	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3381	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3382	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3383	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3384	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3385	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3386	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3387
EricLew	0:d4e5ad7ad71c	3388	/***************** Bit definition for CAN_F10R2 register ****************/
EricLew	0:d4e5ad7ad71c	3389	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3390	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3391	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3392	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3393	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3394	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3395	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3396	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3397	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3398	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3399	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3400	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3401	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3402	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3403	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3404	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3405	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3406	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3407	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3408	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3409	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3410	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3411	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3412	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3413	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3414	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3415	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3416	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3417	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3418	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3419	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3420	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3421
EricLew	0:d4e5ad7ad71c	3422	/***************** Bit definition for CAN_F11R2 register ****************/
EricLew	0:d4e5ad7ad71c	3423	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3424	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3425	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3426	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3427	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3428	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3429	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3430	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3431	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3432	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3433	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3434	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3435	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3436	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3437	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3438	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3439	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3440	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3441	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3442	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3443	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3444	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3445	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3446	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3447	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3448	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3449	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3450	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3451	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3452	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3453	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3454	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3455
EricLew	0:d4e5ad7ad71c	3456	/***************** Bit definition for CAN_F12R2 register ****************/
EricLew	0:d4e5ad7ad71c	3457	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3458	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3459	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3460	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3461	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3462	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3463	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3464	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3465	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3466	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3467	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3468	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3469	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3470	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3471	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3472	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3473	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3474	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3475	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3476	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3477	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3478	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3479	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3480	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3481	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3482	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3483	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3484	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3485	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3486	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3487	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3488	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3489
EricLew	0:d4e5ad7ad71c	3490	/***************** Bit definition for CAN_F13R2 register ****************/
EricLew	0:d4e5ad7ad71c	3491	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
EricLew	0:d4e5ad7ad71c	3492	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
EricLew	0:d4e5ad7ad71c	3493	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
EricLew	0:d4e5ad7ad71c	3494	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
EricLew	0:d4e5ad7ad71c	3495	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
EricLew	0:d4e5ad7ad71c	3496	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
EricLew	0:d4e5ad7ad71c	3497	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
EricLew	0:d4e5ad7ad71c	3498	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
EricLew	0:d4e5ad7ad71c	3499	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
EricLew	0:d4e5ad7ad71c	3500	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
EricLew	0:d4e5ad7ad71c	3501	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
EricLew	0:d4e5ad7ad71c	3502	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
EricLew	0:d4e5ad7ad71c	3503	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
EricLew	0:d4e5ad7ad71c	3504	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
EricLew	0:d4e5ad7ad71c	3505	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
EricLew	0:d4e5ad7ad71c	3506	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
EricLew	0:d4e5ad7ad71c	3507	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
EricLew	0:d4e5ad7ad71c	3508	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
EricLew	0:d4e5ad7ad71c	3509	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
EricLew	0:d4e5ad7ad71c	3510	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
EricLew	0:d4e5ad7ad71c	3511	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
EricLew	0:d4e5ad7ad71c	3512	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
EricLew	0:d4e5ad7ad71c	3513	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
EricLew	0:d4e5ad7ad71c	3514	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
EricLew	0:d4e5ad7ad71c	3515	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
EricLew	0:d4e5ad7ad71c	3516	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
EricLew	0:d4e5ad7ad71c	3517	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
EricLew	0:d4e5ad7ad71c	3518	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
EricLew	0:d4e5ad7ad71c	3519	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
EricLew	0:d4e5ad7ad71c	3520	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
EricLew	0:d4e5ad7ad71c	3521	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
EricLew	0:d4e5ad7ad71c	3522	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
EricLew	0:d4e5ad7ad71c	3523
EricLew	0:d4e5ad7ad71c	3524	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3525	/* */
EricLew	0:d4e5ad7ad71c	3526	/* CRC calculation unit */
EricLew	0:d4e5ad7ad71c	3527	/* */
EricLew	0:d4e5ad7ad71c	3528	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3529	/***************** Bit definition for CRC_DR register *******************/
EricLew	0:d4e5ad7ad71c	3530	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
EricLew	0:d4e5ad7ad71c	3531
EricLew	0:d4e5ad7ad71c	3532	/***************** Bit definition for CRC_IDR register ******************/
EricLew	0:d4e5ad7ad71c	3533	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
EricLew	0:d4e5ad7ad71c	3534
EricLew	0:d4e5ad7ad71c	3535	/****************** Bit definition for CRC_CR register ******************/
EricLew	0:d4e5ad7ad71c	3536	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
EricLew	0:d4e5ad7ad71c	3537	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
EricLew	0:d4e5ad7ad71c	3538	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
EricLew	0:d4e5ad7ad71c	3539	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
EricLew	0:d4e5ad7ad71c	3540	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
EricLew	0:d4e5ad7ad71c	3541	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	3542	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	3543	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
EricLew	0:d4e5ad7ad71c	3544
EricLew	0:d4e5ad7ad71c	3545	/***************** Bit definition for CRC_INIT register *****************/
EricLew	0:d4e5ad7ad71c	3546	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
EricLew	0:d4e5ad7ad71c	3547
EricLew	0:d4e5ad7ad71c	3548	/***************** Bit definition for CRC_POL register ******************/
EricLew	0:d4e5ad7ad71c	3549	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
EricLew	0:d4e5ad7ad71c	3550
EricLew	0:d4e5ad7ad71c	3551	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3552	/* */
EricLew	0:d4e5ad7ad71c	3553	/* Digital to Analog Converter */
EricLew	0:d4e5ad7ad71c	3554	/* */
EricLew	0:d4e5ad7ad71c	3555	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3556	/****************** Bit definition for DAC_CR register ******************/
EricLew	0:d4e5ad7ad71c	3557	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!<DAC channel1 enable /
EricLew	0:d4e5ad7ad71c	3558	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!<DAC channel1 Trigger enable /
EricLew	0:d4e5ad7ad71c	3559
EricLew	0:d4e5ad7ad71c	3560	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
EricLew	0:d4e5ad7ad71c	3561	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3562	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3563	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	3564
EricLew	0:d4e5ad7ad71c	3565	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
EricLew	0:d4e5ad7ad71c	3566	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3567	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3568
EricLew	0:d4e5ad7ad71c	3569	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
EricLew	0:d4e5ad7ad71c	3570	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3571	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3572	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	3573	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	3574
EricLew	0:d4e5ad7ad71c	3575	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!<DAC channel1 DMA enable /
EricLew	0:d4e5ad7ad71c	3576	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!<DAC channel 1 DMA underrun interrupt enable >/
EricLew	0:d4e5ad7ad71c	3577	#define DAC_CR_CEN1 ((uint32_t)0x00004000) /!<DAC channel 1 calibration enable >/
EricLew	0:d4e5ad7ad71c	3578
EricLew	0:d4e5ad7ad71c	3579	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!<DAC channel2 enable /
EricLew	0:d4e5ad7ad71c	3580	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!<DAC channel2 Trigger enable /
EricLew	0:d4e5ad7ad71c	3581
EricLew	0:d4e5ad7ad71c	3582	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
EricLew	0:d4e5ad7ad71c	3583	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3584	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3585	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	3586
EricLew	0:d4e5ad7ad71c	3587	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
EricLew	0:d4e5ad7ad71c	3588	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3589	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3590
EricLew	0:d4e5ad7ad71c	3591	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
EricLew	0:d4e5ad7ad71c	3592	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3593	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3594	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	3595	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	3596
EricLew	0:d4e5ad7ad71c	3597	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!<DAC channel2 DMA enabled /
EricLew	0:d4e5ad7ad71c	3598	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun interrupt enable >/
EricLew	0:d4e5ad7ad71c	3599	#define DAC_CR_CEN2 ((uint32_t)0x40000000) /!<DAC channel2 calibration enable >/
EricLew	0:d4e5ad7ad71c	3600
EricLew	0:d4e5ad7ad71c	3601	/*************** Bit definition for DAC_SWTRIGR register ****************/
EricLew	0:d4e5ad7ad71c	3602	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!<DAC channel1 software trigger /
EricLew	0:d4e5ad7ad71c	3603	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!<DAC channel2 software trigger /
EricLew	0:d4e5ad7ad71c	3604
EricLew	0:d4e5ad7ad71c	3605	/*************** Bit definition for DAC_DHR12R1 register ****************/
EricLew	0:d4e5ad7ad71c	3606	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3607
EricLew	0:d4e5ad7ad71c	3608	/*************** Bit definition for DAC_DHR12L1 register ****************/
EricLew	0:d4e5ad7ad71c	3609	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
EricLew	0:d4e5ad7ad71c	3610
EricLew	0:d4e5ad7ad71c	3611	/**************** Bit definition for DAC_DHR8R1 register ****************/
EricLew	0:d4e5ad7ad71c	3612	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3613
EricLew	0:d4e5ad7ad71c	3614	/*************** Bit definition for DAC_DHR12R2 register ****************/
EricLew	0:d4e5ad7ad71c	3615	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!<DAC channel2 12-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3616
EricLew	0:d4e5ad7ad71c	3617	/*************** Bit definition for DAC_DHR12L2 register ****************/
EricLew	0:d4e5ad7ad71c	3618	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!<DAC channel2 12-bit Left aligned data /
EricLew	0:d4e5ad7ad71c	3619
EricLew	0:d4e5ad7ad71c	3620	/**************** Bit definition for DAC_DHR8R2 register ****************/
EricLew	0:d4e5ad7ad71c	3621	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!<DAC channel2 8-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3622
EricLew	0:d4e5ad7ad71c	3623	/*************** Bit definition for DAC_DHR12RD register ****************/
EricLew	0:d4e5ad7ad71c	3624	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3625	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!<DAC channel2 12-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3626
EricLew	0:d4e5ad7ad71c	3627	/*************** Bit definition for DAC_DHR12LD register ****************/
EricLew	0:d4e5ad7ad71c	3628	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
EricLew	0:d4e5ad7ad71c	3629	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!<DAC channel2 12-bit Left aligned data /
EricLew	0:d4e5ad7ad71c	3630
EricLew	0:d4e5ad7ad71c	3631	/**************** Bit definition for DAC_DHR8RD register ****************/
EricLew	0:d4e5ad7ad71c	3632	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3633	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!<DAC channel2 8-bit Right aligned data /
EricLew	0:d4e5ad7ad71c	3634
EricLew	0:d4e5ad7ad71c	3635	/***************** Bit definition for DAC_DOR1 register *****************/
EricLew	0:d4e5ad7ad71c	3636	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!<DAC channel1 data output /
EricLew	0:d4e5ad7ad71c	3637
EricLew	0:d4e5ad7ad71c	3638	/***************** Bit definition for DAC_DOR2 register *****************/
EricLew	0:d4e5ad7ad71c	3639	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!<DAC channel2 data output /
EricLew	0:d4e5ad7ad71c	3640
EricLew	0:d4e5ad7ad71c	3641	/****************** Bit definition for DAC_SR register ******************/
EricLew	0:d4e5ad7ad71c	3642	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!<DAC channel1 DMA underrun flag /
EricLew	0:d4e5ad7ad71c	3643	#define DAC_SR_CAL_FLAG1 ((uint32_t)0x00004000) /!<DAC channel1 calibration offset status /
EricLew	0:d4e5ad7ad71c	3644	#define DAC_SR_BWST1 ((uint32_t)0x20008000) /!<DAC channel1 busy writing sample time flag /
EricLew	0:d4e5ad7ad71c	3645
EricLew	0:d4e5ad7ad71c	3646	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!<DAC channel2 DMA underrun flag /
EricLew	0:d4e5ad7ad71c	3647	#define DAC_SR_CAL_FLAG2 ((uint32_t)0x40000000) /!<DAC channel2 calibration offset status /
EricLew	0:d4e5ad7ad71c	3648	#define DAC_SR_BWST2 ((uint32_t)0x80000000) /!<DAC channel2 busy writing sample time flag /
EricLew	0:d4e5ad7ad71c	3649
EricLew	0:d4e5ad7ad71c	3650	/***************** Bit definition for DAC_CCR register ******************/
EricLew	0:d4e5ad7ad71c	3651	#define DAC_CCR_OTRIM1 ((uint32_t)0x0000001F) /!<DAC channel1 offset trimming value /
EricLew	0:d4e5ad7ad71c	3652	#define DAC_CCR_OTRIM2 ((uint32_t)0x001F0000) /!<DAC channel2 offset trimming value /
EricLew	0:d4e5ad7ad71c	3653
EricLew	0:d4e5ad7ad71c	3654	/***************** Bit definition for DAC_MCR register *****************/
EricLew	0:d4e5ad7ad71c	3655	#define DAC_MCR_MODE1 ((uint32_t)0x00000007) /!<MODE1[2:0] (DAC channel1 mode) /
EricLew	0:d4e5ad7ad71c	3656	#define DAC_MCR_MODE1_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3657	#define DAC_MCR_MODE1_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3658	#define DAC_MCR_MODE1_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	3659
EricLew	0:d4e5ad7ad71c	3660	#define DAC_MCR_MODE2 ((uint32_t)0x00070000) /!<MODE2[2:0] (DAC channel2 mode) /
EricLew	0:d4e5ad7ad71c	3661	#define DAC_MCR_MODE2_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	3662	#define DAC_MCR_MODE2_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	3663	#define DAC_MCR_MODE2_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	3664
EricLew	0:d4e5ad7ad71c	3665	/**************** Bit definition for DAC_SHSR1 register ****************/
EricLew	0:d4e5ad7ad71c	3666	#define DAC_SHSR1_TSAMPLE1 ((uint32_t)0x000003FF) /!<DAC channel1 sample time /
EricLew	0:d4e5ad7ad71c	3667
EricLew	0:d4e5ad7ad71c	3668	/**************** Bit definition for DAC_SHSR2 register ****************/
EricLew	0:d4e5ad7ad71c	3669	#define DAC_SHSR2_TSAMPLE2 ((uint32_t)0x000003FF) /!<DAC channel2 sample time /
EricLew	0:d4e5ad7ad71c	3670
EricLew	0:d4e5ad7ad71c	3671	/**************** Bit definition for DAC_SHHR register ****************/
EricLew	0:d4e5ad7ad71c	3672	#define DAC_SHHR_THOLD1 ((uint32_t)0x000003FF) /!<DAC channel1 hold time /
EricLew	0:d4e5ad7ad71c	3673	#define DAC_SHHR_THOLD2 ((uint32_t)0x03FF0000) /!<DAC channel2 hold time /
EricLew	0:d4e5ad7ad71c	3674
EricLew	0:d4e5ad7ad71c	3675	/**************** Bit definition for DAC_SHRR register ****************/
EricLew	0:d4e5ad7ad71c	3676	#define DAC_SHRR_TREFRESH1 ((uint32_t)0x000000FF) /!<DAC channel1 refresh time /
EricLew	0:d4e5ad7ad71c	3677	#define DAC_SHRR_TREFRESH2 ((uint32_t)0x00FF0000) /!<DAC channel2 refresh time /
EricLew	0:d4e5ad7ad71c	3678
EricLew	0:d4e5ad7ad71c	3679
EricLew	0:d4e5ad7ad71c	3680	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3681	/* */
EricLew	0:d4e5ad7ad71c	3682	/* Digital Filter for Sigma Delta Modulators */
EricLew	0:d4e5ad7ad71c	3683	/* */
EricLew	0:d4e5ad7ad71c	3684	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3685
EricLew	0:d4e5ad7ad71c	3686	/************** DFSDM channel configuration registers ******************/
EricLew	0:d4e5ad7ad71c	3687
EricLew	0:d4e5ad7ad71c	3688	/************* Bit definition for DFSDM_CHCFGR1 register ****************/
EricLew	0:d4e5ad7ad71c	3689	#define DFSDM_CHCFGR1_DFSDMEN ((uint32_t)0x80000000) /!< Global enable for DFSDM interface /
EricLew	0:d4e5ad7ad71c	3690	#define DFSDM_CHCFGR1_CKOUTSRC ((uint32_t)0x40000000) /!< Output serial clock source selection /
EricLew	0:d4e5ad7ad71c	3691	#define DFSDM_CHCFGR1_CKOUTDIV ((uint32_t)0x00FF0000) /!< CKOUTDIV[7:0] output serial clock divider /
EricLew	0:d4e5ad7ad71c	3692	#define DFSDM_CHCFGR1_DATPACK ((uint32_t)0x0000C000) /!< DATPACK[1:0] Data packing mode /
EricLew	0:d4e5ad7ad71c	3693	#define DFSDM_CHCFGR1_DATPACK_1 ((uint32_t)0x00008000) /!< Data packing mode, Bit 1 /
EricLew	0:d4e5ad7ad71c	3694	#define DFSDM_CHCFGR1_DATPACK_0 ((uint32_t)0x00004000) /!< Data packing mode, Bit 0 /
EricLew	0:d4e5ad7ad71c	3695	#define DFSDM_CHCFGR1_DATMPX ((uint32_t)0x00003000) /!< DATMPX[1:0] Input data multiplexer for channel y /
EricLew	0:d4e5ad7ad71c	3696	#define DFSDM_CHCFGR1_DATMPX_1 ((uint32_t)0x00002000) /!< Input data multiplexer for channel y, Bit 1 /
EricLew	0:d4e5ad7ad71c	3697	#define DFSDM_CHCFGR1_DATMPX_0 ((uint32_t)0x00001000) /!< Input data multiplexer for channel y, Bit 0 /
EricLew	0:d4e5ad7ad71c	3698	#define DFSDM_CHCFGR1_CHINSEL ((uint32_t)0x00000100) /!< Serial inputs selection for channel y /
EricLew	0:d4e5ad7ad71c	3699	#define DFSDM_CHCFGR1_CHEN ((uint32_t)0x00000080) /!< Channel y enable /
EricLew	0:d4e5ad7ad71c	3700	#define DFSDM_CHCFGR1_CKABEN ((uint32_t)0x00000040) /!< Clock absence detector enable on channel y /
EricLew	0:d4e5ad7ad71c	3701	#define DFSDM_CHCFGR1_SCDEN ((uint32_t)0x00000020) /!< Short circuit detector enable on channel y /
EricLew	0:d4e5ad7ad71c	3702	#define DFSDM_CHCFGR1_SPICKSEL ((uint32_t)0x0000000C) /!< SPICKSEL[1:0] SPI clock select for channel y /
EricLew	0:d4e5ad7ad71c	3703	#define DFSDM_CHCFGR1_SPICKSEL_1 ((uint32_t)0x00000008) /!< SPI clock select for channel y, Bit 1 /
EricLew	0:d4e5ad7ad71c	3704	#define DFSDM_CHCFGR1_SPICKSEL_0 ((uint32_t)0x00000004) /!< SPI clock select for channel y, Bit 0 /
EricLew	0:d4e5ad7ad71c	3705	#define DFSDM_CHCFGR1_SITP ((uint32_t)0x00000003) /!< SITP[1:0] Serial interface type for channel y /
EricLew	0:d4e5ad7ad71c	3706	#define DFSDM_CHCFGR1_SITP_1 ((uint32_t)0x00000002) /!< Serial interface type for channel y, Bit 1 /
EricLew	0:d4e5ad7ad71c	3707	#define DFSDM_CHCFGR1_SITP_0 ((uint32_t)0x00000001) /!< Serial interface type for channel y, Bit 0 /
EricLew	0:d4e5ad7ad71c	3708
EricLew	0:d4e5ad7ad71c	3709	/************* Bit definition for DFSDM_CHCFGR2 register ****************/
EricLew	0:d4e5ad7ad71c	3710	#define DFSDM_CHCFGR2_OFFSET ((uint32_t)0xFFFFFF00) /!< OFFSET[23:0] 24-bit calibration offset for channel y /
EricLew	0:d4e5ad7ad71c	3711	#define DFSDM_CHCFGR2_DTRBS ((uint32_t)0x000000F8) /!< DTRBS[4:0] Data right bit-shift for channel y /
EricLew	0:d4e5ad7ad71c	3712
EricLew	0:d4e5ad7ad71c	3713	/**************** Bit definition for DFSDM_AWSCDR register ***************/
EricLew	0:d4e5ad7ad71c	3714	#define DFSDM_AWSCDR_AWFORD ((uint32_t)0x00C00000) /!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y /
EricLew	0:d4e5ad7ad71c	3715	#define DFSDM_AWSCDR_AWFORD_1 ((uint32_t)0x00800000) /!< Analog watchdog Sinc filter order on channel y, Bit 1 /
EricLew	0:d4e5ad7ad71c	3716	#define DFSDM_AWSCDR_AWFORD_0 ((uint32_t)0x00400000) /!< Analog watchdog Sinc filter order on channel y, Bit 0 /
EricLew	0:d4e5ad7ad71c	3717	#define DFSDM_AWSCDR_AWFOSR ((uint32_t)0x001F0000) /!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y /
EricLew	0:d4e5ad7ad71c	3718	#define DFSDM_AWSCDR_BKSCD ((uint32_t)0x0000F000) /!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y /
EricLew	0:d4e5ad7ad71c	3719	#define DFSDM_AWSCDR_SCDT ((uint32_t)0x000000FF) /!< SCDT[7:0] Short circuit detector threshold for channel y /
EricLew	0:d4e5ad7ad71c	3720
EricLew	0:d4e5ad7ad71c	3721	/************** Bit definition for DFSDM_CHWDATR register *****************/
EricLew	0:d4e5ad7ad71c	3722	#define DFSDM_AWSCDR_WDATA ((uint32_t)0x0000FFFF) /!< WDATA[15:0] Input channel y watchdog data /
EricLew	0:d4e5ad7ad71c	3723
EricLew	0:d4e5ad7ad71c	3724	/************** Bit definition for DFSDM_CHDATINR register ***************/
EricLew	0:d4e5ad7ad71c	3725	#define DFSDM_AWSCDR_INDAT0 ((uint32_t)0x0000FFFF) /!< INDAT0[31:16] Input data for channel y or channel (y+1) /
EricLew	0:d4e5ad7ad71c	3726	#define DFSDM_AWSCDR_INDAT1 ((uint32_t)0xFFFF0000) /!< INDAT0[15:0] Input data for channel y /
EricLew	0:d4e5ad7ad71c	3727
EricLew	0:d4e5ad7ad71c	3728	/********************** DFSDM module registers **************************/
EricLew	0:d4e5ad7ad71c	3729
EricLew	0:d4e5ad7ad71c	3730	/****************** Bit definition for DFSDM_CR1 register *****************/
EricLew	0:d4e5ad7ad71c	3731	#define DFSDM_CR1_AWFSEL ((uint32_t)0x40000000) /!< Analog watchdog fast mode select /
EricLew	0:d4e5ad7ad71c	3732	#define DFSDM_CR1_FAST ((uint32_t)0x20000000) /!< Fast conversion mode selection /
EricLew	0:d4e5ad7ad71c	3733	#define DFSDM_CR1_RCH ((uint32_t)0x07000000) /!< RCH[2:0] Regular channel selection /
EricLew	0:d4e5ad7ad71c	3734	#define DFSDM_CR1_RDMAEN ((uint32_t)0x00200000) /!< DMA channel enabled to read data for the regular conversion /
EricLew	0:d4e5ad7ad71c	3735	#define DFSDM_CR1_RSYNC ((uint32_t)0x00080000) /!< Launch regular conversion synchronously with DFSDMx /
EricLew	0:d4e5ad7ad71c	3736	#define DFSDM_CR1_RCONT ((uint32_t)0x00040000) /!< Continuous mode selection for regular conversions /
EricLew	0:d4e5ad7ad71c	3737	#define DFSDM_CR1_RSWSTART ((uint32_t)0x00020000) /!< Software start of a conversion on the regular channel /
EricLew	0:d4e5ad7ad71c	3738	#define DFSDM_CR1_JEXTEN ((uint32_t)0x00006000) /!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions /
EricLew	0:d4e5ad7ad71c	3739	#define DFSDM_CR1_JEXTEN_1 ((uint32_t)0x00004000) /!< Trigger enable and trigger edge selection for injected conversions, Bit 1 /
EricLew	0:d4e5ad7ad71c	3740	#define DFSDM_CR1_JEXTEN_0 ((uint32_t)0x00002000) /!< Trigger enable and trigger edge selection for injected conversions, Bit 0 /
EricLew	0:d4e5ad7ad71c	3741	#define DFSDM_CR1_JEXTSEL ((uint32_t)0x00000700) /!< JEXTSEL[2:0]Trigger signal selection for launching injected conversions /
EricLew	0:d4e5ad7ad71c	3742	#define DFSDM_CR1_JEXTSEL_2 ((uint32_t)0x00000400) /!< Trigger signal selection for launching injected conversions, Bit 2 /
EricLew	0:d4e5ad7ad71c	3743	#define DFSDM_CR1_JEXTSEL_1 ((uint32_t)0x00000200) /!< Trigger signal selection for launching injected conversions, Bit 1 /
EricLew	0:d4e5ad7ad71c	3744	#define DFSDM_CR1_JEXTSEL_0 ((uint32_t)0x00000100) /!< Trigger signal selection for launching injected conversions, Bit 0 /
EricLew	0:d4e5ad7ad71c	3745	#define DFSDM_CR1_JDMAEN ((uint32_t)0x00000020) /!< DMA channel enabled to read data for the injected channel group /
EricLew	0:d4e5ad7ad71c	3746	#define DFSDM_CR1_JSCAN ((uint32_t)0x00000010) /!< Scanning conversion in continuous mode selection for injected conversions /
EricLew	0:d4e5ad7ad71c	3747	#define DFSDM_CR1_JSYNC ((uint32_t)0x00000008) /!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger /
EricLew	0:d4e5ad7ad71c	3748	#define DFSDM_CR1_JSWSTART ((uint32_t)0x00000002) /!< Start the conversion of the injected group of channels /
EricLew	0:d4e5ad7ad71c	3749	#define DFSDM_CR1_DFEN ((uint32_t)0x00000001) /!< DFSDM enable /
EricLew	0:d4e5ad7ad71c	3750
EricLew	0:d4e5ad7ad71c	3751	/****************** Bit definition for DFSDM_CR2 register *****************/
EricLew	0:d4e5ad7ad71c	3752	#define DFSDM_CR2_AWDCH ((uint32_t)0x00FF0000) /!< AWDCH[7:0] Analog watchdog channel selection /
EricLew	0:d4e5ad7ad71c	3753	#define DFSDM_CR2_EXCH ((uint32_t)0x0000FF00) /!< EXCH[7:0] Extreme detector channel selection /
EricLew	0:d4e5ad7ad71c	3754	#define DFSDM_CR2_CKABIE ((uint32_t)0x00000040) /!< Clock absence interrupt enable /
EricLew	0:d4e5ad7ad71c	3755	#define DFSDM_CR2_SCDIE ((uint32_t)0x00000020) /!< Short circuit detector interrupt enable /
EricLew	0:d4e5ad7ad71c	3756	#define DFSDM_CR2_AWDIE ((uint32_t)0x00000010) /!< Analog watchdog interrupt enable /
EricLew	0:d4e5ad7ad71c	3757	#define DFSDM_CR2_ROVRIE ((uint32_t)0x00000008) /!< Regular data overrun interrupt enable /
EricLew	0:d4e5ad7ad71c	3758	#define DFSDM_CR2_JOVRIE ((uint32_t)0x00000004) /!< Injected data overrun interrupt enable /
EricLew	0:d4e5ad7ad71c	3759	#define DFSDM_CR2_REOCIE ((uint32_t)0x00000002) /!< Regular end of conversion interrupt enable /
EricLew	0:d4e5ad7ad71c	3760	#define DFSDM_CR2_JEOCIE ((uint32_t)0x00000001) /!< Injected end of conversion interrupt enable /
EricLew	0:d4e5ad7ad71c	3761
EricLew	0:d4e5ad7ad71c	3762	/****************** Bit definition for DFSDM_ISR register *****************/
EricLew	0:d4e5ad7ad71c	3763	#define DFSDM_ISR_SCDF ((uint32_t)0xFF000000) /!< SCDF[7:0] Short circuit detector flag /
EricLew	0:d4e5ad7ad71c	3764	#define DFSDM_ISR_CKABF ((uint32_t)0x00FF0000) /!< CKABF[7:0] Clock absence flag /
EricLew	0:d4e5ad7ad71c	3765	#define DFSDM_ISR_RCIP ((uint32_t)0x00004000) /!< Regular conversion in progress status /
EricLew	0:d4e5ad7ad71c	3766	#define DFSDM_ISR_JCIP ((uint32_t)0x00002000) /!< Injected conversion in progress status /
EricLew	0:d4e5ad7ad71c	3767	#define DFSDM_ISR_AWDF ((uint32_t)0x00000010) /!< Analog watchdog /
EricLew	0:d4e5ad7ad71c	3768	#define DFSDM_ISR_ROVRF ((uint32_t)0x00000008) /!< Regular conversion overrun flag /
EricLew	0:d4e5ad7ad71c	3769	#define DFSDM_ISR_JOVRF ((uint32_t)0x00000004) /!< Injected conversion overrun flag /
EricLew	0:d4e5ad7ad71c	3770	#define DFSDM_ISR_REOCF ((uint32_t)0x00000002) /!< End of regular conversion flag /
EricLew	0:d4e5ad7ad71c	3771	#define DFSDM_ISR_JEOCF ((uint32_t)0x00000001) /!< End of injected conversion flag /
EricLew	0:d4e5ad7ad71c	3772
EricLew	0:d4e5ad7ad71c	3773	/****************** Bit definition for DFSDM_ICR register *****************/
EricLew	0:d4e5ad7ad71c	3774	#define DFSDM_ICR_CLRSCSDF ((uint32_t)0xFF000000) /!< CLRSCSDF[7:0] Clear the short circuit detector flag /
EricLew	0:d4e5ad7ad71c	3775	#define DFSDM_ICR_CLRCKABF ((uint32_t)0x00FF0000) /!< CLRCKABF[7:0] Clear the clock absence flag /
EricLew	0:d4e5ad7ad71c	3776	#define DFSDM_ICR_CLRROVRF ((uint32_t)0x00000008) /!< Clear the regular conversion overrun flag /
EricLew	0:d4e5ad7ad71c	3777	#define DFSDM_ICR_CLRJOVRF ((uint32_t)0x00000004) /!< Clear the injected conversion overrun flag /
EricLew	0:d4e5ad7ad71c	3778
EricLew	0:d4e5ad7ad71c	3779	/***************** Bit definition for DFSDM_JCHGR register ****************/
EricLew	0:d4e5ad7ad71c	3780	#define DFSDM_JCHGR_JCHG ((uint32_t)0x000000FF) /!< JCHG[7:0] Injected channel group selection /
EricLew	0:d4e5ad7ad71c	3781
EricLew	0:d4e5ad7ad71c	3782	/****************** Bit definition for DFSDM_FCR register *****************/
EricLew	0:d4e5ad7ad71c	3783	#define DFSDM_FCR_FORD ((uint32_t)0xE0000000) /!< FORD[2:0] Sinc filter order /
EricLew	0:d4e5ad7ad71c	3784	#define DFSDM_FCR_FORD_2 ((uint32_t)0x80000000) /!< Sinc filter order, Bit 2 /
EricLew	0:d4e5ad7ad71c	3785	#define DFSDM_FCR_FORD_1 ((uint32_t)0x40000000) /!< Sinc filter order, Bit 1 /
EricLew	0:d4e5ad7ad71c	3786	#define DFSDM_FCR_FORD_0 ((uint32_t)0x20000000) /!< Sinc filter order, Bit 0 /
EricLew	0:d4e5ad7ad71c	3787	#define DFSDM_FCR_FOSR ((uint32_t)0x03FF0000) /!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) /
EricLew	0:d4e5ad7ad71c	3788	#define DFSDM_FCR_IOSR ((uint32_t)0x000000FF) /!< IOSR[7:0] Integrator oversampling ratio (averaging length) /
EricLew	0:d4e5ad7ad71c	3789
EricLew	0:d4e5ad7ad71c	3790	/**************** Bit definition for DFSDM_JDATAR register ***************/
EricLew	0:d4e5ad7ad71c	3791	#define DFSDM_JDATAR_JDATA ((uint32_t)0xFFFFFF00) /!< JDATA[23:0] Injected group conversion data /
EricLew	0:d4e5ad7ad71c	3792	#define DFSDM_JDATAR_JDATACH ((uint32_t)0x00000007) /!< JDATACH[2:0] Injected channel most recently converted /
EricLew	0:d4e5ad7ad71c	3793
EricLew	0:d4e5ad7ad71c	3794	/**************** Bit definition for DFSDM_RDATAR register ***************/
EricLew	0:d4e5ad7ad71c	3795	#define DFSDM_RDATAR_RDATA ((uint32_t)0xFFFFFF00) /!< RDATA[23:0] Regular channel conversion data /
EricLew	0:d4e5ad7ad71c	3796	#define DFSDM_RDATAR_RPEND ((uint32_t)0x00000010) /!< RPEND Regular channel pending data /
EricLew	0:d4e5ad7ad71c	3797	#define DFSDM_RDATAR_RDATACH ((uint32_t)0x00000007) /!< RDATACH[2:0] Regular channel most recently converted /
EricLew	0:d4e5ad7ad71c	3798
EricLew	0:d4e5ad7ad71c	3799	/**************** Bit definition for DFSDM_AWHTR register ****************/
EricLew	0:d4e5ad7ad71c	3800	#define DFSDM_AWHTR_AWHT ((uint32_t)0xFFFFFF00) /!< AWHT[23:0] Analog watchdog high threshold /
EricLew	0:d4e5ad7ad71c	3801	#define DFSDM_AWHTR_BKAWH ((uint32_t)0x0000000F) /!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event /
EricLew	0:d4e5ad7ad71c	3802
EricLew	0:d4e5ad7ad71c	3803	/**************** Bit definition for DFSDM_AWLTR register ****************/
EricLew	0:d4e5ad7ad71c	3804	#define DFSDM_AWLTR_AWLT ((uint32_t)0xFFFFFF00) /!< AWHT[23:0] Analog watchdog low threshold /
EricLew	0:d4e5ad7ad71c	3805	#define DFSDM_AWLTR_BKAWL ((uint32_t)0x0000000F) /!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event /
EricLew	0:d4e5ad7ad71c	3806
EricLew	0:d4e5ad7ad71c	3807	/**************** Bit definition for DFSDM_AWSR register ****************/
EricLew	0:d4e5ad7ad71c	3808	#define DFSDM_AWSR_AWHTF ((uint32_t)0x0000FF00) /!< AWHTF[15:8] Analog watchdog high threshold error on given channels /
EricLew	0:d4e5ad7ad71c	3809	#define DFSDM_AWSR_AWLTF ((uint32_t)0x000000FF) /!< AWLTF[7:0] Analog watchdog low threshold error on given channels /
EricLew	0:d4e5ad7ad71c	3810
EricLew	0:d4e5ad7ad71c	3811	/**************** Bit definition for DFSDM_AWCFR) register ***************/
EricLew	0:d4e5ad7ad71c	3812	#define DFSDM_AWCFR_CLRAWHTF ((uint32_t)0x0000FF00) /!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag /
EricLew	0:d4e5ad7ad71c	3813	#define DFSDM_AWCFR_CLRAWLTF ((uint32_t)0x000000FF) /!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag /
EricLew	0:d4e5ad7ad71c	3814
EricLew	0:d4e5ad7ad71c	3815	/**************** Bit definition for DFSDM_EXMAX register ****************/
EricLew	0:d4e5ad7ad71c	3816	#define DFSDM_EXMAX_EXMAX ((uint32_t)0xFFFFFF00) /!< EXMAX[23:0] Extreme detector maximum value /
EricLew	0:d4e5ad7ad71c	3817	#define DFSDM_EXMAX_EXMAXCH ((uint32_t)0x00000007) /!< EXMAXCH[2:0] Extreme detector maximum data channel /
EricLew	0:d4e5ad7ad71c	3818
EricLew	0:d4e5ad7ad71c	3819	/**************** Bit definition for DFSDM_EXMIN register ****************/
EricLew	0:d4e5ad7ad71c	3820	#define DFSDM_EXMIN_EXMIN ((uint32_t)0xFFFFFF00) /!< EXMIN[23:0] Extreme detector minimum value /
EricLew	0:d4e5ad7ad71c	3821	#define DFSDM_EXMIN_EXMINCH ((uint32_t)0x00000007) /!< EXMINCH[2:0] Extreme detector minimum data channel /
EricLew	0:d4e5ad7ad71c	3822
EricLew	0:d4e5ad7ad71c	3823	/**************** Bit definition for DFSDM_EXMIN register ****************/
EricLew	0:d4e5ad7ad71c	3824	#define DFSDM_CNVTIMR_CNVCNT ((uint32_t)0xFFFFFFF0) /!< CNVCNT[27:0]: 28-bit timer counting conversion time /
EricLew	0:d4e5ad7ad71c	3825
EricLew	0:d4e5ad7ad71c	3826	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3827	/* */
EricLew	0:d4e5ad7ad71c	3828	/* DMA Controller (DMA) */
EricLew	0:d4e5ad7ad71c	3829	/* */
EricLew	0:d4e5ad7ad71c	3830	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3831
EricLew	0:d4e5ad7ad71c	3832	/***************** Bit definition for DMA_ISR register ******************/
EricLew	0:d4e5ad7ad71c	3833	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3834	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3835	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3836	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3837	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3838	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3839	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3840	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3841	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3842	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3843	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3844	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3845	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3846	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3847	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3848	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3849	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3850	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3851	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3852	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3853	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3854	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3855	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3856	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3857	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
EricLew	0:d4e5ad7ad71c	3858	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
EricLew	0:d4e5ad7ad71c	3859	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
EricLew	0:d4e5ad7ad71c	3860	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
EricLew	0:d4e5ad7ad71c	3861
EricLew	0:d4e5ad7ad71c	3862	/***************** Bit definition for DMA_IFCR register *****************/
EricLew	0:d4e5ad7ad71c	3863	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clearr /
EricLew	0:d4e5ad7ad71c	3864	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3865	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3866	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3867	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
EricLew	0:d4e5ad7ad71c	3868	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3869	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3870	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3871	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
EricLew	0:d4e5ad7ad71c	3872	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3873	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3874	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3875	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
EricLew	0:d4e5ad7ad71c	3876	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3877	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3878	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3879	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
EricLew	0:d4e5ad7ad71c	3880	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3881	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3882	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3883	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
EricLew	0:d4e5ad7ad71c	3884	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3885	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3886	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3887	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
EricLew	0:d4e5ad7ad71c	3888	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
EricLew	0:d4e5ad7ad71c	3889	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
EricLew	0:d4e5ad7ad71c	3890	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
EricLew	0:d4e5ad7ad71c	3891
EricLew	0:d4e5ad7ad71c	3892	/***************** Bit definition for DMA_CCR register ******************/
EricLew	0:d4e5ad7ad71c	3893	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
EricLew	0:d4e5ad7ad71c	3894	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
EricLew	0:d4e5ad7ad71c	3895	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
EricLew	0:d4e5ad7ad71c	3896	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
EricLew	0:d4e5ad7ad71c	3897	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
EricLew	0:d4e5ad7ad71c	3898	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
EricLew	0:d4e5ad7ad71c	3899	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
EricLew	0:d4e5ad7ad71c	3900	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
EricLew	0:d4e5ad7ad71c	3901
EricLew	0:d4e5ad7ad71c	3902	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
EricLew	0:d4e5ad7ad71c	3903	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	3904	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	3905
EricLew	0:d4e5ad7ad71c	3906	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
EricLew	0:d4e5ad7ad71c	3907	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	3908	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	3909
EricLew	0:d4e5ad7ad71c	3910	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
EricLew	0:d4e5ad7ad71c	3911	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	3912	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	3913
EricLew	0:d4e5ad7ad71c	3914	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
EricLew	0:d4e5ad7ad71c	3915
EricLew	0:d4e5ad7ad71c	3916	/**************** Bit definition for DMA_CNDTR register *****************/
EricLew	0:d4e5ad7ad71c	3917	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
EricLew	0:d4e5ad7ad71c	3918
EricLew	0:d4e5ad7ad71c	3919	/**************** Bit definition for DMA_CPAR register ******************/
EricLew	0:d4e5ad7ad71c	3920	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
EricLew	0:d4e5ad7ad71c	3921
EricLew	0:d4e5ad7ad71c	3922	/**************** Bit definition for DMA_CMAR register ******************/
EricLew	0:d4e5ad7ad71c	3923	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
EricLew	0:d4e5ad7ad71c	3924
EricLew	0:d4e5ad7ad71c	3925
EricLew	0:d4e5ad7ad71c	3926	/***************** Bit definition for DMA_CSELR register *****************/
EricLew	0:d4e5ad7ad71c	3927	#define DMA_CSELR_C1S ((uint32_t)0x0000000F) /!< Channel 1 Selection /
EricLew	0:d4e5ad7ad71c	3928	#define DMA_CSELR_C2S ((uint32_t)0x000000F0) /!< Channel 2 Selection /
EricLew	0:d4e5ad7ad71c	3929	#define DMA_CSELR_C3S ((uint32_t)0x00000F00) /!< Channel 3 Selection /
EricLew	0:d4e5ad7ad71c	3930	#define DMA_CSELR_C4S ((uint32_t)0x0000F000) /!< Channel 4 Selection /
EricLew	0:d4e5ad7ad71c	3931	#define DMA_CSELR_C5S ((uint32_t)0x000F0000) /!< Channel 5 Selection /
EricLew	0:d4e5ad7ad71c	3932	#define DMA_CSELR_C6S ((uint32_t)0x00F00000) /!< Channel 6 Selection /
EricLew	0:d4e5ad7ad71c	3933	#define DMA_CSELR_C7S ((uint32_t)0x0F000000) /!< Channel 7 Selection /
EricLew	0:d4e5ad7ad71c	3934
EricLew	0:d4e5ad7ad71c	3935
EricLew	0:d4e5ad7ad71c	3936	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3937	/* */
EricLew	0:d4e5ad7ad71c	3938	/* External Interrupt/Event Controller */
EricLew	0:d4e5ad7ad71c	3939	/* */
EricLew	0:d4e5ad7ad71c	3940	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	3941	/***************** Bit definition for EXTI_IMR1 register ****************/
EricLew	0:d4e5ad7ad71c	3942	#define EXTI_IMR1_IM0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
EricLew	0:d4e5ad7ad71c	3943	#define EXTI_IMR1_IM1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
EricLew	0:d4e5ad7ad71c	3944	#define EXTI_IMR1_IM2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
EricLew	0:d4e5ad7ad71c	3945	#define EXTI_IMR1_IM3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
EricLew	0:d4e5ad7ad71c	3946	#define EXTI_IMR1_IM4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
EricLew	0:d4e5ad7ad71c	3947	#define EXTI_IMR1_IM5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
EricLew	0:d4e5ad7ad71c	3948	#define EXTI_IMR1_IM6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
EricLew	0:d4e5ad7ad71c	3949	#define EXTI_IMR1_IM7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
EricLew	0:d4e5ad7ad71c	3950	#define EXTI_IMR1_IM8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
EricLew	0:d4e5ad7ad71c	3951	#define EXTI_IMR1_IM9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
EricLew	0:d4e5ad7ad71c	3952	#define EXTI_IMR1_IM10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
EricLew	0:d4e5ad7ad71c	3953	#define EXTI_IMR1_IM11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
EricLew	0:d4e5ad7ad71c	3954	#define EXTI_IMR1_IM12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
EricLew	0:d4e5ad7ad71c	3955	#define EXTI_IMR1_IM13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
EricLew	0:d4e5ad7ad71c	3956	#define EXTI_IMR1_IM14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
EricLew	0:d4e5ad7ad71c	3957	#define EXTI_IMR1_IM15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
EricLew	0:d4e5ad7ad71c	3958	#define EXTI_IMR1_IM16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
EricLew	0:d4e5ad7ad71c	3959	#define EXTI_IMR1_IM17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
EricLew	0:d4e5ad7ad71c	3960	#define EXTI_IMR1_IM18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
EricLew	0:d4e5ad7ad71c	3961	#define EXTI_IMR1_IM19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
EricLew	0:d4e5ad7ad71c	3962	#define EXTI_IMR1_IM20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
EricLew	0:d4e5ad7ad71c	3963	#define EXTI_IMR1_IM21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
EricLew	0:d4e5ad7ad71c	3964	#define EXTI_IMR1_IM22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
EricLew	0:d4e5ad7ad71c	3965	#define EXTI_IMR1_IM23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
EricLew	0:d4e5ad7ad71c	3966	#define EXTI_IMR1_IM24 ((uint32_t)0x01000000) /!< Interrupt Mask on line 24 /
EricLew	0:d4e5ad7ad71c	3967	#define EXTI_IMR1_IM25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
EricLew	0:d4e5ad7ad71c	3968	#define EXTI_IMR1_IM26 ((uint32_t)0x04000000) /!< Interrupt Mask on line 26 /
EricLew	0:d4e5ad7ad71c	3969	#define EXTI_IMR1_IM27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
EricLew	0:d4e5ad7ad71c	3970	#define EXTI_IMR1_IM28 ((uint32_t)0x10000000) /!< Interrupt Mask on line 28 /
EricLew	0:d4e5ad7ad71c	3971	#define EXTI_IMR1_IM29 ((uint32_t)0x20000000) /!< Interrupt Mask on line 29 /
EricLew	0:d4e5ad7ad71c	3972	#define EXTI_IMR1_IM30 ((uint32_t)0x40000000) /!< Interrupt Mask on line 30 /
EricLew	0:d4e5ad7ad71c	3973	#define EXTI_IMR1_IM31 ((uint32_t)0x80000000) /!< Interrupt Mask on line 31 /
EricLew	0:d4e5ad7ad71c	3974
EricLew	0:d4e5ad7ad71c	3975	/***************** Bit definition for EXTI_EMR1 register ****************/
EricLew	0:d4e5ad7ad71c	3976	#define EXTI_EMR1_EM0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
EricLew	0:d4e5ad7ad71c	3977	#define EXTI_EMR1_EM1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
EricLew	0:d4e5ad7ad71c	3978	#define EXTI_EMR1_EM2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
EricLew	0:d4e5ad7ad71c	3979	#define EXTI_EMR1_EM3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
EricLew	0:d4e5ad7ad71c	3980	#define EXTI_EMR1_EM4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
EricLew	0:d4e5ad7ad71c	3981	#define EXTI_EMR1_EM5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
EricLew	0:d4e5ad7ad71c	3982	#define EXTI_EMR1_EM6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
EricLew	0:d4e5ad7ad71c	3983	#define EXTI_EMR1_EM7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
EricLew	0:d4e5ad7ad71c	3984	#define EXTI_EMR1_EM8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
EricLew	0:d4e5ad7ad71c	3985	#define EXTI_EMR1_EM9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
EricLew	0:d4e5ad7ad71c	3986	#define EXTI_EMR1_EM10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
EricLew	0:d4e5ad7ad71c	3987	#define EXTI_EMR1_EM11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
EricLew	0:d4e5ad7ad71c	3988	#define EXTI_EMR1_EM12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
EricLew	0:d4e5ad7ad71c	3989	#define EXTI_EMR1_EM13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
EricLew	0:d4e5ad7ad71c	3990	#define EXTI_EMR1_EM14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
EricLew	0:d4e5ad7ad71c	3991	#define EXTI_EMR1_EM15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
EricLew	0:d4e5ad7ad71c	3992	#define EXTI_EMR1_EM16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
EricLew	0:d4e5ad7ad71c	3993	#define EXTI_EMR1_EM17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
EricLew	0:d4e5ad7ad71c	3994	#define EXTI_EMR1_EM18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
EricLew	0:d4e5ad7ad71c	3995	#define EXTI_EMR1_EM19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
EricLew	0:d4e5ad7ad71c	3996	#define EXTI_EMR1_EM20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
EricLew	0:d4e5ad7ad71c	3997	#define EXTI_EMR1_EM21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
EricLew	0:d4e5ad7ad71c	3998	#define EXTI_EMR1_EM22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
EricLew	0:d4e5ad7ad71c	3999	#define EXTI_EMR1_EM23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
EricLew	0:d4e5ad7ad71c	4000	#define EXTI_EMR1_EM24 ((uint32_t)0x01000000) /!< Event Mask on line 24 /
EricLew	0:d4e5ad7ad71c	4001	#define EXTI_EMR1_EM25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
EricLew	0:d4e5ad7ad71c	4002	#define EXTI_EMR1_EM26 ((uint32_t)0x04000000) /!< Event Mask on line 26 /
EricLew	0:d4e5ad7ad71c	4003	#define EXTI_EMR1_EM27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
EricLew	0:d4e5ad7ad71c	4004	#define EXTI_EMR1_EM28 ((uint32_t)0x10000000) /!< Event Mask on line 28 /
EricLew	0:d4e5ad7ad71c	4005	#define EXTI_EMR1_EM29 ((uint32_t)0x20000000) /!< Event Mask on line 29 /
EricLew	0:d4e5ad7ad71c	4006	#define EXTI_EMR1_EM30 ((uint32_t)0x40000000) /!< Event Mask on line 30 /
EricLew	0:d4e5ad7ad71c	4007	#define EXTI_EMR1_EM31 ((uint32_t)0x80000000) /!< Event Mask on line 31 /
EricLew	0:d4e5ad7ad71c	4008
EricLew	0:d4e5ad7ad71c	4009	/**************** Bit definition for EXTI_RTSR1 register ****************/
EricLew	0:d4e5ad7ad71c	4010	#define EXTI_RTSR1_RT0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
EricLew	0:d4e5ad7ad71c	4011	#define EXTI_RTSR1_RT1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
EricLew	0:d4e5ad7ad71c	4012	#define EXTI_RTSR1_RT2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
EricLew	0:d4e5ad7ad71c	4013	#define EXTI_RTSR1_RT3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
EricLew	0:d4e5ad7ad71c	4014	#define EXTI_RTSR1_RT4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
EricLew	0:d4e5ad7ad71c	4015	#define EXTI_RTSR1_RT5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
EricLew	0:d4e5ad7ad71c	4016	#define EXTI_RTSR1_RT6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
EricLew	0:d4e5ad7ad71c	4017	#define EXTI_RTSR1_RT7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
EricLew	0:d4e5ad7ad71c	4018	#define EXTI_RTSR1_RT8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
EricLew	0:d4e5ad7ad71c	4019	#define EXTI_RTSR1_RT9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
EricLew	0:d4e5ad7ad71c	4020	#define EXTI_RTSR1_RT10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
EricLew	0:d4e5ad7ad71c	4021	#define EXTI_RTSR1_RT11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
EricLew	0:d4e5ad7ad71c	4022	#define EXTI_RTSR1_RT12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
EricLew	0:d4e5ad7ad71c	4023	#define EXTI_RTSR1_RT13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
EricLew	0:d4e5ad7ad71c	4024	#define EXTI_RTSR1_RT14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
EricLew	0:d4e5ad7ad71c	4025	#define EXTI_RTSR1_RT15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
EricLew	0:d4e5ad7ad71c	4026	#define EXTI_RTSR1_RT16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
EricLew	0:d4e5ad7ad71c	4027	#define EXTI_RTSR1_RT18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
EricLew	0:d4e5ad7ad71c	4028	#define EXTI_RTSR1_RT19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
EricLew	0:d4e5ad7ad71c	4029	#define EXTI_RTSR1_RT20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
EricLew	0:d4e5ad7ad71c	4030	#define EXTI_RTSR1_RT21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
EricLew	0:d4e5ad7ad71c	4031	#define EXTI_RTSR1_RT22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
EricLew	0:d4e5ad7ad71c	4032
EricLew	0:d4e5ad7ad71c	4033	/**************** Bit definition for EXTI_FTSR1 register ****************/
EricLew	0:d4e5ad7ad71c	4034	#define EXTI_FTSR1_FT0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
EricLew	0:d4e5ad7ad71c	4035	#define EXTI_FTSR1_FT1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
EricLew	0:d4e5ad7ad71c	4036	#define EXTI_FTSR1_FT2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
EricLew	0:d4e5ad7ad71c	4037	#define EXTI_FTSR1_FT3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
EricLew	0:d4e5ad7ad71c	4038	#define EXTI_FTSR1_FT4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
EricLew	0:d4e5ad7ad71c	4039	#define EXTI_FTSR1_FT5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
EricLew	0:d4e5ad7ad71c	4040	#define EXTI_FTSR1_FT6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
EricLew	0:d4e5ad7ad71c	4041	#define EXTI_FTSR1_FT7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
EricLew	0:d4e5ad7ad71c	4042	#define EXTI_FTSR1_FT8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
EricLew	0:d4e5ad7ad71c	4043	#define EXTI_FTSR1_FT9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
EricLew	0:d4e5ad7ad71c	4044	#define EXTI_FTSR1_FT10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
EricLew	0:d4e5ad7ad71c	4045	#define EXTI_FTSR1_FT11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
EricLew	0:d4e5ad7ad71c	4046	#define EXTI_FTSR1_FT12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
EricLew	0:d4e5ad7ad71c	4047	#define EXTI_FTSR1_FT13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
EricLew	0:d4e5ad7ad71c	4048	#define EXTI_FTSR1_FT14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
EricLew	0:d4e5ad7ad71c	4049	#define EXTI_FTSR1_FT15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
EricLew	0:d4e5ad7ad71c	4050	#define EXTI_FTSR1_FT16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
EricLew	0:d4e5ad7ad71c	4051	#define EXTI_FTSR1_FT18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
EricLew	0:d4e5ad7ad71c	4052	#define EXTI_FTSR1_FT19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
EricLew	0:d4e5ad7ad71c	4053	#define EXTI_FTSR1_FT20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
EricLew	0:d4e5ad7ad71c	4054	#define EXTI_FTSR1_FT21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
EricLew	0:d4e5ad7ad71c	4055	#define EXTI_FTSR1_FT22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
EricLew	0:d4e5ad7ad71c	4056
EricLew	0:d4e5ad7ad71c	4057	/**************** Bit definition for EXTI_SWIER1 register ***************/
EricLew	0:d4e5ad7ad71c	4058	#define EXTI_SWIER1_SWI0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
EricLew	0:d4e5ad7ad71c	4059	#define EXTI_SWIER1_SWI1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
EricLew	0:d4e5ad7ad71c	4060	#define EXTI_SWIER1_SWI2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
EricLew	0:d4e5ad7ad71c	4061	#define EXTI_SWIER1_SWI3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
EricLew	0:d4e5ad7ad71c	4062	#define EXTI_SWIER1_SWI4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
EricLew	0:d4e5ad7ad71c	4063	#define EXTI_SWIER1_SWI5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
EricLew	0:d4e5ad7ad71c	4064	#define EXTI_SWIER1_SWI6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
EricLew	0:d4e5ad7ad71c	4065	#define EXTI_SWIER1_SWI7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
EricLew	0:d4e5ad7ad71c	4066	#define EXTI_SWIER1_SWI8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
EricLew	0:d4e5ad7ad71c	4067	#define EXTI_SWIER1_SWI9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
EricLew	0:d4e5ad7ad71c	4068	#define EXTI_SWIER1_SWI10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
EricLew	0:d4e5ad7ad71c	4069	#define EXTI_SWIER1_SWI11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
EricLew	0:d4e5ad7ad71c	4070	#define EXTI_SWIER1_SWI12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
EricLew	0:d4e5ad7ad71c	4071	#define EXTI_SWIER1_SWI13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
EricLew	0:d4e5ad7ad71c	4072	#define EXTI_SWIER1_SWI14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
EricLew	0:d4e5ad7ad71c	4073	#define EXTI_SWIER1_SWI15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
EricLew	0:d4e5ad7ad71c	4074	#define EXTI_SWIER1_SWI16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
EricLew	0:d4e5ad7ad71c	4075	#define EXTI_SWIER1_SWI18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
EricLew	0:d4e5ad7ad71c	4076	#define EXTI_SWIER1_SWI19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
EricLew	0:d4e5ad7ad71c	4077	#define EXTI_SWIER1_SWI20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
EricLew	0:d4e5ad7ad71c	4078	#define EXTI_SWIER1_SWI21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
EricLew	0:d4e5ad7ad71c	4079	#define EXTI_SWIER1_SWI22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
EricLew	0:d4e5ad7ad71c	4080
EricLew	0:d4e5ad7ad71c	4081	/***************** Bit definition for EXTI_PR1 register *****************/
EricLew	0:d4e5ad7ad71c	4082	#define EXTI_PR1_PIF0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
EricLew	0:d4e5ad7ad71c	4083	#define EXTI_PR1_PIF1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
EricLew	0:d4e5ad7ad71c	4084	#define EXTI_PR1_PIF2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
EricLew	0:d4e5ad7ad71c	4085	#define EXTI_PR1_PIF3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
EricLew	0:d4e5ad7ad71c	4086	#define EXTI_PR1_PIF4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
EricLew	0:d4e5ad7ad71c	4087	#define EXTI_PR1_PIF5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
EricLew	0:d4e5ad7ad71c	4088	#define EXTI_PR1_PIF6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
EricLew	0:d4e5ad7ad71c	4089	#define EXTI_PR1_PIF7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
EricLew	0:d4e5ad7ad71c	4090	#define EXTI_PR1_PIF8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
EricLew	0:d4e5ad7ad71c	4091	#define EXTI_PR1_PIF9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
EricLew	0:d4e5ad7ad71c	4092	#define EXTI_PR1_PIF10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
EricLew	0:d4e5ad7ad71c	4093	#define EXTI_PR1_PIF11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
EricLew	0:d4e5ad7ad71c	4094	#define EXTI_PR1_PIF12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
EricLew	0:d4e5ad7ad71c	4095	#define EXTI_PR1_PIF13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
EricLew	0:d4e5ad7ad71c	4096	#define EXTI_PR1_PIF14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
EricLew	0:d4e5ad7ad71c	4097	#define EXTI_PR1_PIF15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
EricLew	0:d4e5ad7ad71c	4098	#define EXTI_PR1_PIF16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
EricLew	0:d4e5ad7ad71c	4099	#define EXTI_PR1_PIF18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
EricLew	0:d4e5ad7ad71c	4100	#define EXTI_PR1_PIF19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
EricLew	0:d4e5ad7ad71c	4101	#define EXTI_PR1_PIF20 ((uint32_t)0x00100000) /!< Pending bit for line 20 /
EricLew	0:d4e5ad7ad71c	4102	#define EXTI_PR1_PIF21 ((uint32_t)0x00200000) /!< Pending bit for line 21 /
EricLew	0:d4e5ad7ad71c	4103	#define EXTI_PR1_PIF22 ((uint32_t)0x00400000) /!< Pending bit for line 22 /
EricLew	0:d4e5ad7ad71c	4104
EricLew	0:d4e5ad7ad71c	4105	/***************** Bit definition for EXTI_IMR2 register ****************/
EricLew	0:d4e5ad7ad71c	4106	#define EXTI_IMR2_IM32 ((uint32_t)0x00000001) /!< Interrupt Mask on line 32 /
EricLew	0:d4e5ad7ad71c	4107	#define EXTI_IMR2_IM33 ((uint32_t)0x00000002) /!< Interrupt Mask on line 33 /
EricLew	0:d4e5ad7ad71c	4108	#define EXTI_IMR2_IM34 ((uint32_t)0x00000004) /!< Interrupt Mask on line 34 /
EricLew	0:d4e5ad7ad71c	4109	#define EXTI_IMR2_IM35 ((uint32_t)0x00000008) /!< Interrupt Mask on line 35 /
EricLew	0:d4e5ad7ad71c	4110	#define EXTI_IMR2_IM36 ((uint32_t)0x00000010) /!< Interrupt Mask on line 36 /
EricLew	0:d4e5ad7ad71c	4111	#define EXTI_IMR2_IM37 ((uint32_t)0x00000020) /!< Interrupt Mask on line 37 /
EricLew	0:d4e5ad7ad71c	4112	#define EXTI_IMR2_IM38 ((uint32_t)0x00000040) /!< Interrupt Mask on line 38 /
EricLew	0:d4e5ad7ad71c	4113	#define EXTI_IMR2_IM39 ((uint32_t)0x00000080) /!< Interrupt Mask on line 39 /
EricLew	0:d4e5ad7ad71c	4114
EricLew	0:d4e5ad7ad71c	4115	/***************** Bit definition for EXTI_EMR2 register ****************/
EricLew	0:d4e5ad7ad71c	4116	#define EXTI_EMR2_EM32 ((uint32_t)0x00000001) /!< Event Mask on line 32 /
EricLew	0:d4e5ad7ad71c	4117	#define EXTI_EMR2_EM33 ((uint32_t)0x00000002) /!< Event Mask on line 33 /
EricLew	0:d4e5ad7ad71c	4118	#define EXTI_EMR2_EM34 ((uint32_t)0x00000004) /!< Event Mask on line 34 /
EricLew	0:d4e5ad7ad71c	4119	#define EXTI_EMR2_EM35 ((uint32_t)0x00000008) /!< Event Mask on line 35 /
EricLew	0:d4e5ad7ad71c	4120	#define EXTI_EMR2_EM36 ((uint32_t)0x00000010) /!< Event Mask on line 36 /
EricLew	0:d4e5ad7ad71c	4121	#define EXTI_EMR2_EM37 ((uint32_t)0x00000020) /!< Event Mask on line 37 /
EricLew	0:d4e5ad7ad71c	4122	#define EXTI_EMR2_EM38 ((uint32_t)0x00000040) /!< Event Mask on line 38 /
EricLew	0:d4e5ad7ad71c	4123	#define EXTI_EMR2_EM39 ((uint32_t)0x00000080) /!< Event Mask on line 39 /
EricLew	0:d4e5ad7ad71c	4124
EricLew	0:d4e5ad7ad71c	4125	/**************** Bit definition for EXTI_RTSR2 register ****************/
EricLew	0:d4e5ad7ad71c	4126	#define EXTI_RTSR2_RT35 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 35 /
EricLew	0:d4e5ad7ad71c	4127	#define EXTI_RTSR2_RT36 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 36 /
EricLew	0:d4e5ad7ad71c	4128	#define EXTI_RTSR2_RT37 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 37 /
EricLew	0:d4e5ad7ad71c	4129	#define EXTI_RTSR2_RT38 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 38 /
EricLew	0:d4e5ad7ad71c	4130
EricLew	0:d4e5ad7ad71c	4131	/**************** Bit definition for EXTI_FTSR2 register ****************/
EricLew	0:d4e5ad7ad71c	4132	#define EXTI_FTSR2_FT35 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 35 /
EricLew	0:d4e5ad7ad71c	4133	#define EXTI_FTSR2_FT36 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 36 /
EricLew	0:d4e5ad7ad71c	4134	#define EXTI_FTSR2_FT37 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 37 /
EricLew	0:d4e5ad7ad71c	4135	#define EXTI_FTSR2_FT38 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 38 /
EricLew	0:d4e5ad7ad71c	4136
EricLew	0:d4e5ad7ad71c	4137	/**************** Bit definition for EXTI_SWIER2 register ***************/
EricLew	0:d4e5ad7ad71c	4138	#define EXTI_SWIER2_SWI35 ((uint32_t)0x00000008) /!< Software Interrupt on line 35 /
EricLew	0:d4e5ad7ad71c	4139	#define EXTI_SWIER2_SWI36 ((uint32_t)0x00000010) /!< Software Interrupt on line 36 /
EricLew	0:d4e5ad7ad71c	4140	#define EXTI_SWIER2_SWI37 ((uint32_t)0x00000020) /!< Software Interrupt on line 37 /
EricLew	0:d4e5ad7ad71c	4141	#define EXTI_SWIER2_SWI38 ((uint32_t)0x00000040) /!< Software Interrupt on line 38 /
EricLew	0:d4e5ad7ad71c	4142
EricLew	0:d4e5ad7ad71c	4143	/***************** Bit definition for EXTI_PR2 register *****************/
EricLew	0:d4e5ad7ad71c	4144	#define EXTI_PR2_PIF35 ((uint32_t)0x00000008) /!< Pending bit for line 35 /
EricLew	0:d4e5ad7ad71c	4145	#define EXTI_PR2_PIF36 ((uint32_t)0x00000010) /!< Pending bit for line 36 /
EricLew	0:d4e5ad7ad71c	4146	#define EXTI_PR2_PIF37 ((uint32_t)0x00000020) /!< Pending bit for line 37 /
EricLew	0:d4e5ad7ad71c	4147	#define EXTI_PR2_PIF38 ((uint32_t)0x00000040) /!< Pending bit for line 38 /
EricLew	0:d4e5ad7ad71c	4148
EricLew	0:d4e5ad7ad71c	4149
EricLew	0:d4e5ad7ad71c	4150	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4151	/* */
EricLew	0:d4e5ad7ad71c	4152	/* FLASH */
EricLew	0:d4e5ad7ad71c	4153	/* */
EricLew	0:d4e5ad7ad71c	4154	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4155	/***************** Bits definition for FLASH_ACR register ***************/
EricLew	0:d4e5ad7ad71c	4156	#define FLASH_ACR_LATENCY ((uint32_t)0x00000007)
EricLew	0:d4e5ad7ad71c	4157	#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
EricLew	0:d4e5ad7ad71c	4158	#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4159	#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4160	#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
EricLew	0:d4e5ad7ad71c	4161	#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4162	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4163	#define FLASH_ACR_ICEN ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4164	#define FLASH_ACR_DCEN ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4165	#define FLASH_ACR_ICRST ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4166	#define FLASH_ACR_DCRST ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4167	#define FLASH_ACR_RUN_PD ((uint32_t)0x00002000) /!< Flash power down mode during run /
EricLew	0:d4e5ad7ad71c	4168	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00004000) /!< Flash power down mode during sleep /
EricLew	0:d4e5ad7ad71c	4169
EricLew	0:d4e5ad7ad71c	4170	/***************** Bits definition for FLASH_SR register ****************/
EricLew	0:d4e5ad7ad71c	4171	#define FLASH_SR_EOP ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4172	#define FLASH_SR_OPERR ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4173	#define FLASH_SR_PROGERR ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4174	#define FLASH_SR_WRPERR ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4175	#define FLASH_SR_PGAERR ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4176	#define FLASH_SR_SIZERR ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4177	#define FLASH_SR_PGSERR ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4178	#define FLASH_SR_MISERR ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4179	#define FLASH_SR_FASTERR ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4180	#define FLASH_SR_RDERR ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4181	#define FLASH_SR_OPTVERR ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4182	#define FLASH_SR_BSY ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4183
EricLew	0:d4e5ad7ad71c	4184	/***************** Bits definition for FLASH_CR register ****************/
EricLew	0:d4e5ad7ad71c	4185	#define FLASH_CR_PG ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4186	#define FLASH_CR_PER ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4187	#define FLASH_CR_MER1 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4188	#define FLASH_CR_PNB ((uint32_t)0x000007F8)
EricLew	0:d4e5ad7ad71c	4189	#define FLASH_CR_BKER ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4190	#define FLASH_CR_MER2 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4191	#define FLASH_CR_STRT ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4192	#define FLASH_CR_OPTSTRT ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	4193	#define FLASH_CR_FSTPG ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	4194	#define FLASH_CR_EOPIE ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4195	#define FLASH_CR_ERRIE ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	4196	#define FLASH_CR_RDERRIE ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	4197	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	4198	#define FLASH_CR_OPTLOCK ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	4199	#define FLASH_CR_LOCK ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4200
EricLew	0:d4e5ad7ad71c	4201	/***************** Bits definition for FLASH_ECCR register *************/
EricLew	0:d4e5ad7ad71c	4202	#define FLASH_ECCR_ADDR_ECC ((uint32_t)0x0007FFFF)
EricLew	0:d4e5ad7ad71c	4203	#define FLASH_ECCR_BK_ECC ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	4204	#define FLASH_ECCR_SYSF_ECC ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	4205	#define FLASH_ECCR_ECCIE ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4206	#define FLASH_ECCR_ECCC ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	4207	#define FLASH_ECCR_ECCD ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4208
EricLew	0:d4e5ad7ad71c	4209	/***************** Bits definition for FLASH_OPTR register *************/
EricLew	0:d4e5ad7ad71c	4210	#define FLASH_OPTR_RDP ((uint32_t)0x000000FF)
EricLew	0:d4e5ad7ad71c	4211	#define FLASH_OPTR_BOR_LEV ((uint32_t)0x00000700)
EricLew	0:d4e5ad7ad71c	4212	#define FLASH_OPTR_BOR_LEV_0 ((uint32_t)0x00000000)
EricLew	0:d4e5ad7ad71c	4213	#define FLASH_OPTR_BOR_LEV_1 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4214	#define FLASH_OPTR_BOR_LEV_2 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4215	#define FLASH_OPTR_BOR_LEV_3 ((uint32_t)0x00000300)
EricLew	0:d4e5ad7ad71c	4216	#define FLASH_OPTR_BOR_LEV_4 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4217	#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4218	#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4219	#define FLASH_OPTR_nRST_SHDW ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4220	#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4221	#define FLASH_OPTR_IWDG_STOP ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	4222	#define FLASH_OPTR_IWDG_STDBY ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	4223	#define FLASH_OPTR_WWDG_SW ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	4224	#define FLASH_OPTR_BFB2 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	4225	#define FLASH_OPTR_DUALBANK ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	4226	#define FLASH_OPTR_nBOOT1 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	4227	#define FLASH_OPTR_SRAM2_PE ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4228	#define FLASH_OPTR_SRAM2_RST ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	4229
EricLew	0:d4e5ad7ad71c	4230	/**************** Bits definition for FLASH_PCROP1SR register ********/
EricLew	0:d4e5ad7ad71c	4231	#define FLASH_PCROP1SR_PCROP1_STRT ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	4232
EricLew	0:d4e5ad7ad71c	4233	/**************** Bits definition for FLASH_PCROP1ER register *********/
EricLew	0:d4e5ad7ad71c	4234	#define FLASH_PCROP1ER_PCROP1_END ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	4235	#define FLASH_PCROP1ER_PCROP_RDP ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4236
EricLew	0:d4e5ad7ad71c	4237	/**************** Bits definition for FLASH_WRP1AR register *************/
EricLew	0:d4e5ad7ad71c	4238	#define FLASH_WRP1AR_WRP1A_STRT ((uint32_t)0x000000FF)
EricLew	0:d4e5ad7ad71c	4239	#define FLASH_WRP1AR_WRP1A_END ((uint32_t)0x00FF0000)
EricLew	0:d4e5ad7ad71c	4240
EricLew	0:d4e5ad7ad71c	4241	/**************** Bits definition for FLASH_WRPB1R register *************/
EricLew	0:d4e5ad7ad71c	4242	#define FLASH_WRP1BR_WRP1B_STRT ((uint32_t)0x000000FF)
EricLew	0:d4e5ad7ad71c	4243	#define FLASH_WRP1BR_WRP1B_END ((uint32_t)0x00FF0000)
EricLew	0:d4e5ad7ad71c	4244
EricLew	0:d4e5ad7ad71c	4245	/**************** Bits definition for FLASH_PCROP2SR register ********/
EricLew	0:d4e5ad7ad71c	4246	#define FLASH_PCROP2SR_PCROP2_STRT ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	4247
EricLew	0:d4e5ad7ad71c	4248	/**************** Bits definition for FLASH_PCROP2ER register *********/
EricLew	0:d4e5ad7ad71c	4249	#define FLASH_PCROP2ER_PCROP2_END ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	4250
EricLew	0:d4e5ad7ad71c	4251	/**************** Bits definition for FLASH_WRP2AR register *************/
EricLew	0:d4e5ad7ad71c	4252	#define FLASH_WRP2AR_WRP2A_STRT ((uint32_t)0x000000FF)
EricLew	0:d4e5ad7ad71c	4253	#define FLASH_WRP2AR_WRP2A_END ((uint32_t)0x00FF0000)
EricLew	0:d4e5ad7ad71c	4254
EricLew	0:d4e5ad7ad71c	4255	/**************** Bits definition for FLASH_WRP2BR register *************/
EricLew	0:d4e5ad7ad71c	4256	#define FLASH_WRP2BR_WRP2B_STRT ((uint32_t)0x000000FF)
EricLew	0:d4e5ad7ad71c	4257	#define FLASH_WRP2BR_WRP2B_END ((uint32_t)0x00FF0000)
EricLew	0:d4e5ad7ad71c	4258
EricLew	0:d4e5ad7ad71c	4259
EricLew	0:d4e5ad7ad71c	4260	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4261	/* */
EricLew	0:d4e5ad7ad71c	4262	/* Flexible Memory Controller */
EricLew	0:d4e5ad7ad71c	4263	/* */
EricLew	0:d4e5ad7ad71c	4264	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4265	/**************** Bit definition for FMC_BCR1 register *****************/
EricLew	0:d4e5ad7ad71c	4266	#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /!<Continous clock enable /
EricLew	0:d4e5ad7ad71c	4267	#define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /!<Write FIFO Disable /
EricLew	0:d4e5ad7ad71c	4268
EricLew	0:d4e5ad7ad71c	4269	/**************** Bit definition for FMC_BCRx registers (x=1..4) *******/
EricLew	0:d4e5ad7ad71c	4270	#define FMC_BCRx_MBKEN ((uint32_t)0x00000001) /!<Memory bank enable bit /
EricLew	0:d4e5ad7ad71c	4271	#define FMC_BCRx_MUXEN ((uint32_t)0x00000002) /!<Address/data multiplexing enable bit /
EricLew	0:d4e5ad7ad71c	4272
EricLew	0:d4e5ad7ad71c	4273	#define FMC_BCRx_MTYP ((uint32_t)0x0000000C) /!<MTYP[1:0] bits (Memory type) /
EricLew	0:d4e5ad7ad71c	4274	#define FMC_BCRx_MTYP_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4275	#define FMC_BCRx_MTYP_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4276
EricLew	0:d4e5ad7ad71c	4277	#define FMC_BCRx_MWID ((uint32_t)0x00000030) /!<MWID[1:0] bits (Memory data bus width) /
EricLew	0:d4e5ad7ad71c	4278	#define FMC_BCRx_MWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4279	#define FMC_BCRx_MWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4280
EricLew	0:d4e5ad7ad71c	4281	#define FMC_BCRx_FACCEN ((uint32_t)0x00000040) /!<Flash access enable /
EricLew	0:d4e5ad7ad71c	4282	#define FMC_BCRx_BURSTEN ((uint32_t)0x00000100) /!<Burst enable bit /
EricLew	0:d4e5ad7ad71c	4283	#define FMC_BCRx_WAITPOL ((uint32_t)0x00000200) /!<Wait signal polarity bit /
EricLew	0:d4e5ad7ad71c	4284	#define FMC_BCRx_WAITCFG ((uint32_t)0x00000800) /!<Wait timing configuration /
EricLew	0:d4e5ad7ad71c	4285	#define FMC_BCRx_WREN ((uint32_t)0x00001000) /!<Write enable bit /
EricLew	0:d4e5ad7ad71c	4286	#define FMC_BCRx_WAITEN ((uint32_t)0x00002000) /!<Wait enable bit /
EricLew	0:d4e5ad7ad71c	4287	#define FMC_BCRx_EXTMOD ((uint32_t)0x00004000) /!<Extended mode enable /
EricLew	0:d4e5ad7ad71c	4288	#define FMC_BCRx_ASYNCWAIT ((uint32_t)0x00008000) /!<Asynchronous wait /
EricLew	0:d4e5ad7ad71c	4289
EricLew	0:d4e5ad7ad71c	4290	#define FMC_BCRx_CPSIZE ((uint32_t)0x00070000) /!<CRAM page size /
EricLew	0:d4e5ad7ad71c	4291	#define FMC_BCRx_CPSIZE_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4292	#define FMC_BCRx_CPSIZE_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4293	#define FMC_BCRx_CPSIZE_2 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4294
EricLew	0:d4e5ad7ad71c	4295	#define FMC_BCRx_CBURSTRW ((uint32_t)0x00080000) /!<Write burst enable /
EricLew	0:d4e5ad7ad71c	4296
EricLew	0:d4e5ad7ad71c	4297	/**************** Bit definition for FMC_BTRx registers (x=1..4) *******/
EricLew	0:d4e5ad7ad71c	4298	#define FMC_BTRx_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
EricLew	0:d4e5ad7ad71c	4299	#define FMC_BTRx_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4300	#define FMC_BTRx_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4301	#define FMC_BTRx_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4302	#define FMC_BTRx_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4303
EricLew	0:d4e5ad7ad71c	4304	#define FMC_BTRx_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
EricLew	0:d4e5ad7ad71c	4305	#define FMC_BTRx_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4306	#define FMC_BTRx_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4307	#define FMC_BTRx_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4308	#define FMC_BTRx_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4309
EricLew	0:d4e5ad7ad71c	4310	#define FMC_BTRx_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
EricLew	0:d4e5ad7ad71c	4311	#define FMC_BTRx_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4312	#define FMC_BTRx_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4313	#define FMC_BTRx_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4314	#define FMC_BTRx_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4315	#define FMC_BTRx_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4316	#define FMC_BTRx_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4317	#define FMC_BTRx_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4318	#define FMC_BTRx_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4319
EricLew	0:d4e5ad7ad71c	4320	#define FMC_BTRx_BUSTURN ((uint32_t)0x000F0000) /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
EricLew	0:d4e5ad7ad71c	4321	#define FMC_BTRx_BUSTURN_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4322	#define FMC_BTRx_BUSTURN_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4323	#define FMC_BTRx_BUSTURN_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4324	#define FMC_BTRx_BUSTURN_3 ((uint32_t)0x00080000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4325
EricLew	0:d4e5ad7ad71c	4326	#define FMC_BTRx_CLKDIV ((uint32_t)0x00F00000) /!<CLKDIV[3:0] bits (Clock divide ratio) /
EricLew	0:d4e5ad7ad71c	4327	#define FMC_BTRx_CLKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4328	#define FMC_BTRx_CLKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4329	#define FMC_BTRx_CLKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4330	#define FMC_BTRx_CLKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4331
EricLew	0:d4e5ad7ad71c	4332	#define FMC_BTRx_DATLAT ((uint32_t)0x0F000000) /!<DATLA[3:0] bits (Data latency) /
EricLew	0:d4e5ad7ad71c	4333	#define FMC_BTRx_DATLAT_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4334	#define FMC_BTRx_DATLAT_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4335	#define FMC_BTRx_DATLAT_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4336	#define FMC_BTRx_DATLAT_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4337
EricLew	0:d4e5ad7ad71c	4338	#define FMC_BTRx_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
EricLew	0:d4e5ad7ad71c	4339	#define FMC_BTRx_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4340	#define FMC_BTRx_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4341
EricLew	0:d4e5ad7ad71c	4342	/**************** Bit definition for FMC_BWTRx registers (x=1..4) *******/
EricLew	0:d4e5ad7ad71c	4343	#define FMC_BWTRx_ADDSET ((uint32_t)0x0000000F) /!<ADDSET[3:0] bits (Address setup phase duration) /
EricLew	0:d4e5ad7ad71c	4344	#define FMC_BWTRx_ADDSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4345	#define FMC_BWTRx_ADDSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4346	#define FMC_BWTRx_ADDSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4347	#define FMC_BWTRx_ADDSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4348
EricLew	0:d4e5ad7ad71c	4349	#define FMC_BWTRx_ADDHLD ((uint32_t)0x000000F0) /!<ADDHLD[3:0] bits (Address-hold phase duration) /
EricLew	0:d4e5ad7ad71c	4350	#define FMC_BWTRx_ADDHLD_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4351	#define FMC_BWTRx_ADDHLD_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4352	#define FMC_BWTRx_ADDHLD_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4353	#define FMC_BWTRx_ADDHLD_3 ((uint32_t)0x00000080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4354
EricLew	0:d4e5ad7ad71c	4355	#define FMC_BWTRx_DATAST ((uint32_t)0x0000FF00) /!<DATAST [3:0] bits (Data-phase duration) /
EricLew	0:d4e5ad7ad71c	4356	#define FMC_BWTRx_DATAST_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4357	#define FMC_BWTRx_DATAST_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4358	#define FMC_BWTRx_DATAST_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4359	#define FMC_BWTRx_DATAST_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4360	#define FMC_BWTRx_DATAST_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4361	#define FMC_BWTRx_DATAST_5 ((uint32_t)0x00002000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4362	#define FMC_BWTRx_DATAST_6 ((uint32_t)0x00004000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4363	#define FMC_BWTRx_DATAST_7 ((uint32_t)0x00008000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4364
EricLew	0:d4e5ad7ad71c	4365	#define FMC_BWTRx_ACCMOD ((uint32_t)0x30000000) /!<ACCMOD[1:0] bits (Access mode) /
EricLew	0:d4e5ad7ad71c	4366	#define FMC_BWTRx_ACCMOD_0 ((uint32_t)0x10000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4367	#define FMC_BWTRx_ACCMOD_1 ((uint32_t)0x20000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4368
EricLew	0:d4e5ad7ad71c	4369	/**************** Bit definition for FMC_PCR register ******************/
EricLew	0:d4e5ad7ad71c	4370	#define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /!<Wait feature enable bit /
EricLew	0:d4e5ad7ad71c	4371	#define FMC_PCR_PBKEN ((uint32_t)0x00000004) /!<NAND Flash memory bank enable bit /
EricLew	0:d4e5ad7ad71c	4372	#define FMC_PCR_PTYP ((uint32_t)0x00000008) /!<Memory type /
EricLew	0:d4e5ad7ad71c	4373
EricLew	0:d4e5ad7ad71c	4374	#define FMC_PCR_PWID ((uint32_t)0x00000030) /!<PWID[1:0] bits (NAND Flash databus width) /
EricLew	0:d4e5ad7ad71c	4375	#define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4376	#define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4377
EricLew	0:d4e5ad7ad71c	4378	#define FMC_PCR_ECCEN ((uint32_t)0x00000040) /!<ECC computation logic enable bit /
EricLew	0:d4e5ad7ad71c	4379
EricLew	0:d4e5ad7ad71c	4380	#define FMC_PCR_TCLR ((uint32_t)0x00001E00) /!<TCLR[3:0] bits (CLE to RE delay) /
EricLew	0:d4e5ad7ad71c	4381	#define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4382	#define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4383	#define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4384	#define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4385
EricLew	0:d4e5ad7ad71c	4386	#define FMC_PCR_TAR ((uint32_t)0x0001E000) /!<TAR[3:0] bits (ALE to RE delay) /
EricLew	0:d4e5ad7ad71c	4387	#define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4388	#define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4389	#define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4390	#define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4391
EricLew	0:d4e5ad7ad71c	4392	#define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /!<ECCPS[1:0] bits (ECC page size) /
EricLew	0:d4e5ad7ad71c	4393	#define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4394	#define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4395	#define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4396
EricLew	0:d4e5ad7ad71c	4397	/***************** Bit definition for FMC_SR register ******************/
EricLew	0:d4e5ad7ad71c	4398	#define FMC_SR_IRS ((uint32_t)0x00000001) /!<Interrupt Rising Edge status /
EricLew	0:d4e5ad7ad71c	4399	#define FMC_SR_ILS ((uint32_t)0x00000002) /!<Interrupt Level status /
EricLew	0:d4e5ad7ad71c	4400	#define FMC_SR_IFS ((uint32_t)0x00000004) /!<Interrupt Falling Edge status /
EricLew	0:d4e5ad7ad71c	4401	#define FMC_SR_IREN ((uint32_t)0x00000008) /!<Interrupt Rising Edge detection Enable bit /
EricLew	0:d4e5ad7ad71c	4402	#define FMC_SR_ILEN ((uint32_t)0x00000010) /!<Interrupt Level detection Enable bit /
EricLew	0:d4e5ad7ad71c	4403	#define FMC_SR_IFEN ((uint32_t)0x00000020) /!<Interrupt Falling Edge detection Enable bit /
EricLew	0:d4e5ad7ad71c	4404	#define FMC_SR_FEMPT ((uint32_t)0x00000040) /!<FIFO empty /
EricLew	0:d4e5ad7ad71c	4405
EricLew	0:d4e5ad7ad71c	4406	/**************** Bit definition for FMC_PMEM register ****************/
EricLew	0:d4e5ad7ad71c	4407	#define FMC_PMEM_MEMSET ((uint32_t)0x000000FF) /!<MEMSET[7:0] bits (Common memory setup time) /
EricLew	0:d4e5ad7ad71c	4408	#define FMC_PMEM_MEMSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4409	#define FMC_PMEM_MEMSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4410	#define FMC_PMEM_MEMSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4411	#define FMC_PMEM_MEMSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4412	#define FMC_PMEM_MEMSET_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4413	#define FMC_PMEM_MEMSET_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4414	#define FMC_PMEM_MEMSET_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4415	#define FMC_PMEM_MEMSET_7 ((uint32_t)0x00000080) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4416
EricLew	0:d4e5ad7ad71c	4417	#define FMC_PMEM_MEMWAIT ((uint32_t)0x0000FF00) /!<MEMWAIT[7:0] bits (Common memory wait time) /
EricLew	0:d4e5ad7ad71c	4418	#define FMC_PMEM_MEMWAIT_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4419	#define FMC_PMEM_MEMWAIT_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4420	#define FMC_PMEM_MEMWAIT_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4421	#define FMC_PMEM_MEMWAIT_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4422	#define FMC_PMEM_MEMWAIT_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4423	#define FMC_PMEM_MEMWAIT_5 ((uint32_t)0x00002000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4424	#define FMC_PMEM_MEMWAIT_6 ((uint32_t)0x00004000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4425	#define FMC_PMEM_MEMWAIT_7 ((uint32_t)0x00008000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4426
EricLew	0:d4e5ad7ad71c	4427	#define FMC_PMEM_MEMHOLD ((uint32_t)0x00FF0000) /!<MEMHOLD[7:0] bits (Common memory hold time) /
EricLew	0:d4e5ad7ad71c	4428	#define FMC_PMEM_MEMHOLD_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4429	#define FMC_PMEM_MEMHOLD_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4430	#define FMC_PMEM_MEMHOLD_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4431	#define FMC_PMEM_MEMHOLD_3 ((uint32_t)0x00080000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4432	#define FMC_PMEM_MEMHOLD_4 ((uint32_t)0x00100000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4433	#define FMC_PMEM_MEMHOLD_5 ((uint32_t)0x00200000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4434	#define FMC_PMEM_MEMHOLD_6 ((uint32_t)0x00400000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4435	#define FMC_PMEM_MEMHOLD_7 ((uint32_t)0x00800000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4436
EricLew	0:d4e5ad7ad71c	4437	#define FMC_PMEM_MEMHIZ ((uint32_t)0xFF000000) /!<MEMHIZ[7:0] bits (Common memory databus HiZ time) /
EricLew	0:d4e5ad7ad71c	4438	#define FMC_PMEM_MEMHIZ_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4439	#define FMC_PMEM_MEMHIZ_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4440	#define FMC_PMEM_MEMHIZ_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4441	#define FMC_PMEM_MEMHIZ_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4442	#define FMC_PMEM_MEMHIZ_4 ((uint32_t)0x10000000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4443	#define FMC_PMEM_MEMHIZ_5 ((uint32_t)0x20000000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4444	#define FMC_PMEM_MEMHIZ_6 ((uint32_t)0x40000000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4445	#define FMC_PMEM_MEMHIZ_7 ((uint32_t)0x80000000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4446
EricLew	0:d4e5ad7ad71c	4447	/**************** Bit definition for FMC_PATT register *****************/
EricLew	0:d4e5ad7ad71c	4448	#define FMC_PATT_ATTSET ((uint32_t)0x000000FF) /!<ATTSET[7:0] bits (Attribute memory setup time) /
EricLew	0:d4e5ad7ad71c	4449	#define FMC_PATT_ATTSET_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4450	#define FMC_PATT_ATTSET_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4451	#define FMC_PATT_ATTSET_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4452	#define FMC_PATT_ATTSET_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4453	#define FMC_PATT_ATTSET_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4454	#define FMC_PATT_ATTSET_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4455	#define FMC_PATT_ATTSET_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4456	#define FMC_PATT_ATTSET_7 ((uint32_t)0x00000080) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4457
EricLew	0:d4e5ad7ad71c	4458	#define FMC_PATT_ATTWAIT ((uint32_t)0x0000FF00) /!<ATTWAIT[7:0] bits (Attribute memory wait time) /
EricLew	0:d4e5ad7ad71c	4459	#define FMC_PATT_ATTWAIT_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4460	#define FMC_PATT_ATTWAIT_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4461	#define FMC_PATT_ATTWAIT_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4462	#define FMC_PATT_ATTWAIT_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4463	#define FMC_PATT_ATTWAIT_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4464	#define FMC_PATT_ATTWAIT_5 ((uint32_t)0x00002000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4465	#define FMC_PATT_ATTWAIT_6 ((uint32_t)0x00004000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4466	#define FMC_PATT_ATTWAIT_7 ((uint32_t)0x00008000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4467
EricLew	0:d4e5ad7ad71c	4468	#define FMC_PATT_ATTHOLD ((uint32_t)0x00FF0000) /!<ATTHOLD[7:0] bits (Attribute memory hold time) /
EricLew	0:d4e5ad7ad71c	4469	#define FMC_PATT_ATTHOLD_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4470	#define FMC_PATT_ATTHOLD_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4471	#define FMC_PATT_ATTHOLD_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4472	#define FMC_PATT_ATTHOLD_3 ((uint32_t)0x00080000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4473	#define FMC_PATT_ATTHOLD_4 ((uint32_t)0x00100000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4474	#define FMC_PATT_ATTHOLD_5 ((uint32_t)0x00200000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4475	#define FMC_PATT_ATTHOLD_6 ((uint32_t)0x00400000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4476	#define FMC_PATT_ATTHOLD_7 ((uint32_t)0x00800000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4477
EricLew	0:d4e5ad7ad71c	4478	#define FMC_PATT_ATTHIZ ((uint32_t)0xFF000000) /!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) /
EricLew	0:d4e5ad7ad71c	4479	#define FMC_PATT_ATTHIZ_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4480	#define FMC_PATT_ATTHIZ_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4481	#define FMC_PATT_ATTHIZ_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4482	#define FMC_PATT_ATTHIZ_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	4483	#define FMC_PATT_ATTHIZ_4 ((uint32_t)0x10000000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	4484	#define FMC_PATT_ATTHIZ_5 ((uint32_t)0x20000000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	4485	#define FMC_PATT_ATTHIZ_6 ((uint32_t)0x40000000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	4486	#define FMC_PATT_ATTHIZ_7 ((uint32_t)0x80000000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	4487
EricLew	0:d4e5ad7ad71c	4488	/**************** Bit definition for FMC_ECCR register *****************/
EricLew	0:d4e5ad7ad71c	4489	#define FMC_ECCR_ECC ((uint32_t)0xFFFFFFFF) /!<ECC result /
EricLew	0:d4e5ad7ad71c	4490
EricLew	0:d4e5ad7ad71c	4491	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4492	/* */
EricLew	0:d4e5ad7ad71c	4493	/* General Purpose I/O */
EricLew	0:d4e5ad7ad71c	4494	/* */
EricLew	0:d4e5ad7ad71c	4495	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4496	/**************** Bits definition for GPIO_MODER register ***************/
EricLew	0:d4e5ad7ad71c	4497	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
EricLew	0:d4e5ad7ad71c	4498	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4499	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4500	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
EricLew	0:d4e5ad7ad71c	4501	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4502	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4503	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
EricLew	0:d4e5ad7ad71c	4504	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4505	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4506	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
EricLew	0:d4e5ad7ad71c	4507	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4508	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4509	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
EricLew	0:d4e5ad7ad71c	4510	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4511	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4512	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
EricLew	0:d4e5ad7ad71c	4513	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4514	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4515	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
EricLew	0:d4e5ad7ad71c	4516	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4517	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4518	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
EricLew	0:d4e5ad7ad71c	4519	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4520	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4521	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
EricLew	0:d4e5ad7ad71c	4522	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4523	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	4524	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
EricLew	0:d4e5ad7ad71c	4525	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	4526	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	4527	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	4528	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	4529	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	4530	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
EricLew	0:d4e5ad7ad71c	4531	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	4532	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	4533	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
EricLew	0:d4e5ad7ad71c	4534	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4535	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	4536	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
EricLew	0:d4e5ad7ad71c	4537	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	4538	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	4539	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
EricLew	0:d4e5ad7ad71c	4540	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	4541	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	4542	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
EricLew	0:d4e5ad7ad71c	4543	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	4544	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4545
EricLew	0:d4e5ad7ad71c	4546	/**************** Bits definition for GPIO_OTYPER register **************/
EricLew	0:d4e5ad7ad71c	4547	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4548	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4549	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4550	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4551	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4552	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4553	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4554	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4555	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4556	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4557	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4558	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4559	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4560	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4561	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4562	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4563
EricLew	0:d4e5ad7ad71c	4564	/**************** Bits definition for GPIO_OSPEEDR register *************/
EricLew	0:d4e5ad7ad71c	4565	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
EricLew	0:d4e5ad7ad71c	4566	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4567	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4568	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
EricLew	0:d4e5ad7ad71c	4569	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4570	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4571	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
EricLew	0:d4e5ad7ad71c	4572	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4573	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4574	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
EricLew	0:d4e5ad7ad71c	4575	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4576	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4577	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
EricLew	0:d4e5ad7ad71c	4578	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4579	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4580	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
EricLew	0:d4e5ad7ad71c	4581	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4582	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4583	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
EricLew	0:d4e5ad7ad71c	4584	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4585	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4586	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
EricLew	0:d4e5ad7ad71c	4587	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4588	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4589	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
EricLew	0:d4e5ad7ad71c	4590	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4591	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	4592	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
EricLew	0:d4e5ad7ad71c	4593	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	4594	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	4595	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	4596	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	4597	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	4598	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
EricLew	0:d4e5ad7ad71c	4599	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	4600	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	4601	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
EricLew	0:d4e5ad7ad71c	4602	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4603	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	4604	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
EricLew	0:d4e5ad7ad71c	4605	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	4606	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	4607	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
EricLew	0:d4e5ad7ad71c	4608	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	4609	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	4610	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
EricLew	0:d4e5ad7ad71c	4611	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	4612	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4613
EricLew	0:d4e5ad7ad71c	4614	/**************** Bits definition for GPIO_PUPDR register ***************/
EricLew	0:d4e5ad7ad71c	4615	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
EricLew	0:d4e5ad7ad71c	4616	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4617	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4618	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
EricLew	0:d4e5ad7ad71c	4619	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4620	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4621	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
EricLew	0:d4e5ad7ad71c	4622	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4623	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4624	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
EricLew	0:d4e5ad7ad71c	4625	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4626	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4627	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
EricLew	0:d4e5ad7ad71c	4628	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4629	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4630	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
EricLew	0:d4e5ad7ad71c	4631	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4632	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4633	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
EricLew	0:d4e5ad7ad71c	4634	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4635	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4636	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
EricLew	0:d4e5ad7ad71c	4637	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4638	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4639	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
EricLew	0:d4e5ad7ad71c	4640	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4641	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	4642	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
EricLew	0:d4e5ad7ad71c	4643	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	4644	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	4645	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	4646	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	4647	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	4648	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
EricLew	0:d4e5ad7ad71c	4649	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	4650	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	4651	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
EricLew	0:d4e5ad7ad71c	4652	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4653	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	4654	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
EricLew	0:d4e5ad7ad71c	4655	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	4656	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	4657	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
EricLew	0:d4e5ad7ad71c	4658	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	4659	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	4660	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
EricLew	0:d4e5ad7ad71c	4661	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	4662	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4663
EricLew	0:d4e5ad7ad71c	4664	/**************** Bits definition for GPIO_IDR register *****************/
EricLew	0:d4e5ad7ad71c	4665	#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4666	#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4667	#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4668	#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4669	#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4670	#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4671	#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4672	#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4673	#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4674	#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4675	#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4676	#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4677	#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4678	#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4679	#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4680	#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4681
EricLew	0:d4e5ad7ad71c	4682	/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
EricLew	0:d4e5ad7ad71c	4683	#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
EricLew	0:d4e5ad7ad71c	4684	#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
EricLew	0:d4e5ad7ad71c	4685	#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
EricLew	0:d4e5ad7ad71c	4686	#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
EricLew	0:d4e5ad7ad71c	4687	#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
EricLew	0:d4e5ad7ad71c	4688	#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
EricLew	0:d4e5ad7ad71c	4689	#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
EricLew	0:d4e5ad7ad71c	4690	#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
EricLew	0:d4e5ad7ad71c	4691	#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
EricLew	0:d4e5ad7ad71c	4692	#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
EricLew	0:d4e5ad7ad71c	4693	#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
EricLew	0:d4e5ad7ad71c	4694	#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
EricLew	0:d4e5ad7ad71c	4695	#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
EricLew	0:d4e5ad7ad71c	4696	#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
EricLew	0:d4e5ad7ad71c	4697	#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
EricLew	0:d4e5ad7ad71c	4698	#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
EricLew	0:d4e5ad7ad71c	4699
EricLew	0:d4e5ad7ad71c	4700	/**************** Bits definition for GPIO_ODR register *****************/
EricLew	0:d4e5ad7ad71c	4701	#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4702	#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4703	#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4704	#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4705	#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4706	#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4707	#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4708	#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4709	#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4710	#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4711	#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4712	#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4713	#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4714	#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4715	#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4716	#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4717
EricLew	0:d4e5ad7ad71c	4718	/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
EricLew	0:d4e5ad7ad71c	4719	#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
EricLew	0:d4e5ad7ad71c	4720	#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
EricLew	0:d4e5ad7ad71c	4721	#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
EricLew	0:d4e5ad7ad71c	4722	#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
EricLew	0:d4e5ad7ad71c	4723	#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
EricLew	0:d4e5ad7ad71c	4724	#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
EricLew	0:d4e5ad7ad71c	4725	#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
EricLew	0:d4e5ad7ad71c	4726	#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
EricLew	0:d4e5ad7ad71c	4727	#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
EricLew	0:d4e5ad7ad71c	4728	#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
EricLew	0:d4e5ad7ad71c	4729	#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
EricLew	0:d4e5ad7ad71c	4730	#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
EricLew	0:d4e5ad7ad71c	4731	#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
EricLew	0:d4e5ad7ad71c	4732	#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
EricLew	0:d4e5ad7ad71c	4733	#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
EricLew	0:d4e5ad7ad71c	4734	#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
EricLew	0:d4e5ad7ad71c	4735
EricLew	0:d4e5ad7ad71c	4736	/**************** Bits definition for GPIO_BSRR register ****************/
EricLew	0:d4e5ad7ad71c	4737	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4738	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4739	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4740	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4741	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4742	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4743	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4744	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4745	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4746	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4747	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4748	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4749	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4750	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4751	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4752	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4753	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4754	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	4755	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	4756	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	4757	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	4758	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	4759	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	4760	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	4761	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	4762	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	4763	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	4764	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	4765	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	4766	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	4767	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	4768	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	4769
EricLew	0:d4e5ad7ad71c	4770	/**************** Bits definition for GPIO_BRR register ****************/
EricLew	0:d4e5ad7ad71c	4771	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4772	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4773	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4774	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4775	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4776	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4777	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4778	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4779	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4780	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4781	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4782	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4783	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4784	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4785	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4786	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4787
EricLew	0:d4e5ad7ad71c	4788	/**************** Bit definition for GPIO_LCKR register *******************/
EricLew	0:d4e5ad7ad71c	4789	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4790	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4791	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4792	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4793	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4794	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4795	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4796	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4797	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4798	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4799	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4800	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4801	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4802	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4803	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4804	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4805	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	4806
EricLew	0:d4e5ad7ad71c	4807	/**************** Bit definition for GPIO_AFRL register ******************/
EricLew	0:d4e5ad7ad71c	4808	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	4809	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
EricLew	0:d4e5ad7ad71c	4810	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	4811	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
EricLew	0:d4e5ad7ad71c	4812	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	4813	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
EricLew	0:d4e5ad7ad71c	4814	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
EricLew	0:d4e5ad7ad71c	4815	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
EricLew	0:d4e5ad7ad71c	4816
EricLew	0:d4e5ad7ad71c	4817	/**************** Bit definition for GPIO_AFRH register ******************/
EricLew	0:d4e5ad7ad71c	4818	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	4819	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
EricLew	0:d4e5ad7ad71c	4820	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	4821	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
EricLew	0:d4e5ad7ad71c	4822	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	4823	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
EricLew	0:d4e5ad7ad71c	4824	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
EricLew	0:d4e5ad7ad71c	4825	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
EricLew	0:d4e5ad7ad71c	4826
EricLew	0:d4e5ad7ad71c	4827	/**************** Bits definition for GPIO_ASCR register *****************/
EricLew	0:d4e5ad7ad71c	4828	#define GPIO_ASCR_EN_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	4829	#define GPIO_ASCR_EN_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	4830	#define GPIO_ASCR_EN_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	4831	#define GPIO_ASCR_EN_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	4832	#define GPIO_ASCR_EN_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	4833	#define GPIO_ASCR_EN_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	4834	#define GPIO_ASCR_EN_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	4835	#define GPIO_ASCR_EN_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	4836	#define GPIO_ASCR_EN_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	4837	#define GPIO_ASCR_EN_9 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	4838	#define GPIO_ASCR_EN_10 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	4839	#define GPIO_ASCR_EN_11 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	4840	#define GPIO_ASCR_EN_12 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	4841	#define GPIO_ASCR_EN_13 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	4842	#define GPIO_ASCR_EN_14 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	4843	#define GPIO_ASCR_EN_15 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	4844
EricLew	0:d4e5ad7ad71c	4845	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4846	/* */
EricLew	0:d4e5ad7ad71c	4847	/* Inter-integrated Circuit Interface (I2C) */
EricLew	0:d4e5ad7ad71c	4848	/* */
EricLew	0:d4e5ad7ad71c	4849	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4850	/***************** Bit definition for I2C_CR1 register *****************/
EricLew	0:d4e5ad7ad71c	4851	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
EricLew	0:d4e5ad7ad71c	4852	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
EricLew	0:d4e5ad7ad71c	4853	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
EricLew	0:d4e5ad7ad71c	4854	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
EricLew	0:d4e5ad7ad71c	4855	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
EricLew	0:d4e5ad7ad71c	4856	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
EricLew	0:d4e5ad7ad71c	4857	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
EricLew	0:d4e5ad7ad71c	4858	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
EricLew	0:d4e5ad7ad71c	4859	#define I2C_CR1_DNF ((uint32_t)0x00000F00) /!< Digital noise filter /
EricLew	0:d4e5ad7ad71c	4860	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
EricLew	0:d4e5ad7ad71c	4861	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
EricLew	0:d4e5ad7ad71c	4862	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
EricLew	0:d4e5ad7ad71c	4863	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
EricLew	0:d4e5ad7ad71c	4864	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
EricLew	0:d4e5ad7ad71c	4865	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
EricLew	0:d4e5ad7ad71c	4866	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
EricLew	0:d4e5ad7ad71c	4867	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
EricLew	0:d4e5ad7ad71c	4868	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
EricLew	0:d4e5ad7ad71c	4869	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
EricLew	0:d4e5ad7ad71c	4870	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
EricLew	0:d4e5ad7ad71c	4871	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
EricLew	0:d4e5ad7ad71c	4872
EricLew	0:d4e5ad7ad71c	4873	/**************** Bit definition for I2C_CR2 register ******************/
EricLew	0:d4e5ad7ad71c	4874	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
EricLew	0:d4e5ad7ad71c	4875	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
EricLew	0:d4e5ad7ad71c	4876	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
EricLew	0:d4e5ad7ad71c	4877	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
EricLew	0:d4e5ad7ad71c	4878	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
EricLew	0:d4e5ad7ad71c	4879	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
EricLew	0:d4e5ad7ad71c	4880	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
EricLew	0:d4e5ad7ad71c	4881	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
EricLew	0:d4e5ad7ad71c	4882	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
EricLew	0:d4e5ad7ad71c	4883	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
EricLew	0:d4e5ad7ad71c	4884	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
EricLew	0:d4e5ad7ad71c	4885
EricLew	0:d4e5ad7ad71c	4886	/***************** Bit definition for I2C_OAR1 register ****************/
EricLew	0:d4e5ad7ad71c	4887	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
EricLew	0:d4e5ad7ad71c	4888	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
EricLew	0:d4e5ad7ad71c	4889	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
EricLew	0:d4e5ad7ad71c	4890
EricLew	0:d4e5ad7ad71c	4891	/***************** Bit definition for I2C_OAR2 register ****************/
EricLew	0:d4e5ad7ad71c	4892	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
EricLew	0:d4e5ad7ad71c	4893	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
EricLew	0:d4e5ad7ad71c	4894	#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /!< No mask /
EricLew	0:d4e5ad7ad71c	4895	#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /!< OA2[1] is masked, Only OA2[7:2] are compared /
EricLew	0:d4e5ad7ad71c	4896	#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
EricLew	0:d4e5ad7ad71c	4897	#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
EricLew	0:d4e5ad7ad71c	4898	#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
EricLew	0:d4e5ad7ad71c	4899	#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
EricLew	0:d4e5ad7ad71c	4900	#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /!< OA2[6:1] is masked, Only OA2[7] are compared /
EricLew	0:d4e5ad7ad71c	4901	#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /!< OA2[7:1] is masked, No comparison is done /
EricLew	0:d4e5ad7ad71c	4902	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
EricLew	0:d4e5ad7ad71c	4903
EricLew	0:d4e5ad7ad71c	4904	/***************** Bit definition for I2C_TIMINGR register *****************/
EricLew	0:d4e5ad7ad71c	4905	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
EricLew	0:d4e5ad7ad71c	4906	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
EricLew	0:d4e5ad7ad71c	4907	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
EricLew	0:d4e5ad7ad71c	4908	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
EricLew	0:d4e5ad7ad71c	4909	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
EricLew	0:d4e5ad7ad71c	4910
EricLew	0:d4e5ad7ad71c	4911	/***************** Bit definition for I2C_TIMEOUTR register *****************/
EricLew	0:d4e5ad7ad71c	4912	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
EricLew	0:d4e5ad7ad71c	4913	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
EricLew	0:d4e5ad7ad71c	4914	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
EricLew	0:d4e5ad7ad71c	4915	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B /
EricLew	0:d4e5ad7ad71c	4916	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
EricLew	0:d4e5ad7ad71c	4917
EricLew	0:d4e5ad7ad71c	4918	/**************** Bit definition for I2C_ISR register *******************/
EricLew	0:d4e5ad7ad71c	4919	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
EricLew	0:d4e5ad7ad71c	4920	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
EricLew	0:d4e5ad7ad71c	4921	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
EricLew	0:d4e5ad7ad71c	4922	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode) /
EricLew	0:d4e5ad7ad71c	4923	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
EricLew	0:d4e5ad7ad71c	4924	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
EricLew	0:d4e5ad7ad71c	4925	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
EricLew	0:d4e5ad7ad71c	4926	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
EricLew	0:d4e5ad7ad71c	4927	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
EricLew	0:d4e5ad7ad71c	4928	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
EricLew	0:d4e5ad7ad71c	4929	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
EricLew	0:d4e5ad7ad71c	4930	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
EricLew	0:d4e5ad7ad71c	4931	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
EricLew	0:d4e5ad7ad71c	4932	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
EricLew	0:d4e5ad7ad71c	4933	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
EricLew	0:d4e5ad7ad71c	4934	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
EricLew	0:d4e5ad7ad71c	4935	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
EricLew	0:d4e5ad7ad71c	4936
EricLew	0:d4e5ad7ad71c	4937	/**************** Bit definition for I2C_ICR register *******************/
EricLew	0:d4e5ad7ad71c	4938	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
EricLew	0:d4e5ad7ad71c	4939	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
EricLew	0:d4e5ad7ad71c	4940	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
EricLew	0:d4e5ad7ad71c	4941	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
EricLew	0:d4e5ad7ad71c	4942	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
EricLew	0:d4e5ad7ad71c	4943	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
EricLew	0:d4e5ad7ad71c	4944	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
EricLew	0:d4e5ad7ad71c	4945	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
EricLew	0:d4e5ad7ad71c	4946	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
EricLew	0:d4e5ad7ad71c	4947
EricLew	0:d4e5ad7ad71c	4948	/**************** Bit definition for I2C_PECR register *******************/
EricLew	0:d4e5ad7ad71c	4949	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
EricLew	0:d4e5ad7ad71c	4950
EricLew	0:d4e5ad7ad71c	4951	/**************** Bit definition for I2C_RXDR register *******************/
EricLew	0:d4e5ad7ad71c	4952	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
EricLew	0:d4e5ad7ad71c	4953
EricLew	0:d4e5ad7ad71c	4954	/**************** Bit definition for I2C_TXDR register *******************/
EricLew	0:d4e5ad7ad71c	4955	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
EricLew	0:d4e5ad7ad71c	4956
EricLew	0:d4e5ad7ad71c	4957	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4958	/* */
EricLew	0:d4e5ad7ad71c	4959	/* Independent WATCHDOG */
EricLew	0:d4e5ad7ad71c	4960	/* */
EricLew	0:d4e5ad7ad71c	4961	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4962	/***************** Bit definition for IWDG_KR register ******************/
EricLew	0:d4e5ad7ad71c	4963	#define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /!<Key value (write only, read 0000h) /
EricLew	0:d4e5ad7ad71c	4964
EricLew	0:d4e5ad7ad71c	4965	/***************** Bit definition for IWDG_PR register ******************/
EricLew	0:d4e5ad7ad71c	4966	#define IWDG_PR_PR ((uint32_t)0x00000007) /!<PR[2:0] (Prescaler divider) /
EricLew	0:d4e5ad7ad71c	4967	#define IWDG_PR_PR_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	4968	#define IWDG_PR_PR_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	4969	#define IWDG_PR_PR_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	4970
EricLew	0:d4e5ad7ad71c	4971	/***************** Bit definition for IWDG_RLR register *****************/
EricLew	0:d4e5ad7ad71c	4972	#define IWDG_RLR_RL ((uint32_t)0x00000FFF) /!<Watchdog counter reload value /
EricLew	0:d4e5ad7ad71c	4973
EricLew	0:d4e5ad7ad71c	4974	/***************** Bit definition for IWDG_SR register ******************/
EricLew	0:d4e5ad7ad71c	4975	#define IWDG_SR_PVU ((uint32_t)0x00000001) /!< Watchdog prescaler value update /
EricLew	0:d4e5ad7ad71c	4976	#define IWDG_SR_RVU ((uint32_t)0x00000002) /!< Watchdog counter reload value update /
EricLew	0:d4e5ad7ad71c	4977	#define IWDG_SR_WVU ((uint32_t)0x00000004) /!< Watchdog counter window value update /
EricLew	0:d4e5ad7ad71c	4978
EricLew	0:d4e5ad7ad71c	4979	/***************** Bit definition for IWDG_KR register ******************/
EricLew	0:d4e5ad7ad71c	4980	#define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /!< Watchdog counter window value /
EricLew	0:d4e5ad7ad71c	4981
EricLew	0:d4e5ad7ad71c	4982	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4983	/* */
EricLew	0:d4e5ad7ad71c	4984	/* Firewall */
EricLew	0:d4e5ad7ad71c	4985	/* */
EricLew	0:d4e5ad7ad71c	4986	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	4987
EricLew	0:d4e5ad7ad71c	4988	/******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL;LSSA;LSL register /
EricLew	0:d4e5ad7ad71c	4989	#define FW_CSSA_ADD ((uint32_t)0x00FFFF00) /!< Code Segment Start Address /
EricLew	0:d4e5ad7ad71c	4990	#define FW_CSL_LENG ((uint32_t)0x003FFF00) /!< Code Segment Length /
EricLew	0:d4e5ad7ad71c	4991	#define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00) /!< Non Volatile Dat Segment Start Address /
EricLew	0:d4e5ad7ad71c	4992	#define FW_NVDSL_LENG ((uint32_t)0x003FFF00) /!< Non Volatile Data Segment Length /
EricLew	0:d4e5ad7ad71c	4993	#define FW_VDSSA_ADD ((uint32_t)0x0001FFC0) /!< Volatile Data Segment Start Address /
EricLew	0:d4e5ad7ad71c	4994	#define FW_VDSL_LENG ((uint32_t)0x0001FFC0) /!< Volatile Data Segment Length /
EricLew	0:d4e5ad7ad71c	4995	#define FW_LSSA_ADD ((uint32_t)0x0007FF80) /!< Library Segment Start Address/
EricLew	0:d4e5ad7ad71c	4996	#define FW_LSL_LENG ((uint32_t)0x0007FF80) /!< Library Segment Length/
EricLew	0:d4e5ad7ad71c	4997
EricLew	0:d4e5ad7ad71c	4998	/************************Bit definition for CR register *******************/
EricLew	0:d4e5ad7ad71c	4999	#define FW_CR_FPA ((uint32_t)0x00000001) /!< Firewall Pre Arm/
EricLew	0:d4e5ad7ad71c	5000	#define FW_CR_VDS ((uint32_t)0x00000002) /!< Volatile Data Sharing/
EricLew	0:d4e5ad7ad71c	5001	#define FW_CR_VDE ((uint32_t)0x00000004) /!< Volatile Data Execution/
EricLew	0:d4e5ad7ad71c	5002
EricLew	0:d4e5ad7ad71c	5003	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5004	/* */
EricLew	0:d4e5ad7ad71c	5005	/* Power Control */
EricLew	0:d4e5ad7ad71c	5006	/* */
EricLew	0:d4e5ad7ad71c	5007	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5008
EricLew	0:d4e5ad7ad71c	5009	/****************** Bit definition for PWR_CR1 register ******************/
EricLew	0:d4e5ad7ad71c	5010
EricLew	0:d4e5ad7ad71c	5011	#define PWR_CR1_LPR ((uint32_t)0x00004000) /!< Regulator low-power mode /
EricLew	0:d4e5ad7ad71c	5012	#define PWR_CR1_VOS ((uint32_t)0x00000600) /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
EricLew	0:d4e5ad7ad71c	5013	#define PWR_CR1_VOS_0 ((uint32_t)0x00000200) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	5014	#define PWR_CR1_VOS_1 ((uint32_t)0x00000400) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	5015	#define PWR_CR1_DBP ((uint32_t)0x00000100) /!< Disable Back-up domain Protection /
EricLew	0:d4e5ad7ad71c	5016	#define PWR_CR1_LPMS ((uint32_t)0x00000007) /!< Low-power mode selection field /
EricLew	0:d4e5ad7ad71c	5017	#define PWR_CR1_LPMS_STOP1MR ((uint32_t)0x00000000) /!< Stop 1 mode with Main Regulator /
EricLew	0:d4e5ad7ad71c	5018	#define PWR_CR1_LPMS_STOP1LPR ((uint32_t)0x00000001) /!< Stop 1 mode with Low-Power Regulator /
EricLew	0:d4e5ad7ad71c	5019	#define PWR_CR1_LPMS_STOP2 ((uint32_t)0x00000002) /!< Stop 2 mode /
EricLew	0:d4e5ad7ad71c	5020	#define PWR_CR1_LPMS_STANDBY ((uint32_t)0x00000003) /!< Stand-by mode /
EricLew	0:d4e5ad7ad71c	5021	#define PWR_CR1_LPMS_SHUTDOWN ((uint32_t)0x00000004) /!< Shut-down mode /
EricLew	0:d4e5ad7ad71c	5022
EricLew	0:d4e5ad7ad71c	5023
EricLew	0:d4e5ad7ad71c	5024	/****************** Bit definition for PWR_CR2 register ******************/
EricLew	0:d4e5ad7ad71c	5025	#define PWR_CR2_USV ((uint32_t)0x00000400) /!< VDD USB Supply Valid /
EricLew	0:d4e5ad7ad71c	5026	#define PWR_CR2_IOSV ((uint32_t)0x00000200) /!< VDD IO2 independent I/Os Supply Valid /
EricLew	0:d4e5ad7ad71c	5027	/!< PVME Peripheral Voltage Monitor Enable /
EricLew	0:d4e5ad7ad71c	5028	#define PWR_CR2_PVME ((uint32_t)0x000000F0) /!< PVM bits field /
EricLew	0:d4e5ad7ad71c	5029	#define PWR_CR2_PVME4 ((uint32_t)0x00000080) /!< PVM 4 Enable /
EricLew	0:d4e5ad7ad71c	5030	#define PWR_CR2_PVME3 ((uint32_t)0x00000040) /!< PVM 3 Enable /
EricLew	0:d4e5ad7ad71c	5031	#define PWR_CR2_PVME2 ((uint32_t)0x00000020) /!< PVM 2 Enable /
EricLew	0:d4e5ad7ad71c	5032	#define PWR_CR2_PVME1 ((uint32_t)0x00000010) /!< PVM 1 Enable /
EricLew	0:d4e5ad7ad71c	5033	/!< PVD level configuration /
EricLew	0:d4e5ad7ad71c	5034	#define PWR_CR2_PLS ((uint32_t)0x0000000E) /!< PVD level selection /
EricLew	0:d4e5ad7ad71c	5035	#define PWR_CR2_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
EricLew	0:d4e5ad7ad71c	5036	#define PWR_CR2_PLS_LEV1 ((uint32_t)0x00000002) /!< PVD level 1 /
EricLew	0:d4e5ad7ad71c	5037	#define PWR_CR2_PLS_LEV2 ((uint32_t)0x00000004) /!< PVD level 2 /
EricLew	0:d4e5ad7ad71c	5038	#define PWR_CR2_PLS_LEV3 ((uint32_t)0x00000006) /!< PVD level 3 /
EricLew	0:d4e5ad7ad71c	5039	#define PWR_CR2_PLS_LEV4 ((uint32_t)0x00000008) /!< PVD level 4 /
EricLew	0:d4e5ad7ad71c	5040	#define PWR_CR2_PLS_LEV5 ((uint32_t)0x0000000A) /!< PVD level 5 /
EricLew	0:d4e5ad7ad71c	5041	#define PWR_CR2_PLS_LEV6 ((uint32_t)0x0000000C) /!< PVD level 6 /
EricLew	0:d4e5ad7ad71c	5042	#define PWR_CR2_PLS_LEV7 ((uint32_t)0x0000000E) /!< PVD level 7 /
EricLew	0:d4e5ad7ad71c	5043	#define PWR_CR2_PVDE ((uint32_t)0x00000001) /!< Power Voltage Detector Enable /
EricLew	0:d4e5ad7ad71c	5044
EricLew	0:d4e5ad7ad71c	5045	/****************** Bit definition for PWR_CR3 register ******************/
EricLew	0:d4e5ad7ad71c	5046	#define PWR_CR3_EIWF ((uint32_t)0x00008000) /!< Enable Internal Wake-up line /
EricLew	0:d4e5ad7ad71c	5047	#define PWR_CR3_APC ((uint32_t)0x00000400) /!< Apply pull-up and pull-down configuration /
EricLew	0:d4e5ad7ad71c	5048	#define PWR_CR3_RRS ((uint32_t)0x00000100) /!< SRAM2 Retention in Stand-by mode /
EricLew	0:d4e5ad7ad71c	5049	#define PWR_CR3_EWUP5 ((uint32_t)0x00000010) /!< Enable Wake-Up Pin 5 /
EricLew	0:d4e5ad7ad71c	5050	#define PWR_CR3_EWUP4 ((uint32_t)0x00000008) /!< Enable Wake-Up Pin 4 /
EricLew	0:d4e5ad7ad71c	5051	#define PWR_CR3_EWUP3 ((uint32_t)0x00000004) /!< Enable Wake-Up Pin 3 /
EricLew	0:d4e5ad7ad71c	5052	#define PWR_CR3_EWUP2 ((uint32_t)0x00000002) /!< Enable Wake-Up Pin 2 /
EricLew	0:d4e5ad7ad71c	5053	#define PWR_CR3_EWUP1 ((uint32_t)0x00000001) /!< Enable Wake-Up Pin 1 /
EricLew	0:d4e5ad7ad71c	5054	#define PWR_CR3_EWUP ((uint32_t)0x0000001F) /!< Enable Wake-Up Pins /
EricLew	0:d4e5ad7ad71c	5055
EricLew	0:d4e5ad7ad71c	5056	/****************** Bit definition for PWR_CR4 register ******************/
EricLew	0:d4e5ad7ad71c	5057	#define PWR_CR4_VBRS ((uint32_t)0x00000200) /!< VBAT Battery charging Resistor Selection /
EricLew	0:d4e5ad7ad71c	5058	#define PWR_CR4_VBE ((uint32_t)0x00000100) /!< VBAT Battery charging Enable /
EricLew	0:d4e5ad7ad71c	5059	#define PWR_CR4_WP5 ((uint32_t)0x00000010) /!< Wake-Up Pin 5 polarity /
EricLew	0:d4e5ad7ad71c	5060	#define PWR_CR4_WP4 ((uint32_t)0x00000008) /!< Wake-Up Pin 4 polarity /
EricLew	0:d4e5ad7ad71c	5061	#define PWR_CR4_WP3 ((uint32_t)0x00000004) /!< Wake-Up Pin 3 polarity /
EricLew	0:d4e5ad7ad71c	5062	#define PWR_CR4_WP2 ((uint32_t)0x00000002) /!< Wake-Up Pin 2 polarity /
EricLew	0:d4e5ad7ad71c	5063	#define PWR_CR4_WP1 ((uint32_t)0x00000001) /!< Wake-Up Pin 1 polarity /
EricLew	0:d4e5ad7ad71c	5064
EricLew	0:d4e5ad7ad71c	5065	/****************** Bit definition for PWR_SR1 register ******************/
EricLew	0:d4e5ad7ad71c	5066	#define PWR_SR1_WUFI ((uint32_t)0x00008000) /!< Wake-Up Flag Internal /
EricLew	0:d4e5ad7ad71c	5067	#define PWR_SR1_SBF ((uint32_t)0x00000100) /!< Stand-By Flag /
EricLew	0:d4e5ad7ad71c	5068	#define PWR_SR1_WUF ((uint32_t)0x0000001F) /!< Wake-up Flags /
EricLew	0:d4e5ad7ad71c	5069	#define PWR_SR1_WUF5 ((uint32_t)0x00000010) /!< Wake-up Flag 5 /
EricLew	0:d4e5ad7ad71c	5070	#define PWR_SR1_WUF4 ((uint32_t)0x00000008) /!< Wake-up Flag 4 /
EricLew	0:d4e5ad7ad71c	5071	#define PWR_SR1_WUF3 ((uint32_t)0x00000004) /!< Wake-up Flag 3 /
EricLew	0:d4e5ad7ad71c	5072	#define PWR_SR1_WUF2 ((uint32_t)0x00000002) /!< Wake-up Flag 2 /
EricLew	0:d4e5ad7ad71c	5073	#define PWR_SR1_WUF1 ((uint32_t)0x00000001) /!< Wake-up Flag 1 /
EricLew	0:d4e5ad7ad71c	5074
EricLew	0:d4e5ad7ad71c	5075	/****************** Bit definition for PWR_SR2 register ******************/
EricLew	0:d4e5ad7ad71c	5076	#define PWR_SR2_PVMO4 ((uint32_t)0x00008000) /!< Peripheral Voltage Monitoring Output 4 /
EricLew	0:d4e5ad7ad71c	5077	#define PWR_SR2_PVMO3 ((uint32_t)0x00004000) /!< Peripheral Voltage Monitoring Output 3 /
EricLew	0:d4e5ad7ad71c	5078	#define PWR_SR2_PVMO2 ((uint32_t)0x00002000) /!< Peripheral Voltage Monitoring Output 2 /
EricLew	0:d4e5ad7ad71c	5079	#define PWR_SR2_PVMO1 ((uint32_t)0x00001000) /!< Peripheral Voltage Monitoring Output 1 /
EricLew	0:d4e5ad7ad71c	5080	#define PWR_SR2_PVDO ((uint32_t)0x00000800) /!< Power Voltage Detector Output /
EricLew	0:d4e5ad7ad71c	5081	#define PWR_SR2_VOSF ((uint32_t)0x00000400) /!< Voltage Scaling Flag /
EricLew	0:d4e5ad7ad71c	5082	#define PWR_SR2_REGLPF ((uint32_t)0x00000200) /!< Low-power Regulator Flag /
EricLew	0:d4e5ad7ad71c	5083	#define PWR_SR2_REGLPS ((uint32_t)0x00000100) /!< Low-power Regulator Started /
EricLew	0:d4e5ad7ad71c	5084
EricLew	0:d4e5ad7ad71c	5085	/****************** Bit definition for PWR_SCR register ******************/
EricLew	0:d4e5ad7ad71c	5086	#define PWR_SCR_CSBF ((uint32_t)0x00000100) /!< Clear Stand-By Flag /
EricLew	0:d4e5ad7ad71c	5087	#define PWR_SCR_CWUF ((uint32_t)0x0000001F) /!< Clear Wake-up Flags /
EricLew	0:d4e5ad7ad71c	5088	#define PWR_SCR_CWUF5 ((uint32_t)0x00000010) /!< Clear Wake-up Flag 5 /
EricLew	0:d4e5ad7ad71c	5089	#define PWR_SCR_CWUF4 ((uint32_t)0x00000008) /!< Clear Wake-up Flag 4 /
EricLew	0:d4e5ad7ad71c	5090	#define PWR_SCR_CWUF3 ((uint32_t)0x00000004) /!< Clear Wake-up Flag 3 /
EricLew	0:d4e5ad7ad71c	5091	#define PWR_SCR_CWUF2 ((uint32_t)0x00000002) /!< Clear Wake-up Flag 2 /
EricLew	0:d4e5ad7ad71c	5092	#define PWR_SCR_CWUF1 ((uint32_t)0x00000001) /!< Clear Wake-up Flag 1 /
EricLew	0:d4e5ad7ad71c	5093
EricLew	0:d4e5ad7ad71c	5094	/****************** Bit definition for PWR_PUCRA register ******************/
EricLew	0:d4e5ad7ad71c	5095	#define PWR_PUCRA_PA15 ((uint32_t)0x00008000) /!< Port PA15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5096	#define PWR_PUCRA_PA13 ((uint32_t)0x00002000) /!< Port PA13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5097	#define PWR_PUCRA_PA12 ((uint32_t)0x00001000) /!< Port PA12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5098	#define PWR_PUCRA_PA11 ((uint32_t)0x00000800) /!< Port PA11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5099	#define PWR_PUCRA_PA10 ((uint32_t)0x00000400) /!< Port PA10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5100	#define PWR_PUCRA_PA9 ((uint32_t)0x00000200) /!< Port PA9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5101	#define PWR_PUCRA_PA8 ((uint32_t)0x00000100) /!< Port PA8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5102	#define PWR_PUCRA_PA7 ((uint32_t)0x00000080) /!< Port PA7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5103	#define PWR_PUCRA_PA6 ((uint32_t)0x00000040) /!< Port PA6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5104	#define PWR_PUCRA_PA5 ((uint32_t)0x00000020) /!< Port PA5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5105	#define PWR_PUCRA_PA4 ((uint32_t)0x00000010) /!< Port PA4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5106	#define PWR_PUCRA_PA3 ((uint32_t)0x00000008) /!< Port PA3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5107	#define PWR_PUCRA_PA2 ((uint32_t)0x00000004) /!< Port PA2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5108	#define PWR_PUCRA_PA1 ((uint32_t)0x00000002) /!< Port PA1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5109	#define PWR_PUCRA_PA0 ((uint32_t)0x00000001) /!< Port PA0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5110
EricLew	0:d4e5ad7ad71c	5111	/****************** Bit definition for PWR_PDCRA register ******************/
EricLew	0:d4e5ad7ad71c	5112	#define PWR_PDCRA_PA14 ((uint32_t)0x00004000) /!< Port PA14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5113	#define PWR_PDCRA_PA12 ((uint32_t)0x00001000) /!< Port PA12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5114	#define PWR_PDCRA_PA11 ((uint32_t)0x00000800) /!< Port PA11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5115	#define PWR_PDCRA_PA10 ((uint32_t)0x00000400) /!< Port PA10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5116	#define PWR_PDCRA_PA9 ((uint32_t)0x00000200) /!< Port PA9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5117	#define PWR_PDCRA_PA8 ((uint32_t)0x00000100) /!< Port PA8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5118	#define PWR_PDCRA_PA7 ((uint32_t)0x00000080) /!< Port PA7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5119	#define PWR_PDCRA_PA6 ((uint32_t)0x00000040) /!< Port PA6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5120	#define PWR_PDCRA_PA5 ((uint32_t)0x00000020) /!< Port PA5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5121	#define PWR_PDCRA_PA4 ((uint32_t)0x00000010) /!< Port PA4 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5122	#define PWR_PDCRA_PA3 ((uint32_t)0x00000008) /!< Port PA3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5123	#define PWR_PDCRA_PA2 ((uint32_t)0x00000004) /!< Port PA2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5124	#define PWR_PDCRA_PA1 ((uint32_t)0x00000002) /!< Port PA1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5125	#define PWR_PDCRA_PA0 ((uint32_t)0x00000001) /!< Port PA0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5126
EricLew	0:d4e5ad7ad71c	5127	/****************** Bit definition for PWR_PUCRB register ******************/
EricLew	0:d4e5ad7ad71c	5128	#define PWR_PUCRB_PB15 ((uint32_t)0x00008000) /!< Port PB15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5129	#define PWR_PUCRB_PB14 ((uint32_t)0x00004000) /!< Port PB14 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5130	#define PWR_PUCRB_PB13 ((uint32_t)0x00002000) /!< Port PB13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5131	#define PWR_PUCRB_PB12 ((uint32_t)0x00001000) /!< Port PB12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5132	#define PWR_PUCRB_PB11 ((uint32_t)0x00000800) /!< Port PB11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5133	#define PWR_PUCRB_PB10 ((uint32_t)0x00000400) /!< Port PB10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5134	#define PWR_PUCRB_PB9 ((uint32_t)0x00000200) /!< Port PB9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5135	#define PWR_PUCRB_PB8 ((uint32_t)0x00000100) /!< Port PB8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5136	#define PWR_PUCRB_PB7 ((uint32_t)0x00000080) /!< Port PB7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5137	#define PWR_PUCRB_PB6 ((uint32_t)0x00000040) /!< Port PB6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5138	#define PWR_PUCRB_PB5 ((uint32_t)0x00000020) /!< Port PB5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5139	#define PWR_PUCRB_PB4 ((uint32_t)0x00000010) /!< Port PB4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5140	#define PWR_PUCRB_PB3 ((uint32_t)0x00000008) /!< Port PB3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5141	#define PWR_PUCRB_PB2 ((uint32_t)0x00000004) /!< Port PB2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5142	#define PWR_PUCRB_PB1 ((uint32_t)0x00000002) /!< Port PB1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5143	#define PWR_PUCRB_PB0 ((uint32_t)0x00000001) /!< Port PB0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5144
EricLew	0:d4e5ad7ad71c	5145	/****************** Bit definition for PWR_PDCRB register ******************/
EricLew	0:d4e5ad7ad71c	5146	#define PWR_PDCRB_PB15 ((uint32_t)0x00008000) /!< Port PB15 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5147	#define PWR_PDCRB_PB14 ((uint32_t)0x00004000) /!< Port PB14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5148	#define PWR_PDCRB_PB13 ((uint32_t)0x00002000) /!< Port PB13 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5149	#define PWR_PDCRB_PB12 ((uint32_t)0x00001000) /!< Port PB12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5150	#define PWR_PDCRB_PB11 ((uint32_t)0x00000800) /!< Port PB11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5151	#define PWR_PDCRB_PB10 ((uint32_t)0x00000400) /!< Port PB10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5152	#define PWR_PDCRB_PB9 ((uint32_t)0x00000200) /!< Port PB9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5153	#define PWR_PDCRB_PB8 ((uint32_t)0x00000100) /!< Port PB8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5154	#define PWR_PDCRB_PB7 ((uint32_t)0x00000080) /!< Port PB7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5155	#define PWR_PDCRB_PB6 ((uint32_t)0x00000040) /!< Port PB6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5156	#define PWR_PDCRB_PB5 ((uint32_t)0x00000020) /!< Port PB5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5157	#define PWR_PDCRB_PB3 ((uint32_t)0x00000008) /!< Port PB3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5158	#define PWR_PDCRB_PB2 ((uint32_t)0x00000004) /!< Port PB2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5159	#define PWR_PDCRB_PB1 ((uint32_t)0x00000002) /!< Port PB1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5160	#define PWR_PDCRB_PB0 ((uint32_t)0x00000001) /!< Port PB0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5161
EricLew	0:d4e5ad7ad71c	5162	/****************** Bit definition for PWR_PUCRC register ******************/
EricLew	0:d4e5ad7ad71c	5163	#define PWR_PUCRC_PC15 ((uint32_t)0x00008000) /!< Port PC15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5164	#define PWR_PUCRC_PC14 ((uint32_t)0x00004000) /!< Port PC14 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5165	#define PWR_PUCRC_PC13 ((uint32_t)0x00002000) /!< Port PC13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5166	#define PWR_PUCRC_PC12 ((uint32_t)0x00001000) /!< Port PC12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5167	#define PWR_PUCRC_PC11 ((uint32_t)0x00000800) /!< Port PC11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5168	#define PWR_PUCRC_PC10 ((uint32_t)0x00000400) /!< Port PC10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5169	#define PWR_PUCRC_PC9 ((uint32_t)0x00000200) /!< Port PC9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5170	#define PWR_PUCRC_PC8 ((uint32_t)0x00000100) /!< Port PC8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5171	#define PWR_PUCRC_PC7 ((uint32_t)0x00000080) /!< Port PC7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5172	#define PWR_PUCRC_PC6 ((uint32_t)0x00000040) /!< Port PC6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5173	#define PWR_PUCRC_PC5 ((uint32_t)0x00000020) /!< Port PC5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5174	#define PWR_PUCRC_PC4 ((uint32_t)0x00000010) /!< Port PC4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5175	#define PWR_PUCRC_PC3 ((uint32_t)0x00000008) /!< Port PC3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5176	#define PWR_PUCRC_PC2 ((uint32_t)0x00000004) /!< Port PC2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5177	#define PWR_PUCRC_PC1 ((uint32_t)0x00000002) /!< Port PC1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5178	#define PWR_PUCRC_PC0 ((uint32_t)0x00000001) /!< Port PC0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5179
EricLew	0:d4e5ad7ad71c	5180	/****************** Bit definition for PWR_PDCRC register ******************/
EricLew	0:d4e5ad7ad71c	5181	#define PWR_PDCRC_PC15 ((uint32_t)0x00008000) /!< Port PC15 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5182	#define PWR_PDCRC_PC14 ((uint32_t)0x00004000) /!< Port PC14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5183	#define PWR_PDCRC_PC13 ((uint32_t)0x00002000) /!< Port PC13 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5184	#define PWR_PDCRC_PC12 ((uint32_t)0x00001000) /!< Port PC12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5185	#define PWR_PDCRC_PC11 ((uint32_t)0x00000800) /!< Port PC11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5186	#define PWR_PDCRC_PC10 ((uint32_t)0x00000400) /!< Port PC10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5187	#define PWR_PDCRC_PC9 ((uint32_t)0x00000200) /!< Port PC9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5188	#define PWR_PDCRC_PC8 ((uint32_t)0x00000100) /!< Port PC8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5189	#define PWR_PDCRC_PC7 ((uint32_t)0x00000080) /!< Port PC7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5190	#define PWR_PDCRC_PC6 ((uint32_t)0x00000040) /!< Port PC6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5191	#define PWR_PDCRC_PC5 ((uint32_t)0x00000020) /!< Port PC5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5192	#define PWR_PDCRC_PC4 ((uint32_t)0x00000010) /!< Port PC4 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5193	#define PWR_PDCRC_PC3 ((uint32_t)0x00000008) /!< Port PC3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5194	#define PWR_PDCRC_PC2 ((uint32_t)0x00000004) /!< Port PC2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5195	#define PWR_PDCRC_PC1 ((uint32_t)0x00000002) /!< Port PC1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5196	#define PWR_PDCRC_PC0 ((uint32_t)0x00000001) /!< Port PC0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5197
EricLew	0:d4e5ad7ad71c	5198	/****************** Bit definition for PWR_PUCRD register ******************/
EricLew	0:d4e5ad7ad71c	5199	#define PWR_PUCRD_PD15 ((uint32_t)0x00008000) /!< Port PD15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5200	#define PWR_PUCRD_PD14 ((uint32_t)0x00004000) /!< Port PD14 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5201	#define PWR_PUCRD_PD13 ((uint32_t)0x00002000) /!< Port PD13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5202	#define PWR_PUCRD_PD12 ((uint32_t)0x00001000) /!< Port PD12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5203	#define PWR_PUCRD_PD11 ((uint32_t)0x00000800) /!< Port PD11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5204	#define PWR_PUCRD_PD10 ((uint32_t)0x00000400) /!< Port PD10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5205	#define PWR_PUCRD_PD9 ((uint32_t)0x00000200) /!< Port PD9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5206	#define PWR_PUCRD_PD8 ((uint32_t)0x00000100) /!< Port PD8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5207	#define PWR_PUCRD_PD7 ((uint32_t)0x00000080) /!< Port PD7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5208	#define PWR_PUCRD_PD6 ((uint32_t)0x00000040) /!< Port PD6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5209	#define PWR_PUCRD_PD5 ((uint32_t)0x00000020) /!< Port PD5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5210	#define PWR_PUCRD_PD4 ((uint32_t)0x00000010) /!< Port PD4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5211	#define PWR_PUCRD_PD3 ((uint32_t)0x00000008) /!< Port PD3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5212	#define PWR_PUCRD_PD2 ((uint32_t)0x00000004) /!< Port PD2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5213	#define PWR_PUCRD_PD1 ((uint32_t)0x00000002) /!< Port PD1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5214	#define PWR_PUCRD_PD0 ((uint32_t)0x00000001) /!< Port PD0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5215
EricLew	0:d4e5ad7ad71c	5216	/****************** Bit definition for PWR_PDCRD register ******************/
EricLew	0:d4e5ad7ad71c	5217	#define PWR_PDCRD_PD15 ((uint32_t)0x00008000) /!< Port PD15 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5218	#define PWR_PDCRD_PD14 ((uint32_t)0x00004000) /!< Port PD14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5219	#define PWR_PDCRD_PD13 ((uint32_t)0x00002000) /!< Port PD13 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5220	#define PWR_PDCRD_PD12 ((uint32_t)0x00001000) /!< Port PD12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5221	#define PWR_PDCRD_PD11 ((uint32_t)0x00000800) /!< Port PD11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5222	#define PWR_PDCRD_PD10 ((uint32_t)0x00000400) /!< Port PD10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5223	#define PWR_PDCRD_PD9 ((uint32_t)0x00000200) /!< Port PD9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5224	#define PWR_PDCRD_PD8 ((uint32_t)0x00000100) /!< Port PD8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5225	#define PWR_PDCRD_PD7 ((uint32_t)0x00000080) /!< Port PD7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5226	#define PWR_PDCRD_PD6 ((uint32_t)0x00000040) /!< Port PD6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5227	#define PWR_PDCRD_PD5 ((uint32_t)0x00000020) /!< Port PD5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5228	#define PWR_PDCRD_PD4 ((uint32_t)0x00000010) /!< Port PD4 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5229	#define PWR_PDCRD_PD3 ((uint32_t)0x00000008) /!< Port PD3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5230	#define PWR_PDCRD_PD2 ((uint32_t)0x00000004) /!< Port PD2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5231	#define PWR_PDCRD_PD1 ((uint32_t)0x00000002) /!< Port PD1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5232	#define PWR_PDCRD_PD0 ((uint32_t)0x00000001) /!< Port PD0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5233
EricLew	0:d4e5ad7ad71c	5234	/****************** Bit definition for PWR_PUCRE register ******************/
EricLew	0:d4e5ad7ad71c	5235	#define PWR_PUCRE_PE15 ((uint32_t)0x00008000) /!< Port PE15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5236	#define PWR_PUCRE_PE14 ((uint32_t)0x00004000) /!< Port PE14 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5237	#define PWR_PUCRE_PE13 ((uint32_t)0x00002000) /!< Port PE13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5238	#define PWR_PUCRE_PE12 ((uint32_t)0x00001000) /!< Port PE12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5239	#define PWR_PUCRE_PE11 ((uint32_t)0x00000800) /!< Port PE11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5240	#define PWR_PUCRE_PE10 ((uint32_t)0x00000400) /!< Port PE10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5241	#define PWR_PUCRE_PE9 ((uint32_t)0x00000200) /!< Port PE9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5242	#define PWR_PUCRE_PE8 ((uint32_t)0x00000100) /!< Port PE8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5243	#define PWR_PUCRE_PE7 ((uint32_t)0x00000080) /!< Port PE7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5244	#define PWR_PUCRE_PE6 ((uint32_t)0x00000040) /!< Port PE6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5245	#define PWR_PUCRE_PE5 ((uint32_t)0x00000020) /!< Port PE5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5246	#define PWR_PUCRE_PE4 ((uint32_t)0x00000010) /!< Port PE4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5247	#define PWR_PUCRE_PE3 ((uint32_t)0x00000008) /!< Port PE3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5248	#define PWR_PUCRE_PE2 ((uint32_t)0x00000004) /!< Port PE2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5249	#define PWR_PUCRE_PE1 ((uint32_t)0x00000002) /!< Port PE1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5250	#define PWR_PUCRE_PE0 ((uint32_t)0x00000001) /!< Port PE0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5251
EricLew	0:d4e5ad7ad71c	5252	/****************** Bit definition for PWR_PDCRE register ******************/
EricLew	0:d4e5ad7ad71c	5253	#define PWR_PDCRE_PE15 ((uint32_t)0x00008000) /!< Port PE15 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5254	#define PWR_PDCRE_PE14 ((uint32_t)0x00004000) /!< Port PE14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5255	#define PWR_PDCRE_PE13 ((uint32_t)0x00002000) /!< Port PE13 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5256	#define PWR_PDCRE_PE12 ((uint32_t)0x00001000) /!< Port PE12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5257	#define PWR_PDCRE_PE11 ((uint32_t)0x00000800) /!< Port PE11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5258	#define PWR_PDCRE_PE10 ((uint32_t)0x00000400) /!< Port PE10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5259	#define PWR_PDCRE_PE9 ((uint32_t)0x00000200) /!< Port PE9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5260	#define PWR_PDCRE_PE8 ((uint32_t)0x00000100) /!< Port PE8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5261	#define PWR_PDCRE_PE7 ((uint32_t)0x00000080) /!< Port PE7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5262	#define PWR_PDCRE_PE6 ((uint32_t)0x00000040) /!< Port PE6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5263	#define PWR_PDCRE_PE5 ((uint32_t)0x00000020) /!< Port PE5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5264	#define PWR_PDCRE_PE4 ((uint32_t)0x00000010) /!< Port PE4 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5265	#define PWR_PDCRE_PE3 ((uint32_t)0x00000008) /!< Port PE3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5266	#define PWR_PDCRE_PE2 ((uint32_t)0x00000004) /!< Port PE2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5267	#define PWR_PDCRE_PE1 ((uint32_t)0x00000002) /!< Port PE1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5268	#define PWR_PDCRE_PE0 ((uint32_t)0x00000001) /!< Port PE0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5269
EricLew	0:d4e5ad7ad71c	5270	/****************** Bit definition for PWR_PUCRF register ******************/
EricLew	0:d4e5ad7ad71c	5271	#define PWR_PUCRF_PF15 ((uint32_t)0x00008000) /!< Port PF15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5272	#define PWR_PUCRF_PF14 ((uint32_t)0x00004000) /!< Port PF14 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5273	#define PWR_PUCRF_PF13 ((uint32_t)0x00002000) /!< Port PF13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5274	#define PWR_PUCRF_PF12 ((uint32_t)0x00001000) /!< Port PF12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5275	#define PWR_PUCRF_PF11 ((uint32_t)0x00000800) /!< Port PF11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5276	#define PWR_PUCRF_PF10 ((uint32_t)0x00000400) /!< Port PF10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5277	#define PWR_PUCRF_PF9 ((uint32_t)0x00000200) /!< Port PF9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5278	#define PWR_PUCRF_PF8 ((uint32_t)0x00000100) /!< Port PF8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5279	#define PWR_PUCRF_PF7 ((uint32_t)0x00000080) /!< Port PF7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5280	#define PWR_PUCRF_PF6 ((uint32_t)0x00000040) /!< Port PF6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5281	#define PWR_PUCRF_PF5 ((uint32_t)0x00000020) /!< Port PF5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5282	#define PWR_PUCRF_PF4 ((uint32_t)0x00000010) /!< Port PF4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5283	#define PWR_PUCRF_PF3 ((uint32_t)0x00000008) /!< Port PF3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5284	#define PWR_PUCRF_PF2 ((uint32_t)0x00000004) /!< Port PF2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5285	#define PWR_PUCRF_PF1 ((uint32_t)0x00000002) /!< Port PF1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5286	#define PWR_PUCRF_PF0 ((uint32_t)0x00000001) /!< Port PF0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5287
EricLew	0:d4e5ad7ad71c	5288	/****************** Bit definition for PWR_PDCRF register ******************/
EricLew	0:d4e5ad7ad71c	5289	#define PWR_PDCRF_PF15 ((uint32_t)0x00008000) /!< Port PF15 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5290	#define PWR_PDCRF_PF14 ((uint32_t)0x00004000) /!< Port PF14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5291	#define PWR_PDCRF_PF13 ((uint32_t)0x00002000) /!< Port PF13 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5292	#define PWR_PDCRF_PF12 ((uint32_t)0x00001000) /!< Port PF12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5293	#define PWR_PDCRF_PF11 ((uint32_t)0x00000800) /!< Port PF11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5294	#define PWR_PDCRF_PF10 ((uint32_t)0x00000400) /!< Port PF10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5295	#define PWR_PDCRF_PF9 ((uint32_t)0x00000200) /!< Port PF9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5296	#define PWR_PDCRF_PF8 ((uint32_t)0x00000100) /!< Port PF8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5297	#define PWR_PDCRF_PF7 ((uint32_t)0x00000080) /!< Port PF7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5298	#define PWR_PDCRF_PF6 ((uint32_t)0x00000040) /!< Port PF6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5299	#define PWR_PDCRF_PF5 ((uint32_t)0x00000020) /!< Port PF5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5300	#define PWR_PDCRF_PF4 ((uint32_t)0x00000010) /!< Port PF4 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5301	#define PWR_PDCRF_PF3 ((uint32_t)0x00000008) /!< Port PF3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5302	#define PWR_PDCRF_PF2 ((uint32_t)0x00000004) /!< Port PF2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5303	#define PWR_PDCRF_PF1 ((uint32_t)0x00000002) /!< Port PF1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5304	#define PWR_PDCRF_PF0 ((uint32_t)0x00000001) /!< Port PF0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5305
EricLew	0:d4e5ad7ad71c	5306	/****************** Bit definition for PWR_PUCRG register ******************/
EricLew	0:d4e5ad7ad71c	5307	#define PWR_PUCRG_PG15 ((uint32_t)0x00008000) /!< Port PG15 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5308	#define PWR_PUCRG_PG14 ((uint32_t)0x00004000) /!< Port PG14 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5309	#define PWR_PUCRG_PG13 ((uint32_t)0x00002000) /!< Port PG13 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5310	#define PWR_PUCRG_PG12 ((uint32_t)0x00001000) /!< Port PG12 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5311	#define PWR_PUCRG_PG11 ((uint32_t)0x00000800) /!< Port PG11 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5312	#define PWR_PUCRG_PG10 ((uint32_t)0x00000400) /!< Port PG10 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5313	#define PWR_PUCRG_PG9 ((uint32_t)0x00000200) /!< Port PG9 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5314	#define PWR_PUCRG_PG8 ((uint32_t)0x00000100) /!< Port PG8 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5315	#define PWR_PUCRG_PG7 ((uint32_t)0x00000080) /!< Port PG7 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5316	#define PWR_PUCRG_PG6 ((uint32_t)0x00000040) /!< Port PG6 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5317	#define PWR_PUCRG_PG5 ((uint32_t)0x00000020) /!< Port PG5 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5318	#define PWR_PUCRG_PG4 ((uint32_t)0x00000010) /!< Port PG4 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5319	#define PWR_PUCRG_PG3 ((uint32_t)0x00000008) /!< Port PG3 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5320	#define PWR_PUCRG_PG2 ((uint32_t)0x00000004) /!< Port PG2 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5321	#define PWR_PUCRG_PG1 ((uint32_t)0x00000002) /!< Port PG1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5322	#define PWR_PUCRG_PG0 ((uint32_t)0x00000001) /!< Port PG0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5323
EricLew	0:d4e5ad7ad71c	5324	/****************** Bit definition for PWR_PDCRG register ******************/
EricLew	0:d4e5ad7ad71c	5325	#define PWR_PDCRG_PG15 ((uint32_t)0x00008000) /!< Port PG15 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5326	#define PWR_PDCRG_PG14 ((uint32_t)0x00004000) /!< Port PG14 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5327	#define PWR_PDCRG_PG13 ((uint32_t)0x00002000) /!< Port PG13 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5328	#define PWR_PDCRG_PG12 ((uint32_t)0x00001000) /!< Port PG12 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5329	#define PWR_PDCRG_PG11 ((uint32_t)0x00000800) /!< Port PG11 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5330	#define PWR_PDCRG_PG10 ((uint32_t)0x00000400) /!< Port PG10 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5331	#define PWR_PDCRG_PG9 ((uint32_t)0x00000200) /!< Port PG9 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5332	#define PWR_PDCRG_PG8 ((uint32_t)0x00000100) /!< Port PG8 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5333	#define PWR_PDCRG_PG7 ((uint32_t)0x00000080) /!< Port PG7 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5334	#define PWR_PDCRG_PG6 ((uint32_t)0x00000040) /!< Port PG6 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5335	#define PWR_PDCRG_PG5 ((uint32_t)0x00000020) /!< Port PG5 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5336	#define PWR_PDCRG_PG4 ((uint32_t)0x00000010) /!< Port PG4 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5337	#define PWR_PDCRG_PG3 ((uint32_t)0x00000008) /!< Port PG3 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5338	#define PWR_PDCRG_PG2 ((uint32_t)0x00000004) /!< Port PG2 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5339	#define PWR_PDCRG_PG1 ((uint32_t)0x00000002) /!< Port PG1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5340	#define PWR_PDCRG_PG0 ((uint32_t)0x00000001) /!< Port PG0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5341
EricLew	0:d4e5ad7ad71c	5342	/****************** Bit definition for PWR_PUCRH register ******************/
EricLew	0:d4e5ad7ad71c	5343	#define PWR_PUCRH_PH1 ((uint32_t)0x00000002) /!< Port PH1 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5344	#define PWR_PUCRH_PH0 ((uint32_t)0x00000001) /!< Port PH0 Pull-Up set /
EricLew	0:d4e5ad7ad71c	5345
EricLew	0:d4e5ad7ad71c	5346	/****************** Bit definition for PWR_PDCRH register ******************/
EricLew	0:d4e5ad7ad71c	5347	#define PWR_PDCRH_PH1 ((uint32_t)0x00000002) /!< Port PH1 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5348	#define PWR_PDCRH_PH0 ((uint32_t)0x00000001) /!< Port PH0 Pull-Down set /
EricLew	0:d4e5ad7ad71c	5349
EricLew	0:d4e5ad7ad71c	5350
EricLew	0:d4e5ad7ad71c	5351	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5352	/* */
EricLew	0:d4e5ad7ad71c	5353	/* Reset and Clock Control */
EricLew	0:d4e5ad7ad71c	5354	/* */
EricLew	0:d4e5ad7ad71c	5355	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5356	/****************** Bit definition for RCC_CR register ******************/
EricLew	0:d4e5ad7ad71c	5357	#define RCC_CR_MSION ((uint32_t)0x00000001) /!< Internal Multi Speed oscillator (MSI) clock enable /
EricLew	0:d4e5ad7ad71c	5358	#define RCC_CR_MSIRDY ((uint32_t)0x00000002) /!< Internal Multi Speed oscillator (MSI) clock ready flag /
EricLew	0:d4e5ad7ad71c	5359	#define RCC_CR_MSIPLLEN ((uint32_t)0x00000004) /!< Internal Multi Speed oscillator (MSI) PLL enable /
EricLew	0:d4e5ad7ad71c	5360	#define RCC_CR_MSIRGSEL ((uint32_t)0x00000008) /!< Internal Multi Speed oscillator (MSI) range selection /
EricLew	0:d4e5ad7ad71c	5361
EricLew	0:d4e5ad7ad71c	5362	/!< MSIRANGE configuration : 12 frequency ranges available /
EricLew	0:d4e5ad7ad71c	5363	#define RCC_CR_MSIRANGE ((uint32_t)0x000000F0) /!< Internal Multi Speed oscillator (MSI) clock Range /
EricLew	0:d4e5ad7ad71c	5364	#define RCC_CR_MSIRANGE_0 ((uint32_t)0x00000000) /!< Internal Multi Speed oscillator (MSI) clock Range 100 KHz /
EricLew	0:d4e5ad7ad71c	5365	#define RCC_CR_MSIRANGE_1 ((uint32_t)0x00000010) /!< Internal Multi Speed oscillator (MSI) clock Range 200 KHz /
EricLew	0:d4e5ad7ad71c	5366	#define RCC_CR_MSIRANGE_2 ((uint32_t)0x00000020) /!< Internal Multi Speed oscillator (MSI) clock Range 400 KHz /
EricLew	0:d4e5ad7ad71c	5367	#define RCC_CR_MSIRANGE_3 ((uint32_t)0x00000030) /!< Internal Multi Speed oscillator (MSI) clock Range 800 KHz /
EricLew	0:d4e5ad7ad71c	5368	#define RCC_CR_MSIRANGE_4 ((uint32_t)0x00000040) /!< Internal Multi Speed oscillator (MSI) clock Range 1 MHz /
EricLew	0:d4e5ad7ad71c	5369	#define RCC_CR_MSIRANGE_5 ((uint32_t)0x00000050) /!< Internal Multi Speed oscillator (MSI) clock Range 2 MHz /
EricLew	0:d4e5ad7ad71c	5370	#define RCC_CR_MSIRANGE_6 ((uint32_t)0x00000060) /!< Internal Multi Speed oscillator (MSI) clock Range 4 MHz /
EricLew	0:d4e5ad7ad71c	5371	#define RCC_CR_MSIRANGE_7 ((uint32_t)0x00000070) /!< Internal Multi Speed oscillator (MSI) clock Range 8 KHz /
EricLew	0:d4e5ad7ad71c	5372	#define RCC_CR_MSIRANGE_8 ((uint32_t)0x00000080) /!< Internal Multi Speed oscillator (MSI) clock Range 16 MHz /
EricLew	0:d4e5ad7ad71c	5373	#define RCC_CR_MSIRANGE_9 ((uint32_t)0x00000090) /!< Internal Multi Speed oscillator (MSI) clock Range 24 MHz /
EricLew	0:d4e5ad7ad71c	5374	#define RCC_CR_MSIRANGE_10 ((uint32_t)0x000000A0) /!< Internal Multi Speed oscillator (MSI) clock Range 32 MHz /
EricLew	0:d4e5ad7ad71c	5375	#define RCC_CR_MSIRANGE_11 ((uint32_t)0x000000B0) /!< Internal Multi Speed oscillator (MSI) clock Range 48 MHz /
EricLew	0:d4e5ad7ad71c	5376
EricLew	0:d4e5ad7ad71c	5377	#define RCC_CR_HSION ((uint32_t)0x00000100) /!< Internal High Speed oscillator (HSI16) clock enable /
EricLew	0:d4e5ad7ad71c	5378	#define RCC_CR_HSIKERON ((uint32_t)0x00000200) /!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel /
EricLew	0:d4e5ad7ad71c	5379	#define RCC_CR_HSIRDY ((uint32_t)0x00000400) /!< Internal High Speed oscillator (HSI16) clock ready flag /
EricLew	0:d4e5ad7ad71c	5380	#define RCC_CR_HSIASFS ((uint32_t)0x00000800) /!< HSI16 Automatic Start from Stop /
EricLew	0:d4e5ad7ad71c	5381
EricLew	0:d4e5ad7ad71c	5382	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed oscillator (HSE) clock enable /
EricLew	0:d4e5ad7ad71c	5383	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed oscillator (HSE) clock ready /
EricLew	0:d4e5ad7ad71c	5384	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed oscillator (HSE) clock bypass /
EricLew	0:d4e5ad7ad71c	5385	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< HSE Clock Security System enable /
EricLew	0:d4e5ad7ad71c	5386
EricLew	0:d4e5ad7ad71c	5387	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< System PLL clock enable /
EricLew	0:d4e5ad7ad71c	5388	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< System PLL clock ready /
EricLew	0:d4e5ad7ad71c	5389	#define RCC_CR_PLLSAI1ON ((uint32_t)0x04000000) /!< SAI1 PLL enable /
EricLew	0:d4e5ad7ad71c	5390	#define RCC_CR_PLLSAI1RDY ((uint32_t)0x08000000) /!< SAI1 PLL ready /
EricLew	0:d4e5ad7ad71c	5391	#define RCC_CR_PLLSAI2ON ((uint32_t)0x10000000) /!< SAI2 PLL enable /
EricLew	0:d4e5ad7ad71c	5392	#define RCC_CR_PLLSAI2RDY ((uint32_t)0x20000000) /!< SAI2 PLL ready /
EricLew	0:d4e5ad7ad71c	5393
EricLew	0:d4e5ad7ad71c	5394	/****************** Bit definition for RCC_ICSCR register *************/
EricLew	0:d4e5ad7ad71c	5395	/!< MSICAL configuration /
EricLew	0:d4e5ad7ad71c	5396	#define RCC_ICSCR_MSICAL ((uint32_t)0x000000FF) /!< MSICAL[7:0] bits /
EricLew	0:d4e5ad7ad71c	5397	#define RCC_ICSCR_MSICAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5398	#define RCC_ICSCR_MSICAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5399	#define RCC_ICSCR_MSICAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5400	#define RCC_ICSCR_MSICAL_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	5401	#define RCC_ICSCR_MSICAL_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	5402	#define RCC_ICSCR_MSICAL_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	5403	#define RCC_ICSCR_MSICAL_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	5404	#define RCC_ICSCR_MSICAL_7 ((uint32_t)0x00000080) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	5405
EricLew	0:d4e5ad7ad71c	5406	/!< MSITRIM configuration /
EricLew	0:d4e5ad7ad71c	5407	#define RCC_ICSCR_MSITRIM ((uint32_t)0x0000FF00) /!< MSITRIM[7:0] bits /
EricLew	0:d4e5ad7ad71c	5408	#define RCC_ICSCR_MSITRIM_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5409	#define RCC_ICSCR_MSITRIM_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5410	#define RCC_ICSCR_MSITRIM_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5411	#define RCC_ICSCR_MSITRIM_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	5412	#define RCC_ICSCR_MSITRIM_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	5413	#define RCC_ICSCR_MSITRIM_5 ((uint32_t)0x00002000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	5414	#define RCC_ICSCR_MSITRIM_6 ((uint32_t)0x00004000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	5415	#define RCC_ICSCR_MSITRIM_7 ((uint32_t)0x00008000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	5416
EricLew	0:d4e5ad7ad71c	5417	/!< HSICAL configuration /
EricLew	0:d4e5ad7ad71c	5418	#define RCC_ICSCR_HSICAL ((uint32_t)0x00FF0000) /!< HSICAL[7:0] bits /
EricLew	0:d4e5ad7ad71c	5419	#define RCC_ICSCR_HSICAL_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5420	#define RCC_ICSCR_HSICAL_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5421	#define RCC_ICSCR_HSICAL_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5422	#define RCC_ICSCR_HSICAL_3 ((uint32_t)0x00080000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	5423	#define RCC_ICSCR_HSICAL_4 ((uint32_t)0x00100000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	5424	#define RCC_ICSCR_HSICAL_5 ((uint32_t)0x00200000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	5425	#define RCC_ICSCR_HSICAL_6 ((uint32_t)0x00400000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	5426	#define RCC_ICSCR_HSICAL_7 ((uint32_t)0x00800000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	5427
EricLew	0:d4e5ad7ad71c	5428	/!< HSITRIM configuration /
EricLew	0:d4e5ad7ad71c	5429	#define RCC_ICSCR_HSITRIM ((uint32_t)0x1F000000) /!< HSITRIM[4:0] bits /
EricLew	0:d4e5ad7ad71c	5430	#define RCC_ICSCR_HSITRIM_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5431	#define RCC_ICSCR_HSITRIM_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5432	#define RCC_ICSCR_HSITRIM_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5433	#define RCC_ICSCR_HSITRIM_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	5434	#define RCC_ICSCR_HSITRIM_4 ((uint32_t)0x10000000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	5435
EricLew	0:d4e5ad7ad71c	5436	/****************** Bit definition for RCC_CFGR register ****************/
EricLew	0:d4e5ad7ad71c	5437	/!< SW configuration /
EricLew	0:d4e5ad7ad71c	5438	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
EricLew	0:d4e5ad7ad71c	5439	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5440	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5441
EricLew	0:d4e5ad7ad71c	5442	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /!< MSI oscillator selection as system clock /
EricLew	0:d4e5ad7ad71c	5443	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /!< HSI16 oscillator selection as system clock /
EricLew	0:d4e5ad7ad71c	5444	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /!< HSE oscillator selection as system clock /
EricLew	0:d4e5ad7ad71c	5445	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /!< PLL selection as system clock /
EricLew	0:d4e5ad7ad71c	5446
EricLew	0:d4e5ad7ad71c	5447	/!< SWS configuration /
EricLew	0:d4e5ad7ad71c	5448	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
EricLew	0:d4e5ad7ad71c	5449	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5450	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5451
EricLew	0:d4e5ad7ad71c	5452	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /!< MSI oscillator used as system clock /
EricLew	0:d4e5ad7ad71c	5453	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /!< HSI16 oscillator used as system clock /
EricLew	0:d4e5ad7ad71c	5454	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /!< HSE oscillator used as system clock /
EricLew	0:d4e5ad7ad71c	5455	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /!< PLL used as system clock /
EricLew	0:d4e5ad7ad71c	5456
EricLew	0:d4e5ad7ad71c	5457	/!< HPRE configuration /
EricLew	0:d4e5ad7ad71c	5458	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
EricLew	0:d4e5ad7ad71c	5459	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5460	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5461	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5462	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	5463
EricLew	0:d4e5ad7ad71c	5464	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
EricLew	0:d4e5ad7ad71c	5465	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
EricLew	0:d4e5ad7ad71c	5466	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
EricLew	0:d4e5ad7ad71c	5467	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
EricLew	0:d4e5ad7ad71c	5468	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
EricLew	0:d4e5ad7ad71c	5469	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
EricLew	0:d4e5ad7ad71c	5470	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
EricLew	0:d4e5ad7ad71c	5471	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
EricLew	0:d4e5ad7ad71c	5472	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
EricLew	0:d4e5ad7ad71c	5473
EricLew	0:d4e5ad7ad71c	5474	/!< PPRE1 configuration /
EricLew	0:d4e5ad7ad71c	5475	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB2 prescaler) /
EricLew	0:d4e5ad7ad71c	5476	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5477	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5478	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5479
EricLew	0:d4e5ad7ad71c	5480	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
EricLew	0:d4e5ad7ad71c	5481	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
EricLew	0:d4e5ad7ad71c	5482	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
EricLew	0:d4e5ad7ad71c	5483	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
EricLew	0:d4e5ad7ad71c	5484	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
EricLew	0:d4e5ad7ad71c	5485
EricLew	0:d4e5ad7ad71c	5486	/!< PPRE2 configuration /
EricLew	0:d4e5ad7ad71c	5487	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
EricLew	0:d4e5ad7ad71c	5488	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5489	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5490	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5491
EricLew	0:d4e5ad7ad71c	5492	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
EricLew	0:d4e5ad7ad71c	5493	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
EricLew	0:d4e5ad7ad71c	5494	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
EricLew	0:d4e5ad7ad71c	5495	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
EricLew	0:d4e5ad7ad71c	5496	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
EricLew	0:d4e5ad7ad71c	5497
EricLew	0:d4e5ad7ad71c	5498	#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000) /!< Wake Up from stop and CSS backup clock selection /
EricLew	0:d4e5ad7ad71c	5499
EricLew	0:d4e5ad7ad71c	5500	/!< MCOSEL configuration /
EricLew	0:d4e5ad7ad71c	5501	#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /!< MCOSEL [2:0] bits (Clock output selection) /
EricLew	0:d4e5ad7ad71c	5502	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	5503	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	5504	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	5505
EricLew	0:d4e5ad7ad71c	5506	#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /!< MCO prescaler /
EricLew	0:d4e5ad7ad71c	5507	#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
EricLew	0:d4e5ad7ad71c	5508	#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
EricLew	0:d4e5ad7ad71c	5509	#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
EricLew	0:d4e5ad7ad71c	5510	#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
EricLew	0:d4e5ad7ad71c	5511	#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
EricLew	0:d4e5ad7ad71c	5512
EricLew	0:d4e5ad7ad71c	5513	/****************** Bit definition for RCC_PLLCFGR register *************/
EricLew	0:d4e5ad7ad71c	5514	#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00000003)
EricLew	0:d4e5ad7ad71c	5515
EricLew	0:d4e5ad7ad71c	5516	#define RCC_PLLCFGR_PLLSRC_MSI ((uint32_t)0x00000001) /!< MSI oscillator source clock selected /
EricLew	0:d4e5ad7ad71c	5517	#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000002) /!< HSI16 oscillator source clock selected /
EricLew	0:d4e5ad7ad71c	5518	#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00000003) /!< HSE oscillator source clock selected /
EricLew	0:d4e5ad7ad71c	5519
EricLew	0:d4e5ad7ad71c	5520	#define RCC_PLLCFGR_PLLM ((uint32_t)0x00000070)
EricLew	0:d4e5ad7ad71c	5521	#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5522	#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5523	#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5524
EricLew	0:d4e5ad7ad71c	5525	#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007F00)
EricLew	0:d4e5ad7ad71c	5526	#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5527	#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5528	#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5529	#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5530	#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5531	#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5532	#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5533
EricLew	0:d4e5ad7ad71c	5534	#define RCC_PLLCFGR_PLLPEN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5535	#define RCC_PLLCFGR_PLLP ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5536	#define RCC_PLLCFGR_PLLQEN ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5537
EricLew	0:d4e5ad7ad71c	5538	#define RCC_PLLCFGR_PLLQ ((uint32_t)0x00600000)
EricLew	0:d4e5ad7ad71c	5539	#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5540	#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5541
EricLew	0:d4e5ad7ad71c	5542	#define RCC_PLLCFGR_PLLREN ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5543	#define RCC_PLLCFGR_PLLR ((uint32_t)0x06000000)
EricLew	0:d4e5ad7ad71c	5544	#define RCC_PLLCFGR_PLLR_0 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5545	#define RCC_PLLCFGR_PLLR_1 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	5546
EricLew	0:d4e5ad7ad71c	5547	/****************** Bit definition for RCC_PLLSAI1CFGR register **********/
EricLew	0:d4e5ad7ad71c	5548	#define RCC_PLLSAI1CFGR_PLLSAI1N ((uint32_t)0x00007F00)
EricLew	0:d4e5ad7ad71c	5549	#define RCC_PLLSAI1CFGR_PLLSAI1N_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5550	#define RCC_PLLSAI1CFGR_PLLSAI1N_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5551	#define RCC_PLLSAI1CFGR_PLLSAI1N_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5552	#define RCC_PLLSAI1CFGR_PLLSAI1N_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5553	#define RCC_PLLSAI1CFGR_PLLSAI1N_4 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5554	#define RCC_PLLSAI1CFGR_PLLSAI1N_5 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5555	#define RCC_PLLSAI1CFGR_PLLSAI1N_6 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5556
EricLew	0:d4e5ad7ad71c	5557	#define RCC_PLLSAI1CFGR_PLLSAI1PEN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5558	#define RCC_PLLSAI1CFGR_PLLSAI1P ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5559
EricLew	0:d4e5ad7ad71c	5560	#define RCC_PLLSAI1CFGR_PLLSAI1QEN ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5561	#define RCC_PLLSAI1CFGR_PLLSAI1Q ((uint32_t)0x00600000)
EricLew	0:d4e5ad7ad71c	5562	#define RCC_PLLSAI1CFGR_PLLSAI1Q_0 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5563	#define RCC_PLLSAI1CFGR_PLLSAI1Q_1 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5564
EricLew	0:d4e5ad7ad71c	5565	#define RCC_PLLSAI1CFGR_PLLSAI1REN ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5566	#define RCC_PLLSAI1CFGR_PLLSAI1R ((uint32_t)0x06000000)
EricLew	0:d4e5ad7ad71c	5567	#define RCC_PLLSAI1CFGR_PLLSAI1R_0 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5568	#define RCC_PLLSAI1CFGR_PLLSAI1R_1 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	5569
EricLew	0:d4e5ad7ad71c	5570	/****************** Bit definition for RCC_PLLSAI2CFGR register **********/
EricLew	0:d4e5ad7ad71c	5571	#define RCC_PLLSAI2CFGR_PLLSAI2N ((uint32_t)0x00007F00)
EricLew	0:d4e5ad7ad71c	5572	#define RCC_PLLSAI2CFGR_PLLSAI2N_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5573	#define RCC_PLLSAI2CFGR_PLLSAI2N_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5574	#define RCC_PLLSAI2CFGR_PLLSAI2N_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5575	#define RCC_PLLSAI2CFGR_PLLSAI2N_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5576	#define RCC_PLLSAI2CFGR_PLLSAI2N_4 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5577	#define RCC_PLLSAI2CFGR_PLLSAI2N_5 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5578	#define RCC_PLLSAI2CFGR_PLLSAI2N_6 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5579
EricLew	0:d4e5ad7ad71c	5580	#define RCC_PLLSAI2CFGR_PLLSAI2PEN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5581	#define RCC_PLLSAI2CFGR_PLLSAI2P ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5582
EricLew	0:d4e5ad7ad71c	5583	#define RCC_PLLSAI2CFGR_PLLSAI2REN ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5584	#define RCC_PLLSAI2CFGR_PLLSAI2R ((uint32_t)0x06000000)
EricLew	0:d4e5ad7ad71c	5585	#define RCC_PLLSAI2CFGR_PLLSAI2R_0 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5586	#define RCC_PLLSAI2CFGR_PLLSAI2R_1 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	5587
EricLew	0:d4e5ad7ad71c	5588	/****************** Bit definition for RCC_CIER register ****************/
EricLew	0:d4e5ad7ad71c	5589	#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5590	#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5591	#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5592	#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5593	#define RCC_CIER_HSERDYIE ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5594	#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5595	#define RCC_CIER_PLLSAI1RDYIE ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5596	#define RCC_CIER_PLLSAI2RDYIE ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5597	#define RCC_CIER_LSECSSIE ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5598
EricLew	0:d4e5ad7ad71c	5599	/****************** Bit definition for RCC_CIFR register ****************/
EricLew	0:d4e5ad7ad71c	5600	#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5601	#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5602	#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5603	#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5604	#define RCC_CIFR_HSERDYF ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5605	#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5606	#define RCC_CIFR_PLLSAI1RDYF ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5607	#define RCC_CIFR_PLLSAI2RDYF ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5608	#define RCC_CIFR_CSSF ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5609	#define RCC_CIFR_LSECSSF ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5610
EricLew	0:d4e5ad7ad71c	5611	/****************** Bit definition for RCC_CICR register ****************/
EricLew	0:d4e5ad7ad71c	5612	#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5613	#define RCC_CICR_LSERDYC ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5614	#define RCC_CICR_MSIRDYC ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5615	#define RCC_CICR_HSIRDYC ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5616	#define RCC_CICR_HSERDYC ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5617	#define RCC_CICR_PLLRDYC ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5618	#define RCC_CICR_PLLSAI1RDYC ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5619	#define RCC_CICR_PLLSAI2RDYC ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5620	#define RCC_CICR_CSSC ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5621	#define RCC_CICR_LSECSSC ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5622
EricLew	0:d4e5ad7ad71c	5623	/****************** Bit definition for RCC_AHB1RSTR register ************/
EricLew	0:d4e5ad7ad71c	5624	#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5625	#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5626	#define RCC_AHB1RSTR_FLASHRST ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5627	#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5628	#define RCC_AHB1RSTR_TSCRST ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5629
EricLew	0:d4e5ad7ad71c	5630	/****************** Bit definition for RCC_AHB2RSTR register ************/
EricLew	0:d4e5ad7ad71c	5631	#define RCC_AHB2RSTR_GPIOARST ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5632	#define RCC_AHB2RSTR_GPIOBRST ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5633	#define RCC_AHB2RSTR_GPIOCRST ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5634	#define RCC_AHB2RSTR_GPIODRST ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5635	#define RCC_AHB2RSTR_GPIOERST ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5636	#define RCC_AHB2RSTR_GPIOFRST ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5637	#define RCC_AHB2RSTR_GPIOGRST ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5638	#define RCC_AHB2RSTR_GPIOHRST ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5639	#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5640	#define RCC_AHB2RSTR_ADCRST ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5641	#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5642
EricLew	0:d4e5ad7ad71c	5643	/****************** Bit definition for RCC_AHB3RSTR register ************/
EricLew	0:d4e5ad7ad71c	5644	#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5645	#define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5646
EricLew	0:d4e5ad7ad71c	5647	/****************** Bit definition for RCC_APB1RSTR1 register ************/
EricLew	0:d4e5ad7ad71c	5648	#define RCC_APB1RSTR1_TIM2RST ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5649	#define RCC_APB1RSTR1_TIM3RST ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5650	#define RCC_APB1RSTR1_TIM4RST ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5651	#define RCC_APB1RSTR1_TIM5RST ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5652	#define RCC_APB1RSTR1_TIM6RST ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5653	#define RCC_APB1RSTR1_TIM7RST ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5654	#define RCC_APB1RSTR1_LCDRST ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5655	#define RCC_APB1RSTR1_SPI2RST ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5656	#define RCC_APB1RSTR1_SPI3RST ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	5657	#define RCC_APB1RSTR1_USART2RST ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5658	#define RCC_APB1RSTR1_USART3RST ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5659	#define RCC_APB1RSTR1_UART4RST ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	5660	#define RCC_APB1RSTR1_UART5RST ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5661	#define RCC_APB1RSTR1_I2C1RST ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5662	#define RCC_APB1RSTR1_I2C2RST ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5663	#define RCC_APB1RSTR1_I2C3RST ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	5664	#define RCC_APB1RSTR1_CAN1RST ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5665	#define RCC_APB1RSTR1_PWRRST ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	5666	#define RCC_APB1RSTR1_DAC1RST ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	5667	#define RCC_APB1RSTR1_OPAMPRST ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	5668	#define RCC_APB1RSTR1_LPTIM1RST ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	5669
EricLew	0:d4e5ad7ad71c	5670	/****************** Bit definition for RCC_APB1RSTR2 register ************/
EricLew	0:d4e5ad7ad71c	5671	#define RCC_APB1RSTR2_LPUART1RST ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5672	#define RCC_APB1RSTR2_SWPMI1RST ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5673	#define RCC_APB1RSTR2_LPTIM2RST ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5674
EricLew	0:d4e5ad7ad71c	5675	/****************** Bit definition for RCC_APB2RSTR register ************/
EricLew	0:d4e5ad7ad71c	5676	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5677	#define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5678	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5679	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5680	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5681	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5682	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5683	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5684	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5685	#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5686	#define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5687	#define RCC_APB2RSTR_DFSDMRST ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5688
EricLew	0:d4e5ad7ad71c	5689	/****************** Bit definition for RCC_AHB1ENR register *************/
EricLew	0:d4e5ad7ad71c	5690	#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5691	#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5692	#define RCC_AHB1ENR_FLASHEN ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5693	#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5694	#define RCC_AHB1ENR_TSCEN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5695
EricLew	0:d4e5ad7ad71c	5696	/****************** Bit definition for RCC_AHB2ENR register *************/
EricLew	0:d4e5ad7ad71c	5697	#define RCC_AHB2ENR_GPIOAEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5698	#define RCC_AHB2ENR_GPIOBEN ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5699	#define RCC_AHB2ENR_GPIOCEN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5700	#define RCC_AHB2ENR_GPIODEN ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5701	#define RCC_AHB2ENR_GPIOEEN ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5702	#define RCC_AHB2ENR_GPIOFEN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5703	#define RCC_AHB2ENR_GPIOGEN ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5704	#define RCC_AHB2ENR_GPIOHEN ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5705	#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5706	#define RCC_AHB2ENR_ADCEN ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5707	#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5708
EricLew	0:d4e5ad7ad71c	5709	/****************** Bit definition for RCC_AHB3ENR register *************/
EricLew	0:d4e5ad7ad71c	5710	#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5711	#define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5712
EricLew	0:d4e5ad7ad71c	5713	/****************** Bit definition for RCC_APB1ENR1 register *************/
EricLew	0:d4e5ad7ad71c	5714	#define RCC_APB1ENR1_TIM2EN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5715	#define RCC_APB1ENR1_TIM3EN ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5716	#define RCC_APB1ENR1_TIM4EN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5717	#define RCC_APB1ENR1_TIM5EN ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5718	#define RCC_APB1ENR1_TIM6EN ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5719	#define RCC_APB1ENR1_TIM7EN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5720	#define RCC_APB1ENR1_LCDEN ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5721	#define RCC_APB1ENR1_WWDGEN ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5722	#define RCC_APB1ENR1_SPI2EN ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5723	#define RCC_APB1ENR1_SPI3EN ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	5724	#define RCC_APB1ENR1_USART2EN ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5725	#define RCC_APB1ENR1_USART3EN ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5726	#define RCC_APB1ENR1_UART4EN ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	5727	#define RCC_APB1ENR1_UART5EN ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5728	#define RCC_APB1ENR1_I2C1EN ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5729	#define RCC_APB1ENR1_I2C2EN ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5730	#define RCC_APB1ENR1_I2C3EN ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	5731	#define RCC_APB1ENR1_CAN1EN ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5732	#define RCC_APB1ENR1_PWREN ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	5733	#define RCC_APB1ENR1_DAC1EN ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	5734	#define RCC_APB1ENR1_OPAMPEN ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	5735	#define RCC_APB1ENR1_LPTIM1EN ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	5736
EricLew	0:d4e5ad7ad71c	5737	/****************** Bit definition for RCC_APB1RSTR2 register ************/
EricLew	0:d4e5ad7ad71c	5738	#define RCC_APB1ENR2_LPUART1EN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5739	#define RCC_APB1ENR2_SWPMI1EN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5740	#define RCC_APB1ENR2_LPTIM2EN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5741
EricLew	0:d4e5ad7ad71c	5742	/****************** Bit definition for RCC_APB2ENR register *************/
EricLew	0:d4e5ad7ad71c	5743	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5744	#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5745	#define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5746	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5747	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5748	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5749	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5750	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5751	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5752	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5753	#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5754	#define RCC_APB2ENR_SAI2EN ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5755	#define RCC_APB2ENR_DFSDMEN ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5756
EricLew	0:d4e5ad7ad71c	5757	/****************** Bit definition for RCC_AHB1SMENR register *************/
EricLew	0:d4e5ad7ad71c	5758	#define RCC_AHB1SMENR_DMA1SMEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5759	#define RCC_AHB1SMENR_DMA2SMEN ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5760	#define RCC_AHB1SMENR_FLASHSMEN ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5761	#define RCC_AHB1SMENR_SRAM1SMEN ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5762	#define RCC_AHB1SMENR_CRCSMEN ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5763	#define RCC_AHB1SMENR_TSCSMEN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5764
EricLew	0:d4e5ad7ad71c	5765	/****************** Bit definition for RCC_AHB2SMENR register ***********/
EricLew	0:d4e5ad7ad71c	5766	#define RCC_AHB2SMENR_GPIOASMEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5767	#define RCC_AHB2SMENR_GPIOBSMEN ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5768	#define RCC_AHB2SMENR_GPIOCSMEN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5769	#define RCC_AHB2SMENR_GPIODSMEN ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5770	#define RCC_AHB2SMENR_GPIOESMEN ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5771	#define RCC_AHB2SMENR_GPIOFSMEN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5772	#define RCC_AHB2SMENR_GPIOGSMEN ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5773	#define RCC_AHB2SMENR_GPIOHSMEN ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5774	#define RCC_AHB2SMENR_SRAM2SMEN ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5775	#define RCC_AHB2SMENR_OTGFSSMEN ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5776	#define RCC_AHB2SMENR_ADCSMEN ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5777	#define RCC_AHB2SMENR_RNGSMEN ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5778
EricLew	0:d4e5ad7ad71c	5779	/****************** Bit definition for RCC_AHB3SMENR register ***********/
EricLew	0:d4e5ad7ad71c	5780	#define RCC_AHB3SMENR_FMCSMEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5781	#define RCC_AHB3SMENR_QSPISMEN ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5782
EricLew	0:d4e5ad7ad71c	5783	/****************** Bit definition for RCC_APB1SMENR1 register ***********/
EricLew	0:d4e5ad7ad71c	5784	#define RCC_APB1SMENR1_TIM2SMEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5785	#define RCC_APB1SMENR1_TIM3SMEN ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5786	#define RCC_APB1SMENR1_TIM4SMEN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5787	#define RCC_APB1SMENR1_TIM5SMEN ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5788	#define RCC_APB1SMENR1_TIM6SMEN ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5789	#define RCC_APB1SMENR1_TIM7SMEN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5790	#define RCC_APB1SMENR1_LCDSMEN ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5791	#define RCC_APB1SMENR1_WWDGSMEN ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5792	#define RCC_APB1SMENR1_SPI2SMEN ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5793	#define RCC_APB1SMENR1_SPI3SMEN ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	5794	#define RCC_APB1SMENR1_USART2SMEN ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5795	#define RCC_APB1SMENR1_USART3SMEN ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5796	#define RCC_APB1SMENR1_UART4SMEN ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	5797	#define RCC_APB1SMENR1_UART5SMEN ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5798	#define RCC_APB1SMENR1_I2C1SMEN ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5799	#define RCC_APB1SMENR1_I2C2SMEN ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5800	#define RCC_APB1SMENR1_I2C3SMEN ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	5801	#define RCC_APB1SMENR1_CAN1SMEN ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5802	#define RCC_APB1SMENR1_PWRSMEN ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	5803	#define RCC_APB1SMENR1_DAC1SMEN ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	5804	#define RCC_APB1SMENR1_OPAMPSMEN ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	5805	#define RCC_APB1SMENR1_LPTIM1SMEN ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	5806
EricLew	0:d4e5ad7ad71c	5807	/****************** Bit definition for RCC_APB1SMENR2 register ***********/
EricLew	0:d4e5ad7ad71c	5808	#define RCC_APB1SMENR2_LPUART1SMEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5809	#define RCC_APB1SMENR2_SWPMI1SMEN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5810	#define RCC_APB1SMENR2_LPTIM2SMEN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5811
EricLew	0:d4e5ad7ad71c	5812	/****************** Bit definition for RCC_APB2SMENR register ***********/
EricLew	0:d4e5ad7ad71c	5813	#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5814	#define RCC_APB2SMENR_SDMMC1SMEN ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5815	#define RCC_APB2SMENR_TIM1SMEN ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5816	#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5817	#define RCC_APB2SMENR_TIM8SMEN ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5818	#define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5819	#define RCC_APB2SMENR_TIM15SMEN ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5820	#define RCC_APB2SMENR_TIM16SMEN ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5821	#define RCC_APB2SMENR_TIM17SMEN ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5822	#define RCC_APB2SMENR_SAI1SMEN ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5823	#define RCC_APB2SMENR_SAI2SMEN ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5824	#define RCC_APB2SMENR_DFSDMSMEN ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5825
EricLew	0:d4e5ad7ad71c	5826	/****************** Bit definition for RCC_CCIPR register ****************/
EricLew	0:d4e5ad7ad71c	5827	#define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003)
EricLew	0:d4e5ad7ad71c	5828	#define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5829	#define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5830
EricLew	0:d4e5ad7ad71c	5831	#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000C)
EricLew	0:d4e5ad7ad71c	5832	#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5833	#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5834
EricLew	0:d4e5ad7ad71c	5835	#define RCC_CCIPR_USART3SEL ((uint32_t)0x00000030)
EricLew	0:d4e5ad7ad71c	5836	#define RCC_CCIPR_USART3SEL_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5837	#define RCC_CCIPR_USART3SEL_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5838
EricLew	0:d4e5ad7ad71c	5839	#define RCC_CCIPR_UART4SEL ((uint32_t)0x000000C0)
EricLew	0:d4e5ad7ad71c	5840	#define RCC_CCIPR_UART4SEL_0 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5841	#define RCC_CCIPR_UART4SEL_1 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	5842
EricLew	0:d4e5ad7ad71c	5843	#define RCC_CCIPR_UART5SEL ((uint32_t)0x00000300)
EricLew	0:d4e5ad7ad71c	5844	#define RCC_CCIPR_UART5SEL_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5845	#define RCC_CCIPR_UART5SEL_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5846
EricLew	0:d4e5ad7ad71c	5847	#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x00000C00)
EricLew	0:d4e5ad7ad71c	5848	#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5849	#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5850
EricLew	0:d4e5ad7ad71c	5851	#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000)
EricLew	0:d4e5ad7ad71c	5852	#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5853	#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5854
EricLew	0:d4e5ad7ad71c	5855	#define RCC_CCIPR_I2C2SEL ((uint32_t)0x0000C000)
EricLew	0:d4e5ad7ad71c	5856	#define RCC_CCIPR_I2C2SEL_0 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5857	#define RCC_CCIPR_I2C2SEL_1 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	5858
EricLew	0:d4e5ad7ad71c	5859	#define RCC_CCIPR_I2C3SEL ((uint32_t)0x00030000)
EricLew	0:d4e5ad7ad71c	5860	#define RCC_CCIPR_I2C3SEL_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5861	#define RCC_CCIPR_I2C3SEL_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5862
EricLew	0:d4e5ad7ad71c	5863	#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000)
EricLew	0:d4e5ad7ad71c	5864	#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5865	#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	5866
EricLew	0:d4e5ad7ad71c	5867	#define RCC_CCIPR_LPTIM2SEL ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	5868	#define RCC_CCIPR_LPTIM2SEL_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5869	#define RCC_CCIPR_LPTIM2SEL_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5870
EricLew	0:d4e5ad7ad71c	5871	#define RCC_CCIPR_SAI1SEL ((uint32_t)0x00C00000)
EricLew	0:d4e5ad7ad71c	5872	#define RCC_CCIPR_SAI1SEL_0 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5873	#define RCC_CCIPR_SAI1SEL_1 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	5874
EricLew	0:d4e5ad7ad71c	5875	#define RCC_CCIPR_SAI2SEL ((uint32_t)0x03000000)
EricLew	0:d4e5ad7ad71c	5876	#define RCC_CCIPR_SAI2SEL_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5877	#define RCC_CCIPR_SAI2SEL_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5878
EricLew	0:d4e5ad7ad71c	5879	#define RCC_CCIPR_CLK48SEL ((uint32_t)0x0C000000)
EricLew	0:d4e5ad7ad71c	5880	#define RCC_CCIPR_CLK48SEL_0 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	5881	#define RCC_CCIPR_CLK48SEL_1 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	5882
EricLew	0:d4e5ad7ad71c	5883	#define RCC_CCIPR_ADCSEL ((uint32_t)0x30000000)
EricLew	0:d4e5ad7ad71c	5884	#define RCC_CCIPR_ADCSEL_0 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	5885	#define RCC_CCIPR_ADCSEL_1 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	5886
EricLew	0:d4e5ad7ad71c	5887	#define RCC_CCIPR_SWPMI1SEL ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	5888	#define RCC_CCIPR_DFSDMSEL ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	5889
EricLew	0:d4e5ad7ad71c	5890	/****************** Bit definition for RCC_BDCR register ****************/
EricLew	0:d4e5ad7ad71c	5891	#define RCC_BDCR_LSEON ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5892	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5893	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5894
EricLew	0:d4e5ad7ad71c	5895	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
EricLew	0:d4e5ad7ad71c	5896	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5897	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5898
EricLew	0:d4e5ad7ad71c	5899	#define RCC_BDCR_LSECSSON ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5900	#define RCC_BDCR_LSECSSD ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5901
EricLew	0:d4e5ad7ad71c	5902	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
EricLew	0:d4e5ad7ad71c	5903	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5904	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5905
EricLew	0:d4e5ad7ad71c	5906	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	5907	#define RCC_BDCR_BDRST ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5908	#define RCC_BDCR_LSCOEN ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5909	#define RCC_BDCR_LSCOSEL ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5910
EricLew	0:d4e5ad7ad71c	5911	/****************** Bit definition for RCC_CSR register *****************/
EricLew	0:d4e5ad7ad71c	5912	#define RCC_CSR_LSION ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5913	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5914
EricLew	0:d4e5ad7ad71c	5915	#define RCC_CSR_MSISRANGE ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	5916	#define RCC_CSR_MSISRANGE_1 ((uint32_t)0x00000400) /!< MSI frequency 1MHZ /
EricLew	0:d4e5ad7ad71c	5917	#define RCC_CSR_MSISRANGE_2 ((uint32_t)0x00000500) /!< MSI frequency 2MHZ /
EricLew	0:d4e5ad7ad71c	5918	#define RCC_CSR_MSISRANGE_4 ((uint32_t)0x00000600) /!< The default frequency 4MHZ /
EricLew	0:d4e5ad7ad71c	5919	#define RCC_CSR_MSISRANGE_8 ((uint32_t)0x00000700) /!< MSI frequency 8MHZ /
EricLew	0:d4e5ad7ad71c	5920
EricLew	0:d4e5ad7ad71c	5921	#define RCC_CSR_RMVF ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	5922	#define RCC_CSR_FWRSTF ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	5923	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	5924	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	5925	#define RCC_CSR_BORRSTF ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	5926	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	5927	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	5928	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	5929	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	5930
EricLew	0:d4e5ad7ad71c	5931
EricLew	0:d4e5ad7ad71c	5932
EricLew	0:d4e5ad7ad71c	5933	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5934	/* */
EricLew	0:d4e5ad7ad71c	5935	/* RNG */
EricLew	0:d4e5ad7ad71c	5936	/* */
EricLew	0:d4e5ad7ad71c	5937	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5938	/****************** Bits definition for RNG_CR register *****************/
EricLew	0:d4e5ad7ad71c	5939	#define RNG_CR_RNGEN ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5940	#define RNG_CR_IE ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5941
EricLew	0:d4e5ad7ad71c	5942	/****************** Bits definition for RNG_SR register *****************/
EricLew	0:d4e5ad7ad71c	5943	#define RNG_SR_DRDY ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5944	#define RNG_SR_CECS ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5945	#define RNG_SR_SECS ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5946	#define RNG_SR_CEIS ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5947	#define RNG_SR_SEIS ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5948
EricLew	0:d4e5ad7ad71c	5949	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5950	/* */
EricLew	0:d4e5ad7ad71c	5951	/* Real-Time Clock (RTC) */
EricLew	0:d4e5ad7ad71c	5952	/* */
EricLew	0:d4e5ad7ad71c	5953	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	5954	/****************** Bits definition for RTC_TR register *****************/
EricLew	0:d4e5ad7ad71c	5955	#define RTC_TR_PM ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5956	#define RTC_TR_HT ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	5957	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5958	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5959	#define RTC_TR_HU ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	5960	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5961	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5962	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5963	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	5964	#define RTC_TR_MNT ((uint32_t)0x00007000)
EricLew	0:d4e5ad7ad71c	5965	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5966	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5967	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5968	#define RTC_TR_MNU ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	5969	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	5970	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	5971	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	5972	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	5973	#define RTC_TR_ST ((uint32_t)0x00000070)
EricLew	0:d4e5ad7ad71c	5974	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	5975	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	5976	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	5977	#define RTC_TR_SU ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	5978	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	5979	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	5980	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	5981	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	5982
EricLew	0:d4e5ad7ad71c	5983	/****************** Bits definition for RTC_DR register *****************/
EricLew	0:d4e5ad7ad71c	5984	#define RTC_DR_YT ((uint32_t)0x00F00000)
EricLew	0:d4e5ad7ad71c	5985	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	5986	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	5987	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	5988	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	5989	#define RTC_DR_YU ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	5990	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	5991	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	5992	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	5993	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	5994	#define RTC_DR_WDU ((uint32_t)0x0000E000)
EricLew	0:d4e5ad7ad71c	5995	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	5996	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	5997	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	5998	#define RTC_DR_MT ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	5999	#define RTC_DR_MU ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	6000	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6001	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6002	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6003	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6004	#define RTC_DR_DT ((uint32_t)0x00000030)
EricLew	0:d4e5ad7ad71c	6005	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6006	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6007	#define RTC_DR_DU ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	6008	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6009	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6010	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6011	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6012
EricLew	0:d4e5ad7ad71c	6013	/****************** Bits definition for RTC_CR register *****************/
EricLew	0:d4e5ad7ad71c	6014	#define RTC_CR_ITSE ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	6015	#define RTC_CR_COE ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	6016	#define RTC_CR_OSEL ((uint32_t)0x00600000)
EricLew	0:d4e5ad7ad71c	6017	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	6018	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	6019	#define RTC_CR_POL ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	6020	#define RTC_CR_COSEL ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	6021	#define RTC_CR_BCK ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	6022	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	6023	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	6024	#define RTC_CR_TSIE ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6025	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6026	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6027	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6028	#define RTC_CR_TSE ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6029	#define RTC_CR_WUTE ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6030	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6031	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6032	#define RTC_CR_FMT ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6033	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6034	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6035	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6036	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
EricLew	0:d4e5ad7ad71c	6037	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6038	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6039	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6040
EricLew	0:d4e5ad7ad71c	6041	/****************** Bits definition for RTC_ISR register ****************/
EricLew	0:d4e5ad7ad71c	6042	#define RTC_ISR_ITSF ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	6043	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	6044	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6045	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6046	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6047	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6048	#define RTC_ISR_TSF ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6049	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6050	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6051	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6052	#define RTC_ISR_INIT ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	6053	#define RTC_ISR_INITF ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6054	#define RTC_ISR_RSF ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6055	#define RTC_ISR_INITS ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6056	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6057	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6058	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6059	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6060
EricLew	0:d4e5ad7ad71c	6061	/****************** Bits definition for RTC_PRER register ***************/
EricLew	0:d4e5ad7ad71c	6062	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
EricLew	0:d4e5ad7ad71c	6063	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
EricLew	0:d4e5ad7ad71c	6064
EricLew	0:d4e5ad7ad71c	6065	/****************** Bits definition for RTC_WUTR register ***************/
EricLew	0:d4e5ad7ad71c	6066	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	6067
EricLew	0:d4e5ad7ad71c	6068	/****************** Bits definition for RTC_ALRMAR register *************/
EricLew	0:d4e5ad7ad71c	6069	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	6070	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	6071	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
EricLew	0:d4e5ad7ad71c	6072	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	6073	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	6074	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
EricLew	0:d4e5ad7ad71c	6075	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	6076	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	6077	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	6078	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	6079	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	6080	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	6081	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	6082	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	6083	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	6084	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	6085	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	6086	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	6087	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	6088	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	6089	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6090	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
EricLew	0:d4e5ad7ad71c	6091	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6092	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6093	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6094	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	6095	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6096	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6097	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6098	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6099	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	6100	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
EricLew	0:d4e5ad7ad71c	6101	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6102	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6103	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6104	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	6105	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6106	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6107	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6108	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6109
EricLew	0:d4e5ad7ad71c	6110	/****************** Bits definition for RTC_ALRMBR register *************/
EricLew	0:d4e5ad7ad71c	6111	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	6112	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
EricLew	0:d4e5ad7ad71c	6113	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
EricLew	0:d4e5ad7ad71c	6114	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
EricLew	0:d4e5ad7ad71c	6115	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
EricLew	0:d4e5ad7ad71c	6116	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
EricLew	0:d4e5ad7ad71c	6117	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	6118	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	6119	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	6120	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	6121	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	6122	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	6123	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	6124	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	6125	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	6126	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	6127	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	6128	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	6129	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	6130	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	6131	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6132	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
EricLew	0:d4e5ad7ad71c	6133	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6134	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6135	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6136	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	6137	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6138	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6139	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6140	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6141	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	6142	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
EricLew	0:d4e5ad7ad71c	6143	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6144	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6145	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6146	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	6147	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6148	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6149	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6150	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6151
EricLew	0:d4e5ad7ad71c	6152	/****************** Bits definition for RTC_WPR register ****************/
EricLew	0:d4e5ad7ad71c	6153	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
EricLew	0:d4e5ad7ad71c	6154
EricLew	0:d4e5ad7ad71c	6155	/****************** Bits definition for RTC_SSR register ****************/
EricLew	0:d4e5ad7ad71c	6156	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	6157
EricLew	0:d4e5ad7ad71c	6158	/****************** Bits definition for RTC_SHIFTR register *************/
EricLew	0:d4e5ad7ad71c	6159	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
EricLew	0:d4e5ad7ad71c	6160	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	6161
EricLew	0:d4e5ad7ad71c	6162	/****************** Bits definition for RTC_TSTR register ***************/
EricLew	0:d4e5ad7ad71c	6163	#define RTC_TSTR_PM ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	6164	#define RTC_TSTR_HT ((uint32_t)0x00300000)
EricLew	0:d4e5ad7ad71c	6165	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	6166	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	6167	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
EricLew	0:d4e5ad7ad71c	6168	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	6169	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	6170	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	6171	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	6172	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
EricLew	0:d4e5ad7ad71c	6173	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6174	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6175	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6176	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	6177	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6178	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6179	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6180	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6181	#define RTC_TSTR_ST ((uint32_t)0x00000070)
EricLew	0:d4e5ad7ad71c	6182	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6183	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6184	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6185	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	6186	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6187	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6188	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6189	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6190
EricLew	0:d4e5ad7ad71c	6191	/****************** Bits definition for RTC_TSDR register ***************/
EricLew	0:d4e5ad7ad71c	6192	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
EricLew	0:d4e5ad7ad71c	6193	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6194	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6195	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6196	#define RTC_TSDR_MT ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6197	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
EricLew	0:d4e5ad7ad71c	6198	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6199	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6200	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6201	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6202	#define RTC_TSDR_DT ((uint32_t)0x00000030)
EricLew	0:d4e5ad7ad71c	6203	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6204	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6205	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
EricLew	0:d4e5ad7ad71c	6206	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6207	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6208	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6209	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6210
EricLew	0:d4e5ad7ad71c	6211	/****************** Bits definition for RTC_TSSSR register **************/
EricLew	0:d4e5ad7ad71c	6212	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
EricLew	0:d4e5ad7ad71c	6213
EricLew	0:d4e5ad7ad71c	6214	/****************** Bits definition for RTC_CAL register ***************/
EricLew	0:d4e5ad7ad71c	6215	#define RTC_CALR_CALP ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6216	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6217	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6218	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
EricLew	0:d4e5ad7ad71c	6219	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6220	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6221	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6222	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6223	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6224	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6225	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6226	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	6227	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6228
EricLew	0:d4e5ad7ad71c	6229	/****************** Bits definition for RTC_TAMPCR register *************/
EricLew	0:d4e5ad7ad71c	6230	#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	6231	#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	6232	#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	6233	#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	6234	#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
EricLew	0:d4e5ad7ad71c	6235	#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
EricLew	0:d4e5ad7ad71c	6236	#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	6237	#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	6238	#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	6239	#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
EricLew	0:d4e5ad7ad71c	6240	#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
EricLew	0:d4e5ad7ad71c	6241	#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	6242	#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
EricLew	0:d4e5ad7ad71c	6243	#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
EricLew	0:d4e5ad7ad71c	6244	#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	6245	#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	6246	#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
EricLew	0:d4e5ad7ad71c	6247	#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
EricLew	0:d4e5ad7ad71c	6248	#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
EricLew	0:d4e5ad7ad71c	6249	#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	6250	#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
EricLew	0:d4e5ad7ad71c	6251	#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040)
EricLew	0:d4e5ad7ad71c	6252	#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6253	#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	6254	#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	6255	#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6256	#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6257	#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6258
EricLew	0:d4e5ad7ad71c	6259	/****************** Bits definition for RTC_ALRMASSR register ***********/
EricLew	0:d4e5ad7ad71c	6260	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
EricLew	0:d4e5ad7ad71c	6261	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	6262	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	6263	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	6264	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	6265	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
EricLew	0:d4e5ad7ad71c	6266
EricLew	0:d4e5ad7ad71c	6267	/****************** Bits definition for RTC_ALRMBSSR register ***********/
EricLew	0:d4e5ad7ad71c	6268	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
EricLew	0:d4e5ad7ad71c	6269	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
EricLew	0:d4e5ad7ad71c	6270	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	6271	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
EricLew	0:d4e5ad7ad71c	6272	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
EricLew	0:d4e5ad7ad71c	6273	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
EricLew	0:d4e5ad7ad71c	6274
EricLew	0:d4e5ad7ad71c	6275	/****************** Bits definition for RTC_0R register *****************/
EricLew	0:d4e5ad7ad71c	6276	#define RTC_OR_OUT_RMP ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6277	#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6278
EricLew	0:d4e5ad7ad71c	6279
EricLew	0:d4e5ad7ad71c	6280	/****************** Bits definition for RTC_BKP0R register **************/
EricLew	0:d4e5ad7ad71c	6281	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6282
EricLew	0:d4e5ad7ad71c	6283	/****************** Bits definition for RTC_BKP1R register **************/
EricLew	0:d4e5ad7ad71c	6284	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6285
EricLew	0:d4e5ad7ad71c	6286	/****************** Bits definition for RTC_BKP2R register **************/
EricLew	0:d4e5ad7ad71c	6287	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6288
EricLew	0:d4e5ad7ad71c	6289	/****************** Bits definition for RTC_BKP3R register **************/
EricLew	0:d4e5ad7ad71c	6290	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6291
EricLew	0:d4e5ad7ad71c	6292	/****************** Bits definition for RTC_BKP4R register **************/
EricLew	0:d4e5ad7ad71c	6293	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6294
EricLew	0:d4e5ad7ad71c	6295	/****************** Bits definition for RTC_BKP5R register **************/
EricLew	0:d4e5ad7ad71c	6296	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6297
EricLew	0:d4e5ad7ad71c	6298	/****************** Bits definition for RTC_BKP6R register **************/
EricLew	0:d4e5ad7ad71c	6299	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6300
EricLew	0:d4e5ad7ad71c	6301	/****************** Bits definition for RTC_BKP7R register **************/
EricLew	0:d4e5ad7ad71c	6302	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6303
EricLew	0:d4e5ad7ad71c	6304	/****************** Bits definition for RTC_BKP8R register **************/
EricLew	0:d4e5ad7ad71c	6305	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6306
EricLew	0:d4e5ad7ad71c	6307	/****************** Bits definition for RTC_BKP9R register **************/
EricLew	0:d4e5ad7ad71c	6308	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6309
EricLew	0:d4e5ad7ad71c	6310	/****************** Bits definition for RTC_BKP10R register *************/
EricLew	0:d4e5ad7ad71c	6311	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6312
EricLew	0:d4e5ad7ad71c	6313	/****************** Bits definition for RTC_BKP11R register *************/
EricLew	0:d4e5ad7ad71c	6314	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6315
EricLew	0:d4e5ad7ad71c	6316	/****************** Bits definition for RTC_BKP12R register *************/
EricLew	0:d4e5ad7ad71c	6317	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6318
EricLew	0:d4e5ad7ad71c	6319	/****************** Bits definition for RTC_BKP13R register *************/
EricLew	0:d4e5ad7ad71c	6320	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6321
EricLew	0:d4e5ad7ad71c	6322	/****************** Bits definition for RTC_BKP14R register *************/
EricLew	0:d4e5ad7ad71c	6323	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6324
EricLew	0:d4e5ad7ad71c	6325	/****************** Bits definition for RTC_BKP15R register *************/
EricLew	0:d4e5ad7ad71c	6326	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6327
EricLew	0:d4e5ad7ad71c	6328	/****************** Bits definition for RTC_BKP16R register *************/
EricLew	0:d4e5ad7ad71c	6329	#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6330
EricLew	0:d4e5ad7ad71c	6331	/****************** Bits definition for RTC_BKP17R register *************/
EricLew	0:d4e5ad7ad71c	6332	#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6333
EricLew	0:d4e5ad7ad71c	6334	/****************** Bits definition for RTC_BKP18R register *************/
EricLew	0:d4e5ad7ad71c	6335	#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6336
EricLew	0:d4e5ad7ad71c	6337	/****************** Bits definition for RTC_BKP19R register *************/
EricLew	0:d4e5ad7ad71c	6338	#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6339
EricLew	0:d4e5ad7ad71c	6340	/****************** Bits definition for RTC_BKP20R register *************/
EricLew	0:d4e5ad7ad71c	6341	#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6342
EricLew	0:d4e5ad7ad71c	6343	/****************** Bits definition for RTC_BKP21R register *************/
EricLew	0:d4e5ad7ad71c	6344	#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6345
EricLew	0:d4e5ad7ad71c	6346	/****************** Bits definition for RTC_BKP22R register *************/
EricLew	0:d4e5ad7ad71c	6347	#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6348
EricLew	0:d4e5ad7ad71c	6349	/****************** Bits definition for RTC_BKP23R register *************/
EricLew	0:d4e5ad7ad71c	6350	#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6351
EricLew	0:d4e5ad7ad71c	6352	/****************** Bits definition for RTC_BKP24R register *************/
EricLew	0:d4e5ad7ad71c	6353	#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6354
EricLew	0:d4e5ad7ad71c	6355	/****************** Bits definition for RTC_BKP25R register *************/
EricLew	0:d4e5ad7ad71c	6356	#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6357
EricLew	0:d4e5ad7ad71c	6358	/****************** Bits definition for RTC_BKP26R register *************/
EricLew	0:d4e5ad7ad71c	6359	#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6360
EricLew	0:d4e5ad7ad71c	6361	/****************** Bits definition for RTC_BKP27R register *************/
EricLew	0:d4e5ad7ad71c	6362	#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6363
EricLew	0:d4e5ad7ad71c	6364	/****************** Bits definition for RTC_BKP28R register *************/
EricLew	0:d4e5ad7ad71c	6365	#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6366
EricLew	0:d4e5ad7ad71c	6367	/****************** Bits definition for RTC_BKP29R register *************/
EricLew	0:d4e5ad7ad71c	6368	#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6369
EricLew	0:d4e5ad7ad71c	6370	/****************** Bits definition for RTC_BKP30R register *************/
EricLew	0:d4e5ad7ad71c	6371	#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6372
EricLew	0:d4e5ad7ad71c	6373	/****************** Bits definition for RTC_BKP31R register *************/
EricLew	0:d4e5ad7ad71c	6374	#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6375
EricLew	0:d4e5ad7ad71c	6376	/****************** Number of backup registers ****************************/
EricLew	0:d4e5ad7ad71c	6377	#define RTC_BKP_NUMBER ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	6378
EricLew	0:d4e5ad7ad71c	6379	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6380	/* */
EricLew	0:d4e5ad7ad71c	6381	/* Serial Audio Interface */
EricLew	0:d4e5ad7ad71c	6382	/* */
EricLew	0:d4e5ad7ad71c	6383	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6384	/****************** Bit definition for SAI_GCR register *****************/
EricLew	0:d4e5ad7ad71c	6385	#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /!<SYNCIN[1:0] bits (Synchronization Inputs) /
EricLew	0:d4e5ad7ad71c	6386	#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6387	#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6388
EricLew	0:d4e5ad7ad71c	6389	#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /!<SYNCOUT[1:0] bits (Synchronization Outputs) /
EricLew	0:d4e5ad7ad71c	6390	#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6391	#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6392
EricLew	0:d4e5ad7ad71c	6393	/***************** Bit definition for SAI_xCR1 register *****************/
EricLew	0:d4e5ad7ad71c	6394	#define SAI_xCR1_MODE ((uint32_t)0x00000003) /!<MODE[1:0] bits (Audio Block Mode) /
EricLew	0:d4e5ad7ad71c	6395	#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6396	#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6397
EricLew	0:d4e5ad7ad71c	6398	#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /!<PRTCFG[1:0] bits (Protocol Configuration) /
EricLew	0:d4e5ad7ad71c	6399	#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6400	#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6401
EricLew	0:d4e5ad7ad71c	6402	#define SAI_xCR1_DS ((uint32_t)0x000000E0) /!<DS[1:0] bits (Data Size) /
EricLew	0:d4e5ad7ad71c	6403	#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6404	#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6405	#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6406
EricLew	0:d4e5ad7ad71c	6407	#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /!<LSB First Configuration /
EricLew	0:d4e5ad7ad71c	6408	#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /!<ClocK STRobing edge /
EricLew	0:d4e5ad7ad71c	6409
EricLew	0:d4e5ad7ad71c	6410	#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /!<SYNCEN[1:0](SYNChronization ENable) /
EricLew	0:d4e5ad7ad71c	6411	#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6412	#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6413
EricLew	0:d4e5ad7ad71c	6414	#define SAI_xCR1_MONO ((uint32_t)0x00001000) /!<Mono mode /
EricLew	0:d4e5ad7ad71c	6415	#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /!<Output Drive /
EricLew	0:d4e5ad7ad71c	6416	#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /!<Audio Block enable /
EricLew	0:d4e5ad7ad71c	6417	#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /!<DMA enable /
EricLew	0:d4e5ad7ad71c	6418	#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /!<No Divider Configuration /
EricLew	0:d4e5ad7ad71c	6419
EricLew	0:d4e5ad7ad71c	6420	#define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /!<MCKDIV[3:0] (Master ClocK Divider) /
EricLew	0:d4e5ad7ad71c	6421	#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6422	#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6423	#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6424	#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6425
EricLew	0:d4e5ad7ad71c	6426	/***************** Bit definition for SAI_xCR2 register *****************/
EricLew	0:d4e5ad7ad71c	6427	#define SAI_xCR2_FTH ((uint32_t)0x00000007) /!<FTH[2:0](Fifo THreshold) /
EricLew	0:d4e5ad7ad71c	6428	#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6429	#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6430	#define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6431
EricLew	0:d4e5ad7ad71c	6432	#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /!<Fifo FLUSH /
EricLew	0:d4e5ad7ad71c	6433	#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /!<TRIState Management on data line /
EricLew	0:d4e5ad7ad71c	6434	#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /!<Mute mode /
EricLew	0:d4e5ad7ad71c	6435	#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /!<Muate value /
EricLew	0:d4e5ad7ad71c	6436
EricLew	0:d4e5ad7ad71c	6437
EricLew	0:d4e5ad7ad71c	6438	#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /!<MUTECNT[5:0] (MUTE counter) /
EricLew	0:d4e5ad7ad71c	6439	#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6440	#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6441	#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6442	#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6443	#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	6444	#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	6445
EricLew	0:d4e5ad7ad71c	6446	#define SAI_xCR2_CPL ((uint32_t)0x00002000) /!<CPL mode /
EricLew	0:d4e5ad7ad71c	6447	#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /!<COMP[1:0] (Companding mode) /
EricLew	0:d4e5ad7ad71c	6448	#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6449	#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6450
EricLew	0:d4e5ad7ad71c	6451
EricLew	0:d4e5ad7ad71c	6452	/**************** Bit definition for SAI_xFRCR register *****************/
EricLew	0:d4e5ad7ad71c	6453	#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /!<FRL[7:0](Frame length) /
EricLew	0:d4e5ad7ad71c	6454	#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6455	#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6456	#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6457	#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6458	#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	6459	#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	6460	#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	6461	#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	6462
EricLew	0:d4e5ad7ad71c	6463	#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /!<FRL[6:0] (Frame synchronization active level length) /
EricLew	0:d4e5ad7ad71c	6464	#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6465	#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6466	#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6467	#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6468	#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	6469	#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	6470	#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	6471
EricLew	0:d4e5ad7ad71c	6472	#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /!< Frame Synchronization Definition /
EricLew	0:d4e5ad7ad71c	6473	#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /!<Frame Synchronization POLarity /
EricLew	0:d4e5ad7ad71c	6474	#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /!<Frame Synchronization OFFset /
EricLew	0:d4e5ad7ad71c	6475
EricLew	0:d4e5ad7ad71c	6476	/**************** Bit definition for SAI_xSLOTR register *****************/
EricLew	0:d4e5ad7ad71c	6477	#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /!<FRL[4:0](First Bit Offset) /
EricLew	0:d4e5ad7ad71c	6478	#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6479	#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6480	#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6481	#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6482	#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	6483
EricLew	0:d4e5ad7ad71c	6484	#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /!<SLOTSZ[1:0] (Slot size) /
EricLew	0:d4e5ad7ad71c	6485	#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6486	#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6487
EricLew	0:d4e5ad7ad71c	6488	#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /!<NBSLOT[3:0] (Number of Slot in audio Frame) /
EricLew	0:d4e5ad7ad71c	6489	#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6490	#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6491	#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6492	#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6493
EricLew	0:d4e5ad7ad71c	6494	#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /!<SLOTEN[15:0] (Slot Enable) /
EricLew	0:d4e5ad7ad71c	6495
EricLew	0:d4e5ad7ad71c	6496	/***************** Bit definition for SAI_xIMR register *****************/
EricLew	0:d4e5ad7ad71c	6497	#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /!<Overrun underrun interrupt enable /
EricLew	0:d4e5ad7ad71c	6498	#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /!<Mute detection interrupt enable /
EricLew	0:d4e5ad7ad71c	6499	#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /!<Wrong Clock Configuration interrupt enable /
EricLew	0:d4e5ad7ad71c	6500	#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /!<FIFO request interrupt enable /
EricLew	0:d4e5ad7ad71c	6501	#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /!<Codec not ready interrupt enable /
EricLew	0:d4e5ad7ad71c	6502	#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection interrupt enable /
EricLew	0:d4e5ad7ad71c	6503	#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /!<Late frame synchronization detection interrupt enable /
EricLew	0:d4e5ad7ad71c	6504
EricLew	0:d4e5ad7ad71c	6505	/****************** Bit definition for SAI_xSR register *****************/
EricLew	0:d4e5ad7ad71c	6506	#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /!<Overrun underrun /
EricLew	0:d4e5ad7ad71c	6507	#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /!<Mute detection /
EricLew	0:d4e5ad7ad71c	6508	#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /!<Wrong Clock Configuration /
EricLew	0:d4e5ad7ad71c	6509	#define SAI_xSR_FREQ ((uint32_t)0x00000008) /!<FIFO request /
EricLew	0:d4e5ad7ad71c	6510	#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /!<Codec not ready /
EricLew	0:d4e5ad7ad71c	6511	#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /!<Anticipated frame synchronization detection /
EricLew	0:d4e5ad7ad71c	6512	#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /!<Late frame synchronization detection /
EricLew	0:d4e5ad7ad71c	6513
EricLew	0:d4e5ad7ad71c	6514	#define SAI_xSR_FLVL ((uint32_t)0x00070000) /!<FLVL[2:0] (FIFO Level Threshold) /
EricLew	0:d4e5ad7ad71c	6515	#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6516	#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6517	#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6518
EricLew	0:d4e5ad7ad71c	6519	/**************** Bit definition for SAI_xCLRFR register ****************/
EricLew	0:d4e5ad7ad71c	6520	#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /!<Clear Overrun underrun /
EricLew	0:d4e5ad7ad71c	6521	#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /!<Clear Mute detection /
EricLew	0:d4e5ad7ad71c	6522	#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /!<Clear Wrong Clock Configuration /
EricLew	0:d4e5ad7ad71c	6523	#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /!<Clear FIFO request /
EricLew	0:d4e5ad7ad71c	6524	#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /!<Clear Codec not ready /
EricLew	0:d4e5ad7ad71c	6525	#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /!<Clear Anticipated frame synchronization detection /
EricLew	0:d4e5ad7ad71c	6526	#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /!<Clear Late frame synchronization detection /
EricLew	0:d4e5ad7ad71c	6527
EricLew	0:d4e5ad7ad71c	6528	/**************** Bit definition for SAI_xDR register ****************/
EricLew	0:d4e5ad7ad71c	6529	#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
EricLew	0:d4e5ad7ad71c	6530
EricLew	0:d4e5ad7ad71c	6531	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6532	/* */
EricLew	0:d4e5ad7ad71c	6533	/* LCD Controller (LCD) */
EricLew	0:d4e5ad7ad71c	6534	/* */
EricLew	0:d4e5ad7ad71c	6535	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6536
EricLew	0:d4e5ad7ad71c	6537	/***************** Bit definition for LCD_CR register *******************/
EricLew	0:d4e5ad7ad71c	6538	#define LCD_CR_LCDEN ((uint32_t)0x00000001) /!< LCD Enable Bit /
EricLew	0:d4e5ad7ad71c	6539	#define LCD_CR_VSEL ((uint32_t)0x00000002) /!< Voltage source selector Bit /
EricLew	0:d4e5ad7ad71c	6540
EricLew	0:d4e5ad7ad71c	6541	#define LCD_CR_DUTY ((uint32_t)0x0000001C) /!< DUTY[2:0] bits (Duty selector) /
EricLew	0:d4e5ad7ad71c	6542	#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /!< Duty selector Bit 0 /
EricLew	0:d4e5ad7ad71c	6543	#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /!< Duty selector Bit 1 /
EricLew	0:d4e5ad7ad71c	6544	#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /!< Duty selector Bit 2 /
EricLew	0:d4e5ad7ad71c	6545
EricLew	0:d4e5ad7ad71c	6546	#define LCD_CR_BIAS ((uint32_t)0x00000060) /!< BIAS[1:0] bits (Bias selector) /
EricLew	0:d4e5ad7ad71c	6547	#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /!< Bias selector Bit 0 /
EricLew	0:d4e5ad7ad71c	6548	#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /!< Bias selector Bit 1 /
EricLew	0:d4e5ad7ad71c	6549
EricLew	0:d4e5ad7ad71c	6550	#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /!< Mux Segment Enable Bit /
EricLew	0:d4e5ad7ad71c	6551	#define LCD_CR_BUFEN ((uint32_t)0x00000100) /!< Voltage output buffer enable /
EricLew	0:d4e5ad7ad71c	6552
EricLew	0:d4e5ad7ad71c	6553	/***************** Bit definition for LCD_FCR register ******************/
EricLew	0:d4e5ad7ad71c	6554	#define LCD_FCR_HD ((uint32_t)0x00000001) /!< High Drive Enable Bit /
EricLew	0:d4e5ad7ad71c	6555	#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /!< Start of Frame Interrupt Enable Bit /
EricLew	0:d4e5ad7ad71c	6556	#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /!< Update Display Done Interrupt Enable Bit /
EricLew	0:d4e5ad7ad71c	6557
EricLew	0:d4e5ad7ad71c	6558	#define LCD_FCR_PON ((uint32_t)0x00000070) /!< PON[2:0] bits (Pulse ON Duration) /
EricLew	0:d4e5ad7ad71c	6559	#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6560	#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6561	#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	6562
EricLew	0:d4e5ad7ad71c	6563	#define LCD_FCR_DEAD ((uint32_t)0x00000380) /!< DEAD[2:0] bits (DEAD Time) /
EricLew	0:d4e5ad7ad71c	6564	#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6565	#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6566	#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	6567
EricLew	0:d4e5ad7ad71c	6568	#define LCD_FCR_CC ((uint32_t)0x00001C00) /!< CC[2:0] bits (Contrast Control) /
EricLew	0:d4e5ad7ad71c	6569	#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6570	#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6571	#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	6572
EricLew	0:d4e5ad7ad71c	6573	#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /!< BLINKF[2:0] bits (Blink Frequency) /
EricLew	0:d4e5ad7ad71c	6574	#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6575	#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6576	#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	6577
EricLew	0:d4e5ad7ad71c	6578	#define LCD_FCR_BLINK ((uint32_t)0x00030000) /!< BLINK[1:0] bits (Blink Enable) /
EricLew	0:d4e5ad7ad71c	6579	#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6580	#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6581
EricLew	0:d4e5ad7ad71c	6582	#define LCD_FCR_DIV ((uint32_t)0x003C0000) /!< DIV[3:0] bits (Divider) /
EricLew	0:d4e5ad7ad71c	6583	#define LCD_FCR_PS ((uint32_t)0x03C00000) /!< PS[3:0] bits (Prescaler) /
EricLew	0:d4e5ad7ad71c	6584
EricLew	0:d4e5ad7ad71c	6585	/***************** Bit definition for LCD_SR register *******************/
EricLew	0:d4e5ad7ad71c	6586	#define LCD_SR_ENS ((uint32_t)0x00000001) /!< LCD Enabled Bit /
EricLew	0:d4e5ad7ad71c	6587	#define LCD_SR_SOF ((uint32_t)0x00000002) /!< Start Of Frame Flag Bit /
EricLew	0:d4e5ad7ad71c	6588	#define LCD_SR_UDR ((uint32_t)0x00000004) /!< Update Display Request Bit /
EricLew	0:d4e5ad7ad71c	6589	#define LCD_SR_UDD ((uint32_t)0x00000008) /!< Update Display Done Flag Bit /
EricLew	0:d4e5ad7ad71c	6590	#define LCD_SR_RDY ((uint32_t)0x00000010) /!< Ready Flag Bit /
EricLew	0:d4e5ad7ad71c	6591	#define LCD_SR_FCRSR ((uint32_t)0x00000020) /!< LCD FCR Register Synchronization Flag Bit /
EricLew	0:d4e5ad7ad71c	6592
EricLew	0:d4e5ad7ad71c	6593	/***************** Bit definition for LCD_CLR register ******************/
EricLew	0:d4e5ad7ad71c	6594	#define LCD_CLR_SOFC ((uint32_t)0x00000002) /!< Start Of Frame Flag Clear Bit /
EricLew	0:d4e5ad7ad71c	6595	#define LCD_CLR_UDDC ((uint32_t)0x00000008) /!< Update Display Done Flag Clear Bit /
EricLew	0:d4e5ad7ad71c	6596
EricLew	0:d4e5ad7ad71c	6597	/***************** Bit definition for LCD_RAM register ******************/
EricLew	0:d4e5ad7ad71c	6598	#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /!< Segment Data Bits /
EricLew	0:d4e5ad7ad71c	6599
EricLew	0:d4e5ad7ad71c	6600	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6601	/* */
EricLew	0:d4e5ad7ad71c	6602	/* SDMMC Interface */
EricLew	0:d4e5ad7ad71c	6603	/* */
EricLew	0:d4e5ad7ad71c	6604	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6605	/**************** Bit definition for SDMMC_POWER register ****************/
EricLew	0:d4e5ad7ad71c	6606	#define SDMMC_POWER_PWRCTRL ((uint8_t)0x03) /!<PWRCTRL[1:0] bits (Power supply control bits) /
EricLew	0:d4e5ad7ad71c	6607	#define SDMMC_POWER_PWRCTRL_0 ((uint8_t)0x01) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6608	#define SDMMC_POWER_PWRCTRL_1 ((uint8_t)0x02) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6609
EricLew	0:d4e5ad7ad71c	6610	/**************** Bit definition for SDMMC_CLKCR register ****************/
EricLew	0:d4e5ad7ad71c	6611	#define SDMMC_CLKCR_CLKDIV ((uint16_t)0x00FF) /!<Clock divide factor /
EricLew	0:d4e5ad7ad71c	6612	#define SDMMC_CLKCR_CLKEN ((uint16_t)0x0100) /!<Clock enable bit /
EricLew	0:d4e5ad7ad71c	6613	#define SDMMC_CLKCR_PWRSAV ((uint16_t)0x0200) /!<Power saving configuration bit /
EricLew	0:d4e5ad7ad71c	6614	#define SDMMC_CLKCR_BYPASS ((uint16_t)0x0400) /!<Clock divider bypass enable bit /
EricLew	0:d4e5ad7ad71c	6615
EricLew	0:d4e5ad7ad71c	6616	#define SDMMC_CLKCR_WIDBUS ((uint16_t)0x1800) /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
EricLew	0:d4e5ad7ad71c	6617	#define SDMMC_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6618	#define SDMMC_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6619
EricLew	0:d4e5ad7ad71c	6620	#define SDMMC_CLKCR_NEGEDGE ((uint16_t)0x2000) /!<SDMMC_CK dephasing selection bit /
EricLew	0:d4e5ad7ad71c	6621	#define SDMMC_CLKCR_HWFC_EN ((uint16_t)0x4000) /!<HW Flow Control enable /
EricLew	0:d4e5ad7ad71c	6622
EricLew	0:d4e5ad7ad71c	6623	/***************** Bit definition for SDMMC_ARG register *****************/
EricLew	0:d4e5ad7ad71c	6624	#define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!<Command argument /
EricLew	0:d4e5ad7ad71c	6625
EricLew	0:d4e5ad7ad71c	6626	/***************** Bit definition for SDMMC_CMD register *****************/
EricLew	0:d4e5ad7ad71c	6627	#define SDMMC_CMD_CMDINDEX ((uint16_t)0x003F) /!<Command Index /
EricLew	0:d4e5ad7ad71c	6628
EricLew	0:d4e5ad7ad71c	6629	#define SDMMC_CMD_WAITRESP ((uint16_t)0x00C0) /!<WAITRESP[1:0] bits (Wait for response bits) /
EricLew	0:d4e5ad7ad71c	6630	#define SDMMC_CMD_WAITRESP_0 ((uint16_t)0x0040) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6631	#define SDMMC_CMD_WAITRESP_1 ((uint16_t)0x0080) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6632
EricLew	0:d4e5ad7ad71c	6633	#define SDMMC_CMD_WAITINT ((uint16_t)0x0100) /!<CPSM Waits for Interrupt Request /
EricLew	0:d4e5ad7ad71c	6634	#define SDMMC_CMD_WAITPEND ((uint16_t)0x0200) /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
EricLew	0:d4e5ad7ad71c	6635	#define SDMMC_CMD_CPSMEN ((uint16_t)0x0400) /!<Command path state machine (CPSM) Enable bit /
EricLew	0:d4e5ad7ad71c	6636	#define SDMMC_CMD_SDIOSUSPEND ((uint16_t)0x0800) /!<SD I/O suspend command /
EricLew	0:d4e5ad7ad71c	6637
EricLew	0:d4e5ad7ad71c	6638	/*************** Bit definition for SDMMC_RESPCMD register ***************/
EricLew	0:d4e5ad7ad71c	6639	#define SDMMC_RESPCMD_RESPCMD ((uint8_t)0x3F) /!<Response command index /
EricLew	0:d4e5ad7ad71c	6640
EricLew	0:d4e5ad7ad71c	6641	/**************** Bit definition for SDMMC_RESP0 register ****************/
EricLew	0:d4e5ad7ad71c	6642	#define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!<Card Status /
EricLew	0:d4e5ad7ad71c	6643
EricLew	0:d4e5ad7ad71c	6644	/**************** Bit definition for SDMMC_RESP1 register ****************/
EricLew	0:d4e5ad7ad71c	6645	#define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!<Card Status /
EricLew	0:d4e5ad7ad71c	6646
EricLew	0:d4e5ad7ad71c	6647	/**************** Bit definition for SDMMC_RESP2 register ****************/
EricLew	0:d4e5ad7ad71c	6648	#define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!<Card Status /
EricLew	0:d4e5ad7ad71c	6649
EricLew	0:d4e5ad7ad71c	6650	/**************** Bit definition for SDMMC_RESP3 register ****************/
EricLew	0:d4e5ad7ad71c	6651	#define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!<Card Status /
EricLew	0:d4e5ad7ad71c	6652
EricLew	0:d4e5ad7ad71c	6653	/**************** Bit definition for SDMMC_RESP4 register ****************/
EricLew	0:d4e5ad7ad71c	6654	#define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!<Card Status /
EricLew	0:d4e5ad7ad71c	6655
EricLew	0:d4e5ad7ad71c	6656	/**************** Bit definition for SDMMC_DTIMER register ***************/
EricLew	0:d4e5ad7ad71c	6657	#define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!<Data timeout period. /
EricLew	0:d4e5ad7ad71c	6658
EricLew	0:d4e5ad7ad71c	6659	/**************** Bit definition for SDMMC_DLEN register *****************/
EricLew	0:d4e5ad7ad71c	6660	#define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!<Data length value /
EricLew	0:d4e5ad7ad71c	6661
EricLew	0:d4e5ad7ad71c	6662	/**************** Bit definition for SDMMC_DCTRL register ****************/
EricLew	0:d4e5ad7ad71c	6663	#define SDMMC_DCTRL_DTEN ((uint16_t)0x0001) /!<Data transfer enabled bit /
EricLew	0:d4e5ad7ad71c	6664	#define SDMMC_DCTRL_DTDIR ((uint16_t)0x0002) /!<Data transfer direction selection /
EricLew	0:d4e5ad7ad71c	6665	#define SDMMC_DCTRL_DTMODE ((uint16_t)0x0004) /!<Data transfer mode selection /
EricLew	0:d4e5ad7ad71c	6666	#define SDMMC_DCTRL_DMAEN ((uint16_t)0x0008) /!<DMA enabled bit /
EricLew	0:d4e5ad7ad71c	6667
EricLew	0:d4e5ad7ad71c	6668	#define SDMMC_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /!<DBLOCKSIZE[3:0] bits (Data block size) /
EricLew	0:d4e5ad7ad71c	6669	#define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6670	#define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6671	#define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6672	#define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	6673
EricLew	0:d4e5ad7ad71c	6674	#define SDMMC_DCTRL_RWSTART ((uint16_t)0x0100) /!<Read wait start /
EricLew	0:d4e5ad7ad71c	6675	#define SDMMC_DCTRL_RWSTOP ((uint16_t)0x0200) /!<Read wait stop /
EricLew	0:d4e5ad7ad71c	6676	#define SDMMC_DCTRL_RWMOD ((uint16_t)0x0400) /!<Read wait mode /
EricLew	0:d4e5ad7ad71c	6677	#define SDMMC_DCTRL_SDIOEN ((uint16_t)0x0800) /!<SD I/O enable functions /
EricLew	0:d4e5ad7ad71c	6678
EricLew	0:d4e5ad7ad71c	6679	/**************** Bit definition for SDMMC_DCOUNT register ***************/
EricLew	0:d4e5ad7ad71c	6680	#define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!<Data count value /
EricLew	0:d4e5ad7ad71c	6681
EricLew	0:d4e5ad7ad71c	6682	/**************** Bit definition for SDMMC_STA register ******************/
EricLew	0:d4e5ad7ad71c	6683	#define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /!<Command response received (CRC check failed) /
EricLew	0:d4e5ad7ad71c	6684	#define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /!<Data block sent/received (CRC check failed) /
EricLew	0:d4e5ad7ad71c	6685	#define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /!<Command response timeout /
EricLew	0:d4e5ad7ad71c	6686	#define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /!<Data timeout /
EricLew	0:d4e5ad7ad71c	6687	#define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /!<Transmit FIFO underrun error /
EricLew	0:d4e5ad7ad71c	6688	#define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /!<Received FIFO overrun error /
EricLew	0:d4e5ad7ad71c	6689	#define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /!<Command response received (CRC check passed) /
EricLew	0:d4e5ad7ad71c	6690	#define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /!<Command sent (no response required) /
EricLew	0:d4e5ad7ad71c	6691	#define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /!<Data end (data counter, SDIDCOUNT, is zero) /
EricLew	0:d4e5ad7ad71c	6692	#define SDMMC_STA_STBITERR ((uint32_t)0x00000200) /!<Start bit not detected on all data signals in wide bus mode /
EricLew	0:d4e5ad7ad71c	6693	#define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /!<Data block sent/received (CRC check passed) /
EricLew	0:d4e5ad7ad71c	6694	#define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /!<Command transfer in progress /
EricLew	0:d4e5ad7ad71c	6695	#define SDMMC_STA_TXACT ((uint32_t)0x00001000) /!<Data transmit in progress /
EricLew	0:d4e5ad7ad71c	6696	#define SDMMC_STA_RXACT ((uint32_t)0x00002000) /!<Data receive in progress /
EricLew	0:d4e5ad7ad71c	6697	#define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
EricLew	0:d4e5ad7ad71c	6698	#define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
EricLew	0:d4e5ad7ad71c	6699	#define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /!<Transmit FIFO full /
EricLew	0:d4e5ad7ad71c	6700	#define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /!<Receive FIFO full /
EricLew	0:d4e5ad7ad71c	6701	#define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /!<Transmit FIFO empty /
EricLew	0:d4e5ad7ad71c	6702	#define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /!<Receive FIFO empty /
EricLew	0:d4e5ad7ad71c	6703	#define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /!<Data available in transmit FIFO /
EricLew	0:d4e5ad7ad71c	6704	#define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /!<Data available in receive FIFO /
EricLew	0:d4e5ad7ad71c	6705	#define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /!<SDIO interrupt received /
EricLew	0:d4e5ad7ad71c	6706
EricLew	0:d4e5ad7ad71c	6707	/***************** Bit definition for SDMMC_ICR register *****************/
EricLew	0:d4e5ad7ad71c	6708	#define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /!<CCRCFAIL flag clear bit /
EricLew	0:d4e5ad7ad71c	6709	#define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /!<DCRCFAIL flag clear bit /
EricLew	0:d4e5ad7ad71c	6710	#define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!<CTIMEOUT flag clear bit /
EricLew	0:d4e5ad7ad71c	6711	#define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!<DTIMEOUT flag clear bit /
EricLew	0:d4e5ad7ad71c	6712	#define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /!<TXUNDERR flag clear bit /
EricLew	0:d4e5ad7ad71c	6713	#define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /!<RXOVERR flag clear bit /
EricLew	0:d4e5ad7ad71c	6714	#define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /!<CMDREND flag clear bit /
EricLew	0:d4e5ad7ad71c	6715	#define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /!<CMDSENT flag clear bit /
EricLew	0:d4e5ad7ad71c	6716	#define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /!<DATAEND flag clear bit /
EricLew	0:d4e5ad7ad71c	6717	#define SDMMC_ICR_STBITERRC ((uint32_t)0x00000200) /!<STBITERR flag clear bit /
EricLew	0:d4e5ad7ad71c	6718	#define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /!<DBCKEND flag clear bit /
EricLew	0:d4e5ad7ad71c	6719	#define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /!<SDIOIT flag clear bit /
EricLew	0:d4e5ad7ad71c	6720
EricLew	0:d4e5ad7ad71c	6721	/**************** Bit definition for SDMMC_MASK register *****************/
EricLew	0:d4e5ad7ad71c	6722	#define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!<Command CRC Fail Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6723	#define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!<Data CRC Fail Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6724	#define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!<Command TimeOut Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6725	#define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!<Data TimeOut Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6726	#define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!<Tx FIFO UnderRun Error Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6727	#define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /!<Rx FIFO OverRun Error Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6728	#define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /!<Command Response Received Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6729	#define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /!<Command Sent Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6730	#define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /!<Data End Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6731	#define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /!<Data Block End Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6732	#define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /!<CCommand Acting Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6733	#define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /!<Data Transmit Acting Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6734	#define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /!<Data receive acting interrupt enabled /
EricLew	0:d4e5ad7ad71c	6735	#define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!<Tx FIFO Half Empty interrupt Enable /
EricLew	0:d4e5ad7ad71c	6736	#define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!<Rx FIFO Half Full interrupt Enable /
EricLew	0:d4e5ad7ad71c	6737	#define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!<Tx FIFO Full interrupt Enable /
EricLew	0:d4e5ad7ad71c	6738	#define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!<Rx FIFO Full interrupt Enable /
EricLew	0:d4e5ad7ad71c	6739	#define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!<Tx FIFO Empty interrupt Enable /
EricLew	0:d4e5ad7ad71c	6740	#define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!<Rx FIFO Empty interrupt Enable /
EricLew	0:d4e5ad7ad71c	6741	#define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /!<Data available in Tx FIFO interrupt Enable /
EricLew	0:d4e5ad7ad71c	6742	#define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /!<Data available in Rx FIFO interrupt Enable /
EricLew	0:d4e5ad7ad71c	6743	#define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /!<SDIO Mode Interrupt Received interrupt Enable /
EricLew	0:d4e5ad7ad71c	6744
EricLew	0:d4e5ad7ad71c	6745	/*************** Bit definition for SDMMC_FIFOCNT register ***************/
EricLew	0:d4e5ad7ad71c	6746	#define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!<Remaining number of words to be written to or read from the FIFO /
EricLew	0:d4e5ad7ad71c	6747
EricLew	0:d4e5ad7ad71c	6748	/**************** Bit definition for SDMMC_FIFO register *****************/
EricLew	0:d4e5ad7ad71c	6749	#define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!<Receive and transmit FIFO data /
EricLew	0:d4e5ad7ad71c	6750
EricLew	0:d4e5ad7ad71c	6751	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6752	/* */
EricLew	0:d4e5ad7ad71c	6753	/* Serial Peripheral Interface (SPI) */
EricLew	0:d4e5ad7ad71c	6754	/* */
EricLew	0:d4e5ad7ad71c	6755	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6756	/***************** Bit definition for SPI_CR1 register ******************/
EricLew	0:d4e5ad7ad71c	6757	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!<Clock Phase /
EricLew	0:d4e5ad7ad71c	6758	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!<Clock Polarity /
EricLew	0:d4e5ad7ad71c	6759	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!<Master Selection /
EricLew	0:d4e5ad7ad71c	6760
EricLew	0:d4e5ad7ad71c	6761	#define SPI_CR1_BR ((uint32_t)0x00000038) /!<BR[2:0] bits (Baud Rate Control) /
EricLew	0:d4e5ad7ad71c	6762	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	6763	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	6764	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	6765
EricLew	0:d4e5ad7ad71c	6766	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!<SPI Enable /
EricLew	0:d4e5ad7ad71c	6767	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!<Frame Format /
EricLew	0:d4e5ad7ad71c	6768	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!<Internal slave select /
EricLew	0:d4e5ad7ad71c	6769	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!<Software slave management /
EricLew	0:d4e5ad7ad71c	6770	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!<Receive only /
EricLew	0:d4e5ad7ad71c	6771	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
EricLew	0:d4e5ad7ad71c	6772	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!<Transmit CRC next /
EricLew	0:d4e5ad7ad71c	6773	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!<Hardware CRC calculation enable /
EricLew	0:d4e5ad7ad71c	6774	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!<Output enable in bidirectional mode /
EricLew	0:d4e5ad7ad71c	6775	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!<Bidirectional data mode enable /
EricLew	0:d4e5ad7ad71c	6776
EricLew	0:d4e5ad7ad71c	6777	/***************** Bit definition for SPI_CR2 register ******************/
EricLew	0:d4e5ad7ad71c	6778	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
EricLew	0:d4e5ad7ad71c	6779	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
EricLew	0:d4e5ad7ad71c	6780	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
EricLew	0:d4e5ad7ad71c	6781	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
EricLew	0:d4e5ad7ad71c	6782	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
EricLew	0:d4e5ad7ad71c	6783	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6784	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6785	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6786	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
EricLew	0:d4e5ad7ad71c	6787	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6788	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6789	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	6790	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
EricLew	0:d4e5ad7ad71c	6791	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
EricLew	0:d4e5ad7ad71c	6792	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
EricLew	0:d4e5ad7ad71c	6793	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
EricLew	0:d4e5ad7ad71c	6794
EricLew	0:d4e5ad7ad71c	6795	/****************** Bit definition for SPI_SR register ******************/
EricLew	0:d4e5ad7ad71c	6796	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
EricLew	0:d4e5ad7ad71c	6797	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
EricLew	0:d4e5ad7ad71c	6798	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
EricLew	0:d4e5ad7ad71c	6799	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
EricLew	0:d4e5ad7ad71c	6800	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
EricLew	0:d4e5ad7ad71c	6801	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
EricLew	0:d4e5ad7ad71c	6802	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
EricLew	0:d4e5ad7ad71c	6803	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
EricLew	0:d4e5ad7ad71c	6804	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
EricLew	0:d4e5ad7ad71c	6805	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
EricLew	0:d4e5ad7ad71c	6806	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6807	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6808	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
EricLew	0:d4e5ad7ad71c	6809	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6810	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6811
EricLew	0:d4e5ad7ad71c	6812	/****************** Bit definition for SPI_DR register ******************/
EricLew	0:d4e5ad7ad71c	6813	#define SPI_DR_DR ((uint32_t)0x0000FFFF) /!<Data Register /
EricLew	0:d4e5ad7ad71c	6814
EricLew	0:d4e5ad7ad71c	6815	/***************** Bit definition for SPI_CRCPR register ****************/
EricLew	0:d4e5ad7ad71c	6816	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /!<CRC polynomial register /
EricLew	0:d4e5ad7ad71c	6817
EricLew	0:d4e5ad7ad71c	6818	/**************** Bit definition for SPI_RXCRCR register ****************/
EricLew	0:d4e5ad7ad71c	6819	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /!<Rx CRC Register /
EricLew	0:d4e5ad7ad71c	6820
EricLew	0:d4e5ad7ad71c	6821	/**************** Bit definition for SPI_TXCRCR register ****************/
EricLew	0:d4e5ad7ad71c	6822	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /!<Tx CRC Register /
EricLew	0:d4e5ad7ad71c	6823
EricLew	0:d4e5ad7ad71c	6824	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6825	/* */
EricLew	0:d4e5ad7ad71c	6826	/* QUADSPI */
EricLew	0:d4e5ad7ad71c	6827	/* */
EricLew	0:d4e5ad7ad71c	6828	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6829	/*************** Bit definition for QUADSPI_CR register *****************/
EricLew	0:d4e5ad7ad71c	6830	#define QUADSPI_CR_EN ((uint32_t)0x00000001) /!< Enable /
EricLew	0:d4e5ad7ad71c	6831	#define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /!< Abort request /
EricLew	0:d4e5ad7ad71c	6832	#define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /!< DMA Enable /
EricLew	0:d4e5ad7ad71c	6833	#define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /!< Timeout Counter Enable /
EricLew	0:d4e5ad7ad71c	6834	#define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /!< Sample Shift /
EricLew	0:d4e5ad7ad71c	6835	#define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /!< FTHRES[3:0] FIFO Level /
EricLew	0:d4e5ad7ad71c	6836	#define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /!< Transfer Error Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6837	#define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /!< Transfer Complete Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6838	#define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /!< FIFO Threshold Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6839	#define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /!< Status Match Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6840	#define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /!< TimeOut Interrupt Enable /
EricLew	0:d4e5ad7ad71c	6841	#define QUADSPI_CR_APMS ((uint32_t)0x00400000) /!< Automatic Polling Mode Stop /
EricLew	0:d4e5ad7ad71c	6842	#define QUADSPI_CR_PMM ((uint32_t)0x00800000) /!< Polling Match Mode /
EricLew	0:d4e5ad7ad71c	6843	#define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /!< PRESCALER[7:0] Clock prescaler /
EricLew	0:d4e5ad7ad71c	6844
EricLew	0:d4e5ad7ad71c	6845	/*************** Bit definition for QUADSPI_DCR register ****************/
EricLew	0:d4e5ad7ad71c	6846	#define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /!< Mode 0 / Mode 3 /
EricLew	0:d4e5ad7ad71c	6847	#define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /!< CSHT[2:0]: ChipSelect High Time /
EricLew	0:d4e5ad7ad71c	6848	#define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6849	#define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6850	#define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	6851	#define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /!< FSIZE[4:0]: Flash Size /
EricLew	0:d4e5ad7ad71c	6852
EricLew	0:d4e5ad7ad71c	6853	/**************** Bit definition for QUADSPI_SR register *****************/
EricLew	0:d4e5ad7ad71c	6854	#define QUADSPI_SR_TEF ((uint32_t)0x00000001) /!< Transfer Error Flag /
EricLew	0:d4e5ad7ad71c	6855	#define QUADSPI_SR_TCF ((uint32_t)0x00000002) /!< Transfer Complete Flag /
EricLew	0:d4e5ad7ad71c	6856	#define QUADSPI_SR_FTF ((uint32_t)0x00000004) /!< FIFO Threshlod Flag /
EricLew	0:d4e5ad7ad71c	6857	#define QUADSPI_SR_SMF ((uint32_t)0x00000008) /!< Status Match Flag /
EricLew	0:d4e5ad7ad71c	6858	#define QUADSPI_SR_TOF ((uint32_t)0x00000010) /!< Timeout Flag /
EricLew	0:d4e5ad7ad71c	6859	#define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /!< Busy /
EricLew	0:d4e5ad7ad71c	6860	#define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /!< FIFO Threshlod Flag /
EricLew	0:d4e5ad7ad71c	6861
EricLew	0:d4e5ad7ad71c	6862	/**************** Bit definition for QUADSPI_FCR register ****************/
EricLew	0:d4e5ad7ad71c	6863	#define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /!< Clear Transfer Error Flag /
EricLew	0:d4e5ad7ad71c	6864	#define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /!< Clear Transfer Complete Flag /
EricLew	0:d4e5ad7ad71c	6865	#define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /!< Clear Status Match Flag /
EricLew	0:d4e5ad7ad71c	6866	#define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /!< Clear Timeout Flag /
EricLew	0:d4e5ad7ad71c	6867
EricLew	0:d4e5ad7ad71c	6868	/**************** Bit definition for QUADSPI_DLR register ****************/
EricLew	0:d4e5ad7ad71c	6869	#define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /!< DL[31:0]: Data Length /
EricLew	0:d4e5ad7ad71c	6870
EricLew	0:d4e5ad7ad71c	6871	/**************** Bit definition for QUADSPI_CCR register ****************/
EricLew	0:d4e5ad7ad71c	6872	#define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /!< INSTRUCTION[7:0]: Instruction /
EricLew	0:d4e5ad7ad71c	6873	#define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /!< IMODE[1:0]: Instruction Mode /
EricLew	0:d4e5ad7ad71c	6874	#define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6875	#define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6876	#define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /!< ADMODE[1:0]: Address Mode /
EricLew	0:d4e5ad7ad71c	6877	#define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6878	#define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6879	#define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /!< ADSIZE[1:0]: Address Size /
EricLew	0:d4e5ad7ad71c	6880	#define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6881	#define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6882	#define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /!< ABMODE[1:0]: Alternate Bytes Mode /
EricLew	0:d4e5ad7ad71c	6883	#define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6884	#define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6885	#define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /!< ABSIZE[1:0]: Instruction Mode /
EricLew	0:d4e5ad7ad71c	6886	#define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6887	#define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6888	#define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /!< DCYC[4:0]: Dummy Cycles /
EricLew	0:d4e5ad7ad71c	6889	#define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /!< DMODE[1:0]: Data Mode /
EricLew	0:d4e5ad7ad71c	6890	#define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6891	#define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6892	#define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /!< FMODE[1:0]: Functional Mode /
EricLew	0:d4e5ad7ad71c	6893	#define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	6894	#define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	6895	#define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /!< SIOO: Send Instruction Only Once Mode /
EricLew	0:d4e5ad7ad71c	6896	#define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /!< DDRM: Double Data Rate Mode /
EricLew	0:d4e5ad7ad71c	6897
EricLew	0:d4e5ad7ad71c	6898	/**************** Bit definition for QUADSPI_AR register *****************/
EricLew	0:d4e5ad7ad71c	6899	#define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< ADDRESS[31:0]: Address /
EricLew	0:d4e5ad7ad71c	6900
EricLew	0:d4e5ad7ad71c	6901	/**************** Bit definition for QUADSPI_ABR register ****************/
EricLew	0:d4e5ad7ad71c	6902	#define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /!< ALTERNATE[31:0]: Alternate Bytes /
EricLew	0:d4e5ad7ad71c	6903
EricLew	0:d4e5ad7ad71c	6904	/**************** Bit definition for QUADSPI_DR register *****************/
EricLew	0:d4e5ad7ad71c	6905	#define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /!< DATA[31:0]: Data /
EricLew	0:d4e5ad7ad71c	6906
EricLew	0:d4e5ad7ad71c	6907	/**************** Bit definition for QUADSPI_PSMKR register **************/
EricLew	0:d4e5ad7ad71c	6908	#define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /!< MASK[31:0]: Status Mask /
EricLew	0:d4e5ad7ad71c	6909
EricLew	0:d4e5ad7ad71c	6910	/**************** Bit definition for QUADSPI_PSMAR register **************/
EricLew	0:d4e5ad7ad71c	6911	#define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /!< MATCH[31:0]: Status Match /
EricLew	0:d4e5ad7ad71c	6912
EricLew	0:d4e5ad7ad71c	6913	/**************** Bit definition for QUADSPI_PIR register ***************/
EricLew	0:d4e5ad7ad71c	6914	#define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /!< INTERVAL[15:0]: Polling Interval /
EricLew	0:d4e5ad7ad71c	6915
EricLew	0:d4e5ad7ad71c	6916	/**************** Bit definition for QUADSPI_LPTR register ***************/
EricLew	0:d4e5ad7ad71c	6917	#define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /!< TIMEOUT[15:0]: Timeout period /
EricLew	0:d4e5ad7ad71c	6918
EricLew	0:d4e5ad7ad71c	6919	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6920	/* */
EricLew	0:d4e5ad7ad71c	6921	/* SYSCFG */
EricLew	0:d4e5ad7ad71c	6922	/* */
EricLew	0:d4e5ad7ad71c	6923	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	6924	/**************** Bit definition for SYSCFG_MEMRMP register *************/
EricLew	0:d4e5ad7ad71c	6925	#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /!< SYSCFG_Memory Remap Config /
EricLew	0:d4e5ad7ad71c	6926	#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	6927	#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	6928	#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	6929
EricLew	0:d4e5ad7ad71c	6930	#define SYSCFG_MEMRMP_FB_MODE ((uint32_t)0x00000100) /!< Flash Bank mode selection /
EricLew	0:d4e5ad7ad71c	6931
EricLew	0:d4e5ad7ad71c	6932
EricLew	0:d4e5ad7ad71c	6933	/**************** Bit definition for SYSCFG_CFGR1 register ****************/
EricLew	0:d4e5ad7ad71c	6934	#define SYSCFG_CFGR1_FWDIS ((uint32_t)0x00000001) /!< FIREWALL access enable/
EricLew	0:d4e5ad7ad71c	6935	#define SYSCFG_CFGR1_BOOSTEN ((uint32_t)0x00000100) /!< I/O analog switch voltage booster enable /
EricLew	0:d4e5ad7ad71c	6936	#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6937	#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6938	#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6939	#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6940	#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /!< I2C1 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6941	#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /!< I2C2 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6942	#define SYSCFG_CFGR1_I2C3_FMP ((uint32_t)0x00400000) /!< I2C3 Fast mode plus /
EricLew	0:d4e5ad7ad71c	6943	#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /!< Invalid operation Interrupt enable /
EricLew	0:d4e5ad7ad71c	6944	#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /!< Divide-by-zero Interrupt enable /
EricLew	0:d4e5ad7ad71c	6945	#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /!< Underflow Interrupt enable /
EricLew	0:d4e5ad7ad71c	6946	#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /!< Overflow Interrupt enable /
EricLew	0:d4e5ad7ad71c	6947	#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /!< Input denormal Interrupt enable /
EricLew	0:d4e5ad7ad71c	6948	#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /!< Inexact Interrupt enable (interrupt disabled at reset) /
EricLew	0:d4e5ad7ad71c	6949
EricLew	0:d4e5ad7ad71c	6950	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
EricLew	0:d4e5ad7ad71c	6951	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x00000007) /!<EXTI 0 configuration /
EricLew	0:d4e5ad7ad71c	6952	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00000070) /!<EXTI 1 configuration /
EricLew	0:d4e5ad7ad71c	6953	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000700) /!<EXTI 2 configuration /
EricLew	0:d4e5ad7ad71c	6954	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x00007000) /!<EXTI 3 configuration /
EricLew	0:d4e5ad7ad71c	6955	/**
EricLew	0:d4e5ad7ad71c	6956	* @brief EXTI0 configuration
EricLew	0:d4e5ad7ad71c	6957	*/
EricLew	0:d4e5ad7ad71c	6958	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /!<PA[0] pin /
EricLew	0:d4e5ad7ad71c	6959	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /!<PB[0] pin /
EricLew	0:d4e5ad7ad71c	6960	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /!<PC[0] pin /
EricLew	0:d4e5ad7ad71c	6961	#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /!<PD[0] pin /
EricLew	0:d4e5ad7ad71c	6962	#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /!<PE[0] pin /
EricLew	0:d4e5ad7ad71c	6963	#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /!<PF[0] pin /
EricLew	0:d4e5ad7ad71c	6964	#define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /!<PG[0] pin /
EricLew	0:d4e5ad7ad71c	6965	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /!<PH[0] pin /
EricLew	0:d4e5ad7ad71c	6966
EricLew	0:d4e5ad7ad71c	6967
EricLew	0:d4e5ad7ad71c	6968	/**
EricLew	0:d4e5ad7ad71c	6969	* @brief EXTI1 configuration
EricLew	0:d4e5ad7ad71c	6970	*/
EricLew	0:d4e5ad7ad71c	6971	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /!<PA[1] pin /
EricLew	0:d4e5ad7ad71c	6972	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /!<PB[1] pin /
EricLew	0:d4e5ad7ad71c	6973	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /!<PC[1] pin /
EricLew	0:d4e5ad7ad71c	6974	#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /!<PD[1] pin /
EricLew	0:d4e5ad7ad71c	6975	#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /!<PE[1] pin /
EricLew	0:d4e5ad7ad71c	6976	#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /!<PF[1] pin /
EricLew	0:d4e5ad7ad71c	6977	#define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /!<PG[1] pin /
EricLew	0:d4e5ad7ad71c	6978	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /!<PH[1] pin /
EricLew	0:d4e5ad7ad71c	6979
EricLew	0:d4e5ad7ad71c	6980	/**
EricLew	0:d4e5ad7ad71c	6981	* @brief EXTI2 configuration
EricLew	0:d4e5ad7ad71c	6982	*/
EricLew	0:d4e5ad7ad71c	6983	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /!<PA[2] pin /
EricLew	0:d4e5ad7ad71c	6984	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /!<PB[2] pin /
EricLew	0:d4e5ad7ad71c	6985	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /!<PC[2] pin /
EricLew	0:d4e5ad7ad71c	6986	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /!<PD[2] pin /
EricLew	0:d4e5ad7ad71c	6987	#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /!<PE[2] pin /
EricLew	0:d4e5ad7ad71c	6988	#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /!<PF[2] pin /
EricLew	0:d4e5ad7ad71c	6989	#define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /!<PG[2] pin /
EricLew	0:d4e5ad7ad71c	6990
EricLew	0:d4e5ad7ad71c	6991
EricLew	0:d4e5ad7ad71c	6992	/**
EricLew	0:d4e5ad7ad71c	6993	* @brief EXTI3 configuration
EricLew	0:d4e5ad7ad71c	6994	*/
EricLew	0:d4e5ad7ad71c	6995	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /!<PA[3] pin /
EricLew	0:d4e5ad7ad71c	6996	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /!<PB[3] pin /
EricLew	0:d4e5ad7ad71c	6997	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /!<PC[3] pin /
EricLew	0:d4e5ad7ad71c	6998	#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /!<PD[3] pin /
EricLew	0:d4e5ad7ad71c	6999	#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /!<PE[3] pin /
EricLew	0:d4e5ad7ad71c	7000	#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /!<PF[3] pin /
EricLew	0:d4e5ad7ad71c	7001	#define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /!<PG[3] pin /
EricLew	0:d4e5ad7ad71c	7002
EricLew	0:d4e5ad7ad71c	7003
EricLew	0:d4e5ad7ad71c	7004	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
EricLew	0:d4e5ad7ad71c	7005	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x00000007) /!<EXTI 4 configuration /
EricLew	0:d4e5ad7ad71c	7006	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00000070) /!<EXTI 5 configuration /
EricLew	0:d4e5ad7ad71c	7007	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000700) /!<EXTI 6 configuration /
EricLew	0:d4e5ad7ad71c	7008	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x00007000) /!<EXTI 7 configuration /
EricLew	0:d4e5ad7ad71c	7009	/**
EricLew	0:d4e5ad7ad71c	7010	* @brief EXTI4 configuration
EricLew	0:d4e5ad7ad71c	7011	*/
EricLew	0:d4e5ad7ad71c	7012	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /!<PA[4] pin /
EricLew	0:d4e5ad7ad71c	7013	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /!<PB[4] pin /
EricLew	0:d4e5ad7ad71c	7014	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /!<PC[4] pin /
EricLew	0:d4e5ad7ad71c	7015	#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /!<PD[4] pin /
EricLew	0:d4e5ad7ad71c	7016	#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /!<PE[4] pin /
EricLew	0:d4e5ad7ad71c	7017	#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /!<PF[4] pin /
EricLew	0:d4e5ad7ad71c	7018	#define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /!<PG[4] pin /
EricLew	0:d4e5ad7ad71c	7019
EricLew	0:d4e5ad7ad71c	7020	/**
EricLew	0:d4e5ad7ad71c	7021	* @brief EXTI5 configuration
EricLew	0:d4e5ad7ad71c	7022	*/
EricLew	0:d4e5ad7ad71c	7023	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /!<PA[5] pin /
EricLew	0:d4e5ad7ad71c	7024	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /!<PB[5] pin /
EricLew	0:d4e5ad7ad71c	7025	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /!<PC[5] pin /
EricLew	0:d4e5ad7ad71c	7026	#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /!<PD[5] pin /
EricLew	0:d4e5ad7ad71c	7027	#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /!<PE[5] pin /
EricLew	0:d4e5ad7ad71c	7028	#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /!<PF[5] pin /
EricLew	0:d4e5ad7ad71c	7029	#define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /!<PG[5] pin /
EricLew	0:d4e5ad7ad71c	7030
EricLew	0:d4e5ad7ad71c	7031	/**
EricLew	0:d4e5ad7ad71c	7032	* @brief EXTI6 configuration
EricLew	0:d4e5ad7ad71c	7033	*/
EricLew	0:d4e5ad7ad71c	7034	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /!<PA[6] pin /
EricLew	0:d4e5ad7ad71c	7035	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /!<PB[6] pin /
EricLew	0:d4e5ad7ad71c	7036	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /!<PC[6] pin /
EricLew	0:d4e5ad7ad71c	7037	#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /!<PD[6] pin /
EricLew	0:d4e5ad7ad71c	7038	#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /!<PE[6] pin /
EricLew	0:d4e5ad7ad71c	7039	#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /!<PF[6] pin /
EricLew	0:d4e5ad7ad71c	7040	#define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /!<PG[6] pin /
EricLew	0:d4e5ad7ad71c	7041
EricLew	0:d4e5ad7ad71c	7042	/**
EricLew	0:d4e5ad7ad71c	7043	* @brief EXTI7 configuration
EricLew	0:d4e5ad7ad71c	7044	*/
EricLew	0:d4e5ad7ad71c	7045	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /!<PA[7] pin /
EricLew	0:d4e5ad7ad71c	7046	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /!<PB[7] pin /
EricLew	0:d4e5ad7ad71c	7047	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /!<PC[7] pin /
EricLew	0:d4e5ad7ad71c	7048	#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /!<PD[7] pin /
EricLew	0:d4e5ad7ad71c	7049	#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /!<PE[7] pin /
EricLew	0:d4e5ad7ad71c	7050	#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /!<PF[7] pin /
EricLew	0:d4e5ad7ad71c	7051	#define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /!<PG[7] pin /
EricLew	0:d4e5ad7ad71c	7052
EricLew	0:d4e5ad7ad71c	7053
EricLew	0:d4e5ad7ad71c	7054	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
EricLew	0:d4e5ad7ad71c	7055	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x00000007) /!<EXTI 8 configuration /
EricLew	0:d4e5ad7ad71c	7056	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00000070) /!<EXTI 9 configuration /
EricLew	0:d4e5ad7ad71c	7057	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000700) /!<EXTI 10 configuration /
EricLew	0:d4e5ad7ad71c	7058	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x00007000) /!<EXTI 11 configuration /
EricLew	0:d4e5ad7ad71c	7059
EricLew	0:d4e5ad7ad71c	7060	/**
EricLew	0:d4e5ad7ad71c	7061	* @brief EXTI8 configuration
EricLew	0:d4e5ad7ad71c	7062	*/
EricLew	0:d4e5ad7ad71c	7063	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /!<PA[8] pin /
EricLew	0:d4e5ad7ad71c	7064	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /!<PB[8] pin /
EricLew	0:d4e5ad7ad71c	7065	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /!<PC[8] pin /
EricLew	0:d4e5ad7ad71c	7066	#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /!<PD[8] pin /
EricLew	0:d4e5ad7ad71c	7067	#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /!<PE[8] pin /
EricLew	0:d4e5ad7ad71c	7068	#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /!<PF[8] pin /
EricLew	0:d4e5ad7ad71c	7069	#define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /!<PG[8] pin /
EricLew	0:d4e5ad7ad71c	7070
EricLew	0:d4e5ad7ad71c	7071	/**
EricLew	0:d4e5ad7ad71c	7072	* @brief EXTI9 configuration
EricLew	0:d4e5ad7ad71c	7073	*/
EricLew	0:d4e5ad7ad71c	7074	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /!<PA[9] pin /
EricLew	0:d4e5ad7ad71c	7075	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /!<PB[9] pin /
EricLew	0:d4e5ad7ad71c	7076	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /!<PC[9] pin /
EricLew	0:d4e5ad7ad71c	7077	#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /!<PD[9] pin /
EricLew	0:d4e5ad7ad71c	7078	#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /!<PE[9] pin /
EricLew	0:d4e5ad7ad71c	7079	#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /!<PF[9] pin /
EricLew	0:d4e5ad7ad71c	7080	#define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /!<PG[9] pin /
EricLew	0:d4e5ad7ad71c	7081
EricLew	0:d4e5ad7ad71c	7082	/**
EricLew	0:d4e5ad7ad71c	7083	* @brief EXTI10 configuration
EricLew	0:d4e5ad7ad71c	7084	*/
EricLew	0:d4e5ad7ad71c	7085	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /!<PA[10] pin /
EricLew	0:d4e5ad7ad71c	7086	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /!<PB[10] pin /
EricLew	0:d4e5ad7ad71c	7087	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /!<PC[10] pin /
EricLew	0:d4e5ad7ad71c	7088	#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /!<PD[10] pin /
EricLew	0:d4e5ad7ad71c	7089	#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /!<PE[10] pin /
EricLew	0:d4e5ad7ad71c	7090	#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /!<PF[10] pin /
EricLew	0:d4e5ad7ad71c	7091	#define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /!<PG[10] pin /
EricLew	0:d4e5ad7ad71c	7092
EricLew	0:d4e5ad7ad71c	7093	/**
EricLew	0:d4e5ad7ad71c	7094	* @brief EXTI11 configuration
EricLew	0:d4e5ad7ad71c	7095	*/
EricLew	0:d4e5ad7ad71c	7096	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /!<PA[11] pin /
EricLew	0:d4e5ad7ad71c	7097	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /!<PB[11] pin /
EricLew	0:d4e5ad7ad71c	7098	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /!<PC[11] pin /
EricLew	0:d4e5ad7ad71c	7099	#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /!<PD[11] pin /
EricLew	0:d4e5ad7ad71c	7100	#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /!<PE[11] pin /
EricLew	0:d4e5ad7ad71c	7101	#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /!<PF[11] pin /
EricLew	0:d4e5ad7ad71c	7102	#define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /!<PG[11] pin /
EricLew	0:d4e5ad7ad71c	7103
EricLew	0:d4e5ad7ad71c	7104	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
EricLew	0:d4e5ad7ad71c	7105	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x00000007) /!<EXTI 12 configuration /
EricLew	0:d4e5ad7ad71c	7106	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00000070) /!<EXTI 13 configuration /
EricLew	0:d4e5ad7ad71c	7107	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000700) /!<EXTI 14 configuration /
EricLew	0:d4e5ad7ad71c	7108	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x00007000) /!<EXTI 15 configuration /
EricLew	0:d4e5ad7ad71c	7109	/**
EricLew	0:d4e5ad7ad71c	7110	* @brief EXTI12 configuration
EricLew	0:d4e5ad7ad71c	7111	*/
EricLew	0:d4e5ad7ad71c	7112	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /!<PA[12] pin /
EricLew	0:d4e5ad7ad71c	7113	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /!<PB[12] pin /
EricLew	0:d4e5ad7ad71c	7114	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /!<PC[12] pin /
EricLew	0:d4e5ad7ad71c	7115	#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /!<PD[12] pin /
EricLew	0:d4e5ad7ad71c	7116	#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /!<PE[12] pin /
EricLew	0:d4e5ad7ad71c	7117	#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /!<PF[12] pin /
EricLew	0:d4e5ad7ad71c	7118	#define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /!<PG[12] pin /
EricLew	0:d4e5ad7ad71c	7119
EricLew	0:d4e5ad7ad71c	7120	/**
EricLew	0:d4e5ad7ad71c	7121	* @brief EXTI13 configuration
EricLew	0:d4e5ad7ad71c	7122	*/
EricLew	0:d4e5ad7ad71c	7123	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /!<PA[13] pin /
EricLew	0:d4e5ad7ad71c	7124	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /!<PB[13] pin /
EricLew	0:d4e5ad7ad71c	7125	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /!<PC[13] pin /
EricLew	0:d4e5ad7ad71c	7126	#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /!<PD[13] pin /
EricLew	0:d4e5ad7ad71c	7127	#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /!<PE[13] pin /
EricLew	0:d4e5ad7ad71c	7128	#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /!<PF[13] pin /
EricLew	0:d4e5ad7ad71c	7129	#define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /!<PG[13] pin /
EricLew	0:d4e5ad7ad71c	7130
EricLew	0:d4e5ad7ad71c	7131	/**
EricLew	0:d4e5ad7ad71c	7132	* @brief EXTI14 configuration
EricLew	0:d4e5ad7ad71c	7133	*/
EricLew	0:d4e5ad7ad71c	7134	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /!<PA[14] pin /
EricLew	0:d4e5ad7ad71c	7135	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /!<PB[14] pin /
EricLew	0:d4e5ad7ad71c	7136	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /!<PC[14] pin /
EricLew	0:d4e5ad7ad71c	7137	#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /!<PD[14] pin /
EricLew	0:d4e5ad7ad71c	7138	#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /!<PE[14] pin /
EricLew	0:d4e5ad7ad71c	7139	#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /!<PF[14] pin /
EricLew	0:d4e5ad7ad71c	7140	#define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /!<PG[14] pin /
EricLew	0:d4e5ad7ad71c	7141
EricLew	0:d4e5ad7ad71c	7142	/**
EricLew	0:d4e5ad7ad71c	7143	* @brief EXTI15 configuration
EricLew	0:d4e5ad7ad71c	7144	*/
EricLew	0:d4e5ad7ad71c	7145	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /!<PA[15] pin /
EricLew	0:d4e5ad7ad71c	7146	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /!<PB[15] pin /
EricLew	0:d4e5ad7ad71c	7147	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /!<PC[15] pin /
EricLew	0:d4e5ad7ad71c	7148	#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /!<PD[15] pin /
EricLew	0:d4e5ad7ad71c	7149	#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /!<PE[15] pin /
EricLew	0:d4e5ad7ad71c	7150	#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /!<PF[15] pin /
EricLew	0:d4e5ad7ad71c	7151	#define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /!<PG[15] pin /
EricLew	0:d4e5ad7ad71c	7152
EricLew	0:d4e5ad7ad71c	7153	/**************** Bit definition for SYSCFG_SCSR register **************/
EricLew	0:d4e5ad7ad71c	7154	#define SYSCFG_SCSR_SRAM2ER ((uint32_t)0x00000001) /!< SRAM2 Erase Request /
EricLew	0:d4e5ad7ad71c	7155	#define SYSCFG_SCSR_SRAM2BSY ((uint32_t)0x00000002) /!< SRAM2 Erase Ongoing /
EricLew	0:d4e5ad7ad71c	7156
EricLew	0:d4e5ad7ad71c	7157	/**************** Bit definition for SYSCFG_CFGR2 register **************/
EricLew	0:d4e5ad7ad71c	7158	#define SYSCFG_CFGR2_CLL ((uint32_t)0x00000001) /!< Core Lockup Lock /
EricLew	0:d4e5ad7ad71c	7159	#define SYSCFG_CFGR2_SPL ((uint32_t)0x00000002) /!< SRAM Parity Lock/
EricLew	0:d4e5ad7ad71c	7160	#define SYSCFG_CFGR2_PVDL ((uint32_t)0x00000004) /!< PVD Lock /
EricLew	0:d4e5ad7ad71c	7161	#define SYSCFG_CFGR2_ECCL ((uint32_t)0x00000008) /!< ECC Lock/
EricLew	0:d4e5ad7ad71c	7162	#define SYSCFG_CFGR2_SPF ((uint32_t)0x00000100) /!< SRAM Parity Flag /
EricLew	0:d4e5ad7ad71c	7163
EricLew	0:d4e5ad7ad71c	7164	/**************** Bit definition for SYSCFG_SWPR register **************/
EricLew	0:d4e5ad7ad71c	7165	#define SYSCFG_SWPR_PAGE0 ((uint32_t)0x00000001) /!< SRAM2 Write protection page 0 /
EricLew	0:d4e5ad7ad71c	7166	#define SYSCFG_SWPR_PAGE1 ((uint32_t)0x00000002) /!< SRAM2 Write protection page 1 /
EricLew	0:d4e5ad7ad71c	7167	#define SYSCFG_SWPR_PAGE2 ((uint32_t)0x00000004) /!< SRAM2 Write protection page 2 /
EricLew	0:d4e5ad7ad71c	7168	#define SYSCFG_SWPR_PAGE3 ((uint32_t)0x00000008) /!< SRAM2 Write protection page 3 /
EricLew	0:d4e5ad7ad71c	7169	#define SYSCFG_SWPR_PAGE4 ((uint32_t)0x00000010) /!< SRAM2 Write protection page 4 /
EricLew	0:d4e5ad7ad71c	7170	#define SYSCFG_SWPR_PAGE5 ((uint32_t)0x00000020) /!< SRAM2 Write protection page 5 /
EricLew	0:d4e5ad7ad71c	7171	#define SYSCFG_SWPR_PAGE6 ((uint32_t)0x00000040) /!< SRAM2 Write protection page 6 /
EricLew	0:d4e5ad7ad71c	7172	#define SYSCFG_SWPR_PAGE7 ((uint32_t)0x00000080) /!< SRAM2 Write protection page 7 /
EricLew	0:d4e5ad7ad71c	7173	#define SYSCFG_SWPR_PAGE8 ((uint32_t)0x00000100) /!< SRAM2 Write protection page 8 /
EricLew	0:d4e5ad7ad71c	7174	#define SYSCFG_SWPR_PAGE9 ((uint32_t)0x00000200) /!< SRAM2 Write protection page 9 /
EricLew	0:d4e5ad7ad71c	7175	#define SYSCFG_SWPR_PAGE10 ((uint32_t)0x00000400) /!< SRAM2 Write protection page 10/
EricLew	0:d4e5ad7ad71c	7176	#define SYSCFG_SWPR_PAGE11 ((uint32_t)0x00000800) /!< SRAM2 Write protection page 11/
EricLew	0:d4e5ad7ad71c	7177	#define SYSCFG_SWPR_PAGE12 ((uint32_t)0x00001000) /!< SRAM2 Write protection page 12/
EricLew	0:d4e5ad7ad71c	7178	#define SYSCFG_SWPR_PAGE13 ((uint32_t)0x00002000) /!< SRAM2 Write protection page 13/
EricLew	0:d4e5ad7ad71c	7179	#define SYSCFG_SWPR_PAGE14 ((uint32_t)0x00004000) /!< SRAM2 Write protection page 14/
EricLew	0:d4e5ad7ad71c	7180	#define SYSCFG_SWPR_PAGE15 ((uint32_t)0x00008000) /!< SRAM2 Write protection page 15/
EricLew	0:d4e5ad7ad71c	7181	#define SYSCFG_SWPR_PAGE16 ((uint32_t)0x00010000) /!< SRAM2 Write protection page 16/
EricLew	0:d4e5ad7ad71c	7182	#define SYSCFG_SWPR_PAGE17 ((uint32_t)0x00020000) /!< SRAM2 Write protection page 17/
EricLew	0:d4e5ad7ad71c	7183	#define SYSCFG_SWPR_PAGE18 ((uint32_t)0x00040000) /!< SRAM2 Write protection page 18/
EricLew	0:d4e5ad7ad71c	7184	#define SYSCFG_SWPR_PAGE19 ((uint32_t)0x00080000) /!< SRAM2 Write protection page 19/
EricLew	0:d4e5ad7ad71c	7185	#define SYSCFG_SWPR_PAGE20 ((uint32_t)0x00100000) /!< SRAM2 Write protection page 20/
EricLew	0:d4e5ad7ad71c	7186	#define SYSCFG_SWPR_PAGE21 ((uint32_t)0x00200000) /!< SRAM2 Write protection page 21/
EricLew	0:d4e5ad7ad71c	7187	#define SYSCFG_SWPR_PAGE22 ((uint32_t)0x00400000) /!< SRAM2 Write protection page 22/
EricLew	0:d4e5ad7ad71c	7188	#define SYSCFG_SWPR_PAGE23 ((uint32_t)0x00800000) /!< SRAM2 Write protection page 23/
EricLew	0:d4e5ad7ad71c	7189	#define SYSCFG_SWPR_PAGE24 ((uint32_t)0x01000000) /!< SRAM2 Write protection page 24/
EricLew	0:d4e5ad7ad71c	7190	#define SYSCFG_SWPR_PAGE25 ((uint32_t)0x02000000) /!< SRAM2 Write protection page 25/
EricLew	0:d4e5ad7ad71c	7191	#define SYSCFG_SWPR_PAGE26 ((uint32_t)0x04000000) /!< SRAM2 Write protection page 26/
EricLew	0:d4e5ad7ad71c	7192	#define SYSCFG_SWPR_PAGE27 ((uint32_t)0x08000000) /!< SRAM2 Write protection page 27/
EricLew	0:d4e5ad7ad71c	7193	#define SYSCFG_SWPR_PAGE28 ((uint32_t)0x10000000) /!< SRAM2 Write protection page 28/
EricLew	0:d4e5ad7ad71c	7194	#define SYSCFG_SWPR_PAGE29 ((uint32_t)0x20000000) /!< SRAM2 Write protection page 29/
EricLew	0:d4e5ad7ad71c	7195	#define SYSCFG_SWPR_PAGE30 ((uint32_t)0x40000000) /!< SRAM2 Write protection page 30/
EricLew	0:d4e5ad7ad71c	7196	#define SYSCFG_SWPR_PAGE31 ((uint32_t)0x80000000) /!< SRAM2 Write protection page 31/
EricLew	0:d4e5ad7ad71c	7197
EricLew	0:d4e5ad7ad71c	7198	/**************** Bit definition for SYSCFG_SKR register **************/
EricLew	0:d4e5ad7ad71c	7199	#define SYSCFG_SKR_KEY ((uint32_t)0x000000FF) /!< SRAM2 write protection key for software erase /
EricLew	0:d4e5ad7ad71c	7200
EricLew	0:d4e5ad7ad71c	7201
EricLew	0:d4e5ad7ad71c	7202
EricLew	0:d4e5ad7ad71c	7203
EricLew	0:d4e5ad7ad71c	7204	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7205	/* */
EricLew	0:d4e5ad7ad71c	7206	/* TIM */
EricLew	0:d4e5ad7ad71c	7207	/* */
EricLew	0:d4e5ad7ad71c	7208	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7209	/***************** Bit definition for TIM_CR1 register ******************/
EricLew	0:d4e5ad7ad71c	7210	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
EricLew	0:d4e5ad7ad71c	7211	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
EricLew	0:d4e5ad7ad71c	7212	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
EricLew	0:d4e5ad7ad71c	7213	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
EricLew	0:d4e5ad7ad71c	7214	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
EricLew	0:d4e5ad7ad71c	7215
EricLew	0:d4e5ad7ad71c	7216	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
EricLew	0:d4e5ad7ad71c	7217	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7218	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7219
EricLew	0:d4e5ad7ad71c	7220	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
EricLew	0:d4e5ad7ad71c	7221
EricLew	0:d4e5ad7ad71c	7222	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
EricLew	0:d4e5ad7ad71c	7223	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7224	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7225
EricLew	0:d4e5ad7ad71c	7226	#define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /!<Update interrupt flag remap /
EricLew	0:d4e5ad7ad71c	7227
EricLew	0:d4e5ad7ad71c	7228	/***************** Bit definition for TIM_CR2 register ******************/
EricLew	0:d4e5ad7ad71c	7229	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
EricLew	0:d4e5ad7ad71c	7230	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
EricLew	0:d4e5ad7ad71c	7231	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
EricLew	0:d4e5ad7ad71c	7232
EricLew	0:d4e5ad7ad71c	7233	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
EricLew	0:d4e5ad7ad71c	7234	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7235	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7236	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7237
EricLew	0:d4e5ad7ad71c	7238	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
EricLew	0:d4e5ad7ad71c	7239	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
EricLew	0:d4e5ad7ad71c	7240	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
EricLew	0:d4e5ad7ad71c	7241	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
EricLew	0:d4e5ad7ad71c	7242	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
EricLew	0:d4e5ad7ad71c	7243	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
EricLew	0:d4e5ad7ad71c	7244	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
EricLew	0:d4e5ad7ad71c	7245	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
EricLew	0:d4e5ad7ad71c	7246	#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /!<Output Idle state 5 (OC5 output) /
EricLew	0:d4e5ad7ad71c	7247	#define TIM_CR2_OIS6 ((uint32_t)0x00040000) /!<Output Idle state 6 (OC6 output) /
EricLew	0:d4e5ad7ad71c	7248
EricLew	0:d4e5ad7ad71c	7249	#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /!<MMS[2:0] bits (Master Mode Selection) /
EricLew	0:d4e5ad7ad71c	7250	#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7251	#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7252	#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7253	#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7254
EricLew	0:d4e5ad7ad71c	7255	/***************** Bit definition for TIM_SMCR register *****************/
EricLew	0:d4e5ad7ad71c	7256	#define TIM_SMCR_SMS ((uint32_t)0x00010007) /!<SMS[2:0] bits (Slave mode selection) /
EricLew	0:d4e5ad7ad71c	7257	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7258	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7259	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7260	#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7261
EricLew	0:d4e5ad7ad71c	7262	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
EricLew	0:d4e5ad7ad71c	7263
EricLew	0:d4e5ad7ad71c	7264	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
EricLew	0:d4e5ad7ad71c	7265	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7266	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7267	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7268
EricLew	0:d4e5ad7ad71c	7269	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
EricLew	0:d4e5ad7ad71c	7270
EricLew	0:d4e5ad7ad71c	7271	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
EricLew	0:d4e5ad7ad71c	7272	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7273	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7274	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7275	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7276
EricLew	0:d4e5ad7ad71c	7277	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
EricLew	0:d4e5ad7ad71c	7278	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7279	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7280
EricLew	0:d4e5ad7ad71c	7281	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
EricLew	0:d4e5ad7ad71c	7282	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
EricLew	0:d4e5ad7ad71c	7283
EricLew	0:d4e5ad7ad71c	7284	/***************** Bit definition for TIM_DIER register *****************/
EricLew	0:d4e5ad7ad71c	7285	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
EricLew	0:d4e5ad7ad71c	7286	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
EricLew	0:d4e5ad7ad71c	7287	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
EricLew	0:d4e5ad7ad71c	7288	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
EricLew	0:d4e5ad7ad71c	7289	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
EricLew	0:d4e5ad7ad71c	7290	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
EricLew	0:d4e5ad7ad71c	7291	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
EricLew	0:d4e5ad7ad71c	7292	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
EricLew	0:d4e5ad7ad71c	7293	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
EricLew	0:d4e5ad7ad71c	7294	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
EricLew	0:d4e5ad7ad71c	7295	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
EricLew	0:d4e5ad7ad71c	7296	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
EricLew	0:d4e5ad7ad71c	7297	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
EricLew	0:d4e5ad7ad71c	7298	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
EricLew	0:d4e5ad7ad71c	7299	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
EricLew	0:d4e5ad7ad71c	7300
EricLew	0:d4e5ad7ad71c	7301	/****************** Bit definition for TIM_SR register ******************/
EricLew	0:d4e5ad7ad71c	7302	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
EricLew	0:d4e5ad7ad71c	7303	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7304	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7305	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7306	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7307	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
EricLew	0:d4e5ad7ad71c	7308	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
EricLew	0:d4e5ad7ad71c	7309	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
EricLew	0:d4e5ad7ad71c	7310	#define TIM_SR_B2IF ((uint32_t)0x00000100) /!<Break 2 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7311	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
EricLew	0:d4e5ad7ad71c	7312	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
EricLew	0:d4e5ad7ad71c	7313	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
EricLew	0:d4e5ad7ad71c	7314	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
EricLew	0:d4e5ad7ad71c	7315	#define TIM_SR_SBIF ((uint32_t)0x00002000) /!<System Break interrupt Flag /
EricLew	0:d4e5ad7ad71c	7316	#define TIM_SR_CC5IF ((uint32_t)0x00010000) /!<Capture/Compare 5 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7317	#define TIM_SR_CC6IF ((uint32_t)0x00020000) /!<Capture/Compare 6 interrupt Flag /
EricLew	0:d4e5ad7ad71c	7318
EricLew	0:d4e5ad7ad71c	7319
EricLew	0:d4e5ad7ad71c	7320	/***************** Bit definition for TIM_EGR register ******************/
EricLew	0:d4e5ad7ad71c	7321	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
EricLew	0:d4e5ad7ad71c	7322	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
EricLew	0:d4e5ad7ad71c	7323	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
EricLew	0:d4e5ad7ad71c	7324	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
EricLew	0:d4e5ad7ad71c	7325	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
EricLew	0:d4e5ad7ad71c	7326	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
EricLew	0:d4e5ad7ad71c	7327	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
EricLew	0:d4e5ad7ad71c	7328	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
EricLew	0:d4e5ad7ad71c	7329	#define TIM_EGR_B2G ((uint32_t)0x00000100) /!<Break 2 Generation /
EricLew	0:d4e5ad7ad71c	7330
EricLew	0:d4e5ad7ad71c	7331
EricLew	0:d4e5ad7ad71c	7332	/**************** Bit definition for TIM_CCMR1 register *****************/
EricLew	0:d4e5ad7ad71c	7333	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
EricLew	0:d4e5ad7ad71c	7334	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7335	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7336
EricLew	0:d4e5ad7ad71c	7337	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
EricLew	0:d4e5ad7ad71c	7338	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
EricLew	0:d4e5ad7ad71c	7339
EricLew	0:d4e5ad7ad71c	7340	#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
EricLew	0:d4e5ad7ad71c	7341	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7342	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7343	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7344	#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7345
EricLew	0:d4e5ad7ad71c	7346	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1 Clear Enable /
EricLew	0:d4e5ad7ad71c	7347
EricLew	0:d4e5ad7ad71c	7348	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
EricLew	0:d4e5ad7ad71c	7349	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7350	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7351
EricLew	0:d4e5ad7ad71c	7352	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
EricLew	0:d4e5ad7ad71c	7353	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
EricLew	0:d4e5ad7ad71c	7354
EricLew	0:d4e5ad7ad71c	7355	#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
EricLew	0:d4e5ad7ad71c	7356	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7357	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7358	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7359	#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7360
EricLew	0:d4e5ad7ad71c	7361	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
EricLew	0:d4e5ad7ad71c	7362
EricLew	0:d4e5ad7ad71c	7363	/----------------------------------------------------------------------------/
EricLew	0:d4e5ad7ad71c	7364	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
EricLew	0:d4e5ad7ad71c	7365	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7366	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7367
EricLew	0:d4e5ad7ad71c	7368	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
EricLew	0:d4e5ad7ad71c	7369	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7370	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7371	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7372	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7373
EricLew	0:d4e5ad7ad71c	7374	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
EricLew	0:d4e5ad7ad71c	7375	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7376	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7377
EricLew	0:d4e5ad7ad71c	7378	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
EricLew	0:d4e5ad7ad71c	7379	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7380	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7381	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7382	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7383
EricLew	0:d4e5ad7ad71c	7384	/**************** Bit definition for TIM_CCMR2 register *****************/
EricLew	0:d4e5ad7ad71c	7385	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
EricLew	0:d4e5ad7ad71c	7386	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7387	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7388
EricLew	0:d4e5ad7ad71c	7389	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
EricLew	0:d4e5ad7ad71c	7390	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
EricLew	0:d4e5ad7ad71c	7391
EricLew	0:d4e5ad7ad71c	7392	#define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
EricLew	0:d4e5ad7ad71c	7393	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7394	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7395	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7396	#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7397
EricLew	0:d4e5ad7ad71c	7398	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
EricLew	0:d4e5ad7ad71c	7399
EricLew	0:d4e5ad7ad71c	7400	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
EricLew	0:d4e5ad7ad71c	7401	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7402	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7403
EricLew	0:d4e5ad7ad71c	7404	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
EricLew	0:d4e5ad7ad71c	7405	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
EricLew	0:d4e5ad7ad71c	7406
EricLew	0:d4e5ad7ad71c	7407	#define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
EricLew	0:d4e5ad7ad71c	7408	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7409	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7410	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7411	#define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7412
EricLew	0:d4e5ad7ad71c	7413	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
EricLew	0:d4e5ad7ad71c	7414
EricLew	0:d4e5ad7ad71c	7415	/----------------------------------------------------------------------------/
EricLew	0:d4e5ad7ad71c	7416	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
EricLew	0:d4e5ad7ad71c	7417	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7418	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7419
EricLew	0:d4e5ad7ad71c	7420	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
EricLew	0:d4e5ad7ad71c	7421	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7422	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7423	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7424	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7425
EricLew	0:d4e5ad7ad71c	7426	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
EricLew	0:d4e5ad7ad71c	7427	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7428	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7429
EricLew	0:d4e5ad7ad71c	7430	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
EricLew	0:d4e5ad7ad71c	7431	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7432	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7433	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7434	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7435
EricLew	0:d4e5ad7ad71c	7436	/**************** Bit definition for TIM_CCMR3 register *****************/
EricLew	0:d4e5ad7ad71c	7437	#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /!<Output Compare 5 Fast enable /
EricLew	0:d4e5ad7ad71c	7438	#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /!<Output Compare 5 Preload enable /
EricLew	0:d4e5ad7ad71c	7439
EricLew	0:d4e5ad7ad71c	7440	#define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /!<OC5M[3:0] bits (Output Compare 5 Mode) /
EricLew	0:d4e5ad7ad71c	7441	#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7442	#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7443	#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7444	#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7445
EricLew	0:d4e5ad7ad71c	7446	#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /!<Output Compare 5 Clear Enable /
EricLew	0:d4e5ad7ad71c	7447
EricLew	0:d4e5ad7ad71c	7448	#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /!<Output Compare 6 Fast enable /
EricLew	0:d4e5ad7ad71c	7449	#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /!<Output Compare 6 Preload enable /
EricLew	0:d4e5ad7ad71c	7450
EricLew	0:d4e5ad7ad71c	7451	#define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /!<OC6M[3:0] bits (Output Compare 6 Mode) /
EricLew	0:d4e5ad7ad71c	7452	#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7453	#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7454	#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7455	#define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7456
EricLew	0:d4e5ad7ad71c	7457	#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /!<Output Compare 6 Clear Enable /
EricLew	0:d4e5ad7ad71c	7458
EricLew	0:d4e5ad7ad71c	7459	/***************** Bit definition for TIM_CCER register *****************/
EricLew	0:d4e5ad7ad71c	7460	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
EricLew	0:d4e5ad7ad71c	7461	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
EricLew	0:d4e5ad7ad71c	7462	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
EricLew	0:d4e5ad7ad71c	7463	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
EricLew	0:d4e5ad7ad71c	7464	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
EricLew	0:d4e5ad7ad71c	7465	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
EricLew	0:d4e5ad7ad71c	7466	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
EricLew	0:d4e5ad7ad71c	7467	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
EricLew	0:d4e5ad7ad71c	7468	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
EricLew	0:d4e5ad7ad71c	7469	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
EricLew	0:d4e5ad7ad71c	7470	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
EricLew	0:d4e5ad7ad71c	7471	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
EricLew	0:d4e5ad7ad71c	7472	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
EricLew	0:d4e5ad7ad71c	7473	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
EricLew	0:d4e5ad7ad71c	7474	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
EricLew	0:d4e5ad7ad71c	7475	#define TIM_CCER_CC5E ((uint32_t)0x00010000) /!<Capture/Compare 5 output enable /
EricLew	0:d4e5ad7ad71c	7476	#define TIM_CCER_CC5P ((uint32_t)0x00020000) /!<Capture/Compare 5 output Polarity /
EricLew	0:d4e5ad7ad71c	7477	#define TIM_CCER_CC6E ((uint32_t)0x00100000) /!<Capture/Compare 6 output enable /
EricLew	0:d4e5ad7ad71c	7478	#define TIM_CCER_CC6P ((uint32_t)0x00200000) /!<Capture/Compare 6 output Polarity /
EricLew	0:d4e5ad7ad71c	7479
EricLew	0:d4e5ad7ad71c	7480	/***************** Bit definition for TIM_CNT register ******************/
EricLew	0:d4e5ad7ad71c	7481	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
EricLew	0:d4e5ad7ad71c	7482	#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /!<Update interrupt flag copy (if UIFREMAP=1) /
EricLew	0:d4e5ad7ad71c	7483
EricLew	0:d4e5ad7ad71c	7484	/***************** Bit definition for TIM_PSC register ******************/
EricLew	0:d4e5ad7ad71c	7485	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
EricLew	0:d4e5ad7ad71c	7486
EricLew	0:d4e5ad7ad71c	7487	/***************** Bit definition for TIM_ARR register ******************/
EricLew	0:d4e5ad7ad71c	7488	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<Actual auto-reload Value /
EricLew	0:d4e5ad7ad71c	7489
EricLew	0:d4e5ad7ad71c	7490	/***************** Bit definition for TIM_RCR register ******************/
EricLew	0:d4e5ad7ad71c	7491	#define TIM_RCR_REP ((uint32_t)0x0000FFFF) /!<Repetition Counter Value /
EricLew	0:d4e5ad7ad71c	7492
EricLew	0:d4e5ad7ad71c	7493	/***************** Bit definition for TIM_CCR1 register *****************/
EricLew	0:d4e5ad7ad71c	7494	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
EricLew	0:d4e5ad7ad71c	7495
EricLew	0:d4e5ad7ad71c	7496	/***************** Bit definition for TIM_CCR2 register *****************/
EricLew	0:d4e5ad7ad71c	7497	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
EricLew	0:d4e5ad7ad71c	7498
EricLew	0:d4e5ad7ad71c	7499	/***************** Bit definition for TIM_CCR3 register *****************/
EricLew	0:d4e5ad7ad71c	7500	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
EricLew	0:d4e5ad7ad71c	7501
EricLew	0:d4e5ad7ad71c	7502	/***************** Bit definition for TIM_CCR4 register *****************/
EricLew	0:d4e5ad7ad71c	7503	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
EricLew	0:d4e5ad7ad71c	7504
EricLew	0:d4e5ad7ad71c	7505	/***************** Bit definition for TIM_CCR5 register *****************/
EricLew	0:d4e5ad7ad71c	7506	#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /!<Capture/Compare 5 Value /
EricLew	0:d4e5ad7ad71c	7507	#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /!<Group Channel 5 and Channel 1 /
EricLew	0:d4e5ad7ad71c	7508	#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /!<Group Channel 5 and Channel 2 /
EricLew	0:d4e5ad7ad71c	7509	#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /!<Group Channel 5 and Channel 3 /
EricLew	0:d4e5ad7ad71c	7510
EricLew	0:d4e5ad7ad71c	7511	/***************** Bit definition for TIM_CCR6 register *****************/
EricLew	0:d4e5ad7ad71c	7512	#define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /!<Capture/Compare 6 Value /
EricLew	0:d4e5ad7ad71c	7513
EricLew	0:d4e5ad7ad71c	7514	/***************** Bit definition for TIM_BDTR register *****************/
EricLew	0:d4e5ad7ad71c	7515	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
EricLew	0:d4e5ad7ad71c	7516	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7517	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7518	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7519	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7520	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	7521	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	7522	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	7523	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	7524
EricLew	0:d4e5ad7ad71c	7525	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
EricLew	0:d4e5ad7ad71c	7526	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7527	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7528
EricLew	0:d4e5ad7ad71c	7529	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
EricLew	0:d4e5ad7ad71c	7530	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
EricLew	0:d4e5ad7ad71c	7531	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable for Break 1 /
EricLew	0:d4e5ad7ad71c	7532	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity for Break 1 /
EricLew	0:d4e5ad7ad71c	7533	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
EricLew	0:d4e5ad7ad71c	7534	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
EricLew	0:d4e5ad7ad71c	7535
EricLew	0:d4e5ad7ad71c	7536	#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /!<Break Filter for Break 1 /
EricLew	0:d4e5ad7ad71c	7537	#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /!<Break Filter for Break 2 /
EricLew	0:d4e5ad7ad71c	7538
EricLew	0:d4e5ad7ad71c	7539	#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /!<Break enable for Break 2 /
EricLew	0:d4e5ad7ad71c	7540	#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /!<Break Polarity for Break 2 /
EricLew	0:d4e5ad7ad71c	7541
EricLew	0:d4e5ad7ad71c	7542	/***************** Bit definition for TIM_DCR register ******************/
EricLew	0:d4e5ad7ad71c	7543	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
EricLew	0:d4e5ad7ad71c	7544	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7545	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7546	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7547	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7548	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	7549
EricLew	0:d4e5ad7ad71c	7550	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
EricLew	0:d4e5ad7ad71c	7551	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7552	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7553	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7554	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7555	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	7556
EricLew	0:d4e5ad7ad71c	7557	/***************** Bit definition for TIM_DMAR register *****************/
EricLew	0:d4e5ad7ad71c	7558	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
EricLew	0:d4e5ad7ad71c	7559
EricLew	0:d4e5ad7ad71c	7560	/***************** Bit definition for TIM1_OR1 register *****************/
EricLew	0:d4e5ad7ad71c	7561	#define TIM1_OR1_ETR_ADC1_RMP ((uint32_t)0x00000003) /!<ETR_ADC1_RMP[1:0] bits (TIM1 ETR remap on ADC1) /
EricLew	0:d4e5ad7ad71c	7562	#define TIM1_OR1_ETR_ADC1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7563	#define TIM1_OR1_ETR_ADC1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7564
EricLew	0:d4e5ad7ad71c	7565	#define TIM1_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000C) /!<ETR_ADC3_RMP[1:0] bits (TIM1 ETR remap on ADC3) /
EricLew	0:d4e5ad7ad71c	7566	#define TIM1_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7567	#define TIM1_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7568
EricLew	0:d4e5ad7ad71c	7569	#define TIM1_OR1_TI1_RMP ((uint32_t)0x00000010) /!<TIM1 Input Capture 1 remap /
EricLew	0:d4e5ad7ad71c	7570
EricLew	0:d4e5ad7ad71c	7571	/***************** Bit definition for TIM1_OR2 register *****************/
EricLew	0:d4e5ad7ad71c	7572	#define TIM1_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
EricLew	0:d4e5ad7ad71c	7573	#define TIM1_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
EricLew	0:d4e5ad7ad71c	7574	#define TIM1_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
EricLew	0:d4e5ad7ad71c	7575	#define TIM1_OR2_BKDFBK0E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[0] enable /
EricLew	0:d4e5ad7ad71c	7576	#define TIM1_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
EricLew	0:d4e5ad7ad71c	7577	#define TIM1_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7578	#define TIM1_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7579
EricLew	0:d4e5ad7ad71c	7580	#define TIM1_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM1 ETR source selection) /
EricLew	0:d4e5ad7ad71c	7581	#define TIM1_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7582	#define TIM1_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7583	#define TIM1_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7584
EricLew	0:d4e5ad7ad71c	7585	/***************** Bit definition for TIM1_OR3 register *****************/
EricLew	0:d4e5ad7ad71c	7586	#define TIM1_OR3_BK2INE ((uint32_t)0x00000001) /!<BRK2 BKIN2 input enable /
EricLew	0:d4e5ad7ad71c	7587	#define TIM1_OR3_BK2CMP1E ((uint32_t)0x00000002) /!<BRK2 COMP1 enable /
EricLew	0:d4e5ad7ad71c	7588	#define TIM1_OR3_BK2CMP2E ((uint32_t)0x00000004) /!<BRK2 COMP2 enable /
EricLew	0:d4e5ad7ad71c	7589	#define TIM1_OR3_BK2DFBK1E ((uint32_t)0x00000100) /!<BRK2 DFSDM_BREAK[1] enable /
EricLew	0:d4e5ad7ad71c	7590	#define TIM1_OR3_BK2INP ((uint32_t)0x00000200) /!<BRK2 BKIN2 input polarity /
EricLew	0:d4e5ad7ad71c	7591	#define TIM1_OR3_BK2CMP1P ((uint32_t)0x00000400) /!<BRK2 COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7592	#define TIM1_OR3_BK2CMP2P ((uint32_t)0x00000800) /!<BRK2 COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7593
EricLew	0:d4e5ad7ad71c	7594	/***************** Bit definition for TIM8_OR1 register *****************/
EricLew	0:d4e5ad7ad71c	7595	#define TIM8_OR1_ETR_ADC2_RMP ((uint32_t)0x00000003) /!<ETR_ADC2_RMP[1:0] bits (TIM8 ETR remap on ADC2) /
EricLew	0:d4e5ad7ad71c	7596	#define TIM8_OR1_ETR_ADC2_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7597	#define TIM8_OR1_ETR_ADC2_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7598
EricLew	0:d4e5ad7ad71c	7599	#define TIM8_OR1_ETR_ADC3_RMP ((uint32_t)0x0000000C) /!<ETR_ADC3_RMP[1:0] bits (TIM8 ETR remap on ADC3) /
EricLew	0:d4e5ad7ad71c	7600	#define TIM8_OR1_ETR_ADC3_RMP_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7601	#define TIM8_OR1_ETR_ADC3_RMP_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7602
EricLew	0:d4e5ad7ad71c	7603	#define TIM8_OR1_TI1_RMP ((uint32_t)0x00000010) /!<TIM8 Input Capture 1 remap /
EricLew	0:d4e5ad7ad71c	7604
EricLew	0:d4e5ad7ad71c	7605	/***************** Bit definition for TIM8_OR2 register *****************/
EricLew	0:d4e5ad7ad71c	7606	#define TIM8_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
EricLew	0:d4e5ad7ad71c	7607	#define TIM8_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
EricLew	0:d4e5ad7ad71c	7608	#define TIM8_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
EricLew	0:d4e5ad7ad71c	7609	#define TIM8_OR2_BKDFBK2E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[2] enable /
EricLew	0:d4e5ad7ad71c	7610	#define TIM8_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
EricLew	0:d4e5ad7ad71c	7611	#define TIM8_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7612	#define TIM8_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7613
EricLew	0:d4e5ad7ad71c	7614	#define TIM8_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM8 ETR source selection) /
EricLew	0:d4e5ad7ad71c	7615	#define TIM8_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7616	#define TIM8_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7617	#define TIM8_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7618
EricLew	0:d4e5ad7ad71c	7619	/***************** Bit definition for TIM8_OR3 register *****************/
EricLew	0:d4e5ad7ad71c	7620	#define TIM8_OR3_BK2INE ((uint32_t)0x00000001) /!<BRK2 BKIN2 input enable /
EricLew	0:d4e5ad7ad71c	7621	#define TIM8_OR3_BK2CMP1E ((uint32_t)0x00000002) /!<BRK2 COMP1 enable /
EricLew	0:d4e5ad7ad71c	7622	#define TIM8_OR3_BK2CMP2E ((uint32_t)0x00000004) /!<BRK2 COMP2 enable /
EricLew	0:d4e5ad7ad71c	7623	#define TIM8_OR3_BK2DFBK3E ((uint32_t)0x00000100) /!<BRK2 DFSDM_BREAK[3] enable /
EricLew	0:d4e5ad7ad71c	7624	#define TIM8_OR3_BK2INP ((uint32_t)0x00000200) /!<BRK2 BKIN2 input polarity /
EricLew	0:d4e5ad7ad71c	7625	#define TIM8_OR3_BK2CMP1P ((uint32_t)0x00000400) /!<BRK2 COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7626	#define TIM8_OR3_BK2CMP2P ((uint32_t)0x00000800) /!<BRK2 COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7627
EricLew	0:d4e5ad7ad71c	7628	/***************** Bit definition for TIM2_OR1 register *****************/
EricLew	0:d4e5ad7ad71c	7629	#define TIM2_OR1_ITR1_RMP ((uint32_t)0x00000001) /!<TIM2 Internal trigger 1 remap /
EricLew	0:d4e5ad7ad71c	7630	#define TIM2_OR1_ETR1_RMP ((uint32_t)0x00000002) /!<TIM2 External trigger 1 remap /
EricLew	0:d4e5ad7ad71c	7631
EricLew	0:d4e5ad7ad71c	7632	#define TIM2_OR1_TI4_RMP ((uint32_t)0x0000000C) /!<TI4_RMP[1:0] bits (TIM2 Input Capture 4 remap) /
EricLew	0:d4e5ad7ad71c	7633	#define TIM2_OR1_TI4_RMP_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7634	#define TIM2_OR1_TI4_RMP_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7635
EricLew	0:d4e5ad7ad71c	7636	/***************** Bit definition for TIM2_OR2 register *****************/
EricLew	0:d4e5ad7ad71c	7637	#define TIM2_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM2 ETR source selection) /
EricLew	0:d4e5ad7ad71c	7638	#define TIM2_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7639	#define TIM2_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7640	#define TIM2_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7641
EricLew	0:d4e5ad7ad71c	7642	/***************** Bit definition for TIM3_OR1 register *****************/
EricLew	0:d4e5ad7ad71c	7643	#define TIM3_OR1_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM3 Input Capture 1 remap) /
EricLew	0:d4e5ad7ad71c	7644	#define TIM3_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7645	#define TIM3_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7646
EricLew	0:d4e5ad7ad71c	7647	/***************** Bit definition for TIM3_OR2 register *****************/
EricLew	0:d4e5ad7ad71c	7648	#define TIM3_OR2_ETRSEL ((uint32_t)0x0001C000) /!<ETRSEL[2:0] bits (TIM3 ETR source selection) /
EricLew	0:d4e5ad7ad71c	7649	#define TIM3_OR2_ETRSEL_0 ((uint32_t)0x00004000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7650	#define TIM3_OR2_ETRSEL_1 ((uint32_t)0x00008000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7651	#define TIM3_OR2_ETRSEL_2 ((uint32_t)0x00010000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7652
EricLew	0:d4e5ad7ad71c	7653	/***************** Bit definition for TIM15_OR1 register ****************/
EricLew	0:d4e5ad7ad71c	7654	#define TIM15_OR1_TI1_RMP ((uint32_t)0x00000001) /!<TIM15 Input Capture 1 remap /
EricLew	0:d4e5ad7ad71c	7655
EricLew	0:d4e5ad7ad71c	7656	#define TIM15_OR1_ENCODER_MODE ((uint32_t)0x00000006) /!<ENCODER_MODE[1:0] bits (TIM15 Encoder mode) /
EricLew	0:d4e5ad7ad71c	7657	#define TIM15_OR1_ENCODER_MODE_0 ((uint32_t)0x00000002) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7658	#define TIM15_OR1_ENCODER_MODE_1 ((uint32_t)0x00000004) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7659
EricLew	0:d4e5ad7ad71c	7660	/***************** Bit definition for TIM15_OR2 register ****************/
EricLew	0:d4e5ad7ad71c	7661	#define TIM15_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
EricLew	0:d4e5ad7ad71c	7662	#define TIM15_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
EricLew	0:d4e5ad7ad71c	7663	#define TIM15_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
EricLew	0:d4e5ad7ad71c	7664	#define TIM15_OR2_BKDFBK0E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[0] enable /
EricLew	0:d4e5ad7ad71c	7665	#define TIM15_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
EricLew	0:d4e5ad7ad71c	7666	#define TIM15_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7667	#define TIM15_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7668
EricLew	0:d4e5ad7ad71c	7669	/***************** Bit definition for TIM16_OR1 register ****************/
EricLew	0:d4e5ad7ad71c	7670	#define TIM16_OR1_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM16 Input Capture 1 remap) /
EricLew	0:d4e5ad7ad71c	7671	#define TIM16_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7672	#define TIM16_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7673
EricLew	0:d4e5ad7ad71c	7674	/***************** Bit definition for TIM16_OR2 register ****************/
EricLew	0:d4e5ad7ad71c	7675	#define TIM16_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
EricLew	0:d4e5ad7ad71c	7676	#define TIM16_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
EricLew	0:d4e5ad7ad71c	7677	#define TIM16_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
EricLew	0:d4e5ad7ad71c	7678	#define TIM16_OR2_BKDFBK1E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[1] enable /
EricLew	0:d4e5ad7ad71c	7679	#define TIM16_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
EricLew	0:d4e5ad7ad71c	7680	#define TIM16_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7681	#define TIM16_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7682
EricLew	0:d4e5ad7ad71c	7683	/***************** Bit definition for TIM17_OR1 register ****************/
EricLew	0:d4e5ad7ad71c	7684	#define TIM17_OR1_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM17 Input Capture 1 remap) /
EricLew	0:d4e5ad7ad71c	7685	#define TIM17_OR1_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7686	#define TIM17_OR1_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7687
EricLew	0:d4e5ad7ad71c	7688	/***************** Bit definition for TIM17_OR2 register ****************/
EricLew	0:d4e5ad7ad71c	7689	#define TIM17_OR2_BKINE ((uint32_t)0x00000001) /!<BRK BKIN input enable /
EricLew	0:d4e5ad7ad71c	7690	#define TIM17_OR2_BKCMP1E ((uint32_t)0x00000002) /!<BRK COMP1 enable /
EricLew	0:d4e5ad7ad71c	7691	#define TIM17_OR2_BKCMP2E ((uint32_t)0x00000004) /!<BRK COMP2 enable /
EricLew	0:d4e5ad7ad71c	7692	#define TIM17_OR2_BKDFBK2E ((uint32_t)0x00000100) /!<BRK DFSDM_BREAK[2] enable /
EricLew	0:d4e5ad7ad71c	7693	#define TIM17_OR2_BKINP ((uint32_t)0x00000200) /!<BRK BKIN input polarity /
EricLew	0:d4e5ad7ad71c	7694	#define TIM17_OR2_BKCMP1P ((uint32_t)0x00000400) /!<BRK COMP1 input polarity /
EricLew	0:d4e5ad7ad71c	7695	#define TIM17_OR2_BKCMP2P ((uint32_t)0x00000800) /!<BRK COMP2 input polarity /
EricLew	0:d4e5ad7ad71c	7696
EricLew	0:d4e5ad7ad71c	7697	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7698	/* */
EricLew	0:d4e5ad7ad71c	7699	/* Low Power Timer (LPTTIM) */
EricLew	0:d4e5ad7ad71c	7700	/* */
EricLew	0:d4e5ad7ad71c	7701	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7702	/**************** Bit definition for LPTIM_ISR register *****************/
EricLew	0:d4e5ad7ad71c	7703	#define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /!< Compare match /
EricLew	0:d4e5ad7ad71c	7704	#define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /!< Autoreload match /
EricLew	0:d4e5ad7ad71c	7705	#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /!< External trigger edge event /
EricLew	0:d4e5ad7ad71c	7706	#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /!< Compare register update OK /
EricLew	0:d4e5ad7ad71c	7707	#define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /!< Autoreload register update OK /
EricLew	0:d4e5ad7ad71c	7708	#define LPTIM_ISR_UP ((uint32_t)0x00000020) /!< Counter direction change down to up /
EricLew	0:d4e5ad7ad71c	7709	#define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /!< Counter direction change up to down /
EricLew	0:d4e5ad7ad71c	7710
EricLew	0:d4e5ad7ad71c	7711	/**************** Bit definition for LPTIM_ICR register *****************/
EricLew	0:d4e5ad7ad71c	7712	#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /!< Compare match Clear Flag /
EricLew	0:d4e5ad7ad71c	7713	#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /!< Autoreload match Clear Flag /
EricLew	0:d4e5ad7ad71c	7714	#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /!< External trigger edge event Clear Flag /
EricLew	0:d4e5ad7ad71c	7715	#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /!< Compare register update OK Clear Flag /
EricLew	0:d4e5ad7ad71c	7716	#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /!< Autoreload register update OK Clear Flag /
EricLew	0:d4e5ad7ad71c	7717	#define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /!< Counter direction change down to up Clear Flag /
EricLew	0:d4e5ad7ad71c	7718	#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /!< Counter direction change up to down Clear Flag /
EricLew	0:d4e5ad7ad71c	7719
EricLew	0:d4e5ad7ad71c	7720	/**************** Bit definition for LPTIM_IER register ******************/
EricLew	0:d4e5ad7ad71c	7721	#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /!< Compare match Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7722	#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /!< Autoreload match Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7723	#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /!< External trigger edge event Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7724	#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /!< Compare register update OK Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7725	#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /!< Autoreload register update OK Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7726	#define LPTIM_IER_UPIE ((uint32_t)0x00000020) /!< Counter direction change down to up Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7727	#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /!< Counter direction change up to down Interrupt Enable /
EricLew	0:d4e5ad7ad71c	7728
EricLew	0:d4e5ad7ad71c	7729	/**************** Bit definition for LPTIM_CFGR register *****************/
EricLew	0:d4e5ad7ad71c	7730	#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /!< Clock selector /
EricLew	0:d4e5ad7ad71c	7731
EricLew	0:d4e5ad7ad71c	7732	#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /!< CKPOL[1:0] bits (Clock polarity) /
EricLew	0:d4e5ad7ad71c	7733	#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7734	#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7735
EricLew	0:d4e5ad7ad71c	7736	#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
EricLew	0:d4e5ad7ad71c	7737	#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7738	#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7739
EricLew	0:d4e5ad7ad71c	7740	#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
EricLew	0:d4e5ad7ad71c	7741	#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7742	#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7743
EricLew	0:d4e5ad7ad71c	7744	#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /!< PRESC[2:0] bits (Clock prescaler) /
EricLew	0:d4e5ad7ad71c	7745	#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7746	#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7747	#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	7748
EricLew	0:d4e5ad7ad71c	7749	#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /!< TRIGSEL[2:0]] bits (Trigger selector) /
EricLew	0:d4e5ad7ad71c	7750	#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7751	#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7752	#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	7753
EricLew	0:d4e5ad7ad71c	7754	#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
EricLew	0:d4e5ad7ad71c	7755	#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7756	#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7757
EricLew	0:d4e5ad7ad71c	7758	#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /!< Timout enable /
EricLew	0:d4e5ad7ad71c	7759	#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /!< Waveform shape /
EricLew	0:d4e5ad7ad71c	7760	#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /!< Waveform shape polarity /
EricLew	0:d4e5ad7ad71c	7761	#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /!< Reg update mode /
EricLew	0:d4e5ad7ad71c	7762	#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /!< Counter mode enable /
EricLew	0:d4e5ad7ad71c	7763	#define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /!< Encoder mode enable /
EricLew	0:d4e5ad7ad71c	7764
EricLew	0:d4e5ad7ad71c	7765	/**************** Bit definition for LPTIM_CR register ******************/
EricLew	0:d4e5ad7ad71c	7766	#define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /!< LPTIMer enable /
EricLew	0:d4e5ad7ad71c	7767	#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002) /!< Timer start in single mode /
EricLew	0:d4e5ad7ad71c	7768	#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /!< Timer start in continuous mode /
EricLew	0:d4e5ad7ad71c	7769
EricLew	0:d4e5ad7ad71c	7770	/**************** Bit definition for LPTIM_CMP register *****************/
EricLew	0:d4e5ad7ad71c	7771	#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /!< Compare register /
EricLew	0:d4e5ad7ad71c	7772
EricLew	0:d4e5ad7ad71c	7773	/**************** Bit definition for LPTIM_ARR register *****************/
EricLew	0:d4e5ad7ad71c	7774	#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /!< Auto reload register /
EricLew	0:d4e5ad7ad71c	7775
EricLew	0:d4e5ad7ad71c	7776	/**************** Bit definition for LPTIM_CNT register *****************/
EricLew	0:d4e5ad7ad71c	7777	#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /!< Counter register /
EricLew	0:d4e5ad7ad71c	7778
EricLew	0:d4e5ad7ad71c	7779	/**************** Bit definition for LPTIM_OR register *****************/
EricLew	0:d4e5ad7ad71c	7780	#define LPTIM_OR_OR ((uint32_t)0x00000003) /!< LPTIMER[1:0] bits (Remap selection) /
EricLew	0:d4e5ad7ad71c	7781	#define LPTIM_OR_OR_0 ((uint32_t)0x00000001) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7782	#define LPTIM_OR_OR_1 ((uint32_t)0x00000002) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7783
EricLew	0:d4e5ad7ad71c	7784	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7785	/* */
EricLew	0:d4e5ad7ad71c	7786	/* Analog Comparators (COMP) */
EricLew	0:d4e5ad7ad71c	7787	/* */
EricLew	0:d4e5ad7ad71c	7788	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7789	/******************** Bit definition for COMPx_CSR register *************/
EricLew	0:d4e5ad7ad71c	7790	#define COMP_CSR_EN ((uint32_t)0x00000001) /!< COMPx enable /
EricLew	0:d4e5ad7ad71c	7791
EricLew	0:d4e5ad7ad71c	7792	#define COMP_CSR_PWRMODE ((uint32_t)0x0000000C) /!< COMPx power mode /
EricLew	0:d4e5ad7ad71c	7793	#define COMP_CSR_PWRMODE_0 ((uint32_t)0x00000004) /!< COMPx power mode bit 0 /
EricLew	0:d4e5ad7ad71c	7794	#define COMP_CSR_PWRMODE_1 ((uint32_t)0x00000008) /!< COMPx power mode bit 1 /
EricLew	0:d4e5ad7ad71c	7795
EricLew	0:d4e5ad7ad71c	7796	#define COMP_CSR_INMSEL ((uint32_t)0x00000070) /!< COMPx inverting input (minus) selection /
EricLew	0:d4e5ad7ad71c	7797	#define COMP_CSR_INMSEL_0 ((uint32_t)0x00000010) /!< COMPx inverting input (minus) selection bit 0 /
EricLew	0:d4e5ad7ad71c	7798	#define COMP_CSR_INMSEL_1 ((uint32_t)0x00000020) /!< COMPx inverting input (minus) selection bit 1 /
EricLew	0:d4e5ad7ad71c	7799	#define COMP_CSR_INMSEL_2 ((uint32_t)0x00000040) /!< COMPx inverting input (minus) selection bit 2 /
EricLew	0:d4e5ad7ad71c	7800
EricLew	0:d4e5ad7ad71c	7801	#define COMP_CSR_INPSEL ((uint32_t)0x00000080) /!< COMPx non inverting input (plus) selection /
EricLew	0:d4e5ad7ad71c	7802	#define COMP_CSR_INPSEL_0 ((uint32_t)0x00000080) /!< COMPx non inverting input (plus) selection bit 0/
EricLew	0:d4e5ad7ad71c	7803	#define COMP_CSR_WINMODE ((uint32_t)0x00000200) /!< COMPx window mode (only available on COMP2) /
EricLew	0:d4e5ad7ad71c	7804	#define COMP_CSR_POLARITY ((uint32_t)0x00008000) /!< COMPx output polarity /
EricLew	0:d4e5ad7ad71c	7805
EricLew	0:d4e5ad7ad71c	7806	#define COMP_CSR_HYST ((uint32_t)0x00030000) /!< COMPx hysteresis /
EricLew	0:d4e5ad7ad71c	7807	#define COMP_CSR_HYST_0 ((uint32_t)0x00010000) /!< COMPx hysteresis bit 0 /
EricLew	0:d4e5ad7ad71c	7808	#define COMP_CSR_HYST_1 ((uint32_t)0x00020000) /!< COMPx hysteresis bit 1 /
EricLew	0:d4e5ad7ad71c	7809
EricLew	0:d4e5ad7ad71c	7810	#define COMP_CSR_BLANKING ((uint32_t)0x001C0000) /!< COMPx blanking source /
EricLew	0:d4e5ad7ad71c	7811	#define COMP_CSR_BLANKING_0 ((uint32_t)0x00040000) /!< COMPx blanking source bit 0 /
EricLew	0:d4e5ad7ad71c	7812	#define COMP_CSR_BLANKING_1 ((uint32_t)0x00080000) /!< COMPx blanking source bit 1 /
EricLew	0:d4e5ad7ad71c	7813	#define COMP_CSR_BLANKING_2 ((uint32_t)0x00100000) /!< COMPx blanking source bit 2 /
EricLew	0:d4e5ad7ad71c	7814
EricLew	0:d4e5ad7ad71c	7815	#define COMP_CSR_BRGEN ((uint32_t)0x00400000) /!< COMPx voltage scaler enable /
EricLew	0:d4e5ad7ad71c	7816	#define COMP_CSR_SCALEN ((uint32_t)0x00800000) /!< COMPx scaler bridge enable /
EricLew	0:d4e5ad7ad71c	7817	#define COMP_CSR_VALUE ((uint32_t)0x40000000) /!< COMPx value /
EricLew	0:d4e5ad7ad71c	7818	#define COMP_CSR_LOCK ((uint32_t)0x80000000) /!< COMPx lock /
EricLew	0:d4e5ad7ad71c	7819
EricLew	0:d4e5ad7ad71c	7820	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7821	/* */
EricLew	0:d4e5ad7ad71c	7822	/* Operational Amplifier (OPAMP) */
EricLew	0:d4e5ad7ad71c	7823	/* */
EricLew	0:d4e5ad7ad71c	7824	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7825	/******************* Bit definition for OPAMPx_CSR register *************/
EricLew	0:d4e5ad7ad71c	7826	#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /!< OPAMP enable /
EricLew	0:d4e5ad7ad71c	7827	#define OPAMP_CSR_OPALPM ((uint32_t)0x00000002) /!< Operational amplifier Low Power Mode /
EricLew	0:d4e5ad7ad71c	7828
EricLew	0:d4e5ad7ad71c	7829	#define OPAMP_CSR_OPAMODE ((uint32_t)0x0000000C) /!< Operational amplifier PGA mode /
EricLew	0:d4e5ad7ad71c	7830	#define OPAMP_CSR_OPAMODE_0 ((uint32_t)0x00000004) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7831	#define OPAMP_CSR_OPAMODE_1 ((uint32_t)0x00000008) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7832
EricLew	0:d4e5ad7ad71c	7833	#define OPAMP_CSR_PGGAIN ((uint32_t)0x00000030) /!< Operational amplifier Programmable amplifier gain value /
EricLew	0:d4e5ad7ad71c	7834	#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00000010) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7835	#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00000020) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7836
EricLew	0:d4e5ad7ad71c	7837	#define OPAMP_CSR_VMSEL ((uint32_t)0x00000300) /!< Inverting input selection /
EricLew	0:d4e5ad7ad71c	7838	#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7839	#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7840
EricLew	0:d4e5ad7ad71c	7841	#define OPAMP_CSR_VPSEL ((uint32_t)0x00000400) /!< Non inverted input selection /
EricLew	0:d4e5ad7ad71c	7842	#define OPAMP_CSR_CALON ((uint32_t)0x00001000) /!< Calibration mode enable /
EricLew	0:d4e5ad7ad71c	7843	#define OPAMP_CSR_CALSEL ((uint32_t)0x00002000) /!< Calibration selection /
EricLew	0:d4e5ad7ad71c	7844	#define OPAMP_CSR_USERTRIM ((uint32_t)0x00004000) /!< User trimming enable /
EricLew	0:d4e5ad7ad71c	7845	#define OPAMP_CSR_CALOUT ((uint32_t)0x00008000) /!< Operational amplifier1 calibration output /
EricLew	0:d4e5ad7ad71c	7846
EricLew	0:d4e5ad7ad71c	7847	/******************* Bit definition for OPAMP1_CSR register *************/
EricLew	0:d4e5ad7ad71c	7848	#define OPAMP1_CSR_OPAEN ((uint32_t)0x00000001) /!< Operational amplifier1 Enable /
EricLew	0:d4e5ad7ad71c	7849	#define OPAMP1_CSR_OPALPM ((uint32_t)0x00000002) /!< Operational amplifier1 Low Power Mode /
EricLew	0:d4e5ad7ad71c	7850
EricLew	0:d4e5ad7ad71c	7851	#define OPAMP1_CSR_OPAMODE ((uint32_t)0x0000000C) /!< Operational amplifier1 PGA mode /
EricLew	0:d4e5ad7ad71c	7852	#define OPAMP1_CSR_OPAMODE_0 ((uint32_t)0x00000004) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7853	#define OPAMP1_CSR_OPAMODE_1 ((uint32_t)0x00000008) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7854
EricLew	0:d4e5ad7ad71c	7855	#define OPAMP1_CSR_PGAGAIN ((uint32_t)0x00000030) /!< Operational amplifier1 Programmable amplifier gain value /
EricLew	0:d4e5ad7ad71c	7856	#define OPAMP1_CSR_PGAGAIN_0 ((uint32_t)0x00000010) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7857	#define OPAMP1_CSR_PGAGAIN_1 ((uint32_t)0x00000020) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7858
EricLew	0:d4e5ad7ad71c	7859	#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000300) /!< Inverting input selection /
EricLew	0:d4e5ad7ad71c	7860	#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7861	#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7862
EricLew	0:d4e5ad7ad71c	7863	#define OPAMP1_CSR_VPSEL ((uint32_t)0x00000400) /!< Non inverted input selection /
EricLew	0:d4e5ad7ad71c	7864	#define OPAMP1_CSR_CALON ((uint32_t)0x00001000) /!< Calibration mode enable /
EricLew	0:d4e5ad7ad71c	7865	#define OPAMP1_CSR_CALSEL ((uint32_t)0x00002000) /!< Calibration selection /
EricLew	0:d4e5ad7ad71c	7866	#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00004000) /!< User trimming enable /
EricLew	0:d4e5ad7ad71c	7867	#define OPAMP1_CSR_CALOUT ((uint32_t)0x00008000) /!< Operational amplifier1 calibration output /
EricLew	0:d4e5ad7ad71c	7868	#define OPAMP1_CSR_OPARANGE ((uint32_t)0x80000000) /!< Operational amplifiers power supply range for stability /
EricLew	0:d4e5ad7ad71c	7869
EricLew	0:d4e5ad7ad71c	7870	/******************* Bit definition for OPAMP2_CSR register *************/
EricLew	0:d4e5ad7ad71c	7871	#define OPAMP2_CSR_OPAEN ((uint32_t)0x00000001) /!< Operational amplifier2 Enable /
EricLew	0:d4e5ad7ad71c	7872	#define OPAMP2_CSR_OPALPM ((uint32_t)0x00000002) /!< Operational amplifier2 Low Power Mode /
EricLew	0:d4e5ad7ad71c	7873
EricLew	0:d4e5ad7ad71c	7874	#define OPAMP2_CSR_OPAMODE ((uint32_t)0x0000000C) /!< Operational amplifier2 PGA mode /
EricLew	0:d4e5ad7ad71c	7875	#define OPAMP2_CSR_OPAMODE_0 ((uint32_t)0x00000004) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7876	#define OPAMP2_CSR_OPAMODE_1 ((uint32_t)0x00000008) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7877
EricLew	0:d4e5ad7ad71c	7878	#define OPAMP2_CSR_PGAGAIN ((uint32_t)0x00000030) /!< Operational amplifier2 Programmable amplifier gain value /
EricLew	0:d4e5ad7ad71c	7879	#define OPAMP2_CSR_PGAGAIN_0 ((uint32_t)0x00000010) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7880	#define OPAMP2_CSR_PGAGAIN_1 ((uint32_t)0x00000020) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7881
EricLew	0:d4e5ad7ad71c	7882	#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000300) /!< Inverting input selection /
EricLew	0:d4e5ad7ad71c	7883	#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	7884	#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	7885
EricLew	0:d4e5ad7ad71c	7886	#define OPAMP2_CSR_VPSEL ((uint32_t)0x00000400) /!< Non inverted input selection /
EricLew	0:d4e5ad7ad71c	7887	#define OPAMP2_CSR_CALON ((uint32_t)0x00001000) /!< Calibration mode enable /
EricLew	0:d4e5ad7ad71c	7888	#define OPAMP2_CSR_CALSEL ((uint32_t)0x00002000) /!< Calibration selection /
EricLew	0:d4e5ad7ad71c	7889	#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00004000) /!< User trimming enable /
EricLew	0:d4e5ad7ad71c	7890	#define OPAMP2_CSR_CALOUT ((uint32_t)0x00008000) /!< Operational amplifier2 calibration output /
EricLew	0:d4e5ad7ad71c	7891
EricLew	0:d4e5ad7ad71c	7892	/***************** Bit definition for OPAMP_OTR register ****************/
EricLew	0:d4e5ad7ad71c	7893	#define OPAMP_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7894	#define OPAMP_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7895
EricLew	0:d4e5ad7ad71c	7896	/***************** Bit definition for OPAMP1_OTR register ****************/
EricLew	0:d4e5ad7ad71c	7897	#define OPAMP1_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7898	#define OPAMP1_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7899
EricLew	0:d4e5ad7ad71c	7900	/***************** Bit definition for OPAMP2_OTR register ****************/
EricLew	0:d4e5ad7ad71c	7901	#define OPAMP2_OTR_TRIMOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7902	#define OPAMP2_OTR_TRIMOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7903
EricLew	0:d4e5ad7ad71c	7904	/***************** Bit definition for OPAMP_LPOTR register **************/
EricLew	0:d4e5ad7ad71c	7905	#define OPAMP_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7906	#define OPAMP_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7907
EricLew	0:d4e5ad7ad71c	7908	/***************** Bit definition for OPAMP1_LPOTR register **************/
EricLew	0:d4e5ad7ad71c	7909	#define OPAMP1_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7910	#define OPAMP1_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7911
EricLew	0:d4e5ad7ad71c	7912	/***************** Bit definition for OPAMP2_LPOTR register **************/
EricLew	0:d4e5ad7ad71c	7913	#define OPAMP2_LPOTR_TRIMLPOFFSETN ((uint32_t)0x0000001F) /!< Trim for NMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7914	#define OPAMP2_LPOTR_TRIMLPOFFSETP ((uint32_t)0x00001F00) /!< Trim for PMOS differential pairs /
EricLew	0:d4e5ad7ad71c	7915
EricLew	0:d4e5ad7ad71c	7916	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7917	/* */
EricLew	0:d4e5ad7ad71c	7918	/* Touch Sensing Controller (TSC) */
EricLew	0:d4e5ad7ad71c	7919	/* */
EricLew	0:d4e5ad7ad71c	7920	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	7921	/***************** Bit definition for TSC_CR register *******************/
EricLew	0:d4e5ad7ad71c	7922	#define TSC_CR_TSCE ((uint32_t)0x00000001) /!<Touch sensing controller enable /
EricLew	0:d4e5ad7ad71c	7923	#define TSC_CR_START ((uint32_t)0x00000002) /!<Start acquisition /
EricLew	0:d4e5ad7ad71c	7924	#define TSC_CR_AM ((uint32_t)0x00000004) /!<Acquisition mode /
EricLew	0:d4e5ad7ad71c	7925	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /!<Synchronization pin polarity /
EricLew	0:d4e5ad7ad71c	7926	#define TSC_CR_IODEF ((uint32_t)0x00000010) /!<IO default mode /
EricLew	0:d4e5ad7ad71c	7927
EricLew	0:d4e5ad7ad71c	7928	#define TSC_CR_MCV ((uint32_t)0x000000E0) /!<MCV[2:0] bits (Max Count Value) /
EricLew	0:d4e5ad7ad71c	7929	#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7930	#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7931	#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7932
EricLew	0:d4e5ad7ad71c	7933	#define TSC_CR_PGPSC ((uint32_t)0x00007000) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
EricLew	0:d4e5ad7ad71c	7934	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7935	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7936	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7937
EricLew	0:d4e5ad7ad71c	7938	#define TSC_CR_SSPSC ((uint32_t)0x00008000) /!<Spread Spectrum Prescaler /
EricLew	0:d4e5ad7ad71c	7939	#define TSC_CR_SSE ((uint32_t)0x00010000) /!<Spread Spectrum Enable /
EricLew	0:d4e5ad7ad71c	7940
EricLew	0:d4e5ad7ad71c	7941	#define TSC_CR_SSD ((uint32_t)0x00FE0000) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
EricLew	0:d4e5ad7ad71c	7942	#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7943	#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7944	#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7945	#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7946	#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	7947	#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	7948	#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	7949
EricLew	0:d4e5ad7ad71c	7950	#define TSC_CR_CTPL ((uint32_t)0x0F000000) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
EricLew	0:d4e5ad7ad71c	7951	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7952	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7953	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7954	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7955
EricLew	0:d4e5ad7ad71c	7956	#define TSC_CR_CTPH ((uint32_t)0xF0000000) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
EricLew	0:d4e5ad7ad71c	7957	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	7958	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	7959	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	7960	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	7961
EricLew	0:d4e5ad7ad71c	7962	/***************** Bit definition for TSC_IER register ******************/
EricLew	0:d4e5ad7ad71c	7963	#define TSC_IER_EOAIE ((uint32_t)0x00000001) /!<End of acquisition interrupt enable /
EricLew	0:d4e5ad7ad71c	7964	#define TSC_IER_MCEIE ((uint32_t)0x00000002) /!<Max count error interrupt enable /
EricLew	0:d4e5ad7ad71c	7965
EricLew	0:d4e5ad7ad71c	7966	/***************** Bit definition for TSC_ICR register ******************/
EricLew	0:d4e5ad7ad71c	7967	#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /!<End of acquisition interrupt clear /
EricLew	0:d4e5ad7ad71c	7968	#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /!<Max count error interrupt clear /
EricLew	0:d4e5ad7ad71c	7969
EricLew	0:d4e5ad7ad71c	7970	/***************** Bit definition for TSC_ISR register ******************/
EricLew	0:d4e5ad7ad71c	7971	#define TSC_ISR_EOAF ((uint32_t)0x00000001) /!<End of acquisition flag /
EricLew	0:d4e5ad7ad71c	7972	#define TSC_ISR_MCEF ((uint32_t)0x00000002) /!<Max count error flag /
EricLew	0:d4e5ad7ad71c	7973
EricLew	0:d4e5ad7ad71c	7974	/***************** Bit definition for TSC_IOHCR register ****************/
EricLew	0:d4e5ad7ad71c	7975	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7976	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7977	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7978	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7979	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7980	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7981	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7982	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7983	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7984	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7985	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7986	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7987	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7988	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7989	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7990	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7991	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7992	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7993	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7994	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7995	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7996	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7997	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7998	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	7999	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8000	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8001	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8002	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8003	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8004	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8005	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8006	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
EricLew	0:d4e5ad7ad71c	8007
EricLew	0:d4e5ad7ad71c	8008	/***************** Bit definition for TSC_IOASCR register ***************/
EricLew	0:d4e5ad7ad71c	8009	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8010	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8011	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8012	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8013	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8014	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8015	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8016	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8017	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8018	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8019	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8020	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8021	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8022	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8023	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8024	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8025	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8026	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8027	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8028	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8029	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8030	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8031	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8032	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8033	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8034	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8035	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8036	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8037	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 analog switch enable /
EricLew	0:d4e5ad7ad71c	8038	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 analog switch enable /
EricLew	0:d4e5ad7ad71c	8039	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 analog switch enable /
EricLew	0:d4e5ad7ad71c	8040	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 analog switch enable /
EricLew	0:d4e5ad7ad71c	8041
EricLew	0:d4e5ad7ad71c	8042	/***************** Bit definition for TSC_IOSCR register ****************/
EricLew	0:d4e5ad7ad71c	8043	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8044	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8045	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8046	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8047	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8048	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8049	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8050	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8051	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8052	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8053	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8054	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8055	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8056	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8057	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8058	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8059	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8060	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8061	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8062	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8063	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8064	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8065	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8066	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8067	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8068	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8069	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8070	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8071	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 sampling mode /
EricLew	0:d4e5ad7ad71c	8072	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 sampling mode /
EricLew	0:d4e5ad7ad71c	8073	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 sampling mode /
EricLew	0:d4e5ad7ad71c	8074	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 sampling mode /
EricLew	0:d4e5ad7ad71c	8075
EricLew	0:d4e5ad7ad71c	8076	/***************** Bit definition for TSC_IOCCR register ****************/
EricLew	0:d4e5ad7ad71c	8077	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8078	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8079	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8080	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8081	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8082	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8083	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8084	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8085	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8086	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8087	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8088	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8089	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8090	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8091	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8092	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8093	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8094	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8095	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8096	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8097	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8098	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8099	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8100	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8101	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8102	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8103	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8104	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8105	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 channel mode /
EricLew	0:d4e5ad7ad71c	8106	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 channel mode /
EricLew	0:d4e5ad7ad71c	8107	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 channel mode /
EricLew	0:d4e5ad7ad71c	8108	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 channel mode /
EricLew	0:d4e5ad7ad71c	8109
EricLew	0:d4e5ad7ad71c	8110	/***************** Bit definition for TSC_IOGCSR register ***************/
EricLew	0:d4e5ad7ad71c	8111	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /!<Analog IO GROUP1 enable /
EricLew	0:d4e5ad7ad71c	8112	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /!<Analog IO GROUP2 enable /
EricLew	0:d4e5ad7ad71c	8113	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /!<Analog IO GROUP3 enable /
EricLew	0:d4e5ad7ad71c	8114	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /!<Analog IO GROUP4 enable /
EricLew	0:d4e5ad7ad71c	8115	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /!<Analog IO GROUP5 enable /
EricLew	0:d4e5ad7ad71c	8116	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /!<Analog IO GROUP6 enable /
EricLew	0:d4e5ad7ad71c	8117	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /!<Analog IO GROUP7 enable /
EricLew	0:d4e5ad7ad71c	8118	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /!<Analog IO GROUP8 enable /
EricLew	0:d4e5ad7ad71c	8119	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /!<Analog IO GROUP1 status /
EricLew	0:d4e5ad7ad71c	8120	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /!<Analog IO GROUP2 status /
EricLew	0:d4e5ad7ad71c	8121	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /!<Analog IO GROUP3 status /
EricLew	0:d4e5ad7ad71c	8122	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /!<Analog IO GROUP4 status /
EricLew	0:d4e5ad7ad71c	8123	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /!<Analog IO GROUP5 status /
EricLew	0:d4e5ad7ad71c	8124	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /!<Analog IO GROUP6 status /
EricLew	0:d4e5ad7ad71c	8125	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /!<Analog IO GROUP7 status /
EricLew	0:d4e5ad7ad71c	8126	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /!<Analog IO GROUP8 status /
EricLew	0:d4e5ad7ad71c	8127
EricLew	0:d4e5ad7ad71c	8128	/***************** Bit definition for TSC_IOGXCR register ***************/
EricLew	0:d4e5ad7ad71c	8129	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /!<CNT[13:0] bits (Counter value) /
EricLew	0:d4e5ad7ad71c	8130
EricLew	0:d4e5ad7ad71c	8131	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8132	/* */
EricLew	0:d4e5ad7ad71c	8133	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
EricLew	0:d4e5ad7ad71c	8134	/* */
EricLew	0:d4e5ad7ad71c	8135	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8136	/**************** Bit definition for USART_CR1 register *****************/
EricLew	0:d4e5ad7ad71c	8137	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
EricLew	0:d4e5ad7ad71c	8138	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
EricLew	0:d4e5ad7ad71c	8139	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
EricLew	0:d4e5ad7ad71c	8140	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
EricLew	0:d4e5ad7ad71c	8141	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8142	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8143	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8144	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8145	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8146	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
EricLew	0:d4e5ad7ad71c	8147	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
EricLew	0:d4e5ad7ad71c	8148	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
EricLew	0:d4e5ad7ad71c	8149	#define USART_CR1_M ((uint32_t)0x10001000) /!< Word length /
EricLew	0:d4e5ad7ad71c	8150	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length - Bit 0 /
EricLew	0:d4e5ad7ad71c	8151	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
EricLew	0:d4e5ad7ad71c	8152	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
EricLew	0:d4e5ad7ad71c	8153	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
EricLew	0:d4e5ad7ad71c	8154	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
EricLew	0:d4e5ad7ad71c	8155	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	8156	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	8157	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	8158	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
EricLew	0:d4e5ad7ad71c	8159	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
EricLew	0:d4e5ad7ad71c	8160	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
EricLew	0:d4e5ad7ad71c	8161	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	8162	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	8163	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	8164	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
EricLew	0:d4e5ad7ad71c	8165	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
EricLew	0:d4e5ad7ad71c	8166	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
EricLew	0:d4e5ad7ad71c	8167	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
EricLew	0:d4e5ad7ad71c	8168	#define USART_CR1_M1 ((uint32_t)0x10000000) /!< Word length - Bit 1 /
EricLew	0:d4e5ad7ad71c	8169
EricLew	0:d4e5ad7ad71c	8170	/**************** Bit definition for USART_CR2 register *****************/
EricLew	0:d4e5ad7ad71c	8171	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
EricLew	0:d4e5ad7ad71c	8172	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
EricLew	0:d4e5ad7ad71c	8173	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8174	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
EricLew	0:d4e5ad7ad71c	8175	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
EricLew	0:d4e5ad7ad71c	8176	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
EricLew	0:d4e5ad7ad71c	8177	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
EricLew	0:d4e5ad7ad71c	8178	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
EricLew	0:d4e5ad7ad71c	8179	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	8180	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	8181	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
EricLew	0:d4e5ad7ad71c	8182	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
EricLew	0:d4e5ad7ad71c	8183	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
EricLew	0:d4e5ad7ad71c	8184	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
EricLew	0:d4e5ad7ad71c	8185	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
EricLew	0:d4e5ad7ad71c	8186	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
EricLew	0:d4e5ad7ad71c	8187	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
EricLew	0:d4e5ad7ad71c	8188	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
EricLew	0:d4e5ad7ad71c	8189	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	8190	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	8191	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
EricLew	0:d4e5ad7ad71c	8192	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
EricLew	0:d4e5ad7ad71c	8193
EricLew	0:d4e5ad7ad71c	8194	/**************** Bit definition for USART_CR3 register *****************/
EricLew	0:d4e5ad7ad71c	8195	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8196	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
EricLew	0:d4e5ad7ad71c	8197	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
EricLew	0:d4e5ad7ad71c	8198	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
EricLew	0:d4e5ad7ad71c	8199	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
EricLew	0:d4e5ad7ad71c	8200	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
EricLew	0:d4e5ad7ad71c	8201	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
EricLew	0:d4e5ad7ad71c	8202	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
EricLew	0:d4e5ad7ad71c	8203	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
EricLew	0:d4e5ad7ad71c	8204	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
EricLew	0:d4e5ad7ad71c	8205	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8206	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
EricLew	0:d4e5ad7ad71c	8207	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
EricLew	0:d4e5ad7ad71c	8208	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
EricLew	0:d4e5ad7ad71c	8209	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
EricLew	0:d4e5ad7ad71c	8210	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
EricLew	0:d4e5ad7ad71c	8211	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
EricLew	0:d4e5ad7ad71c	8212	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	8213	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	8214	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
EricLew	0:d4e5ad7ad71c	8215	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
EricLew	0:d4e5ad7ad71c	8216	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
EricLew	0:d4e5ad7ad71c	8217	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
EricLew	0:d4e5ad7ad71c	8218	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
EricLew	0:d4e5ad7ad71c	8219
EricLew	0:d4e5ad7ad71c	8220	/**************** Bit definition for USART_BRR register *****************/
EricLew	0:d4e5ad7ad71c	8221	#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /!< Fraction of USARTDIV /
EricLew	0:d4e5ad7ad71c	8222	#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
EricLew	0:d4e5ad7ad71c	8223
EricLew	0:d4e5ad7ad71c	8224	/**************** Bit definition for USART_GTPR register ****************/
EricLew	0:d4e5ad7ad71c	8225	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
EricLew	0:d4e5ad7ad71c	8226	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
EricLew	0:d4e5ad7ad71c	8227
EricLew	0:d4e5ad7ad71c	8228
EricLew	0:d4e5ad7ad71c	8229	/***************** Bit definition for USART_RTOR register ***************/
EricLew	0:d4e5ad7ad71c	8230	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
EricLew	0:d4e5ad7ad71c	8231	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
EricLew	0:d4e5ad7ad71c	8232
EricLew	0:d4e5ad7ad71c	8233	/***************** Bit definition for USART_RQR register ****************/
EricLew	0:d4e5ad7ad71c	8234	#define USART_RQR_ABRRQ ((uint16_t)0x0001) /!< Auto-Baud Rate Request /
EricLew	0:d4e5ad7ad71c	8235	#define USART_RQR_SBKRQ ((uint16_t)0x0002) /!< Send Break Request /
EricLew	0:d4e5ad7ad71c	8236	#define USART_RQR_MMRQ ((uint16_t)0x0004) /!< Mute Mode Request /
EricLew	0:d4e5ad7ad71c	8237	#define USART_RQR_RXFRQ ((uint16_t)0x0008) /!< Receive Data flush Request /
EricLew	0:d4e5ad7ad71c	8238	#define USART_RQR_TXFRQ ((uint16_t)0x0010) /!< Transmit data flush Request /
EricLew	0:d4e5ad7ad71c	8239
EricLew	0:d4e5ad7ad71c	8240	/***************** Bit definition for USART_ISR register ****************/
EricLew	0:d4e5ad7ad71c	8241	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
EricLew	0:d4e5ad7ad71c	8242	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
EricLew	0:d4e5ad7ad71c	8243	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
EricLew	0:d4e5ad7ad71c	8244	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
EricLew	0:d4e5ad7ad71c	8245	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
EricLew	0:d4e5ad7ad71c	8246	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
EricLew	0:d4e5ad7ad71c	8247	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
EricLew	0:d4e5ad7ad71c	8248	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
EricLew	0:d4e5ad7ad71c	8249	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
EricLew	0:d4e5ad7ad71c	8250	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
EricLew	0:d4e5ad7ad71c	8251	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
EricLew	0:d4e5ad7ad71c	8252	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
EricLew	0:d4e5ad7ad71c	8253	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
EricLew	0:d4e5ad7ad71c	8254	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
EricLew	0:d4e5ad7ad71c	8255	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
EricLew	0:d4e5ad7ad71c	8256	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
EricLew	0:d4e5ad7ad71c	8257	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
EricLew	0:d4e5ad7ad71c	8258	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
EricLew	0:d4e5ad7ad71c	8259	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
EricLew	0:d4e5ad7ad71c	8260	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
EricLew	0:d4e5ad7ad71c	8261	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
EricLew	0:d4e5ad7ad71c	8262	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
EricLew	0:d4e5ad7ad71c	8263
EricLew	0:d4e5ad7ad71c	8264	/***************** Bit definition for USART_ICR register ****************/
EricLew	0:d4e5ad7ad71c	8265	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
EricLew	0:d4e5ad7ad71c	8266	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
EricLew	0:d4e5ad7ad71c	8267	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
EricLew	0:d4e5ad7ad71c	8268	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
EricLew	0:d4e5ad7ad71c	8269	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
EricLew	0:d4e5ad7ad71c	8270	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
EricLew	0:d4e5ad7ad71c	8271	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
EricLew	0:d4e5ad7ad71c	8272	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
EricLew	0:d4e5ad7ad71c	8273	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
EricLew	0:d4e5ad7ad71c	8274	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
EricLew	0:d4e5ad7ad71c	8275	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
EricLew	0:d4e5ad7ad71c	8276	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
EricLew	0:d4e5ad7ad71c	8277
EricLew	0:d4e5ad7ad71c	8278	/***************** Bit definition for USART_RDR register ****************/
EricLew	0:d4e5ad7ad71c	8279	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
EricLew	0:d4e5ad7ad71c	8280
EricLew	0:d4e5ad7ad71c	8281	/***************** Bit definition for USART_TDR register ****************/
EricLew	0:d4e5ad7ad71c	8282	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
EricLew	0:d4e5ad7ad71c	8283
EricLew	0:d4e5ad7ad71c	8284	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8285	/* */
EricLew	0:d4e5ad7ad71c	8286	/* Single Wire Protocol Master Interface (SWPMI) */
EricLew	0:d4e5ad7ad71c	8287	/* */
EricLew	0:d4e5ad7ad71c	8288	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8289
EricLew	0:d4e5ad7ad71c	8290	/***************** Bit definition for SWPMI_CR register ******************/
EricLew	0:d4e5ad7ad71c	8291	#define SWPMI_CR_RXDMA ((uint32_t)0x00000001) /!<Reception DMA enable /
EricLew	0:d4e5ad7ad71c	8292	#define SWPMI_CR_TXDMA ((uint32_t)0x00000002) /!<Transmission DMA enable /
EricLew	0:d4e5ad7ad71c	8293	#define SWPMI_CR_RXMODE ((uint32_t)0x00000004) /!<Reception buffering mode /
EricLew	0:d4e5ad7ad71c	8294	#define SWPMI_CR_TXMODE ((uint32_t)0x00000008) /!<Transmission buffering mode /
EricLew	0:d4e5ad7ad71c	8295	#define SWPMI_CR_LPBK ((uint32_t)0x00000010) /!<Loopback mode enable /
EricLew	0:d4e5ad7ad71c	8296	#define SWPMI_CR_SWPACT ((uint32_t)0x00000020) /!<Single wire protocol master interface activate /
EricLew	0:d4e5ad7ad71c	8297	#define SWPMI_CR_DEACT ((uint32_t)0x00000400) /!<Single wire protocol master interface deactivate /
EricLew	0:d4e5ad7ad71c	8298
EricLew	0:d4e5ad7ad71c	8299	/***************** Bit definition for SWPMI_BRR register ******************/
EricLew	0:d4e5ad7ad71c	8300	#define SWPMI_BRR_BR ((uint32_t)0x0000003F) /!<BR[5:0] bits (Bitrate prescaler) /
EricLew	0:d4e5ad7ad71c	8301
EricLew	0:d4e5ad7ad71c	8302	/***************** Bit definition for SWPMI_ISR register ******************/
EricLew	0:d4e5ad7ad71c	8303	#define SWPMI_ISR_RXBFF ((uint32_t)0x00000001) /!<Receive buffer full flag /
EricLew	0:d4e5ad7ad71c	8304	#define SWPMI_ISR_TXBEF ((uint32_t)0x00000002) /!<Transmit buffer empty flag /
EricLew	0:d4e5ad7ad71c	8305	#define SWPMI_ISR_RXBERF ((uint32_t)0x00000004) /!<Receive CRC error flag /
EricLew	0:d4e5ad7ad71c	8306	#define SWPMI_ISR_RXOVRF ((uint32_t)0x00000008) /!<Receive overrun error flag /
EricLew	0:d4e5ad7ad71c	8307	#define SWPMI_ISR_TXUNRF ((uint32_t)0x00000010) /!<Transmit underrun error flag /
EricLew	0:d4e5ad7ad71c	8308	#define SWPMI_ISR_RXNE ((uint32_t)0x00000020) /!<Receive data register not empty /
EricLew	0:d4e5ad7ad71c	8309	#define SWPMI_ISR_TXE ((uint32_t)0x00000040) /!<Transmit data register empty /
EricLew	0:d4e5ad7ad71c	8310	#define SWPMI_ISR_TCF ((uint32_t)0x00000080) /!<Transfer complete flag /
EricLew	0:d4e5ad7ad71c	8311	#define SWPMI_ISR_SRF ((uint32_t)0x00000100) /!<Slave resume flag /
EricLew	0:d4e5ad7ad71c	8312	#define SWPMI_ISR_SUSP ((uint32_t)0x00000200) /!<SUSPEND flag /
EricLew	0:d4e5ad7ad71c	8313	#define SWPMI_ISR_DEACTF ((uint32_t)0x00000400) /!<DEACTIVATED flag /
EricLew	0:d4e5ad7ad71c	8314
EricLew	0:d4e5ad7ad71c	8315	/***************** Bit definition for SWPMI_ICR register ******************/
EricLew	0:d4e5ad7ad71c	8316	#define SWPMI_ICR_CRXBFF ((uint32_t)0x00000001) /!<Clear receive buffer full flag /
EricLew	0:d4e5ad7ad71c	8317	#define SWPMI_ICR_CTXBEF ((uint32_t)0x00000002) /!<Clear transmit buffer empty flag /
EricLew	0:d4e5ad7ad71c	8318	#define SWPMI_ICR_CRXBERF ((uint32_t)0x00000004) /!<Clear receive CRC error flag /
EricLew	0:d4e5ad7ad71c	8319	#define SWPMI_ICR_CRXOVRF ((uint32_t)0x00000008) /!<Clear receive overrun error flag /
EricLew	0:d4e5ad7ad71c	8320	#define SWPMI_ICR_CTXUNRF ((uint32_t)0x00000010) /!<Clear transmit underrun error flag /
EricLew	0:d4e5ad7ad71c	8321	#define SWPMI_ICR_CTCF ((uint32_t)0x00000080) /!<Clear transfer complete flag /
EricLew	0:d4e5ad7ad71c	8322	#define SWPMI_ICR_CSRF ((uint32_t)0x00000100) /!<Clear slave resume flag /
EricLew	0:d4e5ad7ad71c	8323
EricLew	0:d4e5ad7ad71c	8324	/***************** Bit definition for SWPMI_IER register ******************/
EricLew	0:d4e5ad7ad71c	8325	#define SWPMI_IER_SRIE ((uint32_t)0x00000100) /!<Slave resume interrupt enable /
EricLew	0:d4e5ad7ad71c	8326	#define SWPMI_IER_TCIE ((uint32_t)0x00000080) /!<Transmit complete interrupt enable /
EricLew	0:d4e5ad7ad71c	8327	#define SWPMI_IER_TIE ((uint32_t)0x00000040) /!<Transmit interrupt enable /
EricLew	0:d4e5ad7ad71c	8328	#define SWPMI_IER_RIE ((uint32_t)0x00000020) /!<Receive interrupt enable /
EricLew	0:d4e5ad7ad71c	8329	#define SWPMI_IER_TXUNRIE ((uint32_t)0x00000010) /!<Transmit underrun error interrupt enable /
EricLew	0:d4e5ad7ad71c	8330	#define SWPMI_IER_RXOVRIE ((uint32_t)0x00000008) /!<Receive overrun error interrupt enable /
EricLew	0:d4e5ad7ad71c	8331	#define SWPMI_IER_RXBERIE ((uint32_t)0x00000004) /!<Receive CRC error interrupt enable /
EricLew	0:d4e5ad7ad71c	8332	#define SWPMI_IER_TXBEIE ((uint32_t)0x00000002) /!<Transmit buffer empty interrupt enable /
EricLew	0:d4e5ad7ad71c	8333	#define SWPMI_IER_RXBFIE ((uint32_t)0x00000001) /!<Receive buffer full interrupt enable /
EricLew	0:d4e5ad7ad71c	8334
EricLew	0:d4e5ad7ad71c	8335	/***************** Bit definition for SWPMI_RFL register ******************/
EricLew	0:d4e5ad7ad71c	8336	#define SWPMI_RFL_RFL ((uint32_t)0x0000001F) /!<RFL[4:0] bits (Receive Frame length) /
EricLew	0:d4e5ad7ad71c	8337	#define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) /
EricLew	0:d4e5ad7ad71c	8338
EricLew	0:d4e5ad7ad71c	8339	/***************** Bit definition for SWPMI_TDR register ******************/
EricLew	0:d4e5ad7ad71c	8340	#define SWPMI_TDR_TD ((uint32_t)0xFFFFFFFF) /!<Transmit Data Register /
EricLew	0:d4e5ad7ad71c	8341
EricLew	0:d4e5ad7ad71c	8342	/***************** Bit definition for SWPMI_RDR register ******************/
EricLew	0:d4e5ad7ad71c	8343	#define SWPMI_RDR_RD ((uint32_t)0xFFFFFFFF) /!<Receive Data Register /
EricLew	0:d4e5ad7ad71c	8344
EricLew	0:d4e5ad7ad71c	8345	/***************** Bit definition for SWPMI_OR register ******************/
EricLew	0:d4e5ad7ad71c	8346	#define SWPMI_OR_TBYP ((uint32_t)0x00000001) /!<SWP Transceiver Bypass /
EricLew	0:d4e5ad7ad71c	8347	#define SWPMI_OR_CLASS ((uint32_t)0x00000002) /!<SWP Voltage Class selection /
EricLew	0:d4e5ad7ad71c	8348
EricLew	0:d4e5ad7ad71c	8349	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8350	/* */
EricLew	0:d4e5ad7ad71c	8351	/* VREFBUF */
EricLew	0:d4e5ad7ad71c	8352	/* */
EricLew	0:d4e5ad7ad71c	8353	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8354	/***************** Bit definition for VREFBUF_CSR register **************/
EricLew	0:d4e5ad7ad71c	8355	#define VREFBUF_CSR_ENVR ((uint32_t)0x00000001) /!<Voltage reference buffer enable /
EricLew	0:d4e5ad7ad71c	8356	#define VREFBUF_CSR_HIZ ((uint32_t)0x00000002) /!<High impedance mode /
EricLew	0:d4e5ad7ad71c	8357	#define VREFBUF_CSR_VRS ((uint32_t)0x00000004) /!<Voltage reference scale /
EricLew	0:d4e5ad7ad71c	8358	#define VREFBUF_CSR_VRR ((uint32_t)0x00000008) /!<Voltage reference buffer ready /
EricLew	0:d4e5ad7ad71c	8359
EricLew	0:d4e5ad7ad71c	8360	/***************** Bit definition for VREFBUF_CCR register ****************/
EricLew	0:d4e5ad7ad71c	8361	#define VREFBUF_CCR_TRIM ((uint32_t)0x0000003F) /!<TRIM[5:0] bits (Trimming code) /
EricLew	0:d4e5ad7ad71c	8362
EricLew	0:d4e5ad7ad71c	8363	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8364	/* */
EricLew	0:d4e5ad7ad71c	8365	/* Window WATCHDOG */
EricLew	0:d4e5ad7ad71c	8366	/* */
EricLew	0:d4e5ad7ad71c	8367	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8368	/***************** Bit definition for WWDG_CR register ******************/
EricLew	0:d4e5ad7ad71c	8369	#define WWDG_CR_T ((uint32_t)0x0000007F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
EricLew	0:d4e5ad7ad71c	8370	#define WWDG_CR_T_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8371	#define WWDG_CR_T_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8372	#define WWDG_CR_T_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8373	#define WWDG_CR_T_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8374	#define WWDG_CR_T_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8375	#define WWDG_CR_T_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8376	#define WWDG_CR_T_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8377
EricLew	0:d4e5ad7ad71c	8378	#define WWDG_CR_WDGA ((uint32_t)0x00000080) /!<Activation bit /
EricLew	0:d4e5ad7ad71c	8379
EricLew	0:d4e5ad7ad71c	8380	/***************** Bit definition for WWDG_CFR register *****************/
EricLew	0:d4e5ad7ad71c	8381	#define WWDG_CFR_W ((uint32_t)0x0000007F) /!<W[6:0] bits (7-bit window value) /
EricLew	0:d4e5ad7ad71c	8382	#define WWDG_CFR_W_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8383	#define WWDG_CFR_W_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8384	#define WWDG_CFR_W_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8385	#define WWDG_CFR_W_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8386	#define WWDG_CFR_W_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8387	#define WWDG_CFR_W_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8388	#define WWDG_CFR_W_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8389
EricLew	0:d4e5ad7ad71c	8390	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /!<WDGTB[1:0] bits (Timer Base) /
EricLew	0:d4e5ad7ad71c	8391	#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8392	#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8393
EricLew	0:d4e5ad7ad71c	8394	#define WWDG_CFR_EWI ((uint32_t)0x00000200) /!<Early Wakeup Interrupt /
EricLew	0:d4e5ad7ad71c	8395
EricLew	0:d4e5ad7ad71c	8396	/***************** Bit definition for WWDG_SR register ******************/
EricLew	0:d4e5ad7ad71c	8397	#define WWDG_SR_EWIF ((uint32_t)0x00000001) /!<Early Wakeup Interrupt Flag /
EricLew	0:d4e5ad7ad71c	8398
EricLew	0:d4e5ad7ad71c	8399
EricLew	0:d4e5ad7ad71c	8400	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8401	/* */
EricLew	0:d4e5ad7ad71c	8402	/* Debug MCU */
EricLew	0:d4e5ad7ad71c	8403	/* */
EricLew	0:d4e5ad7ad71c	8404	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8405	/****************** Bit definition for DBGMCU_IDCODE register ***********/
EricLew	0:d4e5ad7ad71c	8406	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
EricLew	0:d4e5ad7ad71c	8407	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
EricLew	0:d4e5ad7ad71c	8408
EricLew	0:d4e5ad7ad71c	8409	/****************** Bit definition for DBGMCU_CR register ***************/
EricLew	0:d4e5ad7ad71c	8410	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	8411	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	8412	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	8413	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	8414
EricLew	0:d4e5ad7ad71c	8415	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
EricLew	0:d4e5ad7ad71c	8416	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8417	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8418
EricLew	0:d4e5ad7ad71c	8419	/****************** Bit definition for DBGMCU_APB1FZR1 register *********/
EricLew	0:d4e5ad7ad71c	8420	#define DBGMCU_APB1FZR1_DBG_TIM2_STOP ((uint32_t)0x00000001)
EricLew	0:d4e5ad7ad71c	8421	#define DBGMCU_APB1FZR1_DBG_TIM3_STOP ((uint32_t)0x00000002)
EricLew	0:d4e5ad7ad71c	8422	#define DBGMCU_APB1FZR1_DBG_TIM4_STOP ((uint32_t)0x00000004)
EricLew	0:d4e5ad7ad71c	8423	#define DBGMCU_APB1FZR1_DBG_TIM5_STOP ((uint32_t)0x00000008)
EricLew	0:d4e5ad7ad71c	8424	#define DBGMCU_APB1FZR1_DBG_TIM6_STOP ((uint32_t)0x00000010)
EricLew	0:d4e5ad7ad71c	8425	#define DBGMCU_APB1FZR1_DBG_TIM7_STOP ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	8426	#define DBGMCU_APB1FZR1_DBG_RTC_STOP ((uint32_t)0x00000400)
EricLew	0:d4e5ad7ad71c	8427	#define DBGMCU_APB1FZR1_DBG_WWDG_STOP ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	8428	#define DBGMCU_APB1FZR1_DBG_IWDG_STOP ((uint32_t)0x00001000)
EricLew	0:d4e5ad7ad71c	8429	#define DBGMCU_APB1FZR1_DBG_I2C1_STOP ((uint32_t)0x00200000)
EricLew	0:d4e5ad7ad71c	8430	#define DBGMCU_APB1FZR1_DBG_I2C2_STOP ((uint32_t)0x00400000)
EricLew	0:d4e5ad7ad71c	8431	#define DBGMCU_APB1FZR1_DBG_I2C3_STOP ((uint32_t)0x00800000)
EricLew	0:d4e5ad7ad71c	8432	#define DBGMCU_APB1FZR1_DBG_CAN_STOP ((uint32_t)0x02000000)
EricLew	0:d4e5ad7ad71c	8433	#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP ((uint32_t)0x80000000)
EricLew	0:d4e5ad7ad71c	8434
EricLew	0:d4e5ad7ad71c	8435	/****************** Bit definition for DBGMCU_APB1FZR2 register ********/
EricLew	0:d4e5ad7ad71c	8436	#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP ((uint32_t)0x00000020)
EricLew	0:d4e5ad7ad71c	8437
EricLew	0:d4e5ad7ad71c	8438	/****************** Bit definition for DBGMCU_APB2FZ register **********/
EricLew	0:d4e5ad7ad71c	8439	#define DBGMCU_APB2FZ_DBG_TIM1_STOP ((uint32_t)0x00000800)
EricLew	0:d4e5ad7ad71c	8440	#define DBGMCU_APB2FZ_DBG_TIM8_STOP ((uint32_t)0x00002000)
EricLew	0:d4e5ad7ad71c	8441	#define DBGMCU_APB2FZ_DBG_TIM15_STOP ((uint32_t)0x00010000)
EricLew	0:d4e5ad7ad71c	8442	#define DBGMCU_APB2FZ_DBG_TIM16_STOP ((uint32_t)0x00020000)
EricLew	0:d4e5ad7ad71c	8443	#define DBGMCU_APB2FZ_DBG_TIM17_STOP ((uint32_t)0x00040000)
EricLew	0:d4e5ad7ad71c	8444
EricLew	0:d4e5ad7ad71c	8445	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8446	/* */
EricLew	0:d4e5ad7ad71c	8447	/* USB_OTG */
EricLew	0:d4e5ad7ad71c	8448	/* */
EricLew	0:d4e5ad7ad71c	8449	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	8450	/****************** Bit definition for USB_OTG_GOTGCTL register ******************/
EricLew	0:d4e5ad7ad71c	8451	#define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /!< Session request success /
EricLew	0:d4e5ad7ad71c	8452	#define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /!< Session request /
EricLew	0:d4e5ad7ad71c	8453	#define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /!< VBUS valid override enable /
EricLew	0:d4e5ad7ad71c	8454	#define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /!< VBUS valid override value /
EricLew	0:d4e5ad7ad71c	8455	#define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /!< A-peripheral session valid override enable /
EricLew	0:d4e5ad7ad71c	8456	#define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /!< A-peripheral session valid override value /
EricLew	0:d4e5ad7ad71c	8457	#define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /!< B-peripheral session valid override enable /
EricLew	0:d4e5ad7ad71c	8458	#define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /!< B-peripheral session valid override value /
EricLew	0:d4e5ad7ad71c	8459	#define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /!< B-session valid/
EricLew	0:d4e5ad7ad71c	8460
EricLew	0:d4e5ad7ad71c	8461	/****************** Bit definition for USB_OTG_HCFG register ******************/
EricLew	0:d4e5ad7ad71c	8462
EricLew	0:d4e5ad7ad71c	8463	#define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /!< FS/LS PHY clock select /
EricLew	0:d4e5ad7ad71c	8464	#define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8465	#define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8466	#define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /!< FS- and LS-only support /
EricLew	0:d4e5ad7ad71c	8467
EricLew	0:d4e5ad7ad71c	8468	/****************** Bit definition for USB_OTG_DCFG register ******************/
EricLew	0:d4e5ad7ad71c	8469
EricLew	0:d4e5ad7ad71c	8470	#define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /!< Device speed /
EricLew	0:d4e5ad7ad71c	8471	#define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8472	#define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8473	#define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /!< Nonzero-length status OUT handshake /
EricLew	0:d4e5ad7ad71c	8474	#define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /!< Device address /
EricLew	0:d4e5ad7ad71c	8475	#define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8476	#define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8477	#define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8478	#define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8479	#define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8480	#define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8481	#define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8482	#define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /!< Periodic (micro)frame interval /
EricLew	0:d4e5ad7ad71c	8483	#define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8484	#define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8485	#define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /!< Periodic scheduling interval /
EricLew	0:d4e5ad7ad71c	8486	#define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8487	#define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8488
EricLew	0:d4e5ad7ad71c	8489	/****************** Bit definition for USB_OTG_PCGCR register ******************/
EricLew	0:d4e5ad7ad71c	8490	#define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /!< Stop PHY clock /
EricLew	0:d4e5ad7ad71c	8491	#define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /!< Gate HCLK /
EricLew	0:d4e5ad7ad71c	8492	#define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /!< PHY suspended /
EricLew	0:d4e5ad7ad71c	8493
EricLew	0:d4e5ad7ad71c	8494	/****************** Bit definition for USB_OTG_GOTGINT register ******************/
EricLew	0:d4e5ad7ad71c	8495	#define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /!< Session end detected /
EricLew	0:d4e5ad7ad71c	8496	#define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /!< Session request success status change /
EricLew	0:d4e5ad7ad71c	8497	#define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /!< Host negotiation success status change /
EricLew	0:d4e5ad7ad71c	8498	#define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /!< Host negotiation detected /
EricLew	0:d4e5ad7ad71c	8499	#define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /!< A-device timeout change /
EricLew	0:d4e5ad7ad71c	8500	#define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /!< Debounce done /
EricLew	0:d4e5ad7ad71c	8501
EricLew	0:d4e5ad7ad71c	8502	/****************** Bit definition for USB_OTG_DCTL register ******************/
EricLew	0:d4e5ad7ad71c	8503	#define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /!< Remote wakeup signaling /
EricLew	0:d4e5ad7ad71c	8504	#define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /!< Soft disconnect /
EricLew	0:d4e5ad7ad71c	8505	#define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /!< Global IN NAK status /
EricLew	0:d4e5ad7ad71c	8506	#define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /!< Global OUT NAK status /
EricLew	0:d4e5ad7ad71c	8507
EricLew	0:d4e5ad7ad71c	8508	#define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /!< Test control /
EricLew	0:d4e5ad7ad71c	8509	#define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8510	#define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8511	#define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8512	#define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /!< Set global IN NAK /
EricLew	0:d4e5ad7ad71c	8513	#define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /!< Clear global IN NAK /
EricLew	0:d4e5ad7ad71c	8514	#define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /!< Set global OUT NAK /
EricLew	0:d4e5ad7ad71c	8515	#define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /!< Clear global OUT NAK /
EricLew	0:d4e5ad7ad71c	8516	#define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /!< Power-on programming done /
EricLew	0:d4e5ad7ad71c	8517
EricLew	0:d4e5ad7ad71c	8518	/****************** Bit definition for USB_OTG_HFIR register ******************/
EricLew	0:d4e5ad7ad71c	8519	#define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /!< Frame interval /
EricLew	0:d4e5ad7ad71c	8520
EricLew	0:d4e5ad7ad71c	8521	/****************** Bit definition for USB_OTG_HFNUM register ******************/
EricLew	0:d4e5ad7ad71c	8522	#define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /!< Frame number /
EricLew	0:d4e5ad7ad71c	8523	#define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /!< Frame time remaining /
EricLew	0:d4e5ad7ad71c	8524
EricLew	0:d4e5ad7ad71c	8525	/****************** Bit definition for USB_OTG_DSTS register ******************/
EricLew	0:d4e5ad7ad71c	8526	#define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /!< Suspend status /
EricLew	0:d4e5ad7ad71c	8527
EricLew	0:d4e5ad7ad71c	8528	#define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /!< Enumerated speed /
EricLew	0:d4e5ad7ad71c	8529	#define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8530	#define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8531	#define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /!< Erratic error /
EricLew	0:d4e5ad7ad71c	8532	#define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /!< Frame number of the received SOF /
EricLew	0:d4e5ad7ad71c	8533
EricLew	0:d4e5ad7ad71c	8534	/****************** Bit definition for USB_OTG_GAHBCFG register ******************/
EricLew	0:d4e5ad7ad71c	8535	#define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /!< Global interrupt mask /
EricLew	0:d4e5ad7ad71c	8536	#define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /!< Burst length/type /
EricLew	0:d4e5ad7ad71c	8537	#define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8538	#define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8539	#define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8540	#define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8541	#define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /!< DMA enable /
EricLew	0:d4e5ad7ad71c	8542	#define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /!< TxFIFO empty level /
EricLew	0:d4e5ad7ad71c	8543	#define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /!< Periodic TxFIFO empty level /
EricLew	0:d4e5ad7ad71c	8544
EricLew	0:d4e5ad7ad71c	8545	/****************** Bit definition for USB_OTG_GUSBCFG register ******************/
EricLew	0:d4e5ad7ad71c	8546
EricLew	0:d4e5ad7ad71c	8547	#define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /!< FS timeout calibration /
EricLew	0:d4e5ad7ad71c	8548	#define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8549	#define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8550	#define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8551	#define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
EricLew	0:d4e5ad7ad71c	8552	#define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /!< SRP-capable /
EricLew	0:d4e5ad7ad71c	8553	#define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /!< HNP-capable /
EricLew	0:d4e5ad7ad71c	8554	#define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /!< USB turnaround time /
EricLew	0:d4e5ad7ad71c	8555	#define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8556	#define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8557	#define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8558	#define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8559	#define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /!< PHY Low-power clock select /
EricLew	0:d4e5ad7ad71c	8560	#define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /!< ULPI FS/LS select /
EricLew	0:d4e5ad7ad71c	8561	#define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /!< ULPI Auto-resume /
EricLew	0:d4e5ad7ad71c	8562	#define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /!< ULPI Clock SuspendM /
EricLew	0:d4e5ad7ad71c	8563	#define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /!< ULPI External VBUS Drive /
EricLew	0:d4e5ad7ad71c	8564	#define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /!< ULPI external VBUS indicator /
EricLew	0:d4e5ad7ad71c	8565	#define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /!< TermSel DLine pulsing selection /
EricLew	0:d4e5ad7ad71c	8566	#define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /!< Indicator complement /
EricLew	0:d4e5ad7ad71c	8567	#define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /!< Indicator pass through /
EricLew	0:d4e5ad7ad71c	8568	#define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /!< ULPI interface protect disable /
EricLew	0:d4e5ad7ad71c	8569	#define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /!< Forced host mode /
EricLew	0:d4e5ad7ad71c	8570	#define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /!< Forced peripheral mode /
EricLew	0:d4e5ad7ad71c	8571	#define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /!< Corrupt Tx packet /
EricLew	0:d4e5ad7ad71c	8572
EricLew	0:d4e5ad7ad71c	8573	/****************** Bit definition for USB_OTG_GRSTCTL register ******************/
EricLew	0:d4e5ad7ad71c	8574	#define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /!< Core soft reset /
EricLew	0:d4e5ad7ad71c	8575	#define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /!< HCLK soft reset /
EricLew	0:d4e5ad7ad71c	8576	#define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /!< Host frame counter reset /
EricLew	0:d4e5ad7ad71c	8577	#define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /!< RxFIFO flush /
EricLew	0:d4e5ad7ad71c	8578	#define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /!< TxFIFO flush /
EricLew	0:d4e5ad7ad71c	8579	#define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /!< TxFIFO number /
EricLew	0:d4e5ad7ad71c	8580	#define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8581	#define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8582	#define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8583	#define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8584	#define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8585	#define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /!< DMA request signal /
EricLew	0:d4e5ad7ad71c	8586	#define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /!< AHB master idle /
EricLew	0:d4e5ad7ad71c	8587
EricLew	0:d4e5ad7ad71c	8588	/****************** Bit definition for USB_OTG_DIEPMSK register ******************/
EricLew	0:d4e5ad7ad71c	8589	#define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
EricLew	0:d4e5ad7ad71c	8590	#define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
EricLew	0:d4e5ad7ad71c	8591	#define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
EricLew	0:d4e5ad7ad71c	8592	#define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
EricLew	0:d4e5ad7ad71c	8593	#define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
EricLew	0:d4e5ad7ad71c	8594	#define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
EricLew	0:d4e5ad7ad71c	8595	#define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
EricLew	0:d4e5ad7ad71c	8596	#define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
EricLew	0:d4e5ad7ad71c	8597
EricLew	0:d4e5ad7ad71c	8598	/****************** Bit definition for USB_OTG_HPTXSTS register ******************/
EricLew	0:d4e5ad7ad71c	8599	#define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /!< Periodic transmit data FIFO space available /
EricLew	0:d4e5ad7ad71c	8600	#define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /!< Periodic transmit request queue space available /
EricLew	0:d4e5ad7ad71c	8601	#define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8602	#define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8603	#define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8604	#define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8605	#define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8606	#define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8607	#define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8608	#define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	8609
EricLew	0:d4e5ad7ad71c	8610	#define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /!< Top of the periodic transmit request queue /
EricLew	0:d4e5ad7ad71c	8611	#define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8612	#define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8613	#define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8614	#define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8615	#define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8616	#define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8617	#define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8618	#define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	8619
EricLew	0:d4e5ad7ad71c	8620	/****************** Bit definition for USB_OTG_HAINT register ******************/
EricLew	0:d4e5ad7ad71c	8621	#define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /!< Channel interrupts /
EricLew	0:d4e5ad7ad71c	8622
EricLew	0:d4e5ad7ad71c	8623	/****************** Bit definition for USB_OTG_DOEPMSK register ******************/
EricLew	0:d4e5ad7ad71c	8624	#define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
EricLew	0:d4e5ad7ad71c	8625	#define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
EricLew	0:d4e5ad7ad71c	8626	#define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /!< SETUP phase done mask /
EricLew	0:d4e5ad7ad71c	8627	#define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled mask /
EricLew	0:d4e5ad7ad71c	8628	#define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received mask /
EricLew	0:d4e5ad7ad71c	8629	#define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /!< OUT packet error mask /
EricLew	0:d4e5ad7ad71c	8630	#define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
EricLew	0:d4e5ad7ad71c	8631
EricLew	0:d4e5ad7ad71c	8632	/****************** Bit definition for USB_OTG_GINTSTS register ******************/
EricLew	0:d4e5ad7ad71c	8633	#define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /!< Current mode of operation /
EricLew	0:d4e5ad7ad71c	8634	#define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /!< Mode mismatch interrupt /
EricLew	0:d4e5ad7ad71c	8635	#define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt /
EricLew	0:d4e5ad7ad71c	8636	#define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /!< Start of frame /
EricLew	0:d4e5ad7ad71c	8637	#define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /!< RxFIFO nonempty /
EricLew	0:d4e5ad7ad71c	8638	#define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty /
EricLew	0:d4e5ad7ad71c	8639	#define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /!< Global IN nonperiodic NAK effective /
EricLew	0:d4e5ad7ad71c	8640	#define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /!< Global OUT NAK effective /
EricLew	0:d4e5ad7ad71c	8641	#define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /!< Early suspend /
EricLew	0:d4e5ad7ad71c	8642	#define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /!< USB suspend /
EricLew	0:d4e5ad7ad71c	8643	#define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /!< USB reset /
EricLew	0:d4e5ad7ad71c	8644	#define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /!< Enumeration done /
EricLew	0:d4e5ad7ad71c	8645	#define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt /
EricLew	0:d4e5ad7ad71c	8646	#define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /!< End of periodic frame interrupt /
EricLew	0:d4e5ad7ad71c	8647	#define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /!< IN endpoint interrupt /
EricLew	0:d4e5ad7ad71c	8648	#define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /!< OUT endpoint interrupt /
EricLew	0:d4e5ad7ad71c	8649	#define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer /
EricLew	0:d4e5ad7ad71c	8650	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /!< Incomplete periodic transfer /
EricLew	0:d4e5ad7ad71c	8651	#define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /!< Data fetch suspended /
EricLew	0:d4e5ad7ad71c	8652	#define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /!< Host port interrupt /
EricLew	0:d4e5ad7ad71c	8653	#define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /!< Host channels interrupt /
EricLew	0:d4e5ad7ad71c	8654	#define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /!< Periodic TxFIFO empty /
EricLew	0:d4e5ad7ad71c	8655	#define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /!< LPM interrupt /
EricLew	0:d4e5ad7ad71c	8656	#define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /!< Connector ID status change /
EricLew	0:d4e5ad7ad71c	8657	#define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt /
EricLew	0:d4e5ad7ad71c	8658	#define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /!< Session request/new session detected interrupt /
EricLew	0:d4e5ad7ad71c	8659	#define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt /
EricLew	0:d4e5ad7ad71c	8660
EricLew	0:d4e5ad7ad71c	8661	/****************** Bit definition for USB_OTG_GINTMSK register ******************/
EricLew	0:d4e5ad7ad71c	8662
EricLew	0:d4e5ad7ad71c	8663	#define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /!< Mode mismatch interrupt mask /
EricLew	0:d4e5ad7ad71c	8664	#define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /!< OTG interrupt mask /
EricLew	0:d4e5ad7ad71c	8665	#define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /!< Start of frame mask /
EricLew	0:d4e5ad7ad71c	8666	#define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /!< Receive FIFO nonempty mask /
EricLew	0:d4e5ad7ad71c	8667	#define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /!< Nonperiodic TxFIFO empty mask /
EricLew	0:d4e5ad7ad71c	8668	#define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /!< Global nonperiodic IN NAK effective mask /
EricLew	0:d4e5ad7ad71c	8669	#define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /!< Global OUT NAK effective mask /
EricLew	0:d4e5ad7ad71c	8670	#define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /!< Early suspend mask /
EricLew	0:d4e5ad7ad71c	8671	#define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /!< USB suspend mask /
EricLew	0:d4e5ad7ad71c	8672	#define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /!< USB reset mask /
EricLew	0:d4e5ad7ad71c	8673	#define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /!< Enumeration done mask /
EricLew	0:d4e5ad7ad71c	8674	#define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /!< Isochronous OUT packet dropped interrupt mask /
EricLew	0:d4e5ad7ad71c	8675	#define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /!< End of periodic frame interrupt mask /
EricLew	0:d4e5ad7ad71c	8676	#define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /!< Endpoint mismatch interrupt mask /
EricLew	0:d4e5ad7ad71c	8677	#define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /!< IN endpoints interrupt mask /
EricLew	0:d4e5ad7ad71c	8678	#define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /!< OUT endpoints interrupt mask /
EricLew	0:d4e5ad7ad71c	8679	#define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /!< Incomplete isochronous IN transfer mask /
EricLew	0:d4e5ad7ad71c	8680	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /!< Incomplete periodic transfer mask /
EricLew	0:d4e5ad7ad71c	8681	#define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /!< Data fetch suspended mask /
EricLew	0:d4e5ad7ad71c	8682	#define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /!< Host port interrupt mask /
EricLew	0:d4e5ad7ad71c	8683	#define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /!< Host channels interrupt mask /
EricLew	0:d4e5ad7ad71c	8684	#define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /!< Periodic TxFIFO empty mask /
EricLew	0:d4e5ad7ad71c	8685	#define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /!< LPM interrupt Mask /
EricLew	0:d4e5ad7ad71c	8686	#define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /!< Connector ID status change mask /
EricLew	0:d4e5ad7ad71c	8687	#define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /!< Disconnect detected interrupt mask /
EricLew	0:d4e5ad7ad71c	8688	#define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /!< Session request/new session detected interrupt mask /
EricLew	0:d4e5ad7ad71c	8689	#define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /!< Resume/remote wakeup detected interrupt mask /
EricLew	0:d4e5ad7ad71c	8690
EricLew	0:d4e5ad7ad71c	8691	/****************** Bit definition for USB_OTG_DAINT register ******************/
EricLew	0:d4e5ad7ad71c	8692	#define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /!< IN endpoint interrupt bits /
EricLew	0:d4e5ad7ad71c	8693	#define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /!< OUT endpoint interrupt bits /
EricLew	0:d4e5ad7ad71c	8694
EricLew	0:d4e5ad7ad71c	8695	/****************** Bit definition for USB_OTG_HAINTMSK register ******************/
EricLew	0:d4e5ad7ad71c	8696	#define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /!< Channel interrupt mask /
EricLew	0:d4e5ad7ad71c	8697
EricLew	0:d4e5ad7ad71c	8698	/****************** Bit definition for USB_OTG_GRXSTSP register ******************/
EricLew	0:d4e5ad7ad71c	8699	#define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /!< IN EP interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8700	#define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /!< OUT EP interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8701	#define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /!< OUT EP interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8702	#define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /!< OUT EP interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8703
EricLew	0:d4e5ad7ad71c	8704	/****************** Bit definition for USB_OTG_DAINTMSK register ******************/
EricLew	0:d4e5ad7ad71c	8705	#define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /!< IN EP interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8706	#define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /!< OUT EP interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8707
EricLew	0:d4e5ad7ad71c	8708	/****************** Bit definition for OTG register ******************/
EricLew	0:d4e5ad7ad71c	8709
EricLew	0:d4e5ad7ad71c	8710	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
EricLew	0:d4e5ad7ad71c	8711	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8712	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8713	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8714	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8715	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
EricLew	0:d4e5ad7ad71c	8716	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
EricLew	0:d4e5ad7ad71c	8717	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8718	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8719	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
EricLew	0:d4e5ad7ad71c	8720	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8721	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8722	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8723	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8724	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
EricLew	0:d4e5ad7ad71c	8725	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8726	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8727	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8728	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8729	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
EricLew	0:d4e5ad7ad71c	8730	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8731	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8732	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8733	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8734
EricLew	0:d4e5ad7ad71c	8735	/****************** Bit definition for OTG register ******************/
EricLew	0:d4e5ad7ad71c	8736
EricLew	0:d4e5ad7ad71c	8737	#define USB_OTG_CHNUM ((uint32_t)0x0000000F) /!< Channel number /
EricLew	0:d4e5ad7ad71c	8738	#define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8739	#define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8740	#define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8741	#define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8742	#define USB_OTG_BCNT ((uint32_t)0x00007FF0) /!< Byte count /
EricLew	0:d4e5ad7ad71c	8743	#define USB_OTG_DPID ((uint32_t)0x00018000) /!< Data PID /
EricLew	0:d4e5ad7ad71c	8744	#define USB_OTG_DPID_0 ((uint32_t)0x00008000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8745	#define USB_OTG_DPID_1 ((uint32_t)0x00010000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8746	#define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /!< Packet status /
EricLew	0:d4e5ad7ad71c	8747	#define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8748	#define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8749	#define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8750	#define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8751	#define USB_OTG_EPNUM ((uint32_t)0x0000000F) /!< Endpoint number /
EricLew	0:d4e5ad7ad71c	8752	#define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8753	#define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8754	#define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8755	#define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8756	#define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /!< Frame number /
EricLew	0:d4e5ad7ad71c	8757	#define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8758	#define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8759	#define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8760	#define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8761
EricLew	0:d4e5ad7ad71c	8762	/****************** Bit definition for USB_OTG_GRXFSIZ register ******************/
EricLew	0:d4e5ad7ad71c	8763	#define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /!< RxFIFO depth /
EricLew	0:d4e5ad7ad71c	8764
EricLew	0:d4e5ad7ad71c	8765	/****************** Bit definition for USB_OTG_DVBUSDIS register ******************/
EricLew	0:d4e5ad7ad71c	8766	#define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /!< Device VBUS discharge time /
EricLew	0:d4e5ad7ad71c	8767
EricLew	0:d4e5ad7ad71c	8768	/****************** Bit definition for OTG register ******************/
EricLew	0:d4e5ad7ad71c	8769	#define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /!< Nonperiodic transmit RAM start address /
EricLew	0:d4e5ad7ad71c	8770	#define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /!< Nonperiodic TxFIFO depth /
EricLew	0:d4e5ad7ad71c	8771	#define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /!< Endpoint 0 transmit RAM start address /
EricLew	0:d4e5ad7ad71c	8772	#define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /!< Endpoint 0 TxFIFO depth /
EricLew	0:d4e5ad7ad71c	8773
EricLew	0:d4e5ad7ad71c	8774	/****************** Bit definition for USB_OTG_DVBUSPULSE register ******************/
EricLew	0:d4e5ad7ad71c	8775	#define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /!< Device VBUS pulsing time /
EricLew	0:d4e5ad7ad71c	8776
EricLew	0:d4e5ad7ad71c	8777	/****************** Bit definition for USB_OTG_GNPTXSTS register ******************/
EricLew	0:d4e5ad7ad71c	8778	#define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /!< Nonperiodic TxFIFO space available /
EricLew	0:d4e5ad7ad71c	8779
EricLew	0:d4e5ad7ad71c	8780	#define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /!< Nonperiodic transmit request queue space available /
EricLew	0:d4e5ad7ad71c	8781	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8782	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8783	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8784	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8785	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8786	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8787	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8788	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	8789
EricLew	0:d4e5ad7ad71c	8790	#define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /!< Top of the nonperiodic transmit request queue /
EricLew	0:d4e5ad7ad71c	8791	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8792	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8793	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8794	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8795	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8796	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8797	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8798
EricLew	0:d4e5ad7ad71c	8799	/****************** Bit definition for USB_OTG_DTHRCTL register *************/
EricLew	0:d4e5ad7ad71c	8800	#define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /!< Nonisochronous IN endpoints threshold enable /
EricLew	0:d4e5ad7ad71c	8801	#define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /!< ISO IN endpoint threshold enable /
EricLew	0:d4e5ad7ad71c	8802
EricLew	0:d4e5ad7ad71c	8803	#define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /!< Transmit threshold length /
EricLew	0:d4e5ad7ad71c	8804	#define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8805	#define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8806	#define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8807	#define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8808	#define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8809	#define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8810	#define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8811	#define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	8812	#define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /!<Bit 8 /
EricLew	0:d4e5ad7ad71c	8813	#define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /!< Receive threshold enable /
EricLew	0:d4e5ad7ad71c	8814
EricLew	0:d4e5ad7ad71c	8815	#define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /!< Receive threshold length /
EricLew	0:d4e5ad7ad71c	8816	#define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8817	#define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8818	#define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8819	#define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8820	#define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8821	#define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8822	#define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8823	#define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /!<Bit 7 /
EricLew	0:d4e5ad7ad71c	8824	#define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /!<Bit 8 /
EricLew	0:d4e5ad7ad71c	8825	#define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /!< Arbiter parking enable /
EricLew	0:d4e5ad7ad71c	8826
EricLew	0:d4e5ad7ad71c	8827	/****************** Bit definition for USB_OTG_DIEPEMPMSK register *************/
EricLew	0:d4e5ad7ad71c	8828	#define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /!< IN EP Tx FIFO empty interrupt mask bits /
EricLew	0:d4e5ad7ad71c	8829
EricLew	0:d4e5ad7ad71c	8830	/****************** Bit definition for USB_OTG_DEACHINT register ******************/
EricLew	0:d4e5ad7ad71c	8831	#define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /!< IN endpoint 1interrupt bit /
EricLew	0:d4e5ad7ad71c	8832	#define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /!< OUT endpoint 1 interrupt bit /
EricLew	0:d4e5ad7ad71c	8833
EricLew	0:d4e5ad7ad71c	8834	/****************** Bit definition for USB_OTG_GCCFG register ******************/
EricLew	0:d4e5ad7ad71c	8835	#define USB_OTG_GCCFG_DCDET ((uint32_t)0x00000001) /!< Data contact detection (DCD) status /
EricLew	0:d4e5ad7ad71c	8836	#define USB_OTG_GCCFG_PDET ((uint32_t)0x00000002) /!< Primary detection (PD) status /
EricLew	0:d4e5ad7ad71c	8837	#define USB_OTG_GCCFG_SDET ((uint32_t)0x00000004) /!< Secondary detection (SD) status /
EricLew	0:d4e5ad7ad71c	8838	#define USB_OTG_GCCFG_PS2DET ((uint32_t)0x00000008) /!< DM pull-up detection status /
EricLew	0:d4e5ad7ad71c	8839	#define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /!< Power down /
EricLew	0:d4e5ad7ad71c	8840	#define USB_OTG_GCCFG_BCDEN ((uint32_t)0x00020000) /!< Battery charging detector (BCD) enable /
EricLew	0:d4e5ad7ad71c	8841	#define USB_OTG_GCCFG_DCDEN ((uint32_t)0x00040000) /!< Data contact detection (DCD) mode enable/
EricLew	0:d4e5ad7ad71c	8842	#define USB_OTG_GCCFG_PDEN ((uint32_t)0x00080000) /!< Primary detection (PD) mode enable/
EricLew	0:d4e5ad7ad71c	8843	#define USB_OTG_GCCFG_SDEN ((uint32_t)0x00100000) /!< Secondary detection (SD) mode enable /
EricLew	0:d4e5ad7ad71c	8844	#define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /!< Secondary detection (SD) mode enable /
EricLew	0:d4e5ad7ad71c	8845
EricLew	0:d4e5ad7ad71c	8846	/****************** Bit definition for USB_OTG_GPWRDN) register ******************/
EricLew	0:d4e5ad7ad71c	8847	#define USB_OTG_GPWRDN_DISABLEVBUS ((uint32_t)0x00000040) /!< Power down /
EricLew	0:d4e5ad7ad71c	8848
EricLew	0:d4e5ad7ad71c	8849	/****************** Bit definition for USB_OTG_DEACHINTMSK register ******************/
EricLew	0:d4e5ad7ad71c	8850	#define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /!< IN Endpoint 1 interrupt mask bit /
EricLew	0:d4e5ad7ad71c	8851	#define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /!< OUT Endpoint 1 interrupt mask bit /
EricLew	0:d4e5ad7ad71c	8852
EricLew	0:d4e5ad7ad71c	8853	/****************** Bit definition for USB_OTG_CID register ******************/
EricLew	0:d4e5ad7ad71c	8854	#define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /!< Product ID field /
EricLew	0:d4e5ad7ad71c	8855
EricLew	0:d4e5ad7ad71c	8856
EricLew	0:d4e5ad7ad71c	8857	/****************** Bit definition for USB_OTG_GHWCFG3 register ******************/
EricLew	0:d4e5ad7ad71c	8858	#define USB_OTG_GHWCFG3_LPMMode ((uint32_t)0x00004000) /* LPM mode specified for Mode of Operation */
EricLew	0:d4e5ad7ad71c	8859
EricLew	0:d4e5ad7ad71c	8860	/****************** Bit definition for USB_OTG_GLPMCFG register ******************/
EricLew	0:d4e5ad7ad71c	8861	#define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /* Enable best effort service latency */
EricLew	0:d4e5ad7ad71c	8862	#define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /* LPM retry count status */
EricLew	0:d4e5ad7ad71c	8863	#define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /* Send LPM transaction */
EricLew	0:d4e5ad7ad71c	8864	#define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /* LPM retry count */
EricLew	0:d4e5ad7ad71c	8865	#define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /* LPMCHIDX: */
EricLew	0:d4e5ad7ad71c	8866	#define USB_OTG_GLPMCFG_L1ResumeOK ((uint32_t)0x00010000) /* Sleep State Resume OK */
EricLew	0:d4e5ad7ad71c	8867	#define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /* Port sleep status */
EricLew	0:d4e5ad7ad71c	8868	#define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /* LPM response */
EricLew	0:d4e5ad7ad71c	8869	#define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /* L1 deep sleep enable */
EricLew	0:d4e5ad7ad71c	8870	#define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /* BESL threshold */
EricLew	0:d4e5ad7ad71c	8871	#define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /* L1 shallow sleep enable */
EricLew	0:d4e5ad7ad71c	8872	#define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /* bRemoteWake value received with last ACKed LPM Token */
EricLew	0:d4e5ad7ad71c	8873	#define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /* BESL value received with last ACKed LPM Token */
EricLew	0:d4e5ad7ad71c	8874	#define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /* LPM Token acknowledge enable*/
EricLew	0:d4e5ad7ad71c	8875	#define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /* LPM support enable */
EricLew	0:d4e5ad7ad71c	8876
EricLew	0:d4e5ad7ad71c	8877
EricLew	0:d4e5ad7ad71c	8878	/****************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******************/
EricLew	0:d4e5ad7ad71c	8879	#define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
EricLew	0:d4e5ad7ad71c	8880	#define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
EricLew	0:d4e5ad7ad71c	8881	#define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask (nonisochronous endpoints) /
EricLew	0:d4e5ad7ad71c	8882	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
EricLew	0:d4e5ad7ad71c	8883	#define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
EricLew	0:d4e5ad7ad71c	8884	#define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
EricLew	0:d4e5ad7ad71c	8885	#define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< FIFO underrun mask /
EricLew	0:d4e5ad7ad71c	8886	#define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
EricLew	0:d4e5ad7ad71c	8887	#define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
EricLew	0:d4e5ad7ad71c	8888
EricLew	0:d4e5ad7ad71c	8889	/****************** Bit definition for USB_OTG_HPRT register ******************/
EricLew	0:d4e5ad7ad71c	8890	#define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /!< Port connect status /
EricLew	0:d4e5ad7ad71c	8891	#define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /!< Port connect detected /
EricLew	0:d4e5ad7ad71c	8892	#define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /!< Port enable /
EricLew	0:d4e5ad7ad71c	8893	#define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /!< Port enable/disable change /
EricLew	0:d4e5ad7ad71c	8894	#define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /!< Port overcurrent active /
EricLew	0:d4e5ad7ad71c	8895	#define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /!< Port overcurrent change /
EricLew	0:d4e5ad7ad71c	8896	#define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /!< Port resume /
EricLew	0:d4e5ad7ad71c	8897	#define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /!< Port suspend /
EricLew	0:d4e5ad7ad71c	8898	#define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /!< Port reset /
EricLew	0:d4e5ad7ad71c	8899
EricLew	0:d4e5ad7ad71c	8900	#define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /!< Port line status /
EricLew	0:d4e5ad7ad71c	8901	#define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8902	#define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8903	#define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /!< Port power /
EricLew	0:d4e5ad7ad71c	8904
EricLew	0:d4e5ad7ad71c	8905	#define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /!< Port test control /
EricLew	0:d4e5ad7ad71c	8906	#define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8907	#define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8908	#define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8909	#define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8910
EricLew	0:d4e5ad7ad71c	8911	#define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /!< Port speed /
EricLew	0:d4e5ad7ad71c	8912	#define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8913	#define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8914
EricLew	0:d4e5ad7ad71c	8915	/****************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******************/
EricLew	0:d4e5ad7ad71c	8916	#define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /!< Transfer completed interrupt mask /
EricLew	0:d4e5ad7ad71c	8917	#define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /!< Endpoint disabled interrupt mask /
EricLew	0:d4e5ad7ad71c	8918	#define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /!< Timeout condition mask /
EricLew	0:d4e5ad7ad71c	8919	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /!< IN token received when TxFIFO empty mask /
EricLew	0:d4e5ad7ad71c	8920	#define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /!< IN token received with EP mismatch mask /
EricLew	0:d4e5ad7ad71c	8921	#define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /!< IN endpoint NAK effective mask /
EricLew	0:d4e5ad7ad71c	8922	#define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /!< OUT packet error mask /
EricLew	0:d4e5ad7ad71c	8923	#define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /!< BNA interrupt mask /
EricLew	0:d4e5ad7ad71c	8924	#define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /!< Bubble error interrupt mask /
EricLew	0:d4e5ad7ad71c	8925	#define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /!< NAK interrupt mask /
EricLew	0:d4e5ad7ad71c	8926	#define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /!< NYET interrupt mask /
EricLew	0:d4e5ad7ad71c	8927
EricLew	0:d4e5ad7ad71c	8928	/****************** Bit definition for USB_OTG_HPTXFSIZ register ******************/
EricLew	0:d4e5ad7ad71c	8929	#define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /!< Host periodic TxFIFO start address /
EricLew	0:d4e5ad7ad71c	8930	#define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /!< Host periodic TxFIFO depth /
EricLew	0:d4e5ad7ad71c	8931
EricLew	0:d4e5ad7ad71c	8932	/****************** Bit definition for USB_OTG_DIEPCTL register ******************/
EricLew	0:d4e5ad7ad71c	8933	#define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
EricLew	0:d4e5ad7ad71c	8934	#define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
EricLew	0:d4e5ad7ad71c	8935	#define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /!< Even/odd frame /
EricLew	0:d4e5ad7ad71c	8936	#define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
EricLew	0:d4e5ad7ad71c	8937
EricLew	0:d4e5ad7ad71c	8938	#define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
EricLew	0:d4e5ad7ad71c	8939	#define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8940	#define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8941	#define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
EricLew	0:d4e5ad7ad71c	8942
EricLew	0:d4e5ad7ad71c	8943	#define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /!< TxFIFO number /
EricLew	0:d4e5ad7ad71c	8944	#define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8945	#define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8946	#define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8947	#define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8948	#define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
EricLew	0:d4e5ad7ad71c	8949	#define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
EricLew	0:d4e5ad7ad71c	8950	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
EricLew	0:d4e5ad7ad71c	8951	#define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
EricLew	0:d4e5ad7ad71c	8952	#define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
EricLew	0:d4e5ad7ad71c	8953	#define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
EricLew	0:d4e5ad7ad71c	8954
EricLew	0:d4e5ad7ad71c	8955	/****************** Bit definition for USB_OTG_HCCHAR register ******************/
EricLew	0:d4e5ad7ad71c	8956	#define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size /
EricLew	0:d4e5ad7ad71c	8957
EricLew	0:d4e5ad7ad71c	8958	#define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /!< Endpoint number /
EricLew	0:d4e5ad7ad71c	8959	#define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8960	#define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8961	#define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8962	#define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8963	#define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /!< Endpoint direction /
EricLew	0:d4e5ad7ad71c	8964	#define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /!< Low-speed device /
EricLew	0:d4e5ad7ad71c	8965
EricLew	0:d4e5ad7ad71c	8966	#define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
EricLew	0:d4e5ad7ad71c	8967	#define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8968	#define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8969
EricLew	0:d4e5ad7ad71c	8970	#define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /!< Multi Count (MC) / Error Count (EC) /
EricLew	0:d4e5ad7ad71c	8971	#define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8972	#define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8973
EricLew	0:d4e5ad7ad71c	8974	#define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /!< Device address /
EricLew	0:d4e5ad7ad71c	8975	#define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8976	#define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8977	#define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8978	#define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8979	#define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8980	#define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8981	#define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8982	#define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /!< Odd frame /
EricLew	0:d4e5ad7ad71c	8983	#define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /!< Channel disable /
EricLew	0:d4e5ad7ad71c	8984	#define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /!< Channel enable /
EricLew	0:d4e5ad7ad71c	8985
EricLew	0:d4e5ad7ad71c	8986	/****************** Bit definition for USB_OTG_HCSPLT register ******************/
EricLew	0:d4e5ad7ad71c	8987
EricLew	0:d4e5ad7ad71c	8988	#define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /!< Port address /
EricLew	0:d4e5ad7ad71c	8989	#define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8990	#define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	8991	#define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	8992	#define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	8993	#define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	8994	#define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	8995	#define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	8996
EricLew	0:d4e5ad7ad71c	8997	#define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /!< Hub address /
EricLew	0:d4e5ad7ad71c	8998	#define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	8999	#define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9000	#define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /!<Bit 2 /
EricLew	0:d4e5ad7ad71c	9001	#define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /!<Bit 3 /
EricLew	0:d4e5ad7ad71c	9002	#define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /!<Bit 4 /
EricLew	0:d4e5ad7ad71c	9003	#define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /!<Bit 5 /
EricLew	0:d4e5ad7ad71c	9004	#define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /!<Bit 6 /
EricLew	0:d4e5ad7ad71c	9005
EricLew	0:d4e5ad7ad71c	9006	#define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /!< XACTPOS /
EricLew	0:d4e5ad7ad71c	9007	#define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	9008	#define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9009	#define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /!< Do complete split /
EricLew	0:d4e5ad7ad71c	9010	#define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /!< Split enable /
EricLew	0:d4e5ad7ad71c	9011
EricLew	0:d4e5ad7ad71c	9012	/****************** Bit definition for USB_OTG_HCINT register ******************/
EricLew	0:d4e5ad7ad71c	9013	#define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed /
EricLew	0:d4e5ad7ad71c	9014	#define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /!< Channel halted /
EricLew	0:d4e5ad7ad71c	9015	#define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /!< AHB error /
EricLew	0:d4e5ad7ad71c	9016	#define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /!< STALL response received interrupt /
EricLew	0:d4e5ad7ad71c	9017	#define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /!< NAK response received interrupt /
EricLew	0:d4e5ad7ad71c	9018	#define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt /
EricLew	0:d4e5ad7ad71c	9019	#define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /!< Response received interrupt /
EricLew	0:d4e5ad7ad71c	9020	#define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /!< Transaction error /
EricLew	0:d4e5ad7ad71c	9021	#define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /!< Babble error /
EricLew	0:d4e5ad7ad71c	9022	#define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /!< Frame overrun /
EricLew	0:d4e5ad7ad71c	9023	#define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /!< Data toggle error /
EricLew	0:d4e5ad7ad71c	9024
EricLew	0:d4e5ad7ad71c	9025	/****************** Bit definition for USB_OTG_DIEPINT register ******************/
EricLew	0:d4e5ad7ad71c	9026	#define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
EricLew	0:d4e5ad7ad71c	9027	#define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
EricLew	0:d4e5ad7ad71c	9028	#define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /!< Timeout condition /
EricLew	0:d4e5ad7ad71c	9029	#define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /!< IN token received when TxFIFO is empty /
EricLew	0:d4e5ad7ad71c	9030	#define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /!< IN endpoint NAK effective /
EricLew	0:d4e5ad7ad71c	9031	#define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /!< Transmit FIFO empty /
EricLew	0:d4e5ad7ad71c	9032	#define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /!< Transmit Fifo Underrun /
EricLew	0:d4e5ad7ad71c	9033	#define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /!< Buffer not available interrupt /
EricLew	0:d4e5ad7ad71c	9034	#define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /!< Packet dropped status /
EricLew	0:d4e5ad7ad71c	9035	#define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /!< Babble error interrupt /
EricLew	0:d4e5ad7ad71c	9036	#define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /!< NAK interrupt /
EricLew	0:d4e5ad7ad71c	9037
EricLew	0:d4e5ad7ad71c	9038	/****************** Bit definition for USB_OTG_HCINTMSK register ******************/
EricLew	0:d4e5ad7ad71c	9039	#define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /!< Transfer completed mask /
EricLew	0:d4e5ad7ad71c	9040	#define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /!< Channel halted mask /
EricLew	0:d4e5ad7ad71c	9041	#define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /!< AHB error /
EricLew	0:d4e5ad7ad71c	9042	#define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /!< STALL response received interrupt mask /
EricLew	0:d4e5ad7ad71c	9043	#define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /!< NAK response received interrupt mask /
EricLew	0:d4e5ad7ad71c	9044	#define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /!< ACK response received/transmitted interrupt mask /
EricLew	0:d4e5ad7ad71c	9045	#define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /!< response received interrupt mask /
EricLew	0:d4e5ad7ad71c	9046	#define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /!< Transaction error mask /
EricLew	0:d4e5ad7ad71c	9047	#define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /!< Babble error mask /
EricLew	0:d4e5ad7ad71c	9048	#define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /!< Frame overrun mask /
EricLew	0:d4e5ad7ad71c	9049	#define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /!< Data toggle error mask /
EricLew	0:d4e5ad7ad71c	9050
EricLew	0:d4e5ad7ad71c	9051	/****************** Bit definition for USB_OTG_DIEPTSIZ register ******************/
EricLew	0:d4e5ad7ad71c	9052
EricLew	0:d4e5ad7ad71c	9053	#define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
EricLew	0:d4e5ad7ad71c	9054	#define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
EricLew	0:d4e5ad7ad71c	9055	#define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /!< Packet count /
EricLew	0:d4e5ad7ad71c	9056	/****************** Bit definition for USB_OTG_HCTSIZ register ******************/
EricLew	0:d4e5ad7ad71c	9057	#define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
EricLew	0:d4e5ad7ad71c	9058	#define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
EricLew	0:d4e5ad7ad71c	9059	#define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /!< Do PING /
EricLew	0:d4e5ad7ad71c	9060	#define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /!< Data PID /
EricLew	0:d4e5ad7ad71c	9061	#define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	9062	#define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9063
EricLew	0:d4e5ad7ad71c	9064	/****************** Bit definition for USB_OTG_DIEPDMA register ******************/
EricLew	0:d4e5ad7ad71c	9065	#define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
EricLew	0:d4e5ad7ad71c	9066
EricLew	0:d4e5ad7ad71c	9067	/****************** Bit definition for USB_OTG_HCDMA register ******************/
EricLew	0:d4e5ad7ad71c	9068	#define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /!< DMA address /
EricLew	0:d4e5ad7ad71c	9069
EricLew	0:d4e5ad7ad71c	9070	/****************** Bit definition for USB_OTG_DTXFSTS register ******************/
EricLew	0:d4e5ad7ad71c	9071	#define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /!< IN endpoint TxFIFO space avail /
EricLew	0:d4e5ad7ad71c	9072
EricLew	0:d4e5ad7ad71c	9073	/****************** Bit definition for USB_OTG_DIEPTXF register ******************/
EricLew	0:d4e5ad7ad71c	9074	#define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /!< IN endpoint FIFOx transmit RAM start address /
EricLew	0:d4e5ad7ad71c	9075	#define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /!< IN endpoint TxFIFO depth /
EricLew	0:d4e5ad7ad71c	9076
EricLew	0:d4e5ad7ad71c	9077	/****************** Bit definition for USB_OTG_DOEPCTL register ******************/
EricLew	0:d4e5ad7ad71c	9078
EricLew	0:d4e5ad7ad71c	9079	#define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /!< Maximum packet size / /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9080	#define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /!< USB active endpoint /
EricLew	0:d4e5ad7ad71c	9081	#define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /!< NAK status /
EricLew	0:d4e5ad7ad71c	9082	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /!< Set DATA0 PID /
EricLew	0:d4e5ad7ad71c	9083	#define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /!< Set odd frame /
EricLew	0:d4e5ad7ad71c	9084	#define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /!< Endpoint type /
EricLew	0:d4e5ad7ad71c	9085	#define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	9086	#define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9087	#define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /!< Snoop mode /
EricLew	0:d4e5ad7ad71c	9088	#define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /!< STALL handshake /
EricLew	0:d4e5ad7ad71c	9089	#define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /!< Clear NAK /
EricLew	0:d4e5ad7ad71c	9090	#define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /!< Set NAK /
EricLew	0:d4e5ad7ad71c	9091	#define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /!< Endpoint disable /
EricLew	0:d4e5ad7ad71c	9092	#define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /!< Endpoint enable /
EricLew	0:d4e5ad7ad71c	9093
EricLew	0:d4e5ad7ad71c	9094	/****************** Bit definition for USB_OTG_DOEPINT register ******************/
EricLew	0:d4e5ad7ad71c	9095	#define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /!< Transfer completed interrupt /
EricLew	0:d4e5ad7ad71c	9096	#define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /!< Endpoint disabled interrupt /
EricLew	0:d4e5ad7ad71c	9097	#define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /!< SETUP phase done /
EricLew	0:d4e5ad7ad71c	9098	#define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /!< OUT token received when endpoint disabled /
EricLew	0:d4e5ad7ad71c	9099	#define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /!< Back-to-back SETUP packets received /
EricLew	0:d4e5ad7ad71c	9100	#define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /!< NYET interrupt /
EricLew	0:d4e5ad7ad71c	9101
EricLew	0:d4e5ad7ad71c	9102	/****************** Bit definition for USB_OTG_DOEPTSIZ register ******************/
EricLew	0:d4e5ad7ad71c	9103
EricLew	0:d4e5ad7ad71c	9104	#define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /!< Transfer size /
EricLew	0:d4e5ad7ad71c	9105	#define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /!< Packet count /
EricLew	0:d4e5ad7ad71c	9106
EricLew	0:d4e5ad7ad71c	9107	#define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /!< SETUP packet count /
EricLew	0:d4e5ad7ad71c	9108	#define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	9109	#define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9110
EricLew	0:d4e5ad7ad71c	9111	/****************** Bit definition for PCGCCTL register ******************/
EricLew	0:d4e5ad7ad71c	9112	#define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /!< SETUP packet count /
EricLew	0:d4e5ad7ad71c	9113	#define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /!<Bit 0 /
EricLew	0:d4e5ad7ad71c	9114	#define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /!<Bit 1 /
EricLew	0:d4e5ad7ad71c	9115
EricLew	0:d4e5ad7ad71c	9116
EricLew	0:d4e5ad7ad71c	9117	/**
EricLew	0:d4e5ad7ad71c	9118	* @}
EricLew	0:d4e5ad7ad71c	9119	*/
EricLew	0:d4e5ad7ad71c	9120
EricLew	0:d4e5ad7ad71c	9121	/**
EricLew	0:d4e5ad7ad71c	9122	* @}
EricLew	0:d4e5ad7ad71c	9123	*/
EricLew	0:d4e5ad7ad71c	9124
EricLew	0:d4e5ad7ad71c	9125	/** @addtogroup Exported_macros
EricLew	0:d4e5ad7ad71c	9126	* @{
EricLew	0:d4e5ad7ad71c	9127	*/
EricLew	0:d4e5ad7ad71c	9128
EricLew	0:d4e5ad7ad71c	9129	/***************************** ADC Instances ******************************/
EricLew	0:d4e5ad7ad71c	9130	#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) \|\| \
EricLew	0:d4e5ad7ad71c	9131	((INSTANCE) == ADC2) \|\| \
EricLew	0:d4e5ad7ad71c	9132	((INSTANCE) == ADC3))
EricLew	0:d4e5ad7ad71c	9133
EricLew	0:d4e5ad7ad71c	9134	#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
EricLew	0:d4e5ad7ad71c	9135
EricLew	0:d4e5ad7ad71c	9136	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
EricLew	0:d4e5ad7ad71c	9137
EricLew	0:d4e5ad7ad71c	9138	/****************************** CAN Instances ****************************/
EricLew	0:d4e5ad7ad71c	9139	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
EricLew	0:d4e5ad7ad71c	9140
EricLew	0:d4e5ad7ad71c	9141	/****************************** COMP Instances ****************************/
EricLew	0:d4e5ad7ad71c	9142	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
EricLew	0:d4e5ad7ad71c	9143	((INSTANCE) == COMP2))
EricLew	0:d4e5ad7ad71c	9144
EricLew	0:d4e5ad7ad71c	9145	/****************** COMP Instances with window mode capability ************/
EricLew	0:d4e5ad7ad71c	9146	#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
EricLew	0:d4e5ad7ad71c	9147
EricLew	0:d4e5ad7ad71c	9148	/***************************** CRC Instances ******************************/
EricLew	0:d4e5ad7ad71c	9149	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
EricLew	0:d4e5ad7ad71c	9150
EricLew	0:d4e5ad7ad71c	9151	/***************************** DAC Instances ******************************/
EricLew	0:d4e5ad7ad71c	9152	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
EricLew	0:d4e5ad7ad71c	9153
EricLew	0:d4e5ad7ad71c	9154	/**************************** DFSDM Instances *****************************/
EricLew	0:d4e5ad7ad71c	9155	#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Filter0) \|\| \
EricLew	0:d4e5ad7ad71c	9156	((INSTANCE) == DFSDM_Filter1) \|\| \
EricLew	0:d4e5ad7ad71c	9157	((INSTANCE) == DFSDM_Filter2) \|\| \
EricLew	0:d4e5ad7ad71c	9158	((INSTANCE) == DFSDM_Filter3))
EricLew	0:d4e5ad7ad71c	9159
EricLew	0:d4e5ad7ad71c	9160	#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM_Channel0) \|\| \
EricLew	0:d4e5ad7ad71c	9161	((INSTANCE) == DFSDM_Channel1) \|\| \
EricLew	0:d4e5ad7ad71c	9162	((INSTANCE) == DFSDM_Channel2) \|\| \
EricLew	0:d4e5ad7ad71c	9163	((INSTANCE) == DFSDM_Channel3) \|\| \
EricLew	0:d4e5ad7ad71c	9164	((INSTANCE) == DFSDM_Channel4) \|\| \
EricLew	0:d4e5ad7ad71c	9165	((INSTANCE) == DFSDM_Channel5) \|\| \
EricLew	0:d4e5ad7ad71c	9166	((INSTANCE) == DFSDM_Channel6) \|\| \
EricLew	0:d4e5ad7ad71c	9167	((INSTANCE) == DFSDM_Channel7))
EricLew	0:d4e5ad7ad71c	9168
EricLew	0:d4e5ad7ad71c	9169	/****************************** DMA Instances *****************************/
EricLew	0:d4e5ad7ad71c	9170	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
EricLew	0:d4e5ad7ad71c	9171	((INSTANCE) == DMA1_Channel2) \|\| \
EricLew	0:d4e5ad7ad71c	9172	((INSTANCE) == DMA1_Channel3) \|\| \
EricLew	0:d4e5ad7ad71c	9173	((INSTANCE) == DMA1_Channel4) \|\| \
EricLew	0:d4e5ad7ad71c	9174	((INSTANCE) == DMA1_Channel5) \|\| \
EricLew	0:d4e5ad7ad71c	9175	((INSTANCE) == DMA1_Channel6) \|\| \
EricLew	0:d4e5ad7ad71c	9176	((INSTANCE) == DMA1_Channel7) \|\| \
EricLew	0:d4e5ad7ad71c	9177	((INSTANCE) == DMA2_Channel1) \|\| \
EricLew	0:d4e5ad7ad71c	9178	((INSTANCE) == DMA2_Channel2) \|\| \
EricLew	0:d4e5ad7ad71c	9179	((INSTANCE) == DMA2_Channel3) \|\| \
EricLew	0:d4e5ad7ad71c	9180	((INSTANCE) == DMA2_Channel4) \|\| \
EricLew	0:d4e5ad7ad71c	9181	((INSTANCE) == DMA2_Channel5) \|\| \
EricLew	0:d4e5ad7ad71c	9182	((INSTANCE) == DMA2_Channel6) \|\| \
EricLew	0:d4e5ad7ad71c	9183	((INSTANCE) == DMA2_Channel7))
EricLew	0:d4e5ad7ad71c	9184
EricLew	0:d4e5ad7ad71c	9185	/***************************** GPIO Instances *****************************/
EricLew	0:d4e5ad7ad71c	9186	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
EricLew	0:d4e5ad7ad71c	9187	((INSTANCE) == GPIOB) \|\| \
EricLew	0:d4e5ad7ad71c	9188	((INSTANCE) == GPIOC) \|\| \
EricLew	0:d4e5ad7ad71c	9189	((INSTANCE) == GPIOD) \|\| \
EricLew	0:d4e5ad7ad71c	9190	((INSTANCE) == GPIOE) \|\| \
EricLew	0:d4e5ad7ad71c	9191	((INSTANCE) == GPIOF) \|\| \
EricLew	0:d4e5ad7ad71c	9192	((INSTANCE) == GPIOG) \|\| \
EricLew	0:d4e5ad7ad71c	9193	((INSTANCE) == GPIOH))
EricLew	0:d4e5ad7ad71c	9194
EricLew	0:d4e5ad7ad71c	9195	/***************************** GPIO AF Instances **************************/
EricLew	0:d4e5ad7ad71c	9196	/* On L4, all GPIO Bank support AF */
EricLew	0:d4e5ad7ad71c	9197	#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
EricLew	0:d4e5ad7ad71c	9198
EricLew	0:d4e5ad7ad71c	9199	/************************** GPIO Lock Instances ***************************/
EricLew	0:d4e5ad7ad71c	9200	/* On L4, all GPIO Bank support the Lock mechanism */
EricLew	0:d4e5ad7ad71c	9201	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
EricLew	0:d4e5ad7ad71c	9202
EricLew	0:d4e5ad7ad71c	9203	/****************************** I2C Instances *****************************/
EricLew	0:d4e5ad7ad71c	9204	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
EricLew	0:d4e5ad7ad71c	9205	((INSTANCE) == I2C2) \|\| \
EricLew	0:d4e5ad7ad71c	9206	((INSTANCE) == I2C3))
EricLew	0:d4e5ad7ad71c	9207
EricLew	0:d4e5ad7ad71c	9208	/***************************** LCD Instances ******************************/
EricLew	0:d4e5ad7ad71c	9209	#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
EricLew	0:d4e5ad7ad71c	9210
EricLew	0:d4e5ad7ad71c	9211	/***************************** HCD Instances *****************************/
EricLew	0:d4e5ad7ad71c	9212	#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
EricLew	0:d4e5ad7ad71c	9213
EricLew	0:d4e5ad7ad71c	9214	/**************************** OPAMP Instances *****************************/
EricLew	0:d4e5ad7ad71c	9215	#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) \|\| \
EricLew	0:d4e5ad7ad71c	9216	((INSTANCE) == OPAMP2))
EricLew	0:d4e5ad7ad71c	9217
EricLew	0:d4e5ad7ad71c	9218	/***************************** PCD Instances *****************************/
EricLew	0:d4e5ad7ad71c	9219	#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)
EricLew	0:d4e5ad7ad71c	9220
EricLew	0:d4e5ad7ad71c	9221	/***************************** QSPI Instances *****************************/
EricLew	0:d4e5ad7ad71c	9222	#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
EricLew	0:d4e5ad7ad71c	9223
EricLew	0:d4e5ad7ad71c	9224	/***************************** RNG Instances ******************************/
EricLew	0:d4e5ad7ad71c	9225	#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
EricLew	0:d4e5ad7ad71c	9226
EricLew	0:d4e5ad7ad71c	9227	/**************************** RTC Instances *******************************/
EricLew	0:d4e5ad7ad71c	9228	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
EricLew	0:d4e5ad7ad71c	9229
EricLew	0:d4e5ad7ad71c	9230	/****************************** SAI Instances *****************************/
EricLew	0:d4e5ad7ad71c	9231	#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) \|\| \
EricLew	0:d4e5ad7ad71c	9232	((INSTANCE) == SAI1_Block_B) \|\| \
EricLew	0:d4e5ad7ad71c	9233	((INSTANCE) == SAI2_Block_A) \|\| \
EricLew	0:d4e5ad7ad71c	9234	((INSTANCE) == SAI2_Block_B))
EricLew	0:d4e5ad7ad71c	9235
EricLew	0:d4e5ad7ad71c	9236	/**************************** SDMMC Instances *****************************/
EricLew	0:d4e5ad7ad71c	9237	#define IS_SDMMC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDMMC1)
EricLew	0:d4e5ad7ad71c	9238
EricLew	0:d4e5ad7ad71c	9239	/**************************** SMBUS Instances *****************************/
EricLew	0:d4e5ad7ad71c	9240	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
EricLew	0:d4e5ad7ad71c	9241	((INSTANCE) == I2C2) \|\| \
EricLew	0:d4e5ad7ad71c	9242	((INSTANCE) == I2C3))
EricLew	0:d4e5ad7ad71c	9243
EricLew	0:d4e5ad7ad71c	9244	/****************************** SPI Instances *****************************/
EricLew	0:d4e5ad7ad71c	9245	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
EricLew	0:d4e5ad7ad71c	9246	((INSTANCE) == SPI2) \|\| \
EricLew	0:d4e5ad7ad71c	9247	((INSTANCE) == SPI3))
EricLew	0:d4e5ad7ad71c	9248
EricLew	0:d4e5ad7ad71c	9249	/****************************** SWPMI Instances ***************************/
EricLew	0:d4e5ad7ad71c	9250	#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
EricLew	0:d4e5ad7ad71c	9251
EricLew	0:d4e5ad7ad71c	9252	/**************** LPTIM Instances : All supported instances ***************/
EricLew	0:d4e5ad7ad71c	9253	#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9254	((INSTANCE) == LPTIM2))
EricLew	0:d4e5ad7ad71c	9255
EricLew	0:d4e5ad7ad71c	9256	/**************** TIM Instances : All supported instances *****************/
EricLew	0:d4e5ad7ad71c	9257	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9258	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9259	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9260	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9261	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9262	((INSTANCE) == TIM6) \|\| \
EricLew	0:d4e5ad7ad71c	9263	((INSTANCE) == TIM7) \|\| \
EricLew	0:d4e5ad7ad71c	9264	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9265	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9266	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9267	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9268
EricLew	0:d4e5ad7ad71c	9269	/**************** TIM Instances : supporting 32 bits counter **************/
EricLew	0:d4e5ad7ad71c	9270	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9271	((INSTANCE) == TIM5))
EricLew	0:d4e5ad7ad71c	9272
EricLew	0:d4e5ad7ad71c	9273	/**************** TIM Instances : supporting the break function ***********/
EricLew	0:d4e5ad7ad71c	9274	#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9275	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9276	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9277	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9278	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9279
EricLew	0:d4e5ad7ad71c	9280	/************ TIM Instances : supporting Break source selection ***********/
EricLew	0:d4e5ad7ad71c	9281	#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9282	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9283	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9284	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9285	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9286
EricLew	0:d4e5ad7ad71c	9287	/**************** TIM Instances : supporting 2 break inputs ***************/
EricLew	0:d4e5ad7ad71c	9288	#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9289	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9290
EricLew	0:d4e5ad7ad71c	9291	/*********** TIM Instances : at least 1 capture/compare channel ***********/
EricLew	0:d4e5ad7ad71c	9292	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9293	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9294	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9295	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9296	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9297	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9298	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9299	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9300	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9301
EricLew	0:d4e5ad7ad71c	9302	/********** TIM Instances : at least 2 capture/compare channels ***********/
EricLew	0:d4e5ad7ad71c	9303	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9304	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9305	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9306	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9307	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9308	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9309	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9310
EricLew	0:d4e5ad7ad71c	9311	/********** TIM Instances : at least 3 capture/compare channels ***********/
EricLew	0:d4e5ad7ad71c	9312	#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9313	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9314	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9315	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9316	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9317	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9318
EricLew	0:d4e5ad7ad71c	9319	/********** TIM Instances : at least 4 capture/compare channels ***********/
EricLew	0:d4e5ad7ad71c	9320	#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9321	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9322	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9323	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9324	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9325	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9326
EricLew	0:d4e5ad7ad71c	9327	/**************** TIM Instances : at least 5 capture/compare channels *****/
EricLew	0:d4e5ad7ad71c	9328	#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9329	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9330
EricLew	0:d4e5ad7ad71c	9331	/**************** TIM Instances : at least 6 capture/compare channels *****/
EricLew	0:d4e5ad7ad71c	9332	#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9333	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9334
EricLew	0:d4e5ad7ad71c	9335	/********** TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *****/
EricLew	0:d4e5ad7ad71c	9336	#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9337	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9338	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9339	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9340	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9341
EricLew	0:d4e5ad7ad71c	9342	/**************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) */
EricLew	0:d4e5ad7ad71c	9343	#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9344	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9345	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9346	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9347	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9348	((INSTANCE) == TIM6) \|\| \
EricLew	0:d4e5ad7ad71c	9349	((INSTANCE) == TIM7) \|\| \
EricLew	0:d4e5ad7ad71c	9350	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9351	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9352	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9353	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9354
EricLew	0:d4e5ad7ad71c	9355	/********** TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *****/
EricLew	0:d4e5ad7ad71c	9356	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9357	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9358	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9359	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9360	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9361	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9362	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9363	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9364	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9365
EricLew	0:d4e5ad7ad71c	9366	/****************** TIM Instances : DMA burst feature *********************/
EricLew	0:d4e5ad7ad71c	9367	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9368	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9369	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9370	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9371	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9372	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9373	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9374	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9375	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9376
EricLew	0:d4e5ad7ad71c	9377	/***************** TIM Instances : output(s) available ********************/
EricLew	0:d4e5ad7ad71c	9378	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
EricLew	0:d4e5ad7ad71c	9379	((((INSTANCE) == TIM1) && \
EricLew	0:d4e5ad7ad71c	9380	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9381	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9382	((CHANNEL) == TIM_CHANNEL_3) \|\| \
EricLew	0:d4e5ad7ad71c	9383	((CHANNEL) == TIM_CHANNEL_4) \|\| \
EricLew	0:d4e5ad7ad71c	9384	((CHANNEL) == TIM_CHANNEL_5) \|\| \
EricLew	0:d4e5ad7ad71c	9385	((CHANNEL) == TIM_CHANNEL_6))) \
EricLew	0:d4e5ad7ad71c	9386	\|\| \
EricLew	0:d4e5ad7ad71c	9387	(((INSTANCE) == TIM2) && \
EricLew	0:d4e5ad7ad71c	9388	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9389	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9390	((CHANNEL) == TIM_CHANNEL_3) \|\| \
EricLew	0:d4e5ad7ad71c	9391	((CHANNEL) == TIM_CHANNEL_4))) \
EricLew	0:d4e5ad7ad71c	9392	\|\| \
EricLew	0:d4e5ad7ad71c	9393	(((INSTANCE) == TIM3) && \
EricLew	0:d4e5ad7ad71c	9394	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9395	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9396	((CHANNEL) == TIM_CHANNEL_3) \|\| \
EricLew	0:d4e5ad7ad71c	9397	((CHANNEL) == TIM_CHANNEL_4))) \
EricLew	0:d4e5ad7ad71c	9398	\|\| \
EricLew	0:d4e5ad7ad71c	9399	(((INSTANCE) == TIM4) && \
EricLew	0:d4e5ad7ad71c	9400	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9401	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9402	((CHANNEL) == TIM_CHANNEL_3) \|\| \
EricLew	0:d4e5ad7ad71c	9403	((CHANNEL) == TIM_CHANNEL_4))) \
EricLew	0:d4e5ad7ad71c	9404	\|\| \
EricLew	0:d4e5ad7ad71c	9405	(((INSTANCE) == TIM5) && \
EricLew	0:d4e5ad7ad71c	9406	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9407	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9408	((CHANNEL) == TIM_CHANNEL_3) \|\| \
EricLew	0:d4e5ad7ad71c	9409	((CHANNEL) == TIM_CHANNEL_4))) \
EricLew	0:d4e5ad7ad71c	9410	\|\| \
EricLew	0:d4e5ad7ad71c	9411	(((INSTANCE) == TIM8) && \
EricLew	0:d4e5ad7ad71c	9412	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9413	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9414	((CHANNEL) == TIM_CHANNEL_3) \|\| \
EricLew	0:d4e5ad7ad71c	9415	((CHANNEL) == TIM_CHANNEL_4) \|\| \
EricLew	0:d4e5ad7ad71c	9416	((CHANNEL) == TIM_CHANNEL_5) \|\| \
EricLew	0:d4e5ad7ad71c	9417	((CHANNEL) == TIM_CHANNEL_6))) \
EricLew	0:d4e5ad7ad71c	9418	\|\| \
EricLew	0:d4e5ad7ad71c	9419	(((INSTANCE) == TIM15) && \
EricLew	0:d4e5ad7ad71c	9420	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9421	((CHANNEL) == TIM_CHANNEL_2))) \
EricLew	0:d4e5ad7ad71c	9422	\|\| \
EricLew	0:d4e5ad7ad71c	9423	(((INSTANCE) == TIM16) && \
EricLew	0:d4e5ad7ad71c	9424	(((CHANNEL) == TIM_CHANNEL_1))) \
EricLew	0:d4e5ad7ad71c	9425	\|\| \
EricLew	0:d4e5ad7ad71c	9426	(((INSTANCE) == TIM17) && \
EricLew	0:d4e5ad7ad71c	9427	(((CHANNEL) == TIM_CHANNEL_1))))
EricLew	0:d4e5ad7ad71c	9428
EricLew	0:d4e5ad7ad71c	9429	/**************** TIM Instances : supporting complementary output(s) ******/
EricLew	0:d4e5ad7ad71c	9430	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
EricLew	0:d4e5ad7ad71c	9431	((((INSTANCE) == TIM1) && \
EricLew	0:d4e5ad7ad71c	9432	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9433	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9434	((CHANNEL) == TIM_CHANNEL_3))) \
EricLew	0:d4e5ad7ad71c	9435	\|\| \
EricLew	0:d4e5ad7ad71c	9436	(((INSTANCE) == TIM8) && \
EricLew	0:d4e5ad7ad71c	9437	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
EricLew	0:d4e5ad7ad71c	9438	((CHANNEL) == TIM_CHANNEL_2) \|\| \
EricLew	0:d4e5ad7ad71c	9439	((CHANNEL) == TIM_CHANNEL_3))) \
EricLew	0:d4e5ad7ad71c	9440	\|\| \
EricLew	0:d4e5ad7ad71c	9441	(((INSTANCE) == TIM15) && \
EricLew	0:d4e5ad7ad71c	9442	((CHANNEL) == TIM_CHANNEL_1)) \
EricLew	0:d4e5ad7ad71c	9443	\|\| \
EricLew	0:d4e5ad7ad71c	9444	(((INSTANCE) == TIM16) && \
EricLew	0:d4e5ad7ad71c	9445	((CHANNEL) == TIM_CHANNEL_1)) \
EricLew	0:d4e5ad7ad71c	9446	\|\| \
EricLew	0:d4e5ad7ad71c	9447	(((INSTANCE) == TIM17) && \
EricLew	0:d4e5ad7ad71c	9448	((CHANNEL) == TIM_CHANNEL_1)))
EricLew	0:d4e5ad7ad71c	9449
EricLew	0:d4e5ad7ad71c	9450	/**************** TIM Instances : supporting clock division ***************/
EricLew	0:d4e5ad7ad71c	9451	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9452	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9453	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9454	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9455	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9456	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9457	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9458	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9459	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9460
EricLew	0:d4e5ad7ad71c	9461	/**** TIM Instances : supporting external clock mode 1 for ETRF input *****/
EricLew	0:d4e5ad7ad71c	9462	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9463	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9464	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9465	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9466	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9467	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9468	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9469
EricLew	0:d4e5ad7ad71c	9470	/**** TIM Instances : supporting external clock mode 2 for ETRF input *****/
EricLew	0:d4e5ad7ad71c	9471	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9472	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9473	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9474	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9475	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9476	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9477
EricLew	0:d4e5ad7ad71c	9478	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
EricLew	0:d4e5ad7ad71c	9479	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9480	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9481	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9482	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9483	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9484	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9485	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9486
EricLew	0:d4e5ad7ad71c	9487	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
EricLew	0:d4e5ad7ad71c	9488	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9489	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9490	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9491	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9492	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9493	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9494	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9495
EricLew	0:d4e5ad7ad71c	9496	/**************** TIM Instances : supporting combined 3-phase PWM mode ****/
EricLew	0:d4e5ad7ad71c	9497	#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9498	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9499
EricLew	0:d4e5ad7ad71c	9500	/**************** TIM Instances : supporting commutation event generation */
EricLew	0:d4e5ad7ad71c	9501	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9502	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9503	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9504	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9505	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9506
EricLew	0:d4e5ad7ad71c	9507	/**************** TIM Instances : supporting counting mode selection ******/
EricLew	0:d4e5ad7ad71c	9508	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9509	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9510	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9511	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9512	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9513	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9514
EricLew	0:d4e5ad7ad71c	9515	/**************** TIM Instances : supporting encoder interface ************/
EricLew	0:d4e5ad7ad71c	9516	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9517	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9518	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9519	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9520	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9521	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9522
EricLew	0:d4e5ad7ad71c	9523	/************** TIM Instances : external trigger input available **********/
EricLew	0:d4e5ad7ad71c	9524	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9525	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9526	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9527	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9528	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9529	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9530
EricLew	0:d4e5ad7ad71c	9531	/*********** TIM Instances : supporting ETR source selection *************/
EricLew	0:d4e5ad7ad71c	9532	#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9533	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9534	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9535	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9536
EricLew	0:d4e5ad7ad71c	9537	/**** TIM Instances : Master mode available (TIMx_CR2.MMS available )******/
EricLew	0:d4e5ad7ad71c	9538	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9539	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9540	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9541	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9542	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9543	((INSTANCE) == TIM6) \|\| \
EricLew	0:d4e5ad7ad71c	9544	((INSTANCE) == TIM7) \|\| \
EricLew	0:d4e5ad7ad71c	9545	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9546	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9547
EricLew	0:d4e5ad7ad71c	9548	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
EricLew	0:d4e5ad7ad71c	9549	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9550	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9551	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9552	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9553	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9554	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9555	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9556
EricLew	0:d4e5ad7ad71c	9557	/**************** TIM Instances : supporting OCxREF clear *****************/
EricLew	0:d4e5ad7ad71c	9558	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9559	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9560	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9561	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9562	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9563	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9564
EricLew	0:d4e5ad7ad71c	9565	/**************** TIM Instances : remapping capability ********************/
EricLew	0:d4e5ad7ad71c	9566	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9567	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9568	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9569	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9570	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9571	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9572	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9573
EricLew	0:d4e5ad7ad71c	9574	/**************** TIM Instances : supporting repetition counter ***********/
EricLew	0:d4e5ad7ad71c	9575	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9576	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9577	((INSTANCE) == TIM15) \|\| \
EricLew	0:d4e5ad7ad71c	9578	((INSTANCE) == TIM16) \|\| \
EricLew	0:d4e5ad7ad71c	9579	((INSTANCE) == TIM17))
EricLew	0:d4e5ad7ad71c	9580
EricLew	0:d4e5ad7ad71c	9581	/**************** TIM Instances : supporting synchronization **************/
EricLew	0:d4e5ad7ad71c	9582	#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
EricLew	0:d4e5ad7ad71c	9583
EricLew	0:d4e5ad7ad71c	9584	/**************** TIM Instances : supporting ADC triggering through TRGO2 */
EricLew	0:d4e5ad7ad71c	9585	#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9586	((INSTANCE) == TIM8))
EricLew	0:d4e5ad7ad71c	9587
EricLew	0:d4e5ad7ad71c	9588	/***************** TIM Instances : Timer input XOR function ***************/
EricLew	0:d4e5ad7ad71c	9589	#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) \|\| \
EricLew	0:d4e5ad7ad71c	9590	((INSTANCE) == TIM2) \|\| \
EricLew	0:d4e5ad7ad71c	9591	((INSTANCE) == TIM3) \|\| \
EricLew	0:d4e5ad7ad71c	9592	((INSTANCE) == TIM4) \|\| \
EricLew	0:d4e5ad7ad71c	9593	((INSTANCE) == TIM5) \|\| \
EricLew	0:d4e5ad7ad71c	9594	((INSTANCE) == TIM8) \|\| \
EricLew	0:d4e5ad7ad71c	9595	((INSTANCE) == TIM15))
EricLew	0:d4e5ad7ad71c	9596
EricLew	0:d4e5ad7ad71c	9597	/**************************** TSC Instances *******************************/
EricLew	0:d4e5ad7ad71c	9598	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
EricLew	0:d4e5ad7ad71c	9599
EricLew	0:d4e5ad7ad71c	9600	/****************** UART Instances : Asynchronous mode ********************/
EricLew	0:d4e5ad7ad71c	9601	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9602	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9603	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9604	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9605	((INSTANCE) == UART5) \|\| \
EricLew	0:d4e5ad7ad71c	9606	((INSTANCE) == LPUART1))
EricLew	0:d4e5ad7ad71c	9607
EricLew	0:d4e5ad7ad71c	9608
EricLew	0:d4e5ad7ad71c	9609	/****************** USART Instances : Synchronous mode ********************/
EricLew	0:d4e5ad7ad71c	9610	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9611	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9612	((INSTANCE) == USART3))
EricLew	0:d4e5ad7ad71c	9613
EricLew	0:d4e5ad7ad71c	9614	/**************** UART Instances : Hardware Flow control ******************/
EricLew	0:d4e5ad7ad71c	9615	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9616	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9617	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9618	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9619	((INSTANCE) == UART5) \|\| \
EricLew	0:d4e5ad7ad71c	9620	((INSTANCE) == LPUART1))
EricLew	0:d4e5ad7ad71c	9621
EricLew	0:d4e5ad7ad71c	9622
EricLew	0:d4e5ad7ad71c	9623	/******************* USART Instances : Smard card mode *********************/
EricLew	0:d4e5ad7ad71c	9624	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9625	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9626	((INSTANCE) == USART3))
EricLew	0:d4e5ad7ad71c	9627
EricLew	0:d4e5ad7ad71c	9628	/**************** UART Instances : Auto Baud Rate detection **************/
EricLew	0:d4e5ad7ad71c	9629	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9630	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9631	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9632	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9633	((INSTANCE) == UART5))
EricLew	0:d4e5ad7ad71c	9634
EricLew	0:d4e5ad7ad71c	9635	/****************** UART Instances : Half-Duplex mode ********************/
EricLew	0:d4e5ad7ad71c	9636	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9637	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9638	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9639	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9640	((INSTANCE) == UART5) \|\| \
EricLew	0:d4e5ad7ad71c	9641	((INSTANCE) == LPUART1))
EricLew	0:d4e5ad7ad71c	9642
EricLew	0:d4e5ad7ad71c	9643	/****************** UART Instances : LIN mode ********************/
EricLew	0:d4e5ad7ad71c	9644	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9645	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9646	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9647	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9648	((INSTANCE) == UART5))
EricLew	0:d4e5ad7ad71c	9649
EricLew	0:d4e5ad7ad71c	9650	/****************** UART Instances : Wake-up from Stop mode ********************/
EricLew	0:d4e5ad7ad71c	9651	#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9652	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9653	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9654	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9655	((INSTANCE) == UART5) \|\| \
EricLew	0:d4e5ad7ad71c	9656	((INSTANCE) == LPUART1))
EricLew	0:d4e5ad7ad71c	9657
EricLew	0:d4e5ad7ad71c	9658	/**************** UART Instances : Driver Enable ***************/
EricLew	0:d4e5ad7ad71c	9659	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9660	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9661	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9662	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9663	((INSTANCE) == UART5) \|\| \
EricLew	0:d4e5ad7ad71c	9664	((INSTANCE) == LPUART1))
EricLew	0:d4e5ad7ad71c	9665
EricLew	0:d4e5ad7ad71c	9666	/****************** UART Instances : Half-Duplex mode ********************/
EricLew	0:d4e5ad7ad71c	9667	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9668	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9669	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9670	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9671	((INSTANCE) == UART5) \|\| \
EricLew	0:d4e5ad7ad71c	9672	((INSTANCE) == LPUART1))
EricLew	0:d4e5ad7ad71c	9673
EricLew	0:d4e5ad7ad71c	9674	/****************** UART Instances : LIN mode ********************/
EricLew	0:d4e5ad7ad71c	9675	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9676	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9677	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9678	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9679	((INSTANCE) == UART5))
EricLew	0:d4e5ad7ad71c	9680
EricLew	0:d4e5ad7ad71c	9681	/********************* UART Instances : IRDA mode *************************/
EricLew	0:d4e5ad7ad71c	9682	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
EricLew	0:d4e5ad7ad71c	9683	((INSTANCE) == USART2) \|\| \
EricLew	0:d4e5ad7ad71c	9684	((INSTANCE) == USART3) \|\| \
EricLew	0:d4e5ad7ad71c	9685	((INSTANCE) == UART4) \|\| \
EricLew	0:d4e5ad7ad71c	9686	((INSTANCE) == UART5))
EricLew	0:d4e5ad7ad71c	9687
EricLew	0:d4e5ad7ad71c	9688	/**************************** IWDG Instances ******************************/
EricLew	0:d4e5ad7ad71c	9689	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
EricLew	0:d4e5ad7ad71c	9690
EricLew	0:d4e5ad7ad71c	9691	/**************************** WWDG Instances ******************************/
EricLew	0:d4e5ad7ad71c	9692	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
EricLew	0:d4e5ad7ad71c	9693
EricLew	0:d4e5ad7ad71c	9694	/**
EricLew	0:d4e5ad7ad71c	9695	* @}
EricLew	0:d4e5ad7ad71c	9696	*/
EricLew	0:d4e5ad7ad71c	9697
EricLew	0:d4e5ad7ad71c	9698
EricLew	0:d4e5ad7ad71c	9699	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	9700	/* For a painless codes migration between the STM32L4xx device product */
EricLew	0:d4e5ad7ad71c	9701	/* lines, the aliases defined below are put in place to overcome the */
EricLew	0:d4e5ad7ad71c	9702	/* differences in the interrupt handlers and IRQn definitions. */
EricLew	0:d4e5ad7ad71c	9703	/* No need to update developed interrupt code when moving across */
EricLew	0:d4e5ad7ad71c	9704	/* product lines within the same STM32L4 Family */
EricLew	0:d4e5ad7ad71c	9705	/******************************************************************************/
EricLew	0:d4e5ad7ad71c	9706
EricLew	0:d4e5ad7ad71c	9707	/* Aliases for __IRQn */
EricLew	0:d4e5ad7ad71c	9708	#define TIM8_IRQn TIM8_UP_IRQn
EricLew	0:d4e5ad7ad71c	9709
EricLew	0:d4e5ad7ad71c	9710	/* Aliases for __IRQHandler */
EricLew	0:d4e5ad7ad71c	9711	#define TIM8_IRQHandler TIM8_UP_IRQHandler
EricLew	0:d4e5ad7ad71c	9712
EricLew	0:d4e5ad7ad71c	9713
EricLew	0:d4e5ad7ad71c	9714	#ifdef __cplusplus
EricLew	0:d4e5ad7ad71c	9715	}
EricLew	0:d4e5ad7ad71c	9716	#endif /* __cplusplus */
EricLew	0:d4e5ad7ad71c	9717
EricLew	0:d4e5ad7ad71c	9718	#endif /* __STM32L476xx_H */
EricLew	0:d4e5ad7ad71c	9719
EricLew	0:d4e5ad7ad71c	9720	/**
EricLew	0:d4e5ad7ad71c	9721	* @}
EricLew	0:d4e5ad7ad71c	9722	*/
EricLew	0:d4e5ad7ad71c	9723
EricLew	0:d4e5ad7ad71c	9724	/**
EricLew	0:d4e5ad7ad71c	9725	* @}
EricLew	0:d4e5ad7ad71c	9726	*/
EricLew	0:d4e5ad7ad71c	9727
EricLew	0:d4e5ad7ad71c	9728	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
EricLew	0:d4e5ad7ad71c	9729

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Type:	Program
Created:	23 Nov 2015
Imports:	15
Forks:	1
Commits:	4
Dependents:	0
Dependencies:	2
Followers:	9

stm32l476xx.h@3:ec7e3c37fe80, 2015-11-26 (annotated)

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