Senior Design: Sound Monitor / OneHopeOnePrayer

AudioRecord

Dependencies:   STM32L4xx_HAL_Driver CMSIS_DSP_401

startup_stm32l476xx.s@3:ec7e3c37fe80, 2015-11-26 (annotated)

Committer:
EricLew
Date:
Thu Nov 26 22:32:56 2015 +0000
Revision:
3:ec7e3c37fe80
Parent:
2:1066910a6cbc 
FFT is currently not working and commented out

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:d4e5ad7ad71c 1 ;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
EricLew 0:d4e5ad7ad71c 2 ;* File Name : startup_stm32l476xx.s
EricLew 0:d4e5ad7ad71c 3 ;* Author : MCD Application Team
EricLew 0:d4e5ad7ad71c 4 ;* Version : V1.1.0
EricLew 0:d4e5ad7ad71c 5 ;* Date : 16-September-2015
EricLew 0:d4e5ad7ad71c 6 ;* Description : STM32L476xx Ultra Low Power devices vector table for MDK-ARM toolchain.
EricLew 0:d4e5ad7ad71c 7 ;* This module performs:
EricLew 0:d4e5ad7ad71c 8 ;* - Set the initial SP
EricLew 0:d4e5ad7ad71c 9 ;* - Set the initial PC == Reset_Handler
EricLew 0:d4e5ad7ad71c 10 ;* - Set the vector table entries with the exceptions ISR address
EricLew 0:d4e5ad7ad71c 11 ;* - Branches to __main in the C library (which eventually
EricLew 0:d4e5ad7ad71c 12 ;* calls main()).
EricLew 0:d4e5ad7ad71c 13 ;* After Reset the Cortex-M4 processor is in Thread mode,
EricLew 0:d4e5ad7ad71c 14 ;* priority is Privileged, and the Stack is set to Main.
EricLew 0:d4e5ad7ad71c 15 ;* <<< Use Configuration Wizard in Context Menu >>>
EricLew 0:d4e5ad7ad71c 16 ;*******************************************************************************
EricLew 0:d4e5ad7ad71c 17 ;*
EricLew 0:d4e5ad7ad71c 18 ;* Redistribution and use in source and binary forms, with or without modification,
EricLew 0:d4e5ad7ad71c 19 ;* are permitted provided that the following conditions are met:
EricLew 0:d4e5ad7ad71c 20 ;* 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:d4e5ad7ad71c 21 ;* this list of conditions and the following disclaimer.
EricLew 0:d4e5ad7ad71c 22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:d4e5ad7ad71c 23 ;* this list of conditions and the following disclaimer in the documentation
EricLew 0:d4e5ad7ad71c 24 ;* and/or other materials provided with the distribution.
EricLew 0:d4e5ad7ad71c 25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:d4e5ad7ad71c 26 ;* may be used to endorse or promote products derived from this software
EricLew 0:d4e5ad7ad71c 27 ;* without specific prior written permission.
EricLew 0:d4e5ad7ad71c 28 ;*
EricLew 0:d4e5ad7ad71c 29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:d4e5ad7ad71c 30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:d4e5ad7ad71c 31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:d4e5ad7ad71c 32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:d4e5ad7ad71c 33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:d4e5ad7ad71c 34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:d4e5ad7ad71c 35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:d4e5ad7ad71c 36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:d4e5ad7ad71c 37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:d4e5ad7ad71c 38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:d4e5ad7ad71c 39 ;*
EricLew 0:d4e5ad7ad71c 40 ;*******************************************************************************
EricLew 0:d4e5ad7ad71c 41 ;
EricLew 0:d4e5ad7ad71c 42 ; Amount of memory (in bytes) allocated for Stack
EricLew 0:d4e5ad7ad71c 43 ; Tailor this value to your application needs
EricLew 0:d4e5ad7ad71c 44 ; <h> Stack Configuration
EricLew 0:d4e5ad7ad71c 45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
EricLew 0:d4e5ad7ad71c 46 ; </h>
EricLew 0:d4e5ad7ad71c 47
EricLew 0:d4e5ad7ad71c 48 Stack_Size EQU 0x400;
EricLew 0:d4e5ad7ad71c 49
EricLew 0:d4e5ad7ad71c 50 AREA STACK, NOINIT, READWRITE, ALIGN=3
EricLew 2:1066910a6cbc 51 EXPORT __initial_sp
EricLew 0:d4e5ad7ad71c 52 Stack_Mem SPACE Stack_Size
EricLew 2:1066910a6cbc 53
EricLew 0:d4e5ad7ad71c 54 __initial_sp
EricLew 0:d4e5ad7ad71c 55
EricLew 0:d4e5ad7ad71c 56
EricLew 0:d4e5ad7ad71c 57 ; <h> Heap Configuration
EricLew 0:d4e5ad7ad71c 58 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
EricLew 0:d4e5ad7ad71c 59 ; </h>
EricLew 0:d4e5ad7ad71c 60
EricLew 2:1066910a6cbc 61 Heap_Size EQU 0x10000;
EricLew 0:d4e5ad7ad71c 62
EricLew 0:d4e5ad7ad71c 63 AREA HEAP, NOINIT, READWRITE, ALIGN=3
EricLew 0:d4e5ad7ad71c 64 EXPORT __heap_base
EricLew 0:d4e5ad7ad71c 65 EXPORT __heap_limit
EricLew 0:d4e5ad7ad71c 66 __heap_base
EricLew 0:d4e5ad7ad71c 67 Heap_Mem SPACE Heap_Size
EricLew 0:d4e5ad7ad71c 68 __heap_limit
EricLew 0:d4e5ad7ad71c 69
EricLew 0:d4e5ad7ad71c 70 PRESERVE8
EricLew 0:d4e5ad7ad71c 71 THUMB
EricLew 0:d4e5ad7ad71c 72
EricLew 0:d4e5ad7ad71c 73
EricLew 0:d4e5ad7ad71c 74 ; Vector Table Mapped to Address 0 at Reset
EricLew 0:d4e5ad7ad71c 75 AREA RESET, DATA, READONLY
EricLew 0:d4e5ad7ad71c 76 EXPORT __Vectors
EricLew 0:d4e5ad7ad71c 77 EXPORT __Vectors_End
EricLew 0:d4e5ad7ad71c 78 EXPORT __Vectors_Size
EricLew 0:d4e5ad7ad71c 79
EricLew 0:d4e5ad7ad71c 80 __Vectors DCD __initial_sp ; Top of Stack
EricLew 0:d4e5ad7ad71c 81 DCD Reset_Handler ; Reset Handler
EricLew 0:d4e5ad7ad71c 82 DCD NMI_Handler ; NMI Handler
EricLew 0:d4e5ad7ad71c 83 DCD HardFault_Handler ; Hard Fault Handler
EricLew 0:d4e5ad7ad71c 84 DCD MemManage_Handler ; MPU Fault Handler
EricLew 0:d4e5ad7ad71c 85 DCD BusFault_Handler ; Bus Fault Handler
EricLew 0:d4e5ad7ad71c 86 DCD UsageFault_Handler ; Usage Fault Handler
EricLew 0:d4e5ad7ad71c 87 DCD 0 ; Reserved
EricLew 0:d4e5ad7ad71c 88 DCD 0 ; Reserved
EricLew 0:d4e5ad7ad71c 89 DCD 0 ; Reserved
EricLew 0:d4e5ad7ad71c 90 DCD 0 ; Reserved
EricLew 0:d4e5ad7ad71c 91 DCD SVC_Handler ; SVCall Handler
EricLew 0:d4e5ad7ad71c 92 DCD DebugMon_Handler ; Debug Monitor Handler
EricLew 0:d4e5ad7ad71c 93 DCD 0 ; Reserved
EricLew 0:d4e5ad7ad71c 94 DCD PendSV_Handler ; PendSV Handler
EricLew 0:d4e5ad7ad71c 95 DCD SysTick_Handler ; SysTick Handler
EricLew 0:d4e5ad7ad71c 96
EricLew 0:d4e5ad7ad71c 97 ; External Interrupts
EricLew 0:d4e5ad7ad71c 98 DCD WWDG_IRQHandler ; Window WatchDog
EricLew 0:d4e5ad7ad71c 99 DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
EricLew 0:d4e5ad7ad71c 100 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
EricLew 0:d4e5ad7ad71c 101 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
EricLew 0:d4e5ad7ad71c 102 DCD FLASH_IRQHandler ; FLASH
EricLew 0:d4e5ad7ad71c 103 DCD RCC_IRQHandler ; RCC
EricLew 0:d4e5ad7ad71c 104 DCD EXTI0_IRQHandler ; EXTI Line0
EricLew 0:d4e5ad7ad71c 105 DCD EXTI1_IRQHandler ; EXTI Line1
EricLew 0:d4e5ad7ad71c 106 DCD EXTI2_IRQHandler ; EXTI Line2
EricLew 0:d4e5ad7ad71c 107 DCD EXTI3_IRQHandler ; EXTI Line3
EricLew 0:d4e5ad7ad71c 108 DCD EXTI4_IRQHandler ; EXTI Line4
EricLew 0:d4e5ad7ad71c 109 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
EricLew 0:d4e5ad7ad71c 110 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
EricLew 0:d4e5ad7ad71c 111 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
EricLew 0:d4e5ad7ad71c 112 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
EricLew 0:d4e5ad7ad71c 113 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
EricLew 0:d4e5ad7ad71c 114 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
EricLew 0:d4e5ad7ad71c 115 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
EricLew 0:d4e5ad7ad71c 116 DCD ADC1_2_IRQHandler ; ADC1, ADC2
EricLew 0:d4e5ad7ad71c 117 DCD CAN1_TX_IRQHandler ; CAN1 TX
EricLew 0:d4e5ad7ad71c 118 DCD CAN1_RX0_IRQHandler ; CAN1 RX0
EricLew 0:d4e5ad7ad71c 119 DCD CAN1_RX1_IRQHandler ; CAN1 RX1
EricLew 0:d4e5ad7ad71c 120 DCD CAN1_SCE_IRQHandler ; CAN1 SCE
EricLew 0:d4e5ad7ad71c 121 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
EricLew 0:d4e5ad7ad71c 122 DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
EricLew 0:d4e5ad7ad71c 123 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
EricLew 0:d4e5ad7ad71c 124 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
EricLew 0:d4e5ad7ad71c 125 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
EricLew 0:d4e5ad7ad71c 126 DCD TIM2_IRQHandler ; TIM2
EricLew 0:d4e5ad7ad71c 127 DCD TIM3_IRQHandler ; TIM3
EricLew 0:d4e5ad7ad71c 128 DCD TIM4_IRQHandler ; TIM4
EricLew 0:d4e5ad7ad71c 129 DCD I2C1_EV_IRQHandler ; I2C1 Event
EricLew 0:d4e5ad7ad71c 130 DCD I2C1_ER_IRQHandler ; I2C1 Error
EricLew 0:d4e5ad7ad71c 131 DCD I2C2_EV_IRQHandler ; I2C2 Event
EricLew 0:d4e5ad7ad71c 132 DCD I2C2_ER_IRQHandler ; I2C2 Error
EricLew 0:d4e5ad7ad71c 133 DCD SPI1_IRQHandler ; SPI1
EricLew 0:d4e5ad7ad71c 134 DCD SPI2_IRQHandler ; SPI2
EricLew 0:d4e5ad7ad71c 135 DCD USART1_IRQHandler ; USART1
EricLew 0:d4e5ad7ad71c 136 DCD USART2_IRQHandler ; USART2
EricLew 0:d4e5ad7ad71c 137 DCD USART3_IRQHandler ; USART3
EricLew 0:d4e5ad7ad71c 138 DCD EXTI15_10_IRQHandler ; External Line[15:10]
EricLew 0:d4e5ad7ad71c 139 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
EricLew 0:d4e5ad7ad71c 140 DCD DFSDM3_IRQHandler ; SD Filter 3 global Interrupt
EricLew 0:d4e5ad7ad71c 141 DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
EricLew 0:d4e5ad7ad71c 142 DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
EricLew 0:d4e5ad7ad71c 143 DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
EricLew 0:d4e5ad7ad71c 144 DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
EricLew 0:d4e5ad7ad71c 145 DCD ADC3_IRQHandler ; ADC3 global Interrupt
EricLew 0:d4e5ad7ad71c 146 DCD FMC_IRQHandler ; FMC
EricLew 0:d4e5ad7ad71c 147 DCD SDMMC1_IRQHandler ; SDMMC1
EricLew 0:d4e5ad7ad71c 148 DCD TIM5_IRQHandler ; TIM5
EricLew 0:d4e5ad7ad71c 149 DCD SPI3_IRQHandler ; SPI3
EricLew 0:d4e5ad7ad71c 150 DCD UART4_IRQHandler ; UART4
EricLew 0:d4e5ad7ad71c 151 DCD UART5_IRQHandler ; UART5
EricLew 0:d4e5ad7ad71c 152 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
EricLew 0:d4e5ad7ad71c 153 DCD TIM7_IRQHandler ; TIM7
EricLew 0:d4e5ad7ad71c 154 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
EricLew 0:d4e5ad7ad71c 155 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
EricLew 0:d4e5ad7ad71c 156 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
EricLew 0:d4e5ad7ad71c 157 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
EricLew 0:d4e5ad7ad71c 158 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
EricLew 0:d4e5ad7ad71c 159 DCD DFSDM0_IRQHandler ; SD Filter 0 global Interrupt
EricLew 0:d4e5ad7ad71c 160 DCD DFSDM1_IRQHandler ; SD Filter 1 global Interrupt
EricLew 0:d4e5ad7ad71c 161 DCD DFSDM2_IRQHandler ; SD Filter 2 global Interrupt
EricLew 0:d4e5ad7ad71c 162 DCD COMP_IRQHandler ; COMP Interrupt
EricLew 0:d4e5ad7ad71c 163 DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
EricLew 0:d4e5ad7ad71c 164 DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
EricLew 0:d4e5ad7ad71c 165 DCD OTG_FS_IRQHandler ; USB OTG FS
EricLew 0:d4e5ad7ad71c 166 DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
EricLew 0:d4e5ad7ad71c 167 DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
EricLew 0:d4e5ad7ad71c 168 DCD LPUART1_IRQHandler ; LP UART1 interrupt
EricLew 0:d4e5ad7ad71c 169 DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
EricLew 0:d4e5ad7ad71c 170 DCD I2C3_EV_IRQHandler ; I2C3 event
EricLew 0:d4e5ad7ad71c 171 DCD I2C3_ER_IRQHandler ; I2C3 error
EricLew 0:d4e5ad7ad71c 172 DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
EricLew 0:d4e5ad7ad71c 173 DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
EricLew 0:d4e5ad7ad71c 174 DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
EricLew 0:d4e5ad7ad71c 175 DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
EricLew 0:d4e5ad7ad71c 176 DCD LCD_IRQHandler ; LCD global interrupt
EricLew 0:d4e5ad7ad71c 177 DCD 0 ; Reserved
EricLew 0:d4e5ad7ad71c 178 DCD RNG_IRQHandler ; RNG global interrupt
EricLew 0:d4e5ad7ad71c 179 DCD FPU_IRQHandler ; FPU
EricLew 0:d4e5ad7ad71c 180
EricLew 0:d4e5ad7ad71c 181 __Vectors_End
EricLew 0:d4e5ad7ad71c 182
EricLew 0:d4e5ad7ad71c 183 __Vectors_Size EQU __Vectors_End - __Vectors
EricLew 0:d4e5ad7ad71c 184
EricLew 0:d4e5ad7ad71c 185 AREA |.text|, CODE, READONLY
EricLew 0:d4e5ad7ad71c 186
EricLew 0:d4e5ad7ad71c 187 ; Reset handler
EricLew 0:d4e5ad7ad71c 188 Reset_Handler PROC
EricLew 0:d4e5ad7ad71c 189 EXPORT Reset_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 190 IMPORT SystemInit
EricLew 0:d4e5ad7ad71c 191 IMPORT __main
EricLew 0:d4e5ad7ad71c 192
EricLew 0:d4e5ad7ad71c 193 LDR R0, =SystemInit
EricLew 0:d4e5ad7ad71c 194 BLX R0
EricLew 0:d4e5ad7ad71c 195 LDR R0, =__main
EricLew 0:d4e5ad7ad71c 196 BX R0
EricLew 0:d4e5ad7ad71c 197 ENDP
EricLew 0:d4e5ad7ad71c 198
EricLew 0:d4e5ad7ad71c 199 ; Dummy Exception Handlers (infinite loops which can be modified)
EricLew 0:d4e5ad7ad71c 200
EricLew 0:d4e5ad7ad71c 201 NMI_Handler PROC
EricLew 0:d4e5ad7ad71c 202 EXPORT NMI_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 203 B .
EricLew 0:d4e5ad7ad71c 204 ENDP
EricLew 0:d4e5ad7ad71c 205 HardFault_Handler\
EricLew 0:d4e5ad7ad71c 206 PROC
EricLew 0:d4e5ad7ad71c 207 EXPORT HardFault_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 208 B .
EricLew 0:d4e5ad7ad71c 209 ENDP
EricLew 0:d4e5ad7ad71c 210 MemManage_Handler\
EricLew 0:d4e5ad7ad71c 211 PROC
EricLew 0:d4e5ad7ad71c 212 EXPORT MemManage_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 213 B .
EricLew 0:d4e5ad7ad71c 214 ENDP
EricLew 0:d4e5ad7ad71c 215 BusFault_Handler\
EricLew 0:d4e5ad7ad71c 216 PROC
EricLew 0:d4e5ad7ad71c 217 EXPORT BusFault_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 218 B .
EricLew 0:d4e5ad7ad71c 219 ENDP
EricLew 0:d4e5ad7ad71c 220 UsageFault_Handler\
EricLew 0:d4e5ad7ad71c 221 PROC
EricLew 0:d4e5ad7ad71c 222 EXPORT UsageFault_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 223 B .
EricLew 0:d4e5ad7ad71c 224 ENDP
EricLew 0:d4e5ad7ad71c 225 SVC_Handler PROC
EricLew 0:d4e5ad7ad71c 226 EXPORT SVC_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 227 B .
EricLew 0:d4e5ad7ad71c 228 ENDP
EricLew 0:d4e5ad7ad71c 229 DebugMon_Handler\
EricLew 0:d4e5ad7ad71c 230 PROC
EricLew 0:d4e5ad7ad71c 231 EXPORT DebugMon_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 232 B .
EricLew 0:d4e5ad7ad71c 233 ENDP
EricLew 0:d4e5ad7ad71c 234 PendSV_Handler PROC
EricLew 0:d4e5ad7ad71c 235 EXPORT PendSV_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 236 B .
EricLew 0:d4e5ad7ad71c 237 ENDP
EricLew 0:d4e5ad7ad71c 238 SysTick_Handler PROC
EricLew 0:d4e5ad7ad71c 239 EXPORT SysTick_Handler [WEAK]
EricLew 0:d4e5ad7ad71c 240 B .
EricLew 0:d4e5ad7ad71c 241 ENDP
EricLew 0:d4e5ad7ad71c 242
EricLew 0:d4e5ad7ad71c 243 Default_Handler PROC
EricLew 0:d4e5ad7ad71c 244
EricLew 0:d4e5ad7ad71c 245 EXPORT WWDG_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 246 EXPORT PVD_PVM_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 247 EXPORT TAMP_STAMP_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 248 EXPORT RTC_WKUP_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 249 EXPORT FLASH_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 250 EXPORT RCC_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 251 EXPORT EXTI0_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 252 EXPORT EXTI1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 253 EXPORT EXTI2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 254 EXPORT EXTI3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 255 EXPORT EXTI4_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 256 EXPORT DMA1_Channel1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 257 EXPORT DMA1_Channel2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 258 EXPORT DMA1_Channel3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 259 EXPORT DMA1_Channel4_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 260 EXPORT DMA1_Channel5_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 261 EXPORT DMA1_Channel6_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 262 EXPORT DMA1_Channel7_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 263 EXPORT ADC1_2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 264 EXPORT CAN1_TX_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 265 EXPORT CAN1_RX0_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 266 EXPORT CAN1_RX1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 267 EXPORT CAN1_SCE_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 268 EXPORT EXTI9_5_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 269 EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 270 EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 271 EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 272 EXPORT TIM1_CC_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 273 EXPORT TIM2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 274 EXPORT TIM3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 275 EXPORT TIM4_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 276 EXPORT I2C1_EV_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 277 EXPORT I2C1_ER_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 278 EXPORT I2C2_EV_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 279 EXPORT I2C2_ER_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 280 EXPORT SPI1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 281 EXPORT SPI2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 282 EXPORT USART1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 283 EXPORT USART2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 284 EXPORT USART3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 285 EXPORT EXTI15_10_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 286 EXPORT RTC_Alarm_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 287 EXPORT DFSDM3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 288 EXPORT TIM8_BRK_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 289 EXPORT TIM8_UP_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 290 EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 291 EXPORT TIM8_CC_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 292 EXPORT ADC3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 293 EXPORT FMC_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 294 EXPORT SDMMC1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 295 EXPORT TIM5_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 296 EXPORT SPI3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 297 EXPORT UART4_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 298 EXPORT UART5_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 299 EXPORT TIM6_DAC_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 300 EXPORT TIM7_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 301 EXPORT DMA2_Channel1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 302 EXPORT DMA2_Channel2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 303 EXPORT DMA2_Channel3_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 304 EXPORT DMA2_Channel4_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 305 EXPORT DMA2_Channel5_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 306 EXPORT DFSDM0_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 307 EXPORT DFSDM1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 308 EXPORT DFSDM2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 309 EXPORT COMP_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 310 EXPORT LPTIM1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 311 EXPORT LPTIM2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 312 EXPORT OTG_FS_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 313 EXPORT DMA2_Channel6_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 314 EXPORT DMA2_Channel7_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 315 EXPORT LPUART1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 316 EXPORT QUADSPI_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 317 EXPORT I2C3_EV_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 318 EXPORT I2C3_ER_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 319 EXPORT SAI1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 320 EXPORT SAI2_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 321 EXPORT SWPMI1_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 322 EXPORT TSC_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 323 EXPORT LCD_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 324 EXPORT RNG_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 325 EXPORT FPU_IRQHandler [WEAK]
EricLew 0:d4e5ad7ad71c 326
EricLew 0:d4e5ad7ad71c 327 WWDG_IRQHandler
EricLew 0:d4e5ad7ad71c 328 PVD_PVM_IRQHandler
EricLew 0:d4e5ad7ad71c 329 TAMP_STAMP_IRQHandler
EricLew 0:d4e5ad7ad71c 330 RTC_WKUP_IRQHandler
EricLew 0:d4e5ad7ad71c 331 FLASH_IRQHandler
EricLew 0:d4e5ad7ad71c 332 RCC_IRQHandler
EricLew 0:d4e5ad7ad71c 333 EXTI0_IRQHandler
EricLew 0:d4e5ad7ad71c 334 EXTI1_IRQHandler
EricLew 0:d4e5ad7ad71c 335 EXTI2_IRQHandler
EricLew 0:d4e5ad7ad71c 336 EXTI3_IRQHandler
EricLew 0:d4e5ad7ad71c 337 EXTI4_IRQHandler
EricLew 0:d4e5ad7ad71c 338 DMA1_Channel1_IRQHandler
EricLew 0:d4e5ad7ad71c 339 DMA1_Channel2_IRQHandler
EricLew 0:d4e5ad7ad71c 340 DMA1_Channel3_IRQHandler
EricLew 0:d4e5ad7ad71c 341 DMA1_Channel4_IRQHandler
EricLew 0:d4e5ad7ad71c 342 DMA1_Channel5_IRQHandler
EricLew 0:d4e5ad7ad71c 343 DMA1_Channel6_IRQHandler
EricLew 0:d4e5ad7ad71c 344 DMA1_Channel7_IRQHandler
EricLew 0:d4e5ad7ad71c 345 ADC1_2_IRQHandler
EricLew 0:d4e5ad7ad71c 346 CAN1_TX_IRQHandler
EricLew 0:d4e5ad7ad71c 347 CAN1_RX0_IRQHandler
EricLew 0:d4e5ad7ad71c 348 CAN1_RX1_IRQHandler
EricLew 0:d4e5ad7ad71c 349 CAN1_SCE_IRQHandler
EricLew 0:d4e5ad7ad71c 350 EXTI9_5_IRQHandler
EricLew 0:d4e5ad7ad71c 351 TIM1_BRK_TIM15_IRQHandler
EricLew 0:d4e5ad7ad71c 352 TIM1_UP_TIM16_IRQHandler
EricLew 0:d4e5ad7ad71c 353 TIM1_TRG_COM_TIM17_IRQHandler
EricLew 0:d4e5ad7ad71c 354 TIM1_CC_IRQHandler
EricLew 0:d4e5ad7ad71c 355 TIM2_IRQHandler
EricLew 0:d4e5ad7ad71c 356 TIM3_IRQHandler
EricLew 0:d4e5ad7ad71c 357 TIM4_IRQHandler
EricLew 0:d4e5ad7ad71c 358 I2C1_EV_IRQHandler
EricLew 0:d4e5ad7ad71c 359 I2C1_ER_IRQHandler
EricLew 0:d4e5ad7ad71c 360 I2C2_EV_IRQHandler
EricLew 0:d4e5ad7ad71c 361 I2C2_ER_IRQHandler
EricLew 0:d4e5ad7ad71c 362 SPI1_IRQHandler
EricLew 0:d4e5ad7ad71c 363 SPI2_IRQHandler
EricLew 0:d4e5ad7ad71c 364 USART1_IRQHandler
EricLew 0:d4e5ad7ad71c 365 USART2_IRQHandler
EricLew 0:d4e5ad7ad71c 366 USART3_IRQHandler
EricLew 0:d4e5ad7ad71c 367 EXTI15_10_IRQHandler
EricLew 0:d4e5ad7ad71c 368 RTC_Alarm_IRQHandler
EricLew 0:d4e5ad7ad71c 369 DFSDM3_IRQHandler
EricLew 0:d4e5ad7ad71c 370 TIM8_BRK_IRQHandler
EricLew 0:d4e5ad7ad71c 371 TIM8_UP_IRQHandler
EricLew 0:d4e5ad7ad71c 372 TIM8_TRG_COM_IRQHandler
EricLew 0:d4e5ad7ad71c 373 TIM8_CC_IRQHandler
EricLew 0:d4e5ad7ad71c 374 ADC3_IRQHandler
EricLew 0:d4e5ad7ad71c 375 FMC_IRQHandler
EricLew 0:d4e5ad7ad71c 376 SDMMC1_IRQHandler
EricLew 0:d4e5ad7ad71c 377 TIM5_IRQHandler
EricLew 0:d4e5ad7ad71c 378 SPI3_IRQHandler
EricLew 0:d4e5ad7ad71c 379 UART4_IRQHandler
EricLew 0:d4e5ad7ad71c 380 UART5_IRQHandler
EricLew 0:d4e5ad7ad71c 381 TIM6_DAC_IRQHandler
EricLew 0:d4e5ad7ad71c 382 TIM7_IRQHandler
EricLew 0:d4e5ad7ad71c 383 DMA2_Channel1_IRQHandler
EricLew 0:d4e5ad7ad71c 384 DMA2_Channel2_IRQHandler
EricLew 0:d4e5ad7ad71c 385 DMA2_Channel3_IRQHandler
EricLew 0:d4e5ad7ad71c 386 DMA2_Channel4_IRQHandler
EricLew 0:d4e5ad7ad71c 387 DMA2_Channel5_IRQHandler
EricLew 0:d4e5ad7ad71c 388 DFSDM0_IRQHandler
EricLew 0:d4e5ad7ad71c 389 DFSDM1_IRQHandler
EricLew 0:d4e5ad7ad71c 390 DFSDM2_IRQHandler
EricLew 0:d4e5ad7ad71c 391 COMP_IRQHandler
EricLew 0:d4e5ad7ad71c 392 LPTIM1_IRQHandler
EricLew 0:d4e5ad7ad71c 393 LPTIM2_IRQHandler
EricLew 0:d4e5ad7ad71c 394 OTG_FS_IRQHandler
EricLew 0:d4e5ad7ad71c 395 DMA2_Channel6_IRQHandler
EricLew 0:d4e5ad7ad71c 396 DMA2_Channel7_IRQHandler
EricLew 0:d4e5ad7ad71c 397 LPUART1_IRQHandler
EricLew 0:d4e5ad7ad71c 398 QUADSPI_IRQHandler
EricLew 0:d4e5ad7ad71c 399 I2C3_EV_IRQHandler
EricLew 0:d4e5ad7ad71c 400 I2C3_ER_IRQHandler
EricLew 0:d4e5ad7ad71c 401 SAI1_IRQHandler
EricLew 0:d4e5ad7ad71c 402 SAI2_IRQHandler
EricLew 0:d4e5ad7ad71c 403 SWPMI1_IRQHandler
EricLew 0:d4e5ad7ad71c 404 TSC_IRQHandler
EricLew 0:d4e5ad7ad71c 405 LCD_IRQHandler
EricLew 0:d4e5ad7ad71c 406 RNG_IRQHandler
EricLew 0:d4e5ad7ad71c 407 FPU_IRQHandler
EricLew 0:d4e5ad7ad71c 408
EricLew 0:d4e5ad7ad71c 409 B .
EricLew 0:d4e5ad7ad71c 410
EricLew 0:d4e5ad7ad71c 411 ENDP
EricLew 0:d4e5ad7ad71c 412
EricLew 0:d4e5ad7ad71c 413 ALIGN
EricLew 0:d4e5ad7ad71c 414
EricLew 0:d4e5ad7ad71c 415 ;*******************************************************************************
EricLew 0:d4e5ad7ad71c 416 ; User Stack and Heap initialization
EricLew 0:d4e5ad7ad71c 417 ;*******************************************************************************
EricLew 2:1066910a6cbc 418 ; IF :DEF:MICROLIB
EricLew 0:d4e5ad7ad71c 419 ;
EricLew 0:d4e5ad7ad71c 420 ; EXPORT __initial_sp
EricLew 0:d4e5ad7ad71c 421 ; EXPORT __heap_base
EricLew 0:d4e5ad7ad71c 422 ; EXPORT __heap_limit
EricLew 0:d4e5ad7ad71c 423 ;
EricLew 0:d4e5ad7ad71c 424 ; ELSE
EricLew 0:d4e5ad7ad71c 425 ;
EricLew 0:d4e5ad7ad71c 426 ; IMPORT __use_two_region_memory
EricLew 0:d4e5ad7ad71c 427 ; EXPORT __user_initial_stackheap
EricLew 0:d4e5ad7ad71c 428 ;
EricLew 0:d4e5ad7ad71c 429 ;__user_initial_stackheap
EricLew 0:d4e5ad7ad71c 430 ;
EricLew 0:d4e5ad7ad71c 431 ; LDR R0, = Heap_Mem
EricLew 0:d4e5ad7ad71c 432 ; LDR R1, =(Stack_Mem + Stack_Size)
EricLew 0:d4e5ad7ad71c 433 ; LDR R2, = (Heap_Mem + Heap_Size)
EricLew 0:d4e5ad7ad71c 434 ; LDR R3, = Stack_Mem
EricLew 0:d4e5ad7ad71c 435 ; BX LR
EricLew 0:d4e5ad7ad71c 436 ;
EricLew 0:d4e5ad7ad71c 437 ; ALIGN
EricLew 0:d4e5ad7ad71c 438 ;
EricLew 0:d4e5ad7ad71c 439 ; ENDIF
EricLew 0:d4e5ad7ad71c 440 ;
EricLew 0:d4e5ad7ad71c 441 END
EricLew 0:d4e5ad7ad71c 442
EricLew 0:d4e5ad7ad71c 443 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
EricLew 0:d4e5ad7ad71c 444