Senior Design: Sound Monitor / FINAL_AUDIO_RECORD

AudioRecord and FFT/MSE comparison. Call AudioRecord_demo for control record and AudioSample for subsequent recordings.

Dependencies:   CMSIS_DSP_401 STM32L4xx_HAL_Driver

Fork of OneHopeOnePrayer by Senior Design: Sound Monitor

system_stm32l4xx.c@5:f6afbd3fc47a, 2015-12-05 (annotated)

Committer:
EricLew
Date:
Sat Dec 05 16:17:25 2015 +0000
Revision:
5:f6afbd3fc47a
Parent:
0:d4e5ad7ad71c 
Ported to Nucleo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:d4e5ad7ad71c 1 /**
EricLew 0:d4e5ad7ad71c 2 ******************************************************************************
EricLew 0:d4e5ad7ad71c 3 * @file system_stm32l4xx.c
EricLew 0:d4e5ad7ad71c 4 * @author MCD Application Team
EricLew 0:d4e5ad7ad71c 5 * @version V1.1.0
EricLew 0:d4e5ad7ad71c 6 * @date 16-September-2015
EricLew 0:d4e5ad7ad71c 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
EricLew 0:d4e5ad7ad71c 8 *
EricLew 0:d4e5ad7ad71c 9 * This file provides two functions and one global variable to be called from
EricLew 0:d4e5ad7ad71c 10 * user application:
EricLew 0:d4e5ad7ad71c 11 * - SystemInit(): This function is called at startup just after reset and
EricLew 0:d4e5ad7ad71c 12 * before branch to main program. This call is made inside
EricLew 0:d4e5ad7ad71c 13 * the "startup_stm32l4xx.s" file.
EricLew 0:d4e5ad7ad71c 14 *
EricLew 0:d4e5ad7ad71c 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
EricLew 0:d4e5ad7ad71c 16 * by the user application to setup the SysTick
EricLew 0:d4e5ad7ad71c 17 * timer or configure other parameters.
EricLew 0:d4e5ad7ad71c 18 *
EricLew 0:d4e5ad7ad71c 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
EricLew 0:d4e5ad7ad71c 20 * be called whenever the core clock is changed
EricLew 0:d4e5ad7ad71c 21 * during program execution.
EricLew 0:d4e5ad7ad71c 22 *
EricLew 0:d4e5ad7ad71c 23 * After each device reset the MSI (4 MHz) is used as system clock source.
EricLew 0:d4e5ad7ad71c 24 * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
EricLew 0:d4e5ad7ad71c 25 * configure the system clock before to branch to main program.
EricLew 0:d4e5ad7ad71c 26 *
EricLew 0:d4e5ad7ad71c 27 * This file configures the system clock as follows:
EricLew 0:d4e5ad7ad71c 28 *=============================================================================
EricLew 0:d4e5ad7ad71c 29 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 30 * System Clock source | MSI
EricLew 0:d4e5ad7ad71c 31 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 32 * SYSCLK(Hz) | 4000000
EricLew 0:d4e5ad7ad71c 33 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 34 * HCLK(Hz) | 4000000
EricLew 0:d4e5ad7ad71c 35 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 36 * AHB Prescaler | 1
EricLew 0:d4e5ad7ad71c 37 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 38 * APB1 Prescaler | 1
EricLew 0:d4e5ad7ad71c 39 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 40 * APB2 Prescaler | 1
EricLew 0:d4e5ad7ad71c 41 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 42 * PLL_M | 1
EricLew 0:d4e5ad7ad71c 43 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 44 * PLL_N | 8
EricLew 0:d4e5ad7ad71c 45 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 46 * PLL_P | 7
EricLew 0:d4e5ad7ad71c 47 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 48 * PLL_Q | 2
EricLew 0:d4e5ad7ad71c 49 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 50 * PLL_R | 2
EricLew 0:d4e5ad7ad71c 51 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 52 * PLLSAI1_P | NA
EricLew 0:d4e5ad7ad71c 53 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 54 * PLLSAI1_Q | NA
EricLew 0:d4e5ad7ad71c 55 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 56 * PLLSAI1_R | NA
EricLew 0:d4e5ad7ad71c 57 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 58 * PLLSAI2_P | NA
EricLew 0:d4e5ad7ad71c 59 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 60 * PLLSAI2_Q | NA
EricLew 0:d4e5ad7ad71c 61 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 62 * PLLSAI2_R | NA
EricLew 0:d4e5ad7ad71c 63 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 64 * Require 48MHz for USB OTG FS, | Disabled
EricLew 0:d4e5ad7ad71c 65 * SDIO and RNG clock |
EricLew 0:d4e5ad7ad71c 66 *-----------------------------------------------------------------------------
EricLew 0:d4e5ad7ad71c 67 *=============================================================================
EricLew 0:d4e5ad7ad71c 68 ******************************************************************************
EricLew 0:d4e5ad7ad71c 69 * @attention
EricLew 0:d4e5ad7ad71c 70 *
EricLew 0:d4e5ad7ad71c 71 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
EricLew 0:d4e5ad7ad71c 72 *
EricLew 0:d4e5ad7ad71c 73 * Redistribution and use in source and binary forms, with or without modification,
EricLew 0:d4e5ad7ad71c 74 * are permitted provided that the following conditions are met:
EricLew 0:d4e5ad7ad71c 75 * 1. Redistributions of source code must retain the above copyright notice,
EricLew 0:d4e5ad7ad71c 76 * this list of conditions and the following disclaimer.
EricLew 0:d4e5ad7ad71c 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
EricLew 0:d4e5ad7ad71c 78 * this list of conditions and the following disclaimer in the documentation
EricLew 0:d4e5ad7ad71c 79 * and/or other materials provided with the distribution.
EricLew 0:d4e5ad7ad71c 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
EricLew 0:d4e5ad7ad71c 81 * may be used to endorse or promote products derived from this software
EricLew 0:d4e5ad7ad71c 82 * without specific prior written permission.
EricLew 0:d4e5ad7ad71c 83 *
EricLew 0:d4e5ad7ad71c 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:d4e5ad7ad71c 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:d4e5ad7ad71c 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
EricLew 0:d4e5ad7ad71c 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
EricLew 0:d4e5ad7ad71c 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
EricLew 0:d4e5ad7ad71c 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
EricLew 0:d4e5ad7ad71c 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
EricLew 0:d4e5ad7ad71c 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
EricLew 0:d4e5ad7ad71c 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
EricLew 0:d4e5ad7ad71c 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
EricLew 0:d4e5ad7ad71c 94 *
EricLew 0:d4e5ad7ad71c 95 ******************************************************************************
EricLew 0:d4e5ad7ad71c 96 */
EricLew 0:d4e5ad7ad71c 97
EricLew 0:d4e5ad7ad71c 98 /** @addtogroup CMSIS
EricLew 0:d4e5ad7ad71c 99 * @{
EricLew 0:d4e5ad7ad71c 100 */
EricLew 0:d4e5ad7ad71c 101
EricLew 0:d4e5ad7ad71c 102 /** @addtogroup stm32l4xx_system
EricLew 0:d4e5ad7ad71c 103 * @{
EricLew 0:d4e5ad7ad71c 104 */
EricLew 0:d4e5ad7ad71c 105
EricLew 0:d4e5ad7ad71c 106 /** @addtogroup STM32L4xx_System_Private_Includes
EricLew 0:d4e5ad7ad71c 107 * @{
EricLew 0:d4e5ad7ad71c 108 */
EricLew 0:d4e5ad7ad71c 109
EricLew 0:d4e5ad7ad71c 110 #include "stm32l4xx.h"
EricLew 0:d4e5ad7ad71c 111
EricLew 0:d4e5ad7ad71c 112 #if !defined (HSE_VALUE)
EricLew 0:d4e5ad7ad71c 113 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
EricLew 0:d4e5ad7ad71c 114 #endif /* HSE_VALUE */
EricLew 0:d4e5ad7ad71c 115
EricLew 0:d4e5ad7ad71c 116 #if !defined (MSI_VALUE)
EricLew 0:d4e5ad7ad71c 117 #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
EricLew 0:d4e5ad7ad71c 118 #endif /* MSI_VALUE */
EricLew 0:d4e5ad7ad71c 119
EricLew 0:d4e5ad7ad71c 120 #if !defined (HSI_VALUE)
EricLew 0:d4e5ad7ad71c 121 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
EricLew 0:d4e5ad7ad71c 122 #endif /* HSI_VALUE */
EricLew 0:d4e5ad7ad71c 123
EricLew 0:d4e5ad7ad71c 124 /**
EricLew 0:d4e5ad7ad71c 125 * @}
EricLew 0:d4e5ad7ad71c 126 */
EricLew 0:d4e5ad7ad71c 127
EricLew 0:d4e5ad7ad71c 128 /** @addtogroup STM32L4xx_System_Private_TypesDefinitions
EricLew 0:d4e5ad7ad71c 129 * @{
EricLew 0:d4e5ad7ad71c 130 */
EricLew 0:d4e5ad7ad71c 131
EricLew 0:d4e5ad7ad71c 132 /**
EricLew 0:d4e5ad7ad71c 133 * @}
EricLew 0:d4e5ad7ad71c 134 */
EricLew 0:d4e5ad7ad71c 135
EricLew 0:d4e5ad7ad71c 136 /** @addtogroup STM32L4xx_System_Private_Defines
EricLew 0:d4e5ad7ad71c 137 * @{
EricLew 0:d4e5ad7ad71c 138 */
EricLew 0:d4e5ad7ad71c 139
EricLew 0:d4e5ad7ad71c 140 /************************* Miscellaneous Configuration ************************/
EricLew 0:d4e5ad7ad71c 141 /*!< Uncomment the following line if you need to relocate your vector Table in
EricLew 0:d4e5ad7ad71c 142 Internal SRAM. */
EricLew 0:d4e5ad7ad71c 143 /* #define VECT_TAB_SRAM */
EricLew 0:d4e5ad7ad71c 144 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
EricLew 0:d4e5ad7ad71c 145 This value must be a multiple of 0x200. */
EricLew 0:d4e5ad7ad71c 146 /******************************************************************************/
EricLew 0:d4e5ad7ad71c 147 /**
EricLew 0:d4e5ad7ad71c 148 * @}
EricLew 0:d4e5ad7ad71c 149 */
EricLew 0:d4e5ad7ad71c 150
EricLew 0:d4e5ad7ad71c 151 /** @addtogroup STM32L4xx_System_Private_Macros
EricLew 0:d4e5ad7ad71c 152 * @{
EricLew 0:d4e5ad7ad71c 153 */
EricLew 0:d4e5ad7ad71c 154
EricLew 0:d4e5ad7ad71c 155 /**
EricLew 0:d4e5ad7ad71c 156 * @}
EricLew 0:d4e5ad7ad71c 157 */
EricLew 0:d4e5ad7ad71c 158
EricLew 0:d4e5ad7ad71c 159 /** @addtogroup STM32L4xx_System_Private_Variables
EricLew 0:d4e5ad7ad71c 160 * @{
EricLew 0:d4e5ad7ad71c 161 */
EricLew 0:d4e5ad7ad71c 162 /* This variable is updated in three ways:
EricLew 0:d4e5ad7ad71c 163 1) by calling CMSIS function SystemCoreClockUpdate()
EricLew 0:d4e5ad7ad71c 164 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
EricLew 0:d4e5ad7ad71c 165 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
EricLew 0:d4e5ad7ad71c 166 Note: If you use this function to configure the system clock; then there
EricLew 0:d4e5ad7ad71c 167 is no need to call the 2 first functions listed above, since SystemCoreClock
EricLew 0:d4e5ad7ad71c 168 variable is updated automatically.
EricLew 0:d4e5ad7ad71c 169 */
EricLew 0:d4e5ad7ad71c 170 uint32_t SystemCoreClock = 4000000;
EricLew 0:d4e5ad7ad71c 171
EricLew 0:d4e5ad7ad71c 172 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
EricLew 0:d4e5ad7ad71c 173 const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
EricLew 0:d4e5ad7ad71c 174 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
EricLew 0:d4e5ad7ad71c 175 /**
EricLew 0:d4e5ad7ad71c 176 * @}
EricLew 0:d4e5ad7ad71c 177 */
EricLew 0:d4e5ad7ad71c 178
EricLew 0:d4e5ad7ad71c 179 /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
EricLew 0:d4e5ad7ad71c 180 * @{
EricLew 0:d4e5ad7ad71c 181 */
EricLew 0:d4e5ad7ad71c 182
EricLew 0:d4e5ad7ad71c 183 /**
EricLew 0:d4e5ad7ad71c 184 * @}
EricLew 0:d4e5ad7ad71c 185 */
EricLew 0:d4e5ad7ad71c 186
EricLew 0:d4e5ad7ad71c 187 /** @addtogroup STM32L4xx_System_Private_Functions
EricLew 0:d4e5ad7ad71c 188 * @{
EricLew 0:d4e5ad7ad71c 189 */
EricLew 0:d4e5ad7ad71c 190
EricLew 0:d4e5ad7ad71c 191 /**
EricLew 0:d4e5ad7ad71c 192 * @brief Setup the microcontroller system.
EricLew 0:d4e5ad7ad71c 193 * @param None
EricLew 0:d4e5ad7ad71c 194 * @retval None
EricLew 0:d4e5ad7ad71c 195 */
EricLew 0:d4e5ad7ad71c 196
EricLew 0:d4e5ad7ad71c 197 void SystemInit(void)
EricLew 0:d4e5ad7ad71c 198 {
EricLew 0:d4e5ad7ad71c 199 /* FPU settings ------------------------------------------------------------*/
EricLew 0:d4e5ad7ad71c 200 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
EricLew 0:d4e5ad7ad71c 201 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
EricLew 0:d4e5ad7ad71c 202 #endif
EricLew 0:d4e5ad7ad71c 203 /* Reset the RCC clock configuration to the default reset state ------------*/
EricLew 0:d4e5ad7ad71c 204 /* Set MSION bit */
EricLew 0:d4e5ad7ad71c 205 RCC->CR |= RCC_CR_MSION;
EricLew 0:d4e5ad7ad71c 206
EricLew 0:d4e5ad7ad71c 207 /* Reset CFGR register */
EricLew 0:d4e5ad7ad71c 208 RCC->CFGR = 0x00000000;
EricLew 0:d4e5ad7ad71c 209
EricLew 0:d4e5ad7ad71c 210 /* Reset HSEON, CSSON , HSION, and PLLON bits */
EricLew 0:d4e5ad7ad71c 211 RCC->CR &= (uint32_t)0xEAF6FFFF;
EricLew 0:d4e5ad7ad71c 212
EricLew 0:d4e5ad7ad71c 213 /* Reset PLLCFGR register */
EricLew 0:d4e5ad7ad71c 214 RCC->PLLCFGR = 0x00000800;
EricLew 0:d4e5ad7ad71c 215
EricLew 0:d4e5ad7ad71c 216 /* Reset HSEBYP bit */
EricLew 0:d4e5ad7ad71c 217 RCC->CR &= (uint32_t)0xFFFBFFFF;
EricLew 0:d4e5ad7ad71c 218
EricLew 0:d4e5ad7ad71c 219 /* Disable all interrupts */
EricLew 0:d4e5ad7ad71c 220 RCC->CIER = 0x00000000;
EricLew 0:d4e5ad7ad71c 221
EricLew 0:d4e5ad7ad71c 222 /* Configure the Vector Table location add offset address ------------------*/
EricLew 0:d4e5ad7ad71c 223 #ifdef VECT_TAB_SRAM
EricLew 0:d4e5ad7ad71c 224 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
EricLew 0:d4e5ad7ad71c 225 #else
EricLew 0:d4e5ad7ad71c 226 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
EricLew 0:d4e5ad7ad71c 227 #endif
EricLew 0:d4e5ad7ad71c 228 }
EricLew 0:d4e5ad7ad71c 229
EricLew 0:d4e5ad7ad71c 230 /**
EricLew 0:d4e5ad7ad71c 231 * @brief Update SystemCoreClock variable according to Clock Register Values.
EricLew 0:d4e5ad7ad71c 232 * The SystemCoreClock variable contains the core clock (HCLK), it can
EricLew 0:d4e5ad7ad71c 233 * be used by the user application to setup the SysTick timer or configure
EricLew 0:d4e5ad7ad71c 234 * other parameters.
EricLew 0:d4e5ad7ad71c 235 *
EricLew 0:d4e5ad7ad71c 236 * @note Each time the core clock (HCLK) changes, this function must be called
EricLew 0:d4e5ad7ad71c 237 * to update SystemCoreClock variable value. Otherwise, any configuration
EricLew 0:d4e5ad7ad71c 238 * based on this variable will be incorrect.
EricLew 0:d4e5ad7ad71c 239 *
EricLew 0:d4e5ad7ad71c 240 * @note - The system frequency computed by this function is not the real
EricLew 0:d4e5ad7ad71c 241 * frequency in the chip. It is calculated based on the predefined
EricLew 0:d4e5ad7ad71c 242 * constant and the selected clock source:
EricLew 0:d4e5ad7ad71c 243 *
EricLew 0:d4e5ad7ad71c 244 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
EricLew 0:d4e5ad7ad71c 245 *
EricLew 0:d4e5ad7ad71c 246 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
EricLew 0:d4e5ad7ad71c 247 *
EricLew 0:d4e5ad7ad71c 248 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
EricLew 0:d4e5ad7ad71c 249 *
EricLew 0:d4e5ad7ad71c 250 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
EricLew 0:d4e5ad7ad71c 251 * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
EricLew 0:d4e5ad7ad71c 252 *
EricLew 0:d4e5ad7ad71c 253 * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
EricLew 0:d4e5ad7ad71c 254 * 4 MHz) but the real value may vary depending on the variations
EricLew 0:d4e5ad7ad71c 255 * in voltage and temperature.
EricLew 0:d4e5ad7ad71c 256 *
EricLew 0:d4e5ad7ad71c 257 * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
EricLew 0:d4e5ad7ad71c 258 * 16 MHz) but the real value may vary depending on the variations
EricLew 0:d4e5ad7ad71c 259 * in voltage and temperature.
EricLew 0:d4e5ad7ad71c 260 *
EricLew 0:d4e5ad7ad71c 261 * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
EricLew 0:d4e5ad7ad71c 262 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
EricLew 0:d4e5ad7ad71c 263 * frequency of the crystal used. Otherwise, this function may
EricLew 0:d4e5ad7ad71c 264 * have wrong result.
EricLew 0:d4e5ad7ad71c 265 *
EricLew 0:d4e5ad7ad71c 266 * - The result of this function could be not correct when using fractional
EricLew 0:d4e5ad7ad71c 267 * value for HSE crystal.
EricLew 0:d4e5ad7ad71c 268 *
EricLew 0:d4e5ad7ad71c 269 * @param None
EricLew 0:d4e5ad7ad71c 270 * @retval None
EricLew 0:d4e5ad7ad71c 271 */
EricLew 0:d4e5ad7ad71c 272 void SystemCoreClockUpdate(void)
EricLew 0:d4e5ad7ad71c 273 {
EricLew 0:d4e5ad7ad71c 274 uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
EricLew 0:d4e5ad7ad71c 275
EricLew 0:d4e5ad7ad71c 276 /* Get MSI Range frequency--------------------------------------------------*/
EricLew 0:d4e5ad7ad71c 277 if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
EricLew 0:d4e5ad7ad71c 278 { /* MSISRANGE from RCC_CSR applies */
EricLew 0:d4e5ad7ad71c 279 msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
EricLew 0:d4e5ad7ad71c 280 }
EricLew 0:d4e5ad7ad71c 281 else
EricLew 0:d4e5ad7ad71c 282 { /* MSIRANGE from RCC_CR applies */
EricLew 0:d4e5ad7ad71c 283 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
EricLew 0:d4e5ad7ad71c 284 }
EricLew 0:d4e5ad7ad71c 285 /*MSI frequency range in HZ*/
EricLew 0:d4e5ad7ad71c 286 msirange = MSIRangeTable[msirange];
EricLew 0:d4e5ad7ad71c 287
EricLew 0:d4e5ad7ad71c 288 /* Get SYSCLK source -------------------------------------------------------*/
EricLew 0:d4e5ad7ad71c 289 switch (RCC->CFGR & RCC_CFGR_SWS)
EricLew 0:d4e5ad7ad71c 290 {
EricLew 0:d4e5ad7ad71c 291 case 0x00: /* MSI used as system clock source */
EricLew 0:d4e5ad7ad71c 292 SystemCoreClock = msirange;
EricLew 0:d4e5ad7ad71c 293 break;
EricLew 0:d4e5ad7ad71c 294
EricLew 0:d4e5ad7ad71c 295 case 0x04: /* HSI used as system clock source */
EricLew 0:d4e5ad7ad71c 296 SystemCoreClock = HSI_VALUE;
EricLew 0:d4e5ad7ad71c 297 break;
EricLew 0:d4e5ad7ad71c 298
EricLew 0:d4e5ad7ad71c 299 case 0x08: /* HSE used as system clock source */
EricLew 0:d4e5ad7ad71c 300 SystemCoreClock = HSE_VALUE;
EricLew 0:d4e5ad7ad71c 301 break;
EricLew 0:d4e5ad7ad71c 302
EricLew 0:d4e5ad7ad71c 303 case 0x0C: /* PLL used as system clock source */
EricLew 0:d4e5ad7ad71c 304 /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
EricLew 0:d4e5ad7ad71c 305 SYSCLK = PLL_VCO / PLLR
EricLew 0:d4e5ad7ad71c 306 */
EricLew 0:d4e5ad7ad71c 307 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
EricLew 0:d4e5ad7ad71c 308 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
EricLew 0:d4e5ad7ad71c 309
EricLew 0:d4e5ad7ad71c 310 switch (pllsource)
EricLew 0:d4e5ad7ad71c 311 {
EricLew 0:d4e5ad7ad71c 312 case 0x02: /* HSI used as PLL clock source */
EricLew 0:d4e5ad7ad71c 313 pllvco = (HSI_VALUE / pllm);
EricLew 0:d4e5ad7ad71c 314 break;
EricLew 0:d4e5ad7ad71c 315
EricLew 0:d4e5ad7ad71c 316 case 0x03: /* HSE used as PLL clock source */
EricLew 0:d4e5ad7ad71c 317 pllvco = (HSE_VALUE / pllm);
EricLew 0:d4e5ad7ad71c 318 break;
EricLew 0:d4e5ad7ad71c 319
EricLew 0:d4e5ad7ad71c 320 default: /* MSI used as PLL clock source */
EricLew 0:d4e5ad7ad71c 321 pllvco = (msirange / pllm);
EricLew 0:d4e5ad7ad71c 322 break;
EricLew 0:d4e5ad7ad71c 323 }
EricLew 0:d4e5ad7ad71c 324 pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
EricLew 0:d4e5ad7ad71c 325 pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
EricLew 0:d4e5ad7ad71c 326 SystemCoreClock = pllvco/pllr;
EricLew 0:d4e5ad7ad71c 327 break;
EricLew 0:d4e5ad7ad71c 328
EricLew 0:d4e5ad7ad71c 329 default:
EricLew 0:d4e5ad7ad71c 330 SystemCoreClock = msirange;
EricLew 0:d4e5ad7ad71c 331 break;
EricLew 0:d4e5ad7ad71c 332 }
EricLew 0:d4e5ad7ad71c 333 /* Compute HCLK clock frequency --------------------------------------------*/
EricLew 0:d4e5ad7ad71c 334 /* Get HCLK prescaler */
EricLew 0:d4e5ad7ad71c 335 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
EricLew 0:d4e5ad7ad71c 336 /* HCLK clock frequency */
EricLew 0:d4e5ad7ad71c 337 SystemCoreClock >>= tmp;
EricLew 0:d4e5ad7ad71c 338 }
EricLew 0:d4e5ad7ad71c 339
EricLew 0:d4e5ad7ad71c 340
EricLew 0:d4e5ad7ad71c 341 /**
EricLew 0:d4e5ad7ad71c 342 * @}
EricLew 0:d4e5ad7ad71c 343 */
EricLew 0:d4e5ad7ad71c 344
EricLew 0:d4e5ad7ad71c 345 /**
EricLew 0:d4e5ad7ad71c 346 * @}
EricLew 0:d4e5ad7ad71c 347 */
EricLew 0:d4e5ad7ad71c 348
EricLew 0:d4e5ad7ad71c 349 /**
EricLew 0:d4e5ad7ad71c 350 * @}
EricLew 0:d4e5ad7ad71c 351 */
EricLew 0:d4e5ad7ad71c 352
EricLew 0:d4e5ad7ad71c 353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
EricLew 0:d4e5ad7ad71c 354