Senior Design: Sound Monitor / FINAL_AUDIO_RECORD

AudioRecord and FFT/MSE comparison. Call AudioRecord_demo for control record and AudioSample for subsequent recordings.

Dependencies:   CMSIS_DSP_401 STM32L4xx_HAL_Driver

Fork of OneHopeOnePrayer by Senior Design: Sound Monitor

core_cmInstr.h@5:f6afbd3fc47a, 2015-12-05 (annotated)

Committer:
EricLew
Date:
Sat Dec 05 16:17:25 2015 +0000
Revision:
5:f6afbd3fc47a
Parent:
0:d4e5ad7ad71c 
Ported to Nucleo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
EricLew 0:d4e5ad7ad71c 1 /**************************************************************************//**
EricLew 0:d4e5ad7ad71c 2 * @file core_cmInstr.h
EricLew 0:d4e5ad7ad71c 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
EricLew 0:d4e5ad7ad71c 4 * @version V4.10
EricLew 0:d4e5ad7ad71c 5 * @date 18. March 2015
EricLew 0:d4e5ad7ad71c 6 *
EricLew 0:d4e5ad7ad71c 7 * @note
EricLew 0:d4e5ad7ad71c 8 *
EricLew 0:d4e5ad7ad71c 9 ******************************************************************************/
EricLew 0:d4e5ad7ad71c 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
EricLew 0:d4e5ad7ad71c 11
EricLew 0:d4e5ad7ad71c 12 All rights reserved.
EricLew 0:d4e5ad7ad71c 13 Redistribution and use in source and binary forms, with or without
EricLew 0:d4e5ad7ad71c 14 modification, are permitted provided that the following conditions are met:
EricLew 0:d4e5ad7ad71c 15 - Redistributions of source code must retain the above copyright
EricLew 0:d4e5ad7ad71c 16 notice, this list of conditions and the following disclaimer.
EricLew 0:d4e5ad7ad71c 17 - Redistributions in binary form must reproduce the above copyright
EricLew 0:d4e5ad7ad71c 18 notice, this list of conditions and the following disclaimer in the
EricLew 0:d4e5ad7ad71c 19 documentation and/or other materials provided with the distribution.
EricLew 0:d4e5ad7ad71c 20 - Neither the name of ARM nor the names of its contributors may be used
EricLew 0:d4e5ad7ad71c 21 to endorse or promote products derived from this software without
EricLew 0:d4e5ad7ad71c 22 specific prior written permission.
EricLew 0:d4e5ad7ad71c 23 *
EricLew 0:d4e5ad7ad71c 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
EricLew 0:d4e5ad7ad71c 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
EricLew 0:d4e5ad7ad71c 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
EricLew 0:d4e5ad7ad71c 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
EricLew 0:d4e5ad7ad71c 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
EricLew 0:d4e5ad7ad71c 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
EricLew 0:d4e5ad7ad71c 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
EricLew 0:d4e5ad7ad71c 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
EricLew 0:d4e5ad7ad71c 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
EricLew 0:d4e5ad7ad71c 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
EricLew 0:d4e5ad7ad71c 34 POSSIBILITY OF SUCH DAMAGE.
EricLew 0:d4e5ad7ad71c 35 ---------------------------------------------------------------------------*/
EricLew 0:d4e5ad7ad71c 36
EricLew 0:d4e5ad7ad71c 37
EricLew 0:d4e5ad7ad71c 38 #ifndef __CORE_CMINSTR_H
EricLew 0:d4e5ad7ad71c 39 #define __CORE_CMINSTR_H
EricLew 0:d4e5ad7ad71c 40
EricLew 0:d4e5ad7ad71c 41
EricLew 0:d4e5ad7ad71c 42 /* ########################## Core Instruction Access ######################### */
EricLew 0:d4e5ad7ad71c 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
EricLew 0:d4e5ad7ad71c 44 Access to dedicated instructions
EricLew 0:d4e5ad7ad71c 45 @{
EricLew 0:d4e5ad7ad71c 46 */
EricLew 0:d4e5ad7ad71c 47
EricLew 0:d4e5ad7ad71c 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
EricLew 0:d4e5ad7ad71c 49 /* ARM armcc specific functions */
EricLew 0:d4e5ad7ad71c 50
EricLew 0:d4e5ad7ad71c 51 #if (__ARMCC_VERSION < 400677)
EricLew 0:d4e5ad7ad71c 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
EricLew 0:d4e5ad7ad71c 53 #endif
EricLew 0:d4e5ad7ad71c 54
EricLew 0:d4e5ad7ad71c 55
EricLew 0:d4e5ad7ad71c 56 /** \brief No Operation
EricLew 0:d4e5ad7ad71c 57
EricLew 0:d4e5ad7ad71c 58 No Operation does nothing. This instruction can be used for code alignment purposes.
EricLew 0:d4e5ad7ad71c 59 */
EricLew 0:d4e5ad7ad71c 60 #define __NOP __nop
EricLew 0:d4e5ad7ad71c 61
EricLew 0:d4e5ad7ad71c 62
EricLew 0:d4e5ad7ad71c 63 /** \brief Wait For Interrupt
EricLew 0:d4e5ad7ad71c 64
EricLew 0:d4e5ad7ad71c 65 Wait For Interrupt is a hint instruction that suspends execution
EricLew 0:d4e5ad7ad71c 66 until one of a number of events occurs.
EricLew 0:d4e5ad7ad71c 67 */
EricLew 0:d4e5ad7ad71c 68 #define __WFI __wfi
EricLew 0:d4e5ad7ad71c 69
EricLew 0:d4e5ad7ad71c 70
EricLew 0:d4e5ad7ad71c 71 /** \brief Wait For Event
EricLew 0:d4e5ad7ad71c 72
EricLew 0:d4e5ad7ad71c 73 Wait For Event is a hint instruction that permits the processor to enter
EricLew 0:d4e5ad7ad71c 74 a low-power state until one of a number of events occurs.
EricLew 0:d4e5ad7ad71c 75 */
EricLew 0:d4e5ad7ad71c 76 #define __WFE __wfe
EricLew 0:d4e5ad7ad71c 77
EricLew 0:d4e5ad7ad71c 78
EricLew 0:d4e5ad7ad71c 79 /** \brief Send Event
EricLew 0:d4e5ad7ad71c 80
EricLew 0:d4e5ad7ad71c 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
EricLew 0:d4e5ad7ad71c 82 */
EricLew 0:d4e5ad7ad71c 83 #define __SEV __sev
EricLew 0:d4e5ad7ad71c 84
EricLew 0:d4e5ad7ad71c 85
EricLew 0:d4e5ad7ad71c 86 /** \brief Instruction Synchronization Barrier
EricLew 0:d4e5ad7ad71c 87
EricLew 0:d4e5ad7ad71c 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
EricLew 0:d4e5ad7ad71c 89 so that all instructions following the ISB are fetched from cache or
EricLew 0:d4e5ad7ad71c 90 memory, after the instruction has been completed.
EricLew 0:d4e5ad7ad71c 91 */
EricLew 0:d4e5ad7ad71c 92 #define __ISB() do {\
EricLew 0:d4e5ad7ad71c 93 __schedule_barrier();\
EricLew 0:d4e5ad7ad71c 94 __isb(0xF);\
EricLew 0:d4e5ad7ad71c 95 __schedule_barrier();\
EricLew 0:d4e5ad7ad71c 96 } while (0)
EricLew 0:d4e5ad7ad71c 97
EricLew 0:d4e5ad7ad71c 98 /** \brief Data Synchronization Barrier
EricLew 0:d4e5ad7ad71c 99
EricLew 0:d4e5ad7ad71c 100 This function acts as a special kind of Data Memory Barrier.
EricLew 0:d4e5ad7ad71c 101 It completes when all explicit memory accesses before this instruction complete.
EricLew 0:d4e5ad7ad71c 102 */
EricLew 0:d4e5ad7ad71c 103 #define __DSB() do {\
EricLew 0:d4e5ad7ad71c 104 __schedule_barrier();\
EricLew 0:d4e5ad7ad71c 105 __dsb(0xF);\
EricLew 0:d4e5ad7ad71c 106 __schedule_barrier();\
EricLew 0:d4e5ad7ad71c 107 } while (0)
EricLew 0:d4e5ad7ad71c 108
EricLew 0:d4e5ad7ad71c 109 /** \brief Data Memory Barrier
EricLew 0:d4e5ad7ad71c 110
EricLew 0:d4e5ad7ad71c 111 This function ensures the apparent order of the explicit memory operations before
EricLew 0:d4e5ad7ad71c 112 and after the instruction, without ensuring their completion.
EricLew 0:d4e5ad7ad71c 113 */
EricLew 0:d4e5ad7ad71c 114 #define __DMB() do {\
EricLew 0:d4e5ad7ad71c 115 __schedule_barrier();\
EricLew 0:d4e5ad7ad71c 116 __dmb(0xF);\
EricLew 0:d4e5ad7ad71c 117 __schedule_barrier();\
EricLew 0:d4e5ad7ad71c 118 } while (0)
EricLew 0:d4e5ad7ad71c 119
EricLew 0:d4e5ad7ad71c 120 /** \brief Reverse byte order (32 bit)
EricLew 0:d4e5ad7ad71c 121
EricLew 0:d4e5ad7ad71c 122 This function reverses the byte order in integer value.
EricLew 0:d4e5ad7ad71c 123
EricLew 0:d4e5ad7ad71c 124 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 125 \return Reversed value
EricLew 0:d4e5ad7ad71c 126 */
EricLew 0:d4e5ad7ad71c 127 #define __REV __rev
EricLew 0:d4e5ad7ad71c 128
EricLew 0:d4e5ad7ad71c 129
EricLew 0:d4e5ad7ad71c 130 /** \brief Reverse byte order (16 bit)
EricLew 0:d4e5ad7ad71c 131
EricLew 0:d4e5ad7ad71c 132 This function reverses the byte order in two unsigned short values.
EricLew 0:d4e5ad7ad71c 133
EricLew 0:d4e5ad7ad71c 134 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 135 \return Reversed value
EricLew 0:d4e5ad7ad71c 136 */
EricLew 0:d4e5ad7ad71c 137 #ifndef __NO_EMBEDDED_ASM
EricLew 0:d4e5ad7ad71c 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
EricLew 0:d4e5ad7ad71c 139 {
EricLew 0:d4e5ad7ad71c 140 rev16 r0, r0
EricLew 0:d4e5ad7ad71c 141 bx lr
EricLew 0:d4e5ad7ad71c 142 }
EricLew 0:d4e5ad7ad71c 143 #endif
EricLew 0:d4e5ad7ad71c 144
EricLew 0:d4e5ad7ad71c 145 /** \brief Reverse byte order in signed short value
EricLew 0:d4e5ad7ad71c 146
EricLew 0:d4e5ad7ad71c 147 This function reverses the byte order in a signed short value with sign extension to integer.
EricLew 0:d4e5ad7ad71c 148
EricLew 0:d4e5ad7ad71c 149 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 150 \return Reversed value
EricLew 0:d4e5ad7ad71c 151 */
EricLew 0:d4e5ad7ad71c 152 #ifndef __NO_EMBEDDED_ASM
EricLew 0:d4e5ad7ad71c 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
EricLew 0:d4e5ad7ad71c 154 {
EricLew 0:d4e5ad7ad71c 155 revsh r0, r0
EricLew 0:d4e5ad7ad71c 156 bx lr
EricLew 0:d4e5ad7ad71c 157 }
EricLew 0:d4e5ad7ad71c 158 #endif
EricLew 0:d4e5ad7ad71c 159
EricLew 0:d4e5ad7ad71c 160
EricLew 0:d4e5ad7ad71c 161 /** \brief Rotate Right in unsigned value (32 bit)
EricLew 0:d4e5ad7ad71c 162
EricLew 0:d4e5ad7ad71c 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
EricLew 0:d4e5ad7ad71c 164
EricLew 0:d4e5ad7ad71c 165 \param [in] value Value to rotate
EricLew 0:d4e5ad7ad71c 166 \param [in] value Number of Bits to rotate
EricLew 0:d4e5ad7ad71c 167 \return Rotated value
EricLew 0:d4e5ad7ad71c 168 */
EricLew 0:d4e5ad7ad71c 169 #define __ROR __ror
EricLew 0:d4e5ad7ad71c 170
EricLew 0:d4e5ad7ad71c 171
EricLew 0:d4e5ad7ad71c 172 /** \brief Breakpoint
EricLew 0:d4e5ad7ad71c 173
EricLew 0:d4e5ad7ad71c 174 This function causes the processor to enter Debug state.
EricLew 0:d4e5ad7ad71c 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
EricLew 0:d4e5ad7ad71c 176
EricLew 0:d4e5ad7ad71c 177 \param [in] value is ignored by the processor.
EricLew 0:d4e5ad7ad71c 178 If required, a debugger can use it to store additional information about the breakpoint.
EricLew 0:d4e5ad7ad71c 179 */
EricLew 0:d4e5ad7ad71c 180 #define __BKPT(value) __breakpoint(value)
EricLew 0:d4e5ad7ad71c 181
EricLew 0:d4e5ad7ad71c 182
EricLew 0:d4e5ad7ad71c 183 /** \brief Reverse bit order of value
EricLew 0:d4e5ad7ad71c 184
EricLew 0:d4e5ad7ad71c 185 This function reverses the bit order of the given value.
EricLew 0:d4e5ad7ad71c 186
EricLew 0:d4e5ad7ad71c 187 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 188 \return Reversed value
EricLew 0:d4e5ad7ad71c 189 */
EricLew 0:d4e5ad7ad71c 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
EricLew 0:d4e5ad7ad71c 191 #define __RBIT __rbit
EricLew 0:d4e5ad7ad71c 192 #else
EricLew 0:d4e5ad7ad71c 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
EricLew 0:d4e5ad7ad71c 194 {
EricLew 0:d4e5ad7ad71c 195 uint32_t result;
EricLew 0:d4e5ad7ad71c 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
EricLew 0:d4e5ad7ad71c 197
EricLew 0:d4e5ad7ad71c 198 result = value; // r will be reversed bits of v; first get LSB of v
EricLew 0:d4e5ad7ad71c 199 for (value >>= 1; value; value >>= 1)
EricLew 0:d4e5ad7ad71c 200 {
EricLew 0:d4e5ad7ad71c 201 result <<= 1;
EricLew 0:d4e5ad7ad71c 202 result |= value & 1;
EricLew 0:d4e5ad7ad71c 203 s--;
EricLew 0:d4e5ad7ad71c 204 }
EricLew 0:d4e5ad7ad71c 205 result <<= s; // shift when v's highest bits are zero
EricLew 0:d4e5ad7ad71c 206 return(result);
EricLew 0:d4e5ad7ad71c 207 }
EricLew 0:d4e5ad7ad71c 208 #endif
EricLew 0:d4e5ad7ad71c 209
EricLew 0:d4e5ad7ad71c 210
EricLew 0:d4e5ad7ad71c 211 /** \brief Count leading zeros
EricLew 0:d4e5ad7ad71c 212
EricLew 0:d4e5ad7ad71c 213 This function counts the number of leading zeros of a data value.
EricLew 0:d4e5ad7ad71c 214
EricLew 0:d4e5ad7ad71c 215 \param [in] value Value to count the leading zeros
EricLew 0:d4e5ad7ad71c 216 \return number of leading zeros in value
EricLew 0:d4e5ad7ad71c 217 */
EricLew 0:d4e5ad7ad71c 218 #define __CLZ __clz
EricLew 0:d4e5ad7ad71c 219
EricLew 0:d4e5ad7ad71c 220
EricLew 0:d4e5ad7ad71c 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
EricLew 0:d4e5ad7ad71c 222
EricLew 0:d4e5ad7ad71c 223 /** \brief LDR Exclusive (8 bit)
EricLew 0:d4e5ad7ad71c 224
EricLew 0:d4e5ad7ad71c 225 This function executes a exclusive LDR instruction for 8 bit value.
EricLew 0:d4e5ad7ad71c 226
EricLew 0:d4e5ad7ad71c 227 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 228 \return value of type uint8_t at (*ptr)
EricLew 0:d4e5ad7ad71c 229 */
EricLew 0:d4e5ad7ad71c 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
EricLew 0:d4e5ad7ad71c 231
EricLew 0:d4e5ad7ad71c 232
EricLew 0:d4e5ad7ad71c 233 /** \brief LDR Exclusive (16 bit)
EricLew 0:d4e5ad7ad71c 234
EricLew 0:d4e5ad7ad71c 235 This function executes a exclusive LDR instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 236
EricLew 0:d4e5ad7ad71c 237 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 238 \return value of type uint16_t at (*ptr)
EricLew 0:d4e5ad7ad71c 239 */
EricLew 0:d4e5ad7ad71c 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
EricLew 0:d4e5ad7ad71c 241
EricLew 0:d4e5ad7ad71c 242
EricLew 0:d4e5ad7ad71c 243 /** \brief LDR Exclusive (32 bit)
EricLew 0:d4e5ad7ad71c 244
EricLew 0:d4e5ad7ad71c 245 This function executes a exclusive LDR instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 246
EricLew 0:d4e5ad7ad71c 247 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 248 \return value of type uint32_t at (*ptr)
EricLew 0:d4e5ad7ad71c 249 */
EricLew 0:d4e5ad7ad71c 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
EricLew 0:d4e5ad7ad71c 251
EricLew 0:d4e5ad7ad71c 252
EricLew 0:d4e5ad7ad71c 253 /** \brief STR Exclusive (8 bit)
EricLew 0:d4e5ad7ad71c 254
EricLew 0:d4e5ad7ad71c 255 This function executes a exclusive STR instruction for 8 bit values.
EricLew 0:d4e5ad7ad71c 256
EricLew 0:d4e5ad7ad71c 257 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 258 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 259 \return 0 Function succeeded
EricLew 0:d4e5ad7ad71c 260 \return 1 Function failed
EricLew 0:d4e5ad7ad71c 261 */
EricLew 0:d4e5ad7ad71c 262 #define __STREXB(value, ptr) __strex(value, ptr)
EricLew 0:d4e5ad7ad71c 263
EricLew 0:d4e5ad7ad71c 264
EricLew 0:d4e5ad7ad71c 265 /** \brief STR Exclusive (16 bit)
EricLew 0:d4e5ad7ad71c 266
EricLew 0:d4e5ad7ad71c 267 This function executes a exclusive STR instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 268
EricLew 0:d4e5ad7ad71c 269 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 270 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 271 \return 0 Function succeeded
EricLew 0:d4e5ad7ad71c 272 \return 1 Function failed
EricLew 0:d4e5ad7ad71c 273 */
EricLew 0:d4e5ad7ad71c 274 #define __STREXH(value, ptr) __strex(value, ptr)
EricLew 0:d4e5ad7ad71c 275
EricLew 0:d4e5ad7ad71c 276
EricLew 0:d4e5ad7ad71c 277 /** \brief STR Exclusive (32 bit)
EricLew 0:d4e5ad7ad71c 278
EricLew 0:d4e5ad7ad71c 279 This function executes a exclusive STR instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 280
EricLew 0:d4e5ad7ad71c 281 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 282 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 283 \return 0 Function succeeded
EricLew 0:d4e5ad7ad71c 284 \return 1 Function failed
EricLew 0:d4e5ad7ad71c 285 */
EricLew 0:d4e5ad7ad71c 286 #define __STREXW(value, ptr) __strex(value, ptr)
EricLew 0:d4e5ad7ad71c 287
EricLew 0:d4e5ad7ad71c 288
EricLew 0:d4e5ad7ad71c 289 /** \brief Remove the exclusive lock
EricLew 0:d4e5ad7ad71c 290
EricLew 0:d4e5ad7ad71c 291 This function removes the exclusive lock which is created by LDREX.
EricLew 0:d4e5ad7ad71c 292
EricLew 0:d4e5ad7ad71c 293 */
EricLew 0:d4e5ad7ad71c 294 #define __CLREX __clrex
EricLew 0:d4e5ad7ad71c 295
EricLew 0:d4e5ad7ad71c 296
EricLew 0:d4e5ad7ad71c 297 /** \brief Signed Saturate
EricLew 0:d4e5ad7ad71c 298
EricLew 0:d4e5ad7ad71c 299 This function saturates a signed value.
EricLew 0:d4e5ad7ad71c 300
EricLew 0:d4e5ad7ad71c 301 \param [in] value Value to be saturated
EricLew 0:d4e5ad7ad71c 302 \param [in] sat Bit position to saturate to (1..32)
EricLew 0:d4e5ad7ad71c 303 \return Saturated value
EricLew 0:d4e5ad7ad71c 304 */
EricLew 0:d4e5ad7ad71c 305 #define __SSAT __ssat
EricLew 0:d4e5ad7ad71c 306
EricLew 0:d4e5ad7ad71c 307
EricLew 0:d4e5ad7ad71c 308 /** \brief Unsigned Saturate
EricLew 0:d4e5ad7ad71c 309
EricLew 0:d4e5ad7ad71c 310 This function saturates an unsigned value.
EricLew 0:d4e5ad7ad71c 311
EricLew 0:d4e5ad7ad71c 312 \param [in] value Value to be saturated
EricLew 0:d4e5ad7ad71c 313 \param [in] sat Bit position to saturate to (0..31)
EricLew 0:d4e5ad7ad71c 314 \return Saturated value
EricLew 0:d4e5ad7ad71c 315 */
EricLew 0:d4e5ad7ad71c 316 #define __USAT __usat
EricLew 0:d4e5ad7ad71c 317
EricLew 0:d4e5ad7ad71c 318
EricLew 0:d4e5ad7ad71c 319 /** \brief Rotate Right with Extend (32 bit)
EricLew 0:d4e5ad7ad71c 320
EricLew 0:d4e5ad7ad71c 321 This function moves each bit of a bitstring right by one bit.
EricLew 0:d4e5ad7ad71c 322 The carry input is shifted in at the left end of the bitstring.
EricLew 0:d4e5ad7ad71c 323
EricLew 0:d4e5ad7ad71c 324 \param [in] value Value to rotate
EricLew 0:d4e5ad7ad71c 325 \return Rotated value
EricLew 0:d4e5ad7ad71c 326 */
EricLew 0:d4e5ad7ad71c 327 #ifndef __NO_EMBEDDED_ASM
EricLew 0:d4e5ad7ad71c 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
EricLew 0:d4e5ad7ad71c 329 {
EricLew 0:d4e5ad7ad71c 330 rrx r0, r0
EricLew 0:d4e5ad7ad71c 331 bx lr
EricLew 0:d4e5ad7ad71c 332 }
EricLew 0:d4e5ad7ad71c 333 #endif
EricLew 0:d4e5ad7ad71c 334
EricLew 0:d4e5ad7ad71c 335
EricLew 0:d4e5ad7ad71c 336 /** \brief LDRT Unprivileged (8 bit)
EricLew 0:d4e5ad7ad71c 337
EricLew 0:d4e5ad7ad71c 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
EricLew 0:d4e5ad7ad71c 339
EricLew 0:d4e5ad7ad71c 340 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 341 \return value of type uint8_t at (*ptr)
EricLew 0:d4e5ad7ad71c 342 */
EricLew 0:d4e5ad7ad71c 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
EricLew 0:d4e5ad7ad71c 344
EricLew 0:d4e5ad7ad71c 345
EricLew 0:d4e5ad7ad71c 346 /** \brief LDRT Unprivileged (16 bit)
EricLew 0:d4e5ad7ad71c 347
EricLew 0:d4e5ad7ad71c 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 349
EricLew 0:d4e5ad7ad71c 350 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 351 \return value of type uint16_t at (*ptr)
EricLew 0:d4e5ad7ad71c 352 */
EricLew 0:d4e5ad7ad71c 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
EricLew 0:d4e5ad7ad71c 354
EricLew 0:d4e5ad7ad71c 355
EricLew 0:d4e5ad7ad71c 356 /** \brief LDRT Unprivileged (32 bit)
EricLew 0:d4e5ad7ad71c 357
EricLew 0:d4e5ad7ad71c 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 359
EricLew 0:d4e5ad7ad71c 360 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 361 \return value of type uint32_t at (*ptr)
EricLew 0:d4e5ad7ad71c 362 */
EricLew 0:d4e5ad7ad71c 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
EricLew 0:d4e5ad7ad71c 364
EricLew 0:d4e5ad7ad71c 365
EricLew 0:d4e5ad7ad71c 366 /** \brief STRT Unprivileged (8 bit)
EricLew 0:d4e5ad7ad71c 367
EricLew 0:d4e5ad7ad71c 368 This function executes a Unprivileged STRT instruction for 8 bit values.
EricLew 0:d4e5ad7ad71c 369
EricLew 0:d4e5ad7ad71c 370 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 371 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 372 */
EricLew 0:d4e5ad7ad71c 373 #define __STRBT(value, ptr) __strt(value, ptr)
EricLew 0:d4e5ad7ad71c 374
EricLew 0:d4e5ad7ad71c 375
EricLew 0:d4e5ad7ad71c 376 /** \brief STRT Unprivileged (16 bit)
EricLew 0:d4e5ad7ad71c 377
EricLew 0:d4e5ad7ad71c 378 This function executes a Unprivileged STRT instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 379
EricLew 0:d4e5ad7ad71c 380 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 381 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 382 */
EricLew 0:d4e5ad7ad71c 383 #define __STRHT(value, ptr) __strt(value, ptr)
EricLew 0:d4e5ad7ad71c 384
EricLew 0:d4e5ad7ad71c 385
EricLew 0:d4e5ad7ad71c 386 /** \brief STRT Unprivileged (32 bit)
EricLew 0:d4e5ad7ad71c 387
EricLew 0:d4e5ad7ad71c 388 This function executes a Unprivileged STRT instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 389
EricLew 0:d4e5ad7ad71c 390 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 391 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 392 */
EricLew 0:d4e5ad7ad71c 393 #define __STRT(value, ptr) __strt(value, ptr)
EricLew 0:d4e5ad7ad71c 394
EricLew 0:d4e5ad7ad71c 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
EricLew 0:d4e5ad7ad71c 396
EricLew 0:d4e5ad7ad71c 397
EricLew 0:d4e5ad7ad71c 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
EricLew 0:d4e5ad7ad71c 399 /* GNU gcc specific functions */
EricLew 0:d4e5ad7ad71c 400
EricLew 0:d4e5ad7ad71c 401 /* Define macros for porting to both thumb1 and thumb2.
EricLew 0:d4e5ad7ad71c 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
EricLew 0:d4e5ad7ad71c 403 * Otherwise, use general registers, specified by constrant "r" */
EricLew 0:d4e5ad7ad71c 404 #if defined (__thumb__) && !defined (__thumb2__)
EricLew 0:d4e5ad7ad71c 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
EricLew 0:d4e5ad7ad71c 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
EricLew 0:d4e5ad7ad71c 407 #else
EricLew 0:d4e5ad7ad71c 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
EricLew 0:d4e5ad7ad71c 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
EricLew 0:d4e5ad7ad71c 410 #endif
EricLew 0:d4e5ad7ad71c 411
EricLew 0:d4e5ad7ad71c 412 /** \brief No Operation
EricLew 0:d4e5ad7ad71c 413
EricLew 0:d4e5ad7ad71c 414 No Operation does nothing. This instruction can be used for code alignment purposes.
EricLew 0:d4e5ad7ad71c 415 */
EricLew 0:d4e5ad7ad71c 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
EricLew 0:d4e5ad7ad71c 417 {
EricLew 0:d4e5ad7ad71c 418 __ASM volatile ("nop");
EricLew 0:d4e5ad7ad71c 419 }
EricLew 0:d4e5ad7ad71c 420
EricLew 0:d4e5ad7ad71c 421
EricLew 0:d4e5ad7ad71c 422 /** \brief Wait For Interrupt
EricLew 0:d4e5ad7ad71c 423
EricLew 0:d4e5ad7ad71c 424 Wait For Interrupt is a hint instruction that suspends execution
EricLew 0:d4e5ad7ad71c 425 until one of a number of events occurs.
EricLew 0:d4e5ad7ad71c 426 */
EricLew 0:d4e5ad7ad71c 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
EricLew 0:d4e5ad7ad71c 428 {
EricLew 0:d4e5ad7ad71c 429 __ASM volatile ("wfi");
EricLew 0:d4e5ad7ad71c 430 }
EricLew 0:d4e5ad7ad71c 431
EricLew 0:d4e5ad7ad71c 432
EricLew 0:d4e5ad7ad71c 433 /** \brief Wait For Event
EricLew 0:d4e5ad7ad71c 434
EricLew 0:d4e5ad7ad71c 435 Wait For Event is a hint instruction that permits the processor to enter
EricLew 0:d4e5ad7ad71c 436 a low-power state until one of a number of events occurs.
EricLew 0:d4e5ad7ad71c 437 */
EricLew 0:d4e5ad7ad71c 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
EricLew 0:d4e5ad7ad71c 439 {
EricLew 0:d4e5ad7ad71c 440 __ASM volatile ("wfe");
EricLew 0:d4e5ad7ad71c 441 }
EricLew 0:d4e5ad7ad71c 442
EricLew 0:d4e5ad7ad71c 443
EricLew 0:d4e5ad7ad71c 444 /** \brief Send Event
EricLew 0:d4e5ad7ad71c 445
EricLew 0:d4e5ad7ad71c 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
EricLew 0:d4e5ad7ad71c 447 */
EricLew 0:d4e5ad7ad71c 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
EricLew 0:d4e5ad7ad71c 449 {
EricLew 0:d4e5ad7ad71c 450 __ASM volatile ("sev");
EricLew 0:d4e5ad7ad71c 451 }
EricLew 0:d4e5ad7ad71c 452
EricLew 0:d4e5ad7ad71c 453
EricLew 0:d4e5ad7ad71c 454 /** \brief Instruction Synchronization Barrier
EricLew 0:d4e5ad7ad71c 455
EricLew 0:d4e5ad7ad71c 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
EricLew 0:d4e5ad7ad71c 457 so that all instructions following the ISB are fetched from cache or
EricLew 0:d4e5ad7ad71c 458 memory, after the instruction has been completed.
EricLew 0:d4e5ad7ad71c 459 */
EricLew 0:d4e5ad7ad71c 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
EricLew 0:d4e5ad7ad71c 461 {
EricLew 0:d4e5ad7ad71c 462 __ASM volatile ("isb 0xF":::"memory");
EricLew 0:d4e5ad7ad71c 463 }
EricLew 0:d4e5ad7ad71c 464
EricLew 0:d4e5ad7ad71c 465
EricLew 0:d4e5ad7ad71c 466 /** \brief Data Synchronization Barrier
EricLew 0:d4e5ad7ad71c 467
EricLew 0:d4e5ad7ad71c 468 This function acts as a special kind of Data Memory Barrier.
EricLew 0:d4e5ad7ad71c 469 It completes when all explicit memory accesses before this instruction complete.
EricLew 0:d4e5ad7ad71c 470 */
EricLew 0:d4e5ad7ad71c 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
EricLew 0:d4e5ad7ad71c 472 {
EricLew 0:d4e5ad7ad71c 473 __ASM volatile ("dsb 0xF":::"memory");
EricLew 0:d4e5ad7ad71c 474 }
EricLew 0:d4e5ad7ad71c 475
EricLew 0:d4e5ad7ad71c 476
EricLew 0:d4e5ad7ad71c 477 /** \brief Data Memory Barrier
EricLew 0:d4e5ad7ad71c 478
EricLew 0:d4e5ad7ad71c 479 This function ensures the apparent order of the explicit memory operations before
EricLew 0:d4e5ad7ad71c 480 and after the instruction, without ensuring their completion.
EricLew 0:d4e5ad7ad71c 481 */
EricLew 0:d4e5ad7ad71c 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
EricLew 0:d4e5ad7ad71c 483 {
EricLew 0:d4e5ad7ad71c 484 __ASM volatile ("dmb 0xF":::"memory");
EricLew 0:d4e5ad7ad71c 485 }
EricLew 0:d4e5ad7ad71c 486
EricLew 0:d4e5ad7ad71c 487
EricLew 0:d4e5ad7ad71c 488 /** \brief Reverse byte order (32 bit)
EricLew 0:d4e5ad7ad71c 489
EricLew 0:d4e5ad7ad71c 490 This function reverses the byte order in integer value.
EricLew 0:d4e5ad7ad71c 491
EricLew 0:d4e5ad7ad71c 492 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 493 \return Reversed value
EricLew 0:d4e5ad7ad71c 494 */
EricLew 0:d4e5ad7ad71c 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
EricLew 0:d4e5ad7ad71c 496 {
EricLew 0:d4e5ad7ad71c 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
EricLew 0:d4e5ad7ad71c 498 return __builtin_bswap32(value);
EricLew 0:d4e5ad7ad71c 499 #else
EricLew 0:d4e5ad7ad71c 500 uint32_t result;
EricLew 0:d4e5ad7ad71c 501
EricLew 0:d4e5ad7ad71c 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
EricLew 0:d4e5ad7ad71c 503 return(result);
EricLew 0:d4e5ad7ad71c 504 #endif
EricLew 0:d4e5ad7ad71c 505 }
EricLew 0:d4e5ad7ad71c 506
EricLew 0:d4e5ad7ad71c 507
EricLew 0:d4e5ad7ad71c 508 /** \brief Reverse byte order (16 bit)
EricLew 0:d4e5ad7ad71c 509
EricLew 0:d4e5ad7ad71c 510 This function reverses the byte order in two unsigned short values.
EricLew 0:d4e5ad7ad71c 511
EricLew 0:d4e5ad7ad71c 512 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 513 \return Reversed value
EricLew 0:d4e5ad7ad71c 514 */
EricLew 0:d4e5ad7ad71c 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
EricLew 0:d4e5ad7ad71c 516 {
EricLew 0:d4e5ad7ad71c 517 uint32_t result;
EricLew 0:d4e5ad7ad71c 518
EricLew 0:d4e5ad7ad71c 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
EricLew 0:d4e5ad7ad71c 520 return(result);
EricLew 0:d4e5ad7ad71c 521 }
EricLew 0:d4e5ad7ad71c 522
EricLew 0:d4e5ad7ad71c 523
EricLew 0:d4e5ad7ad71c 524 /** \brief Reverse byte order in signed short value
EricLew 0:d4e5ad7ad71c 525
EricLew 0:d4e5ad7ad71c 526 This function reverses the byte order in a signed short value with sign extension to integer.
EricLew 0:d4e5ad7ad71c 527
EricLew 0:d4e5ad7ad71c 528 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 529 \return Reversed value
EricLew 0:d4e5ad7ad71c 530 */
EricLew 0:d4e5ad7ad71c 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
EricLew 0:d4e5ad7ad71c 532 {
EricLew 0:d4e5ad7ad71c 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
EricLew 0:d4e5ad7ad71c 534 return (short)__builtin_bswap16(value);
EricLew 0:d4e5ad7ad71c 535 #else
EricLew 0:d4e5ad7ad71c 536 uint32_t result;
EricLew 0:d4e5ad7ad71c 537
EricLew 0:d4e5ad7ad71c 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
EricLew 0:d4e5ad7ad71c 539 return(result);
EricLew 0:d4e5ad7ad71c 540 #endif
EricLew 0:d4e5ad7ad71c 541 }
EricLew 0:d4e5ad7ad71c 542
EricLew 0:d4e5ad7ad71c 543
EricLew 0:d4e5ad7ad71c 544 /** \brief Rotate Right in unsigned value (32 bit)
EricLew 0:d4e5ad7ad71c 545
EricLew 0:d4e5ad7ad71c 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
EricLew 0:d4e5ad7ad71c 547
EricLew 0:d4e5ad7ad71c 548 \param [in] value Value to rotate
EricLew 0:d4e5ad7ad71c 549 \param [in] value Number of Bits to rotate
EricLew 0:d4e5ad7ad71c 550 \return Rotated value
EricLew 0:d4e5ad7ad71c 551 */
EricLew 0:d4e5ad7ad71c 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
EricLew 0:d4e5ad7ad71c 553 {
EricLew 0:d4e5ad7ad71c 554 return (op1 >> op2) | (op1 << (32 - op2));
EricLew 0:d4e5ad7ad71c 555 }
EricLew 0:d4e5ad7ad71c 556
EricLew 0:d4e5ad7ad71c 557
EricLew 0:d4e5ad7ad71c 558 /** \brief Breakpoint
EricLew 0:d4e5ad7ad71c 559
EricLew 0:d4e5ad7ad71c 560 This function causes the processor to enter Debug state.
EricLew 0:d4e5ad7ad71c 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
EricLew 0:d4e5ad7ad71c 562
EricLew 0:d4e5ad7ad71c 563 \param [in] value is ignored by the processor.
EricLew 0:d4e5ad7ad71c 564 If required, a debugger can use it to store additional information about the breakpoint.
EricLew 0:d4e5ad7ad71c 565 */
EricLew 0:d4e5ad7ad71c 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
EricLew 0:d4e5ad7ad71c 567
EricLew 0:d4e5ad7ad71c 568
EricLew 0:d4e5ad7ad71c 569 /** \brief Reverse bit order of value
EricLew 0:d4e5ad7ad71c 570
EricLew 0:d4e5ad7ad71c 571 This function reverses the bit order of the given value.
EricLew 0:d4e5ad7ad71c 572
EricLew 0:d4e5ad7ad71c 573 \param [in] value Value to reverse
EricLew 0:d4e5ad7ad71c 574 \return Reversed value
EricLew 0:d4e5ad7ad71c 575 */
EricLew 0:d4e5ad7ad71c 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
EricLew 0:d4e5ad7ad71c 577 {
EricLew 0:d4e5ad7ad71c 578 uint32_t result;
EricLew 0:d4e5ad7ad71c 579
EricLew 0:d4e5ad7ad71c 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
EricLew 0:d4e5ad7ad71c 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
EricLew 0:d4e5ad7ad71c 582 #else
EricLew 0:d4e5ad7ad71c 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
EricLew 0:d4e5ad7ad71c 584
EricLew 0:d4e5ad7ad71c 585 result = value; // r will be reversed bits of v; first get LSB of v
EricLew 0:d4e5ad7ad71c 586 for (value >>= 1; value; value >>= 1)
EricLew 0:d4e5ad7ad71c 587 {
EricLew 0:d4e5ad7ad71c 588 result <<= 1;
EricLew 0:d4e5ad7ad71c 589 result |= value & 1;
EricLew 0:d4e5ad7ad71c 590 s--;
EricLew 0:d4e5ad7ad71c 591 }
EricLew 0:d4e5ad7ad71c 592 result <<= s; // shift when v's highest bits are zero
EricLew 0:d4e5ad7ad71c 593 #endif
EricLew 0:d4e5ad7ad71c 594 return(result);
EricLew 0:d4e5ad7ad71c 595 }
EricLew 0:d4e5ad7ad71c 596
EricLew 0:d4e5ad7ad71c 597
EricLew 0:d4e5ad7ad71c 598 /** \brief Count leading zeros
EricLew 0:d4e5ad7ad71c 599
EricLew 0:d4e5ad7ad71c 600 This function counts the number of leading zeros of a data value.
EricLew 0:d4e5ad7ad71c 601
EricLew 0:d4e5ad7ad71c 602 \param [in] value Value to count the leading zeros
EricLew 0:d4e5ad7ad71c 603 \return number of leading zeros in value
EricLew 0:d4e5ad7ad71c 604 */
EricLew 0:d4e5ad7ad71c 605 #define __CLZ __builtin_clz
EricLew 0:d4e5ad7ad71c 606
EricLew 0:d4e5ad7ad71c 607
EricLew 0:d4e5ad7ad71c 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
EricLew 0:d4e5ad7ad71c 609
EricLew 0:d4e5ad7ad71c 610 /** \brief LDR Exclusive (8 bit)
EricLew 0:d4e5ad7ad71c 611
EricLew 0:d4e5ad7ad71c 612 This function executes a exclusive LDR instruction for 8 bit value.
EricLew 0:d4e5ad7ad71c 613
EricLew 0:d4e5ad7ad71c 614 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 615 \return value of type uint8_t at (*ptr)
EricLew 0:d4e5ad7ad71c 616 */
EricLew 0:d4e5ad7ad71c 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
EricLew 0:d4e5ad7ad71c 618 {
EricLew 0:d4e5ad7ad71c 619 uint32_t result;
EricLew 0:d4e5ad7ad71c 620
EricLew 0:d4e5ad7ad71c 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
EricLew 0:d4e5ad7ad71c 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
EricLew 0:d4e5ad7ad71c 623 #else
EricLew 0:d4e5ad7ad71c 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
EricLew 0:d4e5ad7ad71c 625 accepted by assembler. So has to use following less efficient pattern.
EricLew 0:d4e5ad7ad71c 626 */
EricLew 0:d4e5ad7ad71c 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
EricLew 0:d4e5ad7ad71c 628 #endif
EricLew 0:d4e5ad7ad71c 629 return ((uint8_t) result); /* Add explicit type cast here */
EricLew 0:d4e5ad7ad71c 630 }
EricLew 0:d4e5ad7ad71c 631
EricLew 0:d4e5ad7ad71c 632
EricLew 0:d4e5ad7ad71c 633 /** \brief LDR Exclusive (16 bit)
EricLew 0:d4e5ad7ad71c 634
EricLew 0:d4e5ad7ad71c 635 This function executes a exclusive LDR instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 636
EricLew 0:d4e5ad7ad71c 637 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 638 \return value of type uint16_t at (*ptr)
EricLew 0:d4e5ad7ad71c 639 */
EricLew 0:d4e5ad7ad71c 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
EricLew 0:d4e5ad7ad71c 641 {
EricLew 0:d4e5ad7ad71c 642 uint32_t result;
EricLew 0:d4e5ad7ad71c 643
EricLew 0:d4e5ad7ad71c 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
EricLew 0:d4e5ad7ad71c 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
EricLew 0:d4e5ad7ad71c 646 #else
EricLew 0:d4e5ad7ad71c 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
EricLew 0:d4e5ad7ad71c 648 accepted by assembler. So has to use following less efficient pattern.
EricLew 0:d4e5ad7ad71c 649 */
EricLew 0:d4e5ad7ad71c 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
EricLew 0:d4e5ad7ad71c 651 #endif
EricLew 0:d4e5ad7ad71c 652 return ((uint16_t) result); /* Add explicit type cast here */
EricLew 0:d4e5ad7ad71c 653 }
EricLew 0:d4e5ad7ad71c 654
EricLew 0:d4e5ad7ad71c 655
EricLew 0:d4e5ad7ad71c 656 /** \brief LDR Exclusive (32 bit)
EricLew 0:d4e5ad7ad71c 657
EricLew 0:d4e5ad7ad71c 658 This function executes a exclusive LDR instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 659
EricLew 0:d4e5ad7ad71c 660 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 661 \return value of type uint32_t at (*ptr)
EricLew 0:d4e5ad7ad71c 662 */
EricLew 0:d4e5ad7ad71c 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
EricLew 0:d4e5ad7ad71c 664 {
EricLew 0:d4e5ad7ad71c 665 uint32_t result;
EricLew 0:d4e5ad7ad71c 666
EricLew 0:d4e5ad7ad71c 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
EricLew 0:d4e5ad7ad71c 668 return(result);
EricLew 0:d4e5ad7ad71c 669 }
EricLew 0:d4e5ad7ad71c 670
EricLew 0:d4e5ad7ad71c 671
EricLew 0:d4e5ad7ad71c 672 /** \brief STR Exclusive (8 bit)
EricLew 0:d4e5ad7ad71c 673
EricLew 0:d4e5ad7ad71c 674 This function executes a exclusive STR instruction for 8 bit values.
EricLew 0:d4e5ad7ad71c 675
EricLew 0:d4e5ad7ad71c 676 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 677 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 678 \return 0 Function succeeded
EricLew 0:d4e5ad7ad71c 679 \return 1 Function failed
EricLew 0:d4e5ad7ad71c 680 */
EricLew 0:d4e5ad7ad71c 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
EricLew 0:d4e5ad7ad71c 682 {
EricLew 0:d4e5ad7ad71c 683 uint32_t result;
EricLew 0:d4e5ad7ad71c 684
EricLew 0:d4e5ad7ad71c 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
EricLew 0:d4e5ad7ad71c 686 return(result);
EricLew 0:d4e5ad7ad71c 687 }
EricLew 0:d4e5ad7ad71c 688
EricLew 0:d4e5ad7ad71c 689
EricLew 0:d4e5ad7ad71c 690 /** \brief STR Exclusive (16 bit)
EricLew 0:d4e5ad7ad71c 691
EricLew 0:d4e5ad7ad71c 692 This function executes a exclusive STR instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 693
EricLew 0:d4e5ad7ad71c 694 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 695 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 696 \return 0 Function succeeded
EricLew 0:d4e5ad7ad71c 697 \return 1 Function failed
EricLew 0:d4e5ad7ad71c 698 */
EricLew 0:d4e5ad7ad71c 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
EricLew 0:d4e5ad7ad71c 700 {
EricLew 0:d4e5ad7ad71c 701 uint32_t result;
EricLew 0:d4e5ad7ad71c 702
EricLew 0:d4e5ad7ad71c 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
EricLew 0:d4e5ad7ad71c 704 return(result);
EricLew 0:d4e5ad7ad71c 705 }
EricLew 0:d4e5ad7ad71c 706
EricLew 0:d4e5ad7ad71c 707
EricLew 0:d4e5ad7ad71c 708 /** \brief STR Exclusive (32 bit)
EricLew 0:d4e5ad7ad71c 709
EricLew 0:d4e5ad7ad71c 710 This function executes a exclusive STR instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 711
EricLew 0:d4e5ad7ad71c 712 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 713 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 714 \return 0 Function succeeded
EricLew 0:d4e5ad7ad71c 715 \return 1 Function failed
EricLew 0:d4e5ad7ad71c 716 */
EricLew 0:d4e5ad7ad71c 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
EricLew 0:d4e5ad7ad71c 718 {
EricLew 0:d4e5ad7ad71c 719 uint32_t result;
EricLew 0:d4e5ad7ad71c 720
EricLew 0:d4e5ad7ad71c 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
EricLew 0:d4e5ad7ad71c 722 return(result);
EricLew 0:d4e5ad7ad71c 723 }
EricLew 0:d4e5ad7ad71c 724
EricLew 0:d4e5ad7ad71c 725
EricLew 0:d4e5ad7ad71c 726 /** \brief Remove the exclusive lock
EricLew 0:d4e5ad7ad71c 727
EricLew 0:d4e5ad7ad71c 728 This function removes the exclusive lock which is created by LDREX.
EricLew 0:d4e5ad7ad71c 729
EricLew 0:d4e5ad7ad71c 730 */
EricLew 0:d4e5ad7ad71c 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
EricLew 0:d4e5ad7ad71c 732 {
EricLew 0:d4e5ad7ad71c 733 __ASM volatile ("clrex" ::: "memory");
EricLew 0:d4e5ad7ad71c 734 }
EricLew 0:d4e5ad7ad71c 735
EricLew 0:d4e5ad7ad71c 736
EricLew 0:d4e5ad7ad71c 737 /** \brief Signed Saturate
EricLew 0:d4e5ad7ad71c 738
EricLew 0:d4e5ad7ad71c 739 This function saturates a signed value.
EricLew 0:d4e5ad7ad71c 740
EricLew 0:d4e5ad7ad71c 741 \param [in] value Value to be saturated
EricLew 0:d4e5ad7ad71c 742 \param [in] sat Bit position to saturate to (1..32)
EricLew 0:d4e5ad7ad71c 743 \return Saturated value
EricLew 0:d4e5ad7ad71c 744 */
EricLew 0:d4e5ad7ad71c 745 #define __SSAT(ARG1,ARG2) \
EricLew 0:d4e5ad7ad71c 746 ({ \
EricLew 0:d4e5ad7ad71c 747 uint32_t __RES, __ARG1 = (ARG1); \
EricLew 0:d4e5ad7ad71c 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
EricLew 0:d4e5ad7ad71c 749 __RES; \
EricLew 0:d4e5ad7ad71c 750 })
EricLew 0:d4e5ad7ad71c 751
EricLew 0:d4e5ad7ad71c 752
EricLew 0:d4e5ad7ad71c 753 /** \brief Unsigned Saturate
EricLew 0:d4e5ad7ad71c 754
EricLew 0:d4e5ad7ad71c 755 This function saturates an unsigned value.
EricLew 0:d4e5ad7ad71c 756
EricLew 0:d4e5ad7ad71c 757 \param [in] value Value to be saturated
EricLew 0:d4e5ad7ad71c 758 \param [in] sat Bit position to saturate to (0..31)
EricLew 0:d4e5ad7ad71c 759 \return Saturated value
EricLew 0:d4e5ad7ad71c 760 */
EricLew 0:d4e5ad7ad71c 761 #define __USAT(ARG1,ARG2) \
EricLew 0:d4e5ad7ad71c 762 ({ \
EricLew 0:d4e5ad7ad71c 763 uint32_t __RES, __ARG1 = (ARG1); \
EricLew 0:d4e5ad7ad71c 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
EricLew 0:d4e5ad7ad71c 765 __RES; \
EricLew 0:d4e5ad7ad71c 766 })
EricLew 0:d4e5ad7ad71c 767
EricLew 0:d4e5ad7ad71c 768
EricLew 0:d4e5ad7ad71c 769 /** \brief Rotate Right with Extend (32 bit)
EricLew 0:d4e5ad7ad71c 770
EricLew 0:d4e5ad7ad71c 771 This function moves each bit of a bitstring right by one bit.
EricLew 0:d4e5ad7ad71c 772 The carry input is shifted in at the left end of the bitstring.
EricLew 0:d4e5ad7ad71c 773
EricLew 0:d4e5ad7ad71c 774 \param [in] value Value to rotate
EricLew 0:d4e5ad7ad71c 775 \return Rotated value
EricLew 0:d4e5ad7ad71c 776 */
EricLew 0:d4e5ad7ad71c 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
EricLew 0:d4e5ad7ad71c 778 {
EricLew 0:d4e5ad7ad71c 779 uint32_t result;
EricLew 0:d4e5ad7ad71c 780
EricLew 0:d4e5ad7ad71c 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
EricLew 0:d4e5ad7ad71c 782 return(result);
EricLew 0:d4e5ad7ad71c 783 }
EricLew 0:d4e5ad7ad71c 784
EricLew 0:d4e5ad7ad71c 785
EricLew 0:d4e5ad7ad71c 786 /** \brief LDRT Unprivileged (8 bit)
EricLew 0:d4e5ad7ad71c 787
EricLew 0:d4e5ad7ad71c 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
EricLew 0:d4e5ad7ad71c 789
EricLew 0:d4e5ad7ad71c 790 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 791 \return value of type uint8_t at (*ptr)
EricLew 0:d4e5ad7ad71c 792 */
EricLew 0:d4e5ad7ad71c 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
EricLew 0:d4e5ad7ad71c 794 {
EricLew 0:d4e5ad7ad71c 795 uint32_t result;
EricLew 0:d4e5ad7ad71c 796
EricLew 0:d4e5ad7ad71c 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
EricLew 0:d4e5ad7ad71c 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
EricLew 0:d4e5ad7ad71c 799 #else
EricLew 0:d4e5ad7ad71c 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
EricLew 0:d4e5ad7ad71c 801 accepted by assembler. So has to use following less efficient pattern.
EricLew 0:d4e5ad7ad71c 802 */
EricLew 0:d4e5ad7ad71c 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
EricLew 0:d4e5ad7ad71c 804 #endif
EricLew 0:d4e5ad7ad71c 805 return ((uint8_t) result); /* Add explicit type cast here */
EricLew 0:d4e5ad7ad71c 806 }
EricLew 0:d4e5ad7ad71c 807
EricLew 0:d4e5ad7ad71c 808
EricLew 0:d4e5ad7ad71c 809 /** \brief LDRT Unprivileged (16 bit)
EricLew 0:d4e5ad7ad71c 810
EricLew 0:d4e5ad7ad71c 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 812
EricLew 0:d4e5ad7ad71c 813 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 814 \return value of type uint16_t at (*ptr)
EricLew 0:d4e5ad7ad71c 815 */
EricLew 0:d4e5ad7ad71c 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
EricLew 0:d4e5ad7ad71c 817 {
EricLew 0:d4e5ad7ad71c 818 uint32_t result;
EricLew 0:d4e5ad7ad71c 819
EricLew 0:d4e5ad7ad71c 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
EricLew 0:d4e5ad7ad71c 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
EricLew 0:d4e5ad7ad71c 822 #else
EricLew 0:d4e5ad7ad71c 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
EricLew 0:d4e5ad7ad71c 824 accepted by assembler. So has to use following less efficient pattern.
EricLew 0:d4e5ad7ad71c 825 */
EricLew 0:d4e5ad7ad71c 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
EricLew 0:d4e5ad7ad71c 827 #endif
EricLew 0:d4e5ad7ad71c 828 return ((uint16_t) result); /* Add explicit type cast here */
EricLew 0:d4e5ad7ad71c 829 }
EricLew 0:d4e5ad7ad71c 830
EricLew 0:d4e5ad7ad71c 831
EricLew 0:d4e5ad7ad71c 832 /** \brief LDRT Unprivileged (32 bit)
EricLew 0:d4e5ad7ad71c 833
EricLew 0:d4e5ad7ad71c 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 835
EricLew 0:d4e5ad7ad71c 836 \param [in] ptr Pointer to data
EricLew 0:d4e5ad7ad71c 837 \return value of type uint32_t at (*ptr)
EricLew 0:d4e5ad7ad71c 838 */
EricLew 0:d4e5ad7ad71c 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
EricLew 0:d4e5ad7ad71c 840 {
EricLew 0:d4e5ad7ad71c 841 uint32_t result;
EricLew 0:d4e5ad7ad71c 842
EricLew 0:d4e5ad7ad71c 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
EricLew 0:d4e5ad7ad71c 844 return(result);
EricLew 0:d4e5ad7ad71c 845 }
EricLew 0:d4e5ad7ad71c 846
EricLew 0:d4e5ad7ad71c 847
EricLew 0:d4e5ad7ad71c 848 /** \brief STRT Unprivileged (8 bit)
EricLew 0:d4e5ad7ad71c 849
EricLew 0:d4e5ad7ad71c 850 This function executes a Unprivileged STRT instruction for 8 bit values.
EricLew 0:d4e5ad7ad71c 851
EricLew 0:d4e5ad7ad71c 852 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 853 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 854 */
EricLew 0:d4e5ad7ad71c 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
EricLew 0:d4e5ad7ad71c 856 {
EricLew 0:d4e5ad7ad71c 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
EricLew 0:d4e5ad7ad71c 858 }
EricLew 0:d4e5ad7ad71c 859
EricLew 0:d4e5ad7ad71c 860
EricLew 0:d4e5ad7ad71c 861 /** \brief STRT Unprivileged (16 bit)
EricLew 0:d4e5ad7ad71c 862
EricLew 0:d4e5ad7ad71c 863 This function executes a Unprivileged STRT instruction for 16 bit values.
EricLew 0:d4e5ad7ad71c 864
EricLew 0:d4e5ad7ad71c 865 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 866 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 867 */
EricLew 0:d4e5ad7ad71c 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
EricLew 0:d4e5ad7ad71c 869 {
EricLew 0:d4e5ad7ad71c 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
EricLew 0:d4e5ad7ad71c 871 }
EricLew 0:d4e5ad7ad71c 872
EricLew 0:d4e5ad7ad71c 873
EricLew 0:d4e5ad7ad71c 874 /** \brief STRT Unprivileged (32 bit)
EricLew 0:d4e5ad7ad71c 875
EricLew 0:d4e5ad7ad71c 876 This function executes a Unprivileged STRT instruction for 32 bit values.
EricLew 0:d4e5ad7ad71c 877
EricLew 0:d4e5ad7ad71c 878 \param [in] value Value to store
EricLew 0:d4e5ad7ad71c 879 \param [in] ptr Pointer to location
EricLew 0:d4e5ad7ad71c 880 */
EricLew 0:d4e5ad7ad71c 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
EricLew 0:d4e5ad7ad71c 882 {
EricLew 0:d4e5ad7ad71c 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
EricLew 0:d4e5ad7ad71c 884 }
EricLew 0:d4e5ad7ad71c 885
EricLew 0:d4e5ad7ad71c 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
EricLew 0:d4e5ad7ad71c 887
EricLew 0:d4e5ad7ad71c 888
EricLew 0:d4e5ad7ad71c 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
EricLew 0:d4e5ad7ad71c 890 /* IAR iccarm specific functions */
EricLew 0:d4e5ad7ad71c 891 #include <cmsis_iar.h>
EricLew 0:d4e5ad7ad71c 892
EricLew 0:d4e5ad7ad71c 893
EricLew 0:d4e5ad7ad71c 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
EricLew 0:d4e5ad7ad71c 895 /* TI CCS specific functions */
EricLew 0:d4e5ad7ad71c 896 #include <cmsis_ccs.h>
EricLew 0:d4e5ad7ad71c 897
EricLew 0:d4e5ad7ad71c 898
EricLew 0:d4e5ad7ad71c 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
EricLew 0:d4e5ad7ad71c 900 /* TASKING carm specific functions */
EricLew 0:d4e5ad7ad71c 901 /*
EricLew 0:d4e5ad7ad71c 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
EricLew 0:d4e5ad7ad71c 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
EricLew 0:d4e5ad7ad71c 904 * Including the CMSIS ones.
EricLew 0:d4e5ad7ad71c 905 */
EricLew 0:d4e5ad7ad71c 906
EricLew 0:d4e5ad7ad71c 907
EricLew 0:d4e5ad7ad71c 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
EricLew 0:d4e5ad7ad71c 909 /* Cosmic specific functions */
EricLew 0:d4e5ad7ad71c 910 #include <cmsis_csm.h>
EricLew 0:d4e5ad7ad71c 911
EricLew 0:d4e5ad7ad71c 912 #endif
EricLew 0:d4e5ad7ad71c 913
EricLew 0:d4e5ad7ad71c 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
EricLew 0:d4e5ad7ad71c 915
EricLew 0:d4e5ad7ad71c 916 #endif /* __CORE_CMINSTR_H */
EricLew 0:d4e5ad7ad71c 917